omap_hsmmc.c 32 KB

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  1. /*
  2. * drivers/mmc/host/omap_hsmmc.c
  3. *
  4. * Driver for OMAP2430/3430 MMC controller.
  5. *
  6. * Copyright (C) 2007 Texas Instruments.
  7. *
  8. * Authors:
  9. * Syed Mohammed Khasim <x0khasim@ti.com>
  10. * Madhusudhan <madhu.cr@ti.com>
  11. * Mohit Jalori <mjalori@ti.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/delay.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/timer.h>
  25. #include <linux/clk.h>
  26. #include <linux/mmc/host.h>
  27. #include <linux/io.h>
  28. #include <linux/semaphore.h>
  29. #include <mach/dma.h>
  30. #include <mach/hardware.h>
  31. #include <mach/board.h>
  32. #include <mach/mmc.h>
  33. #include <mach/cpu.h>
  34. /* OMAP HSMMC Host Controller Registers */
  35. #define OMAP_HSMMC_SYSCONFIG 0x0010
  36. #define OMAP_HSMMC_CON 0x002C
  37. #define OMAP_HSMMC_BLK 0x0104
  38. #define OMAP_HSMMC_ARG 0x0108
  39. #define OMAP_HSMMC_CMD 0x010C
  40. #define OMAP_HSMMC_RSP10 0x0110
  41. #define OMAP_HSMMC_RSP32 0x0114
  42. #define OMAP_HSMMC_RSP54 0x0118
  43. #define OMAP_HSMMC_RSP76 0x011C
  44. #define OMAP_HSMMC_DATA 0x0120
  45. #define OMAP_HSMMC_HCTL 0x0128
  46. #define OMAP_HSMMC_SYSCTL 0x012C
  47. #define OMAP_HSMMC_STAT 0x0130
  48. #define OMAP_HSMMC_IE 0x0134
  49. #define OMAP_HSMMC_ISE 0x0138
  50. #define OMAP_HSMMC_CAPA 0x0140
  51. #define VS18 (1 << 26)
  52. #define VS30 (1 << 25)
  53. #define SDVS18 (0x5 << 9)
  54. #define SDVS30 (0x6 << 9)
  55. #define SDVS33 (0x7 << 9)
  56. #define SDVS_MASK 0x00000E00
  57. #define SDVSCLR 0xFFFFF1FF
  58. #define SDVSDET 0x00000400
  59. #define AUTOIDLE 0x1
  60. #define SDBP (1 << 8)
  61. #define DTO 0xe
  62. #define ICE 0x1
  63. #define ICS 0x2
  64. #define CEN (1 << 2)
  65. #define CLKD_MASK 0x0000FFC0
  66. #define CLKD_SHIFT 6
  67. #define DTO_MASK 0x000F0000
  68. #define DTO_SHIFT 16
  69. #define INT_EN_MASK 0x307F0033
  70. #define INIT_STREAM (1 << 1)
  71. #define DP_SELECT (1 << 21)
  72. #define DDIR (1 << 4)
  73. #define DMA_EN 0x1
  74. #define MSBS (1 << 5)
  75. #define BCE (1 << 1)
  76. #define FOUR_BIT (1 << 1)
  77. #define CC 0x1
  78. #define TC 0x02
  79. #define OD 0x1
  80. #define ERR (1 << 15)
  81. #define CMD_TIMEOUT (1 << 16)
  82. #define DATA_TIMEOUT (1 << 20)
  83. #define CMD_CRC (1 << 17)
  84. #define DATA_CRC (1 << 21)
  85. #define CARD_ERR (1 << 28)
  86. #define STAT_CLEAR 0xFFFFFFFF
  87. #define INIT_STREAM_CMD 0x00000000
  88. #define DUAL_VOLT_OCR_BIT 7
  89. #define SRC (1 << 25)
  90. #define SRD (1 << 26)
  91. /*
  92. * FIXME: Most likely all the data using these _DEVID defines should come
  93. * from the platform_data, or implemented in controller and slot specific
  94. * functions.
  95. */
  96. #define OMAP_MMC1_DEVID 0
  97. #define OMAP_MMC2_DEVID 1
  98. #define MMC_TIMEOUT_MS 20
  99. #define OMAP_MMC_MASTER_CLOCK 96000000
  100. #define DRIVER_NAME "mmci-omap-hs"
  101. /*
  102. * One controller can have multiple slots, like on some omap boards using
  103. * omap.c controller driver. Luckily this is not currently done on any known
  104. * omap_hsmmc.c device.
  105. */
  106. #define mmc_slot(host) (host->pdata->slots[host->slot_id])
  107. /*
  108. * MMC Host controller read/write API's
  109. */
  110. #define OMAP_HSMMC_READ(base, reg) \
  111. __raw_readl((base) + OMAP_HSMMC_##reg)
  112. #define OMAP_HSMMC_WRITE(base, reg, val) \
  113. __raw_writel((val), (base) + OMAP_HSMMC_##reg)
  114. struct mmc_omap_host {
  115. struct device *dev;
  116. struct mmc_host *mmc;
  117. struct mmc_request *mrq;
  118. struct mmc_command *cmd;
  119. struct mmc_data *data;
  120. struct clk *fclk;
  121. struct clk *iclk;
  122. struct clk *dbclk;
  123. struct semaphore sem;
  124. struct work_struct mmc_carddetect_work;
  125. void __iomem *base;
  126. resource_size_t mapbase;
  127. unsigned int id;
  128. unsigned int dma_len;
  129. unsigned int dma_sg_idx;
  130. unsigned char bus_mode;
  131. u32 *buffer;
  132. u32 bytesleft;
  133. int suspended;
  134. int irq;
  135. int carddetect;
  136. int use_dma, dma_ch;
  137. int slot_id;
  138. int dbclk_enabled;
  139. int response_busy;
  140. struct omap_mmc_platform_data *pdata;
  141. };
  142. /*
  143. * Stop clock to the card
  144. */
  145. static void omap_mmc_stop_clock(struct mmc_omap_host *host)
  146. {
  147. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  148. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  149. if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
  150. dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
  151. }
  152. /*
  153. * Send init stream sequence to card
  154. * before sending IDLE command
  155. */
  156. static void send_init_stream(struct mmc_omap_host *host)
  157. {
  158. int reg = 0;
  159. unsigned long timeout;
  160. disable_irq(host->irq);
  161. OMAP_HSMMC_WRITE(host->base, CON,
  162. OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
  163. OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
  164. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  165. while ((reg != CC) && time_before(jiffies, timeout))
  166. reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
  167. OMAP_HSMMC_WRITE(host->base, CON,
  168. OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
  169. enable_irq(host->irq);
  170. }
  171. static inline
  172. int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
  173. {
  174. int r = 1;
  175. if (host->pdata->slots[host->slot_id].get_cover_state)
  176. r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
  177. host->slot_id);
  178. return r;
  179. }
  180. static ssize_t
  181. mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
  182. char *buf)
  183. {
  184. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  185. struct mmc_omap_host *host = mmc_priv(mmc);
  186. return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
  187. "open");
  188. }
  189. static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
  190. static ssize_t
  191. mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
  192. char *buf)
  193. {
  194. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  195. struct mmc_omap_host *host = mmc_priv(mmc);
  196. struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
  197. return sprintf(buf, "slot:%s\n", slot.name);
  198. }
  199. static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
  200. /*
  201. * Configure the response type and send the cmd.
  202. */
  203. static void
  204. mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
  205. struct mmc_data *data)
  206. {
  207. int cmdreg = 0, resptype = 0, cmdtype = 0;
  208. dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
  209. mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
  210. host->cmd = cmd;
  211. /*
  212. * Clear status bits and enable interrupts
  213. */
  214. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  215. OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
  216. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  217. host->response_busy = 0;
  218. if (cmd->flags & MMC_RSP_PRESENT) {
  219. if (cmd->flags & MMC_RSP_136)
  220. resptype = 1;
  221. else if (cmd->flags & MMC_RSP_BUSY) {
  222. resptype = 3;
  223. host->response_busy = 1;
  224. } else
  225. resptype = 2;
  226. }
  227. /*
  228. * Unlike OMAP1 controller, the cmdtype does not seem to be based on
  229. * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
  230. * a val of 0x3, rest 0x0.
  231. */
  232. if (cmd == host->mrq->stop)
  233. cmdtype = 0x3;
  234. cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
  235. if (data) {
  236. cmdreg |= DP_SELECT | MSBS | BCE;
  237. if (data->flags & MMC_DATA_READ)
  238. cmdreg |= DDIR;
  239. else
  240. cmdreg &= ~(DDIR);
  241. }
  242. if (host->use_dma)
  243. cmdreg |= DMA_EN;
  244. OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
  245. OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
  246. }
  247. static int
  248. mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
  249. {
  250. if (data->flags & MMC_DATA_WRITE)
  251. return DMA_TO_DEVICE;
  252. else
  253. return DMA_FROM_DEVICE;
  254. }
  255. /*
  256. * Notify the transfer complete to MMC core
  257. */
  258. static void
  259. mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
  260. {
  261. if (!data) {
  262. struct mmc_request *mrq = host->mrq;
  263. host->mrq = NULL;
  264. mmc_omap_fclk_lazy_disable(host);
  265. mmc_request_done(host->mmc, mrq);
  266. return;
  267. }
  268. host->data = NULL;
  269. if (host->use_dma && host->dma_ch != -1)
  270. dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
  271. mmc_omap_get_dma_dir(host, data));
  272. if (!data->error)
  273. data->bytes_xfered += data->blocks * (data->blksz);
  274. else
  275. data->bytes_xfered = 0;
  276. if (!data->stop) {
  277. host->mrq = NULL;
  278. mmc_request_done(host->mmc, data->mrq);
  279. return;
  280. }
  281. mmc_omap_start_command(host, data->stop, NULL);
  282. }
  283. /*
  284. * Notify the core about command completion
  285. */
  286. static void
  287. mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
  288. {
  289. host->cmd = NULL;
  290. if (cmd->flags & MMC_RSP_PRESENT) {
  291. if (cmd->flags & MMC_RSP_136) {
  292. /* response type 2 */
  293. cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
  294. cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
  295. cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
  296. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
  297. } else {
  298. /* response types 1, 1b, 3, 4, 5, 6 */
  299. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
  300. }
  301. }
  302. if ((host->data == NULL && !host->response_busy) || cmd->error) {
  303. host->mrq = NULL;
  304. mmc_request_done(host->mmc, cmd->mrq);
  305. }
  306. }
  307. /*
  308. * DMA clean up for command errors
  309. */
  310. static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
  311. {
  312. host->data->error = errno;
  313. if (host->use_dma && host->dma_ch != -1) {
  314. dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
  315. mmc_omap_get_dma_dir(host, host->data));
  316. omap_free_dma(host->dma_ch);
  317. host->dma_ch = -1;
  318. up(&host->sem);
  319. }
  320. host->data = NULL;
  321. }
  322. /*
  323. * Readable error output
  324. */
  325. #ifdef CONFIG_MMC_DEBUG
  326. static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
  327. {
  328. /* --- means reserved bit without definition at documentation */
  329. static const char *mmc_omap_status_bits[] = {
  330. "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
  331. "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
  332. "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
  333. "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
  334. };
  335. char res[256];
  336. char *buf = res;
  337. int len, i;
  338. len = sprintf(buf, "MMC IRQ 0x%x :", status);
  339. buf += len;
  340. for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
  341. if (status & (1 << i)) {
  342. len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
  343. buf += len;
  344. }
  345. dev_dbg(mmc_dev(host->mmc), "%s\n", res);
  346. }
  347. #endif /* CONFIG_MMC_DEBUG */
  348. /*
  349. * MMC controller internal state machines reset
  350. *
  351. * Used to reset command or data internal state machines, using respectively
  352. * SRC or SRD bit of SYSCTL register
  353. * Can be called from interrupt context
  354. */
  355. static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
  356. unsigned long bit)
  357. {
  358. unsigned long i = 0;
  359. unsigned long limit = (loops_per_jiffy *
  360. msecs_to_jiffies(MMC_TIMEOUT_MS));
  361. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  362. OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
  363. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
  364. (i++ < limit))
  365. cpu_relax();
  366. if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
  367. dev_err(mmc_dev(host->mmc),
  368. "Timeout waiting on controller reset in %s\n",
  369. __func__);
  370. }
  371. /*
  372. * MMC controller IRQ handler
  373. */
  374. static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
  375. {
  376. struct mmc_omap_host *host = dev_id;
  377. struct mmc_data *data;
  378. int end_cmd = 0, end_trans = 0, status;
  379. if (host->mrq == NULL) {
  380. OMAP_HSMMC_WRITE(host->base, STAT,
  381. OMAP_HSMMC_READ(host->base, STAT));
  382. return IRQ_HANDLED;
  383. }
  384. data = host->data;
  385. status = OMAP_HSMMC_READ(host->base, STAT);
  386. dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
  387. if (status & ERR) {
  388. #ifdef CONFIG_MMC_DEBUG
  389. mmc_omap_report_irq(host, status);
  390. #endif
  391. if ((status & CMD_TIMEOUT) ||
  392. (status & CMD_CRC)) {
  393. if (host->cmd) {
  394. if (status & CMD_TIMEOUT) {
  395. mmc_omap_reset_controller_fsm(host, SRC);
  396. host->cmd->error = -ETIMEDOUT;
  397. } else {
  398. host->cmd->error = -EILSEQ;
  399. }
  400. end_cmd = 1;
  401. }
  402. if (host->data || host->response_busy) {
  403. if (host->data)
  404. mmc_dma_cleanup(host, -ETIMEDOUT);
  405. host->response_busy = 0;
  406. mmc_omap_reset_controller_fsm(host, SRD);
  407. }
  408. }
  409. if ((status & DATA_TIMEOUT) ||
  410. (status & DATA_CRC)) {
  411. if (host->data || host->response_busy) {
  412. int err = (status & DATA_TIMEOUT) ?
  413. -ETIMEDOUT : -EILSEQ;
  414. if (host->data)
  415. mmc_dma_cleanup(host, err);
  416. else
  417. host->mrq->cmd->error = err;
  418. host->response_busy = 0;
  419. mmc_omap_reset_controller_fsm(host, SRD);
  420. end_trans = 1;
  421. }
  422. }
  423. if (status & CARD_ERR) {
  424. dev_dbg(mmc_dev(host->mmc),
  425. "Ignoring card err CMD%d\n", host->cmd->opcode);
  426. if (host->cmd)
  427. end_cmd = 1;
  428. if (host->data)
  429. end_trans = 1;
  430. }
  431. }
  432. OMAP_HSMMC_WRITE(host->base, STAT, status);
  433. if (end_cmd || (status & CC))
  434. mmc_omap_cmd_done(host, host->cmd);
  435. if (end_trans || (status & TC))
  436. mmc_omap_xfer_done(host, data);
  437. return IRQ_HANDLED;
  438. }
  439. /*
  440. * Switch MMC interface voltage ... only relevant for MMC1.
  441. *
  442. * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
  443. * The MMC2 transceiver controls are used instead of DAT4..DAT7.
  444. * Some chips, like eMMC ones, use internal transceivers.
  445. */
  446. static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
  447. {
  448. u32 reg_val = 0;
  449. int ret;
  450. /* Disable the clocks */
  451. clk_disable(host->fclk);
  452. clk_disable(host->iclk);
  453. clk_disable(host->dbclk);
  454. /* Turn the power off */
  455. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
  456. if (ret != 0)
  457. goto err;
  458. /* Turn the power ON with given VDD 1.8 or 3.0v */
  459. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
  460. if (ret != 0)
  461. goto err;
  462. clk_enable(host->fclk);
  463. clk_enable(host->iclk);
  464. clk_enable(host->dbclk);
  465. OMAP_HSMMC_WRITE(host->base, HCTL,
  466. OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
  467. reg_val = OMAP_HSMMC_READ(host->base, HCTL);
  468. /*
  469. * If a MMC dual voltage card is detected, the set_ios fn calls
  470. * this fn with VDD bit set for 1.8V. Upon card removal from the
  471. * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
  472. *
  473. * Cope with a bit of slop in the range ... per data sheets:
  474. * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
  475. * but recommended values are 1.71V to 1.89V
  476. * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
  477. * but recommended values are 2.7V to 3.3V
  478. *
  479. * Board setup code shouldn't permit anything very out-of-range.
  480. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
  481. * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
  482. */
  483. if ((1 << vdd) <= MMC_VDD_23_24)
  484. reg_val |= SDVS18;
  485. else
  486. reg_val |= SDVS30;
  487. OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
  488. OMAP_HSMMC_WRITE(host->base, HCTL,
  489. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  490. return 0;
  491. err:
  492. dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
  493. return ret;
  494. }
  495. /*
  496. * Work Item to notify the core about card insertion/removal
  497. */
  498. static void mmc_omap_detect(struct work_struct *work)
  499. {
  500. struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
  501. mmc_carddetect_work);
  502. struct omap_mmc_slot_data *slot = &mmc_slot(host);
  503. host->carddetect = slot->card_detect(slot->card_detect_irq);
  504. sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
  505. if (host->carddetect) {
  506. mmc_detect_change(host->mmc, (HZ * 200) / 1000);
  507. } else {
  508. mmc_omap_reset_controller_fsm(host, SRD);
  509. mmc_detect_change(host->mmc, (HZ * 50) / 1000);
  510. }
  511. }
  512. /*
  513. * ISR for handling card insertion and removal
  514. */
  515. static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
  516. {
  517. struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
  518. schedule_work(&host->mmc_carddetect_work);
  519. return IRQ_HANDLED;
  520. }
  521. static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
  522. struct mmc_data *data)
  523. {
  524. int sync_dev;
  525. if (data->flags & MMC_DATA_WRITE) {
  526. if (host->id == OMAP_MMC1_DEVID)
  527. sync_dev = OMAP24XX_DMA_MMC1_TX;
  528. else
  529. sync_dev = OMAP24XX_DMA_MMC2_TX;
  530. } else {
  531. if (host->id == OMAP_MMC1_DEVID)
  532. sync_dev = OMAP24XX_DMA_MMC1_RX;
  533. else
  534. sync_dev = OMAP24XX_DMA_MMC2_RX;
  535. }
  536. return sync_dev;
  537. }
  538. static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
  539. struct mmc_data *data,
  540. struct scatterlist *sgl)
  541. {
  542. int blksz, nblk, dma_ch;
  543. dma_ch = host->dma_ch;
  544. if (data->flags & MMC_DATA_WRITE) {
  545. omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  546. (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
  547. omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  548. sg_dma_address(sgl), 0, 0);
  549. } else {
  550. omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  551. (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
  552. omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  553. sg_dma_address(sgl), 0, 0);
  554. }
  555. blksz = host->data->blksz;
  556. nblk = sg_dma_len(sgl) / blksz;
  557. omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
  558. blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
  559. mmc_omap_get_dma_sync_dev(host, data),
  560. !(data->flags & MMC_DATA_WRITE));
  561. omap_start_dma(dma_ch);
  562. }
  563. /*
  564. * DMA call back function
  565. */
  566. static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
  567. {
  568. struct mmc_omap_host *host = data;
  569. if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
  570. dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
  571. if (host->dma_ch < 0)
  572. return;
  573. host->dma_sg_idx++;
  574. if (host->dma_sg_idx < host->dma_len) {
  575. /* Fire up the next transfer. */
  576. mmc_omap_config_dma_params(host, host->data,
  577. host->data->sg + host->dma_sg_idx);
  578. return;
  579. }
  580. omap_free_dma(host->dma_ch);
  581. host->dma_ch = -1;
  582. /*
  583. * DMA Callback: run in interrupt context.
  584. * mutex_unlock will through a kernel warning if used.
  585. */
  586. up(&host->sem);
  587. }
  588. /*
  589. * Routine to configure and start DMA for the MMC card
  590. */
  591. static int
  592. mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
  593. {
  594. int dma_ch = 0, ret = 0, err = 1, i;
  595. struct mmc_data *data = req->data;
  596. /* Sanity check: all the SG entries must be aligned by block size. */
  597. for (i = 0; i < host->dma_len; i++) {
  598. struct scatterlist *sgl;
  599. sgl = data->sg + i;
  600. if (sgl->length % data->blksz)
  601. return -EINVAL;
  602. }
  603. if ((data->blksz % 4) != 0)
  604. /* REVISIT: The MMC buffer increments only when MSB is written.
  605. * Return error for blksz which is non multiple of four.
  606. */
  607. return -EINVAL;
  608. /*
  609. * If for some reason the DMA transfer is still active,
  610. * we wait for timeout period and free the dma
  611. */
  612. if (host->dma_ch != -1) {
  613. set_current_state(TASK_UNINTERRUPTIBLE);
  614. schedule_timeout(100);
  615. if (down_trylock(&host->sem)) {
  616. omap_free_dma(host->dma_ch);
  617. host->dma_ch = -1;
  618. up(&host->sem);
  619. return err;
  620. }
  621. } else {
  622. if (down_trylock(&host->sem))
  623. return err;
  624. }
  625. ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
  626. mmc_omap_dma_cb,host, &dma_ch);
  627. if (ret != 0) {
  628. dev_err(mmc_dev(host->mmc),
  629. "%s: omap_request_dma() failed with %d\n",
  630. mmc_hostname(host->mmc), ret);
  631. return ret;
  632. }
  633. host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
  634. data->sg_len, mmc_omap_get_dma_dir(host, data));
  635. host->dma_ch = dma_ch;
  636. host->dma_sg_idx = 0;
  637. mmc_omap_config_dma_params(host, data, data->sg);
  638. return 0;
  639. }
  640. static void set_data_timeout(struct mmc_omap_host *host,
  641. struct mmc_request *req)
  642. {
  643. unsigned int timeout, cycle_ns;
  644. uint32_t reg, clkd, dto = 0;
  645. reg = OMAP_HSMMC_READ(host->base, SYSCTL);
  646. clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
  647. if (clkd == 0)
  648. clkd = 1;
  649. cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
  650. timeout = req->data->timeout_ns / cycle_ns;
  651. timeout += req->data->timeout_clks;
  652. if (timeout) {
  653. while ((timeout & 0x80000000) == 0) {
  654. dto += 1;
  655. timeout <<= 1;
  656. }
  657. dto = 31 - dto;
  658. timeout <<= 1;
  659. if (timeout && dto)
  660. dto += 1;
  661. if (dto >= 13)
  662. dto -= 13;
  663. else
  664. dto = 0;
  665. if (dto > 14)
  666. dto = 14;
  667. }
  668. reg &= ~DTO_MASK;
  669. reg |= dto << DTO_SHIFT;
  670. OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
  671. }
  672. /*
  673. * Configure block length for MMC/SD cards and initiate the transfer.
  674. */
  675. static int
  676. mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
  677. {
  678. int ret;
  679. host->data = req->data;
  680. if (req->data == NULL) {
  681. OMAP_HSMMC_WRITE(host->base, BLK, 0);
  682. return 0;
  683. }
  684. OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
  685. | (req->data->blocks << 16));
  686. set_data_timeout(host, req);
  687. if (host->use_dma) {
  688. ret = mmc_omap_start_dma_transfer(host, req);
  689. if (ret != 0) {
  690. dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
  691. return ret;
  692. }
  693. }
  694. return 0;
  695. }
  696. /*
  697. * Request function. for read/write operation
  698. */
  699. static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
  700. {
  701. struct mmc_omap_host *host = mmc_priv(mmc);
  702. WARN_ON(host->mrq != NULL);
  703. host->mrq = req;
  704. mmc_omap_prepare_data(host, req);
  705. mmc_omap_start_command(host, req->cmd, req->data);
  706. }
  707. /* Routine to configure clock values. Exposed API to core */
  708. static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  709. {
  710. struct mmc_omap_host *host = mmc_priv(mmc);
  711. u16 dsor = 0;
  712. unsigned long regval;
  713. unsigned long timeout;
  714. switch (ios->power_mode) {
  715. case MMC_POWER_OFF:
  716. mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
  717. break;
  718. case MMC_POWER_UP:
  719. mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
  720. break;
  721. }
  722. switch (mmc->ios.bus_width) {
  723. case MMC_BUS_WIDTH_4:
  724. OMAP_HSMMC_WRITE(host->base, HCTL,
  725. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  726. break;
  727. case MMC_BUS_WIDTH_1:
  728. OMAP_HSMMC_WRITE(host->base, HCTL,
  729. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  730. break;
  731. }
  732. if (host->id == OMAP_MMC1_DEVID) {
  733. /* Only MMC1 can interface at 3V without some flavor
  734. * of external transceiver; but they all handle 1.8V.
  735. */
  736. if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
  737. (ios->vdd == DUAL_VOLT_OCR_BIT)) {
  738. /*
  739. * The mmc_select_voltage fn of the core does
  740. * not seem to set the power_mode to
  741. * MMC_POWER_UP upon recalculating the voltage.
  742. * vdd 1.8v.
  743. */
  744. if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
  745. dev_dbg(mmc_dev(host->mmc),
  746. "Switch operation failed\n");
  747. }
  748. }
  749. if (ios->clock) {
  750. dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
  751. if (dsor < 1)
  752. dsor = 1;
  753. if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
  754. dsor++;
  755. if (dsor > 250)
  756. dsor = 250;
  757. }
  758. omap_mmc_stop_clock(host);
  759. regval = OMAP_HSMMC_READ(host->base, SYSCTL);
  760. regval = regval & ~(CLKD_MASK);
  761. regval = regval | (dsor << 6) | (DTO << 16);
  762. OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
  763. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  764. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  765. /* Wait till the ICS bit is set */
  766. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  767. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
  768. && time_before(jiffies, timeout))
  769. msleep(1);
  770. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  771. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  772. if (ios->power_mode == MMC_POWER_ON)
  773. send_init_stream(host);
  774. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  775. OMAP_HSMMC_WRITE(host->base, CON,
  776. OMAP_HSMMC_READ(host->base, CON) | OD);
  777. }
  778. static int omap_hsmmc_get_cd(struct mmc_host *mmc)
  779. {
  780. struct mmc_omap_host *host = mmc_priv(mmc);
  781. struct omap_mmc_platform_data *pdata = host->pdata;
  782. if (!pdata->slots[0].card_detect)
  783. return -ENOSYS;
  784. return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
  785. }
  786. static int omap_hsmmc_get_ro(struct mmc_host *mmc)
  787. {
  788. struct mmc_omap_host *host = mmc_priv(mmc);
  789. struct omap_mmc_platform_data *pdata = host->pdata;
  790. if (!pdata->slots[0].get_ro)
  791. return -ENOSYS;
  792. return pdata->slots[0].get_ro(host->dev, 0);
  793. }
  794. static void omap_hsmmc_init(struct mmc_omap_host *host)
  795. {
  796. u32 hctl, capa, value;
  797. /* Only MMC1 supports 3.0V */
  798. if (host->id == OMAP_MMC1_DEVID) {
  799. hctl = SDVS30;
  800. capa = VS30 | VS18;
  801. } else {
  802. hctl = SDVS18;
  803. capa = VS18;
  804. }
  805. value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
  806. OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
  807. value = OMAP_HSMMC_READ(host->base, CAPA);
  808. OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
  809. /* Set the controller to AUTO IDLE mode */
  810. value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
  811. OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
  812. /* Set SD bus power bit */
  813. value = OMAP_HSMMC_READ(host->base, HCTL);
  814. OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP);
  815. }
  816. static struct mmc_host_ops mmc_omap_ops = {
  817. .request = omap_mmc_request,
  818. .set_ios = omap_mmc_set_ios,
  819. .get_cd = omap_hsmmc_get_cd,
  820. .get_ro = omap_hsmmc_get_ro,
  821. /* NYET -- enable_sdio_irq */
  822. };
  823. static int __init omap_mmc_probe(struct platform_device *pdev)
  824. {
  825. struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
  826. struct mmc_host *mmc;
  827. struct mmc_omap_host *host = NULL;
  828. struct resource *res;
  829. int ret = 0, irq;
  830. if (pdata == NULL) {
  831. dev_err(&pdev->dev, "Platform Data is missing\n");
  832. return -ENXIO;
  833. }
  834. if (pdata->nr_slots == 0) {
  835. dev_err(&pdev->dev, "No Slots\n");
  836. return -ENXIO;
  837. }
  838. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  839. irq = platform_get_irq(pdev, 0);
  840. if (res == NULL || irq < 0)
  841. return -ENXIO;
  842. res = request_mem_region(res->start, res->end - res->start + 1,
  843. pdev->name);
  844. if (res == NULL)
  845. return -EBUSY;
  846. mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
  847. if (!mmc) {
  848. ret = -ENOMEM;
  849. goto err;
  850. }
  851. host = mmc_priv(mmc);
  852. host->mmc = mmc;
  853. host->pdata = pdata;
  854. host->dev = &pdev->dev;
  855. host->use_dma = 1;
  856. host->dev->dma_mask = &pdata->dma_mask;
  857. host->dma_ch = -1;
  858. host->irq = irq;
  859. host->id = pdev->id;
  860. host->slot_id = 0;
  861. host->mapbase = res->start;
  862. host->base = ioremap(host->mapbase, SZ_4K);
  863. platform_set_drvdata(pdev, host);
  864. INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
  865. mmc->ops = &mmc_omap_ops;
  866. mmc->f_min = 400000;
  867. mmc->f_max = 52000000;
  868. sema_init(&host->sem, 1);
  869. host->iclk = clk_get(&pdev->dev, "mmchs_ick");
  870. if (IS_ERR(host->iclk)) {
  871. ret = PTR_ERR(host->iclk);
  872. host->iclk = NULL;
  873. goto err1;
  874. }
  875. host->fclk = clk_get(&pdev->dev, "mmchs_fck");
  876. if (IS_ERR(host->fclk)) {
  877. ret = PTR_ERR(host->fclk);
  878. host->fclk = NULL;
  879. clk_put(host->iclk);
  880. goto err1;
  881. }
  882. if (clk_enable(host->fclk) != 0) {
  883. clk_put(host->iclk);
  884. clk_put(host->fclk);
  885. goto err1;
  886. }
  887. if (clk_enable(host->iclk) != 0) {
  888. clk_disable(host->fclk);
  889. clk_put(host->iclk);
  890. clk_put(host->fclk);
  891. goto err1;
  892. }
  893. host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
  894. /*
  895. * MMC can still work without debounce clock.
  896. */
  897. if (IS_ERR(host->dbclk))
  898. dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
  899. else
  900. if (clk_enable(host->dbclk) != 0)
  901. dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
  902. " clk failed\n");
  903. else
  904. host->dbclk_enabled = 1;
  905. /* Since we do only SG emulation, we can have as many segs
  906. * as we want. */
  907. mmc->max_phys_segs = 1024;
  908. mmc->max_hw_segs = 1024;
  909. mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
  910. mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
  911. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  912. mmc->max_seg_size = mmc->max_req_size;
  913. mmc->ocr_avail = mmc_slot(host).ocr_mask;
  914. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
  915. if (pdata->slots[host->slot_id].wires >= 4)
  916. mmc->caps |= MMC_CAP_4_BIT_DATA;
  917. omap_hsmmc_init(host);
  918. /* Request IRQ for MMC operations */
  919. ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
  920. mmc_hostname(mmc), host);
  921. if (ret) {
  922. dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
  923. goto err_irq;
  924. }
  925. if (pdata->init != NULL) {
  926. if (pdata->init(&pdev->dev) != 0) {
  927. dev_dbg(mmc_dev(host->mmc),
  928. "Unable to configure MMC IRQs\n");
  929. goto err_irq_cd_init;
  930. }
  931. }
  932. /* Request IRQ for card detect */
  933. if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
  934. ret = request_irq(mmc_slot(host).card_detect_irq,
  935. omap_mmc_cd_handler,
  936. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
  937. | IRQF_DISABLED,
  938. mmc_hostname(mmc), host);
  939. if (ret) {
  940. dev_dbg(mmc_dev(host->mmc),
  941. "Unable to grab MMC CD IRQ\n");
  942. goto err_irq_cd;
  943. }
  944. }
  945. OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
  946. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  947. mmc_add_host(mmc);
  948. if (host->pdata->slots[host->slot_id].name != NULL) {
  949. ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
  950. if (ret < 0)
  951. goto err_slot_name;
  952. }
  953. if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
  954. host->pdata->slots[host->slot_id].get_cover_state) {
  955. ret = device_create_file(&mmc->class_dev,
  956. &dev_attr_cover_switch);
  957. if (ret < 0)
  958. goto err_cover_switch;
  959. }
  960. return 0;
  961. err_cover_switch:
  962. device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
  963. err_slot_name:
  964. mmc_remove_host(mmc);
  965. err_irq_cd:
  966. free_irq(mmc_slot(host).card_detect_irq, host);
  967. err_irq_cd_init:
  968. free_irq(host->irq, host);
  969. err_irq:
  970. clk_disable(host->fclk);
  971. clk_disable(host->iclk);
  972. clk_put(host->fclk);
  973. clk_put(host->iclk);
  974. if (host->dbclk_enabled) {
  975. clk_disable(host->dbclk);
  976. clk_put(host->dbclk);
  977. }
  978. err1:
  979. iounmap(host->base);
  980. err:
  981. dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
  982. release_mem_region(res->start, res->end - res->start + 1);
  983. if (host)
  984. mmc_free_host(mmc);
  985. return ret;
  986. }
  987. static int omap_mmc_remove(struct platform_device *pdev)
  988. {
  989. struct mmc_omap_host *host = platform_get_drvdata(pdev);
  990. struct resource *res;
  991. if (host) {
  992. mmc_remove_host(host->mmc);
  993. if (host->pdata->cleanup)
  994. host->pdata->cleanup(&pdev->dev);
  995. free_irq(host->irq, host);
  996. if (mmc_slot(host).card_detect_irq)
  997. free_irq(mmc_slot(host).card_detect_irq, host);
  998. flush_scheduled_work();
  999. clk_disable(host->fclk);
  1000. clk_disable(host->iclk);
  1001. clk_put(host->fclk);
  1002. clk_put(host->iclk);
  1003. if (host->dbclk_enabled) {
  1004. clk_disable(host->dbclk);
  1005. clk_put(host->dbclk);
  1006. }
  1007. mmc_free_host(host->mmc);
  1008. iounmap(host->base);
  1009. }
  1010. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1011. if (res)
  1012. release_mem_region(res->start, res->end - res->start + 1);
  1013. platform_set_drvdata(pdev, NULL);
  1014. return 0;
  1015. }
  1016. #ifdef CONFIG_PM
  1017. static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
  1018. {
  1019. int ret = 0;
  1020. struct mmc_omap_host *host = platform_get_drvdata(pdev);
  1021. if (host && host->suspended)
  1022. return 0;
  1023. if (host) {
  1024. ret = mmc_suspend_host(host->mmc, state);
  1025. if (ret == 0) {
  1026. host->suspended = 1;
  1027. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  1028. OMAP_HSMMC_WRITE(host->base, IE, 0);
  1029. if (host->pdata->suspend) {
  1030. ret = host->pdata->suspend(&pdev->dev,
  1031. host->slot_id);
  1032. if (ret)
  1033. dev_dbg(mmc_dev(host->mmc),
  1034. "Unable to handle MMC board"
  1035. " level suspend\n");
  1036. }
  1037. if (host->id == OMAP_MMC1_DEVID
  1038. && !(OMAP_HSMMC_READ(host->base, HCTL)
  1039. & SDVSDET)) {
  1040. OMAP_HSMMC_WRITE(host->base, HCTL,
  1041. OMAP_HSMMC_READ(host->base, HCTL)
  1042. & SDVSCLR);
  1043. OMAP_HSMMC_WRITE(host->base, HCTL,
  1044. OMAP_HSMMC_READ(host->base, HCTL)
  1045. | SDVS30);
  1046. OMAP_HSMMC_WRITE(host->base, HCTL,
  1047. OMAP_HSMMC_READ(host->base, HCTL)
  1048. | SDBP);
  1049. }
  1050. clk_disable(host->fclk);
  1051. clk_disable(host->iclk);
  1052. clk_disable(host->dbclk);
  1053. }
  1054. }
  1055. return ret;
  1056. }
  1057. /* Routine to resume the MMC device */
  1058. static int omap_mmc_resume(struct platform_device *pdev)
  1059. {
  1060. int ret = 0;
  1061. struct mmc_omap_host *host = platform_get_drvdata(pdev);
  1062. if (host && !host->suspended)
  1063. return 0;
  1064. if (host) {
  1065. ret = clk_enable(host->fclk);
  1066. if (ret)
  1067. goto clk_en_err;
  1068. ret = clk_enable(host->iclk);
  1069. if (ret) {
  1070. clk_disable(host->fclk);
  1071. clk_put(host->fclk);
  1072. goto clk_en_err;
  1073. }
  1074. if (clk_enable(host->dbclk) != 0)
  1075. dev_dbg(mmc_dev(host->mmc),
  1076. "Enabling debounce clk failed\n");
  1077. omap_hsmmc_init(host);
  1078. if (host->pdata->resume) {
  1079. ret = host->pdata->resume(&pdev->dev, host->slot_id);
  1080. if (ret)
  1081. dev_dbg(mmc_dev(host->mmc),
  1082. "Unmask interrupt failed\n");
  1083. }
  1084. /* Notify the core to resume the host */
  1085. ret = mmc_resume_host(host->mmc);
  1086. if (ret == 0)
  1087. host->suspended = 0;
  1088. }
  1089. return ret;
  1090. clk_en_err:
  1091. dev_dbg(mmc_dev(host->mmc),
  1092. "Failed to enable MMC clocks during resume\n");
  1093. return ret;
  1094. }
  1095. #else
  1096. #define omap_mmc_suspend NULL
  1097. #define omap_mmc_resume NULL
  1098. #endif
  1099. static struct platform_driver omap_mmc_driver = {
  1100. .probe = omap_mmc_probe,
  1101. .remove = omap_mmc_remove,
  1102. .suspend = omap_mmc_suspend,
  1103. .resume = omap_mmc_resume,
  1104. .driver = {
  1105. .name = DRIVER_NAME,
  1106. .owner = THIS_MODULE,
  1107. },
  1108. };
  1109. static int __init omap_mmc_init(void)
  1110. {
  1111. /* Register the MMC driver */
  1112. return platform_driver_register(&omap_mmc_driver);
  1113. }
  1114. static void __exit omap_mmc_cleanup(void)
  1115. {
  1116. /* Unregister MMC driver */
  1117. platform_driver_unregister(&omap_mmc_driver);
  1118. }
  1119. module_init(omap_mmc_init);
  1120. module_exit(omap_mmc_cleanup);
  1121. MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
  1122. MODULE_LICENSE("GPL");
  1123. MODULE_ALIAS("platform:" DRIVER_NAME);
  1124. MODULE_AUTHOR("Texas Instruments Inc");