sh_mobile_lcdcfb.c 21 KB

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  1. /*
  2. * SuperH Mobile LCDC Framebuffer
  3. *
  4. * Copyright (c) 2008 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/mm.h>
  14. #include <linux/fb.h>
  15. #include <linux/clk.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/interrupt.h>
  19. #include <video/sh_mobile_lcdc.h>
  20. #include <asm/atomic.h>
  21. #define PALETTE_NR 16
  22. struct sh_mobile_lcdc_priv;
  23. struct sh_mobile_lcdc_chan {
  24. struct sh_mobile_lcdc_priv *lcdc;
  25. unsigned long *reg_offs;
  26. unsigned long ldmt1r_value;
  27. unsigned long enabled; /* ME and SE in LDCNT2R */
  28. struct sh_mobile_lcdc_chan_cfg cfg;
  29. u32 pseudo_palette[PALETTE_NR];
  30. struct fb_info info;
  31. dma_addr_t dma_handle;
  32. struct fb_deferred_io defio;
  33. };
  34. struct sh_mobile_lcdc_priv {
  35. void __iomem *base;
  36. int irq;
  37. #ifdef CONFIG_HAVE_CLK
  38. atomic_t clk_usecnt;
  39. struct clk *dot_clk;
  40. struct clk *clk;
  41. #endif
  42. unsigned long lddckr;
  43. struct sh_mobile_lcdc_chan ch[2];
  44. };
  45. /* shared registers */
  46. #define _LDDCKR 0x410
  47. #define _LDDCKSTPR 0x414
  48. #define _LDINTR 0x468
  49. #define _LDSR 0x46c
  50. #define _LDCNT1R 0x470
  51. #define _LDCNT2R 0x474
  52. #define _LDDDSR 0x47c
  53. #define _LDDWD0R 0x800
  54. #define _LDDRDR 0x840
  55. #define _LDDWAR 0x900
  56. #define _LDDRAR 0x904
  57. /* per-channel registers */
  58. enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
  59. LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
  60. static unsigned long lcdc_offs_mainlcd[] = {
  61. [LDDCKPAT1R] = 0x400,
  62. [LDDCKPAT2R] = 0x404,
  63. [LDMT1R] = 0x418,
  64. [LDMT2R] = 0x41c,
  65. [LDMT3R] = 0x420,
  66. [LDDFR] = 0x424,
  67. [LDSM1R] = 0x428,
  68. [LDSM2R] = 0x42c,
  69. [LDSA1R] = 0x430,
  70. [LDMLSR] = 0x438,
  71. [LDHCNR] = 0x448,
  72. [LDHSYNR] = 0x44c,
  73. [LDVLNR] = 0x450,
  74. [LDVSYNR] = 0x454,
  75. [LDPMR] = 0x460,
  76. };
  77. static unsigned long lcdc_offs_sublcd[] = {
  78. [LDDCKPAT1R] = 0x408,
  79. [LDDCKPAT2R] = 0x40c,
  80. [LDMT1R] = 0x600,
  81. [LDMT2R] = 0x604,
  82. [LDMT3R] = 0x608,
  83. [LDDFR] = 0x60c,
  84. [LDSM1R] = 0x610,
  85. [LDSM2R] = 0x614,
  86. [LDSA1R] = 0x618,
  87. [LDMLSR] = 0x620,
  88. [LDHCNR] = 0x624,
  89. [LDHSYNR] = 0x628,
  90. [LDVLNR] = 0x62c,
  91. [LDVSYNR] = 0x630,
  92. [LDPMR] = 0x63c,
  93. };
  94. #define START_LCDC 0x00000001
  95. #define LCDC_RESET 0x00000100
  96. #define DISPLAY_BEU 0x00000008
  97. #define LCDC_ENABLE 0x00000001
  98. #define LDINTR_FE 0x00000400
  99. #define LDINTR_FS 0x00000004
  100. static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
  101. int reg_nr, unsigned long data)
  102. {
  103. iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
  104. }
  105. static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
  106. int reg_nr)
  107. {
  108. return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
  109. }
  110. static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
  111. unsigned long reg_offs, unsigned long data)
  112. {
  113. iowrite32(data, priv->base + reg_offs);
  114. }
  115. static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
  116. unsigned long reg_offs)
  117. {
  118. return ioread32(priv->base + reg_offs);
  119. }
  120. static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
  121. unsigned long reg_offs,
  122. unsigned long mask, unsigned long until)
  123. {
  124. while ((lcdc_read(priv, reg_offs) & mask) != until)
  125. cpu_relax();
  126. }
  127. static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
  128. {
  129. return chan->cfg.chan == LCDC_CHAN_SUBLCD;
  130. }
  131. static void lcdc_sys_write_index(void *handle, unsigned long data)
  132. {
  133. struct sh_mobile_lcdc_chan *ch = handle;
  134. lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
  135. lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
  136. lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
  137. }
  138. static void lcdc_sys_write_data(void *handle, unsigned long data)
  139. {
  140. struct sh_mobile_lcdc_chan *ch = handle;
  141. lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
  142. lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
  143. lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
  144. }
  145. static unsigned long lcdc_sys_read_data(void *handle)
  146. {
  147. struct sh_mobile_lcdc_chan *ch = handle;
  148. lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
  149. lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
  150. lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
  151. udelay(1);
  152. return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
  153. }
  154. struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
  155. lcdc_sys_write_index,
  156. lcdc_sys_write_data,
  157. lcdc_sys_read_data,
  158. };
  159. #ifdef CONFIG_HAVE_CLK
  160. static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
  161. {
  162. if (atomic_inc_and_test(&priv->clk_usecnt)) {
  163. clk_enable(priv->clk);
  164. if (priv->dot_clk)
  165. clk_enable(priv->dot_clk);
  166. }
  167. }
  168. static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
  169. {
  170. if (atomic_sub_return(1, &priv->clk_usecnt) == -1) {
  171. if (priv->dot_clk)
  172. clk_disable(priv->dot_clk);
  173. clk_disable(priv->clk);
  174. }
  175. }
  176. #else
  177. static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) {}
  178. static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) {}
  179. #endif
  180. static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
  181. struct list_head *pagelist)
  182. {
  183. struct sh_mobile_lcdc_chan *ch = info->par;
  184. /* enable clocks before accessing hardware */
  185. sh_mobile_lcdc_clk_on(ch->lcdc);
  186. /* trigger panel update */
  187. lcdc_write_chan(ch, LDSM2R, 1);
  188. }
  189. static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
  190. {
  191. struct fb_deferred_io *fbdefio = info->fbdefio;
  192. if (fbdefio)
  193. schedule_delayed_work(&info->deferred_work, fbdefio->delay);
  194. }
  195. static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
  196. {
  197. struct sh_mobile_lcdc_priv *priv = data;
  198. unsigned long tmp;
  199. /* acknowledge interrupt */
  200. tmp = lcdc_read(priv, _LDINTR);
  201. tmp &= 0xffffff00; /* mask in high 24 bits */
  202. tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */
  203. lcdc_write(priv, _LDINTR, tmp);
  204. /* disable clocks */
  205. sh_mobile_lcdc_clk_off(priv);
  206. return IRQ_HANDLED;
  207. }
  208. static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
  209. int start)
  210. {
  211. unsigned long tmp = lcdc_read(priv, _LDCNT2R);
  212. int k;
  213. /* start or stop the lcdc */
  214. if (start)
  215. lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
  216. else
  217. lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
  218. /* wait until power is applied/stopped on all channels */
  219. for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
  220. if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
  221. while (1) {
  222. tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
  223. if (start && tmp == 3)
  224. break;
  225. if (!start && tmp == 0)
  226. break;
  227. cpu_relax();
  228. }
  229. if (!start)
  230. lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
  231. }
  232. static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
  233. {
  234. struct sh_mobile_lcdc_chan *ch;
  235. struct fb_videomode *lcd_cfg;
  236. struct sh_mobile_lcdc_board_cfg *board_cfg;
  237. unsigned long tmp;
  238. int k, m;
  239. int ret = 0;
  240. /* enable clocks before accessing the hardware */
  241. for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
  242. if (priv->ch[k].enabled)
  243. sh_mobile_lcdc_clk_on(priv);
  244. /* reset */
  245. lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
  246. lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
  247. /* enable LCDC channels */
  248. tmp = lcdc_read(priv, _LDCNT2R);
  249. tmp |= priv->ch[0].enabled;
  250. tmp |= priv->ch[1].enabled;
  251. lcdc_write(priv, _LDCNT2R, tmp);
  252. /* read data from external memory, avoid using the BEU for now */
  253. lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
  254. /* stop the lcdc first */
  255. sh_mobile_lcdc_start_stop(priv, 0);
  256. /* configure clocks */
  257. tmp = priv->lddckr;
  258. for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
  259. ch = &priv->ch[k];
  260. if (!priv->ch[k].enabled)
  261. continue;
  262. m = ch->cfg.clock_divider;
  263. if (!m)
  264. continue;
  265. if (m == 1)
  266. m = 1 << 6;
  267. tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
  268. lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
  269. lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
  270. }
  271. lcdc_write(priv, _LDDCKR, tmp);
  272. /* start dotclock again */
  273. lcdc_write(priv, _LDDCKSTPR, 0);
  274. lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
  275. /* interrupts are disabled to begin with */
  276. lcdc_write(priv, _LDINTR, 0);
  277. for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
  278. ch = &priv->ch[k];
  279. lcd_cfg = &ch->cfg.lcd_cfg;
  280. if (!ch->enabled)
  281. continue;
  282. tmp = ch->ldmt1r_value;
  283. tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
  284. tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
  285. tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
  286. tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
  287. tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
  288. tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
  289. tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
  290. lcdc_write_chan(ch, LDMT1R, tmp);
  291. /* setup SYS bus */
  292. lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
  293. lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
  294. /* horizontal configuration */
  295. tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
  296. tmp += lcd_cfg->left_margin;
  297. tmp += lcd_cfg->right_margin;
  298. tmp /= 8; /* HTCN */
  299. tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
  300. lcdc_write_chan(ch, LDHCNR, tmp);
  301. tmp = lcd_cfg->xres;
  302. tmp += lcd_cfg->right_margin;
  303. tmp /= 8; /* HSYNP */
  304. tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
  305. lcdc_write_chan(ch, LDHSYNR, tmp);
  306. /* power supply */
  307. lcdc_write_chan(ch, LDPMR, 0);
  308. /* vertical configuration */
  309. tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
  310. tmp += lcd_cfg->upper_margin;
  311. tmp += lcd_cfg->lower_margin; /* VTLN */
  312. tmp |= lcd_cfg->yres << 16; /* VDLN */
  313. lcdc_write_chan(ch, LDVLNR, tmp);
  314. tmp = lcd_cfg->yres;
  315. tmp += lcd_cfg->lower_margin; /* VSYNP */
  316. tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
  317. lcdc_write_chan(ch, LDVSYNR, tmp);
  318. board_cfg = &ch->cfg.board_cfg;
  319. if (board_cfg->setup_sys)
  320. ret = board_cfg->setup_sys(board_cfg->board_data, ch,
  321. &sh_mobile_lcdc_sys_bus_ops);
  322. if (ret)
  323. return ret;
  324. }
  325. /* word and long word swap */
  326. lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
  327. for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
  328. ch = &priv->ch[k];
  329. if (!priv->ch[k].enabled)
  330. continue;
  331. /* set bpp format in PKF[4:0] */
  332. tmp = lcdc_read_chan(ch, LDDFR);
  333. tmp &= ~(0x0001001f);
  334. tmp |= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
  335. lcdc_write_chan(ch, LDDFR, tmp);
  336. /* point out our frame buffer */
  337. lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);
  338. /* set line size */
  339. lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
  340. /* setup deferred io if SYS bus */
  341. tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
  342. if (ch->ldmt1r_value & (1 << 12) && tmp) {
  343. ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
  344. ch->defio.delay = msecs_to_jiffies(tmp);
  345. ch->info.fbdefio = &ch->defio;
  346. fb_deferred_io_init(&ch->info);
  347. /* one-shot mode */
  348. lcdc_write_chan(ch, LDSM1R, 1);
  349. /* enable "Frame End Interrupt Enable" bit */
  350. lcdc_write(priv, _LDINTR, LDINTR_FE);
  351. } else {
  352. /* continuous read mode */
  353. lcdc_write_chan(ch, LDSM1R, 0);
  354. }
  355. }
  356. /* display output */
  357. lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
  358. /* start the lcdc */
  359. sh_mobile_lcdc_start_stop(priv, 1);
  360. /* tell the board code to enable the panel */
  361. for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
  362. ch = &priv->ch[k];
  363. board_cfg = &ch->cfg.board_cfg;
  364. if (board_cfg->display_on)
  365. board_cfg->display_on(board_cfg->board_data);
  366. }
  367. return 0;
  368. }
  369. static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
  370. {
  371. struct sh_mobile_lcdc_chan *ch;
  372. struct sh_mobile_lcdc_board_cfg *board_cfg;
  373. int k;
  374. /* tell the board code to disable the panel */
  375. for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
  376. ch = &priv->ch[k];
  377. board_cfg = &ch->cfg.board_cfg;
  378. if (board_cfg->display_off)
  379. board_cfg->display_off(board_cfg->board_data);
  380. /* cleanup deferred io if enabled */
  381. if (ch->info.fbdefio) {
  382. fb_deferred_io_cleanup(&ch->info);
  383. ch->info.fbdefio = NULL;
  384. }
  385. }
  386. /* stop the lcdc */
  387. sh_mobile_lcdc_start_stop(priv, 0);
  388. /* stop clocks */
  389. for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
  390. if (priv->ch[k].enabled)
  391. sh_mobile_lcdc_clk_off(priv);
  392. }
  393. static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
  394. {
  395. int ifm, miftyp;
  396. switch (ch->cfg.interface_type) {
  397. case RGB8: ifm = 0; miftyp = 0; break;
  398. case RGB9: ifm = 0; miftyp = 4; break;
  399. case RGB12A: ifm = 0; miftyp = 5; break;
  400. case RGB12B: ifm = 0; miftyp = 6; break;
  401. case RGB16: ifm = 0; miftyp = 7; break;
  402. case RGB18: ifm = 0; miftyp = 10; break;
  403. case RGB24: ifm = 0; miftyp = 11; break;
  404. case SYS8A: ifm = 1; miftyp = 0; break;
  405. case SYS8B: ifm = 1; miftyp = 1; break;
  406. case SYS8C: ifm = 1; miftyp = 2; break;
  407. case SYS8D: ifm = 1; miftyp = 3; break;
  408. case SYS9: ifm = 1; miftyp = 4; break;
  409. case SYS12: ifm = 1; miftyp = 5; break;
  410. case SYS16A: ifm = 1; miftyp = 7; break;
  411. case SYS16B: ifm = 1; miftyp = 8; break;
  412. case SYS16C: ifm = 1; miftyp = 9; break;
  413. case SYS18: ifm = 1; miftyp = 10; break;
  414. case SYS24: ifm = 1; miftyp = 11; break;
  415. default: goto bad;
  416. }
  417. /* SUBLCD only supports SYS interface */
  418. if (lcdc_chan_is_sublcd(ch)) {
  419. if (ifm == 0)
  420. goto bad;
  421. else
  422. ifm = 0;
  423. }
  424. ch->ldmt1r_value = (ifm << 12) | miftyp;
  425. return 0;
  426. bad:
  427. return -EINVAL;
  428. }
  429. static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
  430. int clock_source,
  431. struct sh_mobile_lcdc_priv *priv)
  432. {
  433. #ifdef CONFIG_HAVE_CLK
  434. char clk_name[8];
  435. #endif
  436. char *str;
  437. int icksel;
  438. switch (clock_source) {
  439. case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
  440. case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
  441. case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
  442. default:
  443. return -EINVAL;
  444. }
  445. priv->lddckr = icksel << 16;
  446. #ifdef CONFIG_HAVE_CLK
  447. atomic_set(&priv->clk_usecnt, -1);
  448. snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
  449. priv->clk = clk_get(&pdev->dev, clk_name);
  450. if (IS_ERR(priv->clk)) {
  451. dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
  452. return PTR_ERR(priv->clk);
  453. }
  454. if (str) {
  455. priv->dot_clk = clk_get(&pdev->dev, str);
  456. if (IS_ERR(priv->dot_clk)) {
  457. dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
  458. clk_put(priv->clk);
  459. return PTR_ERR(priv->dot_clk);
  460. }
  461. }
  462. #endif
  463. return 0;
  464. }
  465. static int sh_mobile_lcdc_setcolreg(u_int regno,
  466. u_int red, u_int green, u_int blue,
  467. u_int transp, struct fb_info *info)
  468. {
  469. u32 *palette = info->pseudo_palette;
  470. if (regno >= PALETTE_NR)
  471. return -EINVAL;
  472. /* only FB_VISUAL_TRUECOLOR supported */
  473. red >>= 16 - info->var.red.length;
  474. green >>= 16 - info->var.green.length;
  475. blue >>= 16 - info->var.blue.length;
  476. transp >>= 16 - info->var.transp.length;
  477. palette[regno] = (red << info->var.red.offset) |
  478. (green << info->var.green.offset) |
  479. (blue << info->var.blue.offset) |
  480. (transp << info->var.transp.offset);
  481. return 0;
  482. }
  483. static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
  484. .id = "SH Mobile LCDC",
  485. .type = FB_TYPE_PACKED_PIXELS,
  486. .visual = FB_VISUAL_TRUECOLOR,
  487. .accel = FB_ACCEL_NONE,
  488. };
  489. static void sh_mobile_lcdc_fillrect(struct fb_info *info,
  490. const struct fb_fillrect *rect)
  491. {
  492. sys_fillrect(info, rect);
  493. sh_mobile_lcdc_deferred_io_touch(info);
  494. }
  495. static void sh_mobile_lcdc_copyarea(struct fb_info *info,
  496. const struct fb_copyarea *area)
  497. {
  498. sys_copyarea(info, area);
  499. sh_mobile_lcdc_deferred_io_touch(info);
  500. }
  501. static void sh_mobile_lcdc_imageblit(struct fb_info *info,
  502. const struct fb_image *image)
  503. {
  504. sys_imageblit(info, image);
  505. sh_mobile_lcdc_deferred_io_touch(info);
  506. }
  507. static struct fb_ops sh_mobile_lcdc_ops = {
  508. .fb_setcolreg = sh_mobile_lcdc_setcolreg,
  509. .fb_read = fb_sys_read,
  510. .fb_write = fb_sys_write,
  511. .fb_fillrect = sh_mobile_lcdc_fillrect,
  512. .fb_copyarea = sh_mobile_lcdc_copyarea,
  513. .fb_imageblit = sh_mobile_lcdc_imageblit,
  514. };
  515. static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
  516. {
  517. switch (bpp) {
  518. case 16: /* PKF[4:0] = 00011 - RGB 565 */
  519. var->red.offset = 11;
  520. var->red.length = 5;
  521. var->green.offset = 5;
  522. var->green.length = 6;
  523. var->blue.offset = 0;
  524. var->blue.length = 5;
  525. var->transp.offset = 0;
  526. var->transp.length = 0;
  527. break;
  528. case 32: /* PKF[4:0] = 00000 - RGB 888
  529. * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
  530. * this may be because LDDDSR has word swap enabled..
  531. */
  532. var->red.offset = 0;
  533. var->red.length = 8;
  534. var->green.offset = 24;
  535. var->green.length = 8;
  536. var->blue.offset = 16;
  537. var->blue.length = 8;
  538. var->transp.offset = 0;
  539. var->transp.length = 0;
  540. break;
  541. default:
  542. return -EINVAL;
  543. }
  544. var->bits_per_pixel = bpp;
  545. var->red.msb_right = 0;
  546. var->green.msb_right = 0;
  547. var->blue.msb_right = 0;
  548. var->transp.msb_right = 0;
  549. return 0;
  550. }
  551. static int sh_mobile_lcdc_remove(struct platform_device *pdev);
  552. static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
  553. {
  554. struct fb_info *info;
  555. struct sh_mobile_lcdc_priv *priv;
  556. struct sh_mobile_lcdc_info *pdata;
  557. struct sh_mobile_lcdc_chan_cfg *cfg;
  558. struct resource *res;
  559. int error;
  560. void *buf;
  561. int i, j;
  562. if (!pdev->dev.platform_data) {
  563. dev_err(&pdev->dev, "no platform data defined\n");
  564. error = -EINVAL;
  565. goto err0;
  566. }
  567. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  568. i = platform_get_irq(pdev, 0);
  569. if (!res || i < 0) {
  570. dev_err(&pdev->dev, "cannot get platform resources\n");
  571. error = -ENOENT;
  572. goto err0;
  573. }
  574. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  575. if (!priv) {
  576. dev_err(&pdev->dev, "cannot allocate device data\n");
  577. error = -ENOMEM;
  578. goto err0;
  579. }
  580. error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
  581. pdev->dev.bus_id, priv);
  582. if (error) {
  583. dev_err(&pdev->dev, "unable to request irq\n");
  584. goto err1;
  585. }
  586. priv->irq = i;
  587. platform_set_drvdata(pdev, priv);
  588. pdata = pdev->dev.platform_data;
  589. j = 0;
  590. for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
  591. priv->ch[j].lcdc = priv;
  592. memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
  593. error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
  594. if (error) {
  595. dev_err(&pdev->dev, "unsupported interface type\n");
  596. goto err1;
  597. }
  598. switch (pdata->ch[i].chan) {
  599. case LCDC_CHAN_MAINLCD:
  600. priv->ch[j].enabled = 1 << 1;
  601. priv->ch[j].reg_offs = lcdc_offs_mainlcd;
  602. j++;
  603. break;
  604. case LCDC_CHAN_SUBLCD:
  605. priv->ch[j].enabled = 1 << 2;
  606. priv->ch[j].reg_offs = lcdc_offs_sublcd;
  607. j++;
  608. break;
  609. }
  610. }
  611. if (!j) {
  612. dev_err(&pdev->dev, "no channels defined\n");
  613. error = -EINVAL;
  614. goto err1;
  615. }
  616. error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
  617. if (error) {
  618. dev_err(&pdev->dev, "unable to setup clocks\n");
  619. goto err1;
  620. }
  621. priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
  622. for (i = 0; i < j; i++) {
  623. info = &priv->ch[i].info;
  624. cfg = &priv->ch[i].cfg;
  625. info->fbops = &sh_mobile_lcdc_ops;
  626. info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
  627. info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
  628. info->var.width = cfg->lcd_size_cfg.width;
  629. info->var.height = cfg->lcd_size_cfg.height;
  630. info->var.activate = FB_ACTIVATE_NOW;
  631. error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
  632. if (error)
  633. break;
  634. info->fix = sh_mobile_lcdc_fix;
  635. info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
  636. info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
  637. buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
  638. &priv->ch[i].dma_handle, GFP_KERNEL);
  639. if (!buf) {
  640. dev_err(&pdev->dev, "unable to allocate buffer\n");
  641. error = -ENOMEM;
  642. break;
  643. }
  644. info->pseudo_palette = &priv->ch[i].pseudo_palette;
  645. info->flags = FBINFO_FLAG_DEFAULT;
  646. error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
  647. if (error < 0) {
  648. dev_err(&pdev->dev, "unable to allocate cmap\n");
  649. dma_free_coherent(&pdev->dev, info->fix.smem_len,
  650. buf, priv->ch[i].dma_handle);
  651. break;
  652. }
  653. memset(buf, 0, info->fix.smem_len);
  654. info->fix.smem_start = priv->ch[i].dma_handle;
  655. info->screen_base = buf;
  656. info->device = &pdev->dev;
  657. info->par = &priv->ch[i];
  658. }
  659. if (error)
  660. goto err1;
  661. error = sh_mobile_lcdc_start(priv);
  662. if (error) {
  663. dev_err(&pdev->dev, "unable to start hardware\n");
  664. goto err1;
  665. }
  666. for (i = 0; i < j; i++) {
  667. error = register_framebuffer(&priv->ch[i].info);
  668. if (error < 0)
  669. goto err1;
  670. }
  671. for (i = 0; i < j; i++) {
  672. info = &priv->ch[i].info;
  673. dev_info(info->dev,
  674. "registered %s/%s as %dx%d %dbpp.\n",
  675. pdev->name,
  676. (priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
  677. "mainlcd" : "sublcd",
  678. (int) priv->ch[i].cfg.lcd_cfg.xres,
  679. (int) priv->ch[i].cfg.lcd_cfg.yres,
  680. priv->ch[i].cfg.bpp);
  681. /* deferred io mode: disable clock to save power */
  682. if (info->fbdefio)
  683. sh_mobile_lcdc_clk_off(priv);
  684. }
  685. return 0;
  686. err1:
  687. sh_mobile_lcdc_remove(pdev);
  688. err0:
  689. return error;
  690. }
  691. static int sh_mobile_lcdc_remove(struct platform_device *pdev)
  692. {
  693. struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
  694. struct fb_info *info;
  695. int i;
  696. for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
  697. if (priv->ch[i].info.dev)
  698. unregister_framebuffer(&priv->ch[i].info);
  699. sh_mobile_lcdc_stop(priv);
  700. for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
  701. info = &priv->ch[i].info;
  702. if (!info->device)
  703. continue;
  704. dma_free_coherent(&pdev->dev, info->fix.smem_len,
  705. info->screen_base, priv->ch[i].dma_handle);
  706. fb_dealloc_cmap(&info->cmap);
  707. }
  708. #ifdef CONFIG_HAVE_CLK
  709. if (priv->dot_clk)
  710. clk_put(priv->dot_clk);
  711. clk_put(priv->clk);
  712. #endif
  713. if (priv->base)
  714. iounmap(priv->base);
  715. if (priv->irq)
  716. free_irq(priv->irq, priv);
  717. kfree(priv);
  718. return 0;
  719. }
  720. static struct platform_driver sh_mobile_lcdc_driver = {
  721. .driver = {
  722. .name = "sh_mobile_lcdc_fb",
  723. .owner = THIS_MODULE,
  724. },
  725. .probe = sh_mobile_lcdc_probe,
  726. .remove = sh_mobile_lcdc_remove,
  727. };
  728. static int __init sh_mobile_lcdc_init(void)
  729. {
  730. return platform_driver_register(&sh_mobile_lcdc_driver);
  731. }
  732. static void __exit sh_mobile_lcdc_exit(void)
  733. {
  734. platform_driver_unregister(&sh_mobile_lcdc_driver);
  735. }
  736. module_init(sh_mobile_lcdc_init);
  737. module_exit(sh_mobile_lcdc_exit);
  738. MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
  739. MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
  740. MODULE_LICENSE("GPL v2");