libata-sff.c 75 KB

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  1. /*
  2. * libata-sff.c - helper library for PCI IDE BMDMA
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
  9. * Copyright 2003-2006 Jeff Garzik
  10. *
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2, or (at your option)
  15. * any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; see the file COPYING. If not, write to
  24. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  25. *
  26. *
  27. * libata documentation is available via 'make {ps|pdf}docs',
  28. * as Documentation/DocBook/libata.*
  29. *
  30. * Hardware documentation available from http://www.t13.org/ and
  31. * http://www.sata-io.org/
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/pci.h>
  36. #include <linux/libata.h>
  37. #include <linux/highmem.h>
  38. #include "libata.h"
  39. const struct ata_port_operations ata_sff_port_ops = {
  40. .inherits = &ata_base_port_ops,
  41. .qc_prep = ata_sff_qc_prep,
  42. .qc_issue = ata_sff_qc_issue,
  43. .qc_fill_rtf = ata_sff_qc_fill_rtf,
  44. .freeze = ata_sff_freeze,
  45. .thaw = ata_sff_thaw,
  46. .prereset = ata_sff_prereset,
  47. .softreset = ata_sff_softreset,
  48. .hardreset = sata_sff_hardreset,
  49. .postreset = ata_sff_postreset,
  50. .error_handler = ata_sff_error_handler,
  51. .post_internal_cmd = ata_sff_post_internal_cmd,
  52. .sff_dev_select = ata_sff_dev_select,
  53. .sff_check_status = ata_sff_check_status,
  54. .sff_tf_load = ata_sff_tf_load,
  55. .sff_tf_read = ata_sff_tf_read,
  56. .sff_exec_command = ata_sff_exec_command,
  57. .sff_data_xfer = ata_sff_data_xfer,
  58. .sff_irq_on = ata_sff_irq_on,
  59. .sff_irq_clear = ata_sff_irq_clear,
  60. .port_start = ata_sff_port_start,
  61. };
  62. EXPORT_SYMBOL_GPL(ata_sff_port_ops);
  63. const struct ata_port_operations ata_bmdma_port_ops = {
  64. .inherits = &ata_sff_port_ops,
  65. .mode_filter = ata_bmdma_mode_filter,
  66. .bmdma_setup = ata_bmdma_setup,
  67. .bmdma_start = ata_bmdma_start,
  68. .bmdma_stop = ata_bmdma_stop,
  69. .bmdma_status = ata_bmdma_status,
  70. };
  71. EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
  72. const struct ata_port_operations ata_bmdma32_port_ops = {
  73. .inherits = &ata_bmdma_port_ops,
  74. .sff_data_xfer = ata_sff_data_xfer32,
  75. };
  76. EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
  77. /**
  78. * ata_fill_sg - Fill PCI IDE PRD table
  79. * @qc: Metadata associated with taskfile to be transferred
  80. *
  81. * Fill PCI IDE PRD (scatter-gather) table with segments
  82. * associated with the current disk command.
  83. *
  84. * LOCKING:
  85. * spin_lock_irqsave(host lock)
  86. *
  87. */
  88. static void ata_fill_sg(struct ata_queued_cmd *qc)
  89. {
  90. struct ata_port *ap = qc->ap;
  91. struct scatterlist *sg;
  92. unsigned int si, pi;
  93. pi = 0;
  94. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  95. u32 addr, offset;
  96. u32 sg_len, len;
  97. /* determine if physical DMA addr spans 64K boundary.
  98. * Note h/w doesn't support 64-bit, so we unconditionally
  99. * truncate dma_addr_t to u32.
  100. */
  101. addr = (u32) sg_dma_address(sg);
  102. sg_len = sg_dma_len(sg);
  103. while (sg_len) {
  104. offset = addr & 0xffff;
  105. len = sg_len;
  106. if ((offset + sg_len) > 0x10000)
  107. len = 0x10000 - offset;
  108. ap->prd[pi].addr = cpu_to_le32(addr);
  109. ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
  110. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
  111. pi++;
  112. sg_len -= len;
  113. addr += len;
  114. }
  115. }
  116. ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
  117. }
  118. /**
  119. * ata_fill_sg_dumb - Fill PCI IDE PRD table
  120. * @qc: Metadata associated with taskfile to be transferred
  121. *
  122. * Fill PCI IDE PRD (scatter-gather) table with segments
  123. * associated with the current disk command. Perform the fill
  124. * so that we avoid writing any length 64K records for
  125. * controllers that don't follow the spec.
  126. *
  127. * LOCKING:
  128. * spin_lock_irqsave(host lock)
  129. *
  130. */
  131. static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
  132. {
  133. struct ata_port *ap = qc->ap;
  134. struct scatterlist *sg;
  135. unsigned int si, pi;
  136. pi = 0;
  137. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  138. u32 addr, offset;
  139. u32 sg_len, len, blen;
  140. /* determine if physical DMA addr spans 64K boundary.
  141. * Note h/w doesn't support 64-bit, so we unconditionally
  142. * truncate dma_addr_t to u32.
  143. */
  144. addr = (u32) sg_dma_address(sg);
  145. sg_len = sg_dma_len(sg);
  146. while (sg_len) {
  147. offset = addr & 0xffff;
  148. len = sg_len;
  149. if ((offset + sg_len) > 0x10000)
  150. len = 0x10000 - offset;
  151. blen = len & 0xffff;
  152. ap->prd[pi].addr = cpu_to_le32(addr);
  153. if (blen == 0) {
  154. /* Some PATA chipsets like the CS5530 can't
  155. cope with 0x0000 meaning 64K as the spec
  156. says */
  157. ap->prd[pi].flags_len = cpu_to_le32(0x8000);
  158. blen = 0x8000;
  159. ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
  160. }
  161. ap->prd[pi].flags_len = cpu_to_le32(blen);
  162. VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
  163. pi++;
  164. sg_len -= len;
  165. addr += len;
  166. }
  167. }
  168. ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
  169. }
  170. /**
  171. * ata_sff_qc_prep - Prepare taskfile for submission
  172. * @qc: Metadata associated with taskfile to be prepared
  173. *
  174. * Prepare ATA taskfile for submission.
  175. *
  176. * LOCKING:
  177. * spin_lock_irqsave(host lock)
  178. */
  179. void ata_sff_qc_prep(struct ata_queued_cmd *qc)
  180. {
  181. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  182. return;
  183. ata_fill_sg(qc);
  184. }
  185. EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
  186. /**
  187. * ata_sff_dumb_qc_prep - Prepare taskfile for submission
  188. * @qc: Metadata associated with taskfile to be prepared
  189. *
  190. * Prepare ATA taskfile for submission.
  191. *
  192. * LOCKING:
  193. * spin_lock_irqsave(host lock)
  194. */
  195. void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
  196. {
  197. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  198. return;
  199. ata_fill_sg_dumb(qc);
  200. }
  201. EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
  202. /**
  203. * ata_sff_check_status - Read device status reg & clear interrupt
  204. * @ap: port where the device is
  205. *
  206. * Reads ATA taskfile status register for currently-selected device
  207. * and return its value. This also clears pending interrupts
  208. * from this device
  209. *
  210. * LOCKING:
  211. * Inherited from caller.
  212. */
  213. u8 ata_sff_check_status(struct ata_port *ap)
  214. {
  215. return ioread8(ap->ioaddr.status_addr);
  216. }
  217. EXPORT_SYMBOL_GPL(ata_sff_check_status);
  218. /**
  219. * ata_sff_altstatus - Read device alternate status reg
  220. * @ap: port where the device is
  221. *
  222. * Reads ATA taskfile alternate status register for
  223. * currently-selected device and return its value.
  224. *
  225. * Note: may NOT be used as the check_altstatus() entry in
  226. * ata_port_operations.
  227. *
  228. * LOCKING:
  229. * Inherited from caller.
  230. */
  231. static u8 ata_sff_altstatus(struct ata_port *ap)
  232. {
  233. if (ap->ops->sff_check_altstatus)
  234. return ap->ops->sff_check_altstatus(ap);
  235. return ioread8(ap->ioaddr.altstatus_addr);
  236. }
  237. /**
  238. * ata_sff_irq_status - Check if the device is busy
  239. * @ap: port where the device is
  240. *
  241. * Determine if the port is currently busy. Uses altstatus
  242. * if available in order to avoid clearing shared IRQ status
  243. * when finding an IRQ source. Non ctl capable devices don't
  244. * share interrupt lines fortunately for us.
  245. *
  246. * LOCKING:
  247. * Inherited from caller.
  248. */
  249. static u8 ata_sff_irq_status(struct ata_port *ap)
  250. {
  251. u8 status;
  252. if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
  253. status = ata_sff_altstatus(ap);
  254. /* Not us: We are busy */
  255. if (status & ATA_BUSY)
  256. return status;
  257. }
  258. /* Clear INTRQ latch */
  259. status = ap->ops->sff_check_status(ap);
  260. return status;
  261. }
  262. /**
  263. * ata_sff_sync - Flush writes
  264. * @ap: Port to wait for.
  265. *
  266. * CAUTION:
  267. * If we have an mmio device with no ctl and no altstatus
  268. * method this will fail. No such devices are known to exist.
  269. *
  270. * LOCKING:
  271. * Inherited from caller.
  272. */
  273. static void ata_sff_sync(struct ata_port *ap)
  274. {
  275. if (ap->ops->sff_check_altstatus)
  276. ap->ops->sff_check_altstatus(ap);
  277. else if (ap->ioaddr.altstatus_addr)
  278. ioread8(ap->ioaddr.altstatus_addr);
  279. }
  280. /**
  281. * ata_sff_pause - Flush writes and wait 400nS
  282. * @ap: Port to pause for.
  283. *
  284. * CAUTION:
  285. * If we have an mmio device with no ctl and no altstatus
  286. * method this will fail. No such devices are known to exist.
  287. *
  288. * LOCKING:
  289. * Inherited from caller.
  290. */
  291. void ata_sff_pause(struct ata_port *ap)
  292. {
  293. ata_sff_sync(ap);
  294. ndelay(400);
  295. }
  296. EXPORT_SYMBOL_GPL(ata_sff_pause);
  297. /**
  298. * ata_sff_dma_pause - Pause before commencing DMA
  299. * @ap: Port to pause for.
  300. *
  301. * Perform I/O fencing and ensure sufficient cycle delays occur
  302. * for the HDMA1:0 transition
  303. */
  304. void ata_sff_dma_pause(struct ata_port *ap)
  305. {
  306. if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
  307. /* An altstatus read will cause the needed delay without
  308. messing up the IRQ status */
  309. ata_sff_altstatus(ap);
  310. return;
  311. }
  312. /* There are no DMA controllers without ctl. BUG here to ensure
  313. we never violate the HDMA1:0 transition timing and risk
  314. corruption. */
  315. BUG();
  316. }
  317. EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
  318. /**
  319. * ata_sff_busy_sleep - sleep until BSY clears, or timeout
  320. * @ap: port containing status register to be polled
  321. * @tmout_pat: impatience timeout in msecs
  322. * @tmout: overall timeout in msecs
  323. *
  324. * Sleep until ATA Status register bit BSY clears,
  325. * or a timeout occurs.
  326. *
  327. * LOCKING:
  328. * Kernel thread context (may sleep).
  329. *
  330. * RETURNS:
  331. * 0 on success, -errno otherwise.
  332. */
  333. int ata_sff_busy_sleep(struct ata_port *ap,
  334. unsigned long tmout_pat, unsigned long tmout)
  335. {
  336. unsigned long timer_start, timeout;
  337. u8 status;
  338. status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
  339. timer_start = jiffies;
  340. timeout = ata_deadline(timer_start, tmout_pat);
  341. while (status != 0xff && (status & ATA_BUSY) &&
  342. time_before(jiffies, timeout)) {
  343. msleep(50);
  344. status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
  345. }
  346. if (status != 0xff && (status & ATA_BUSY))
  347. ata_port_printk(ap, KERN_WARNING,
  348. "port is slow to respond, please be patient "
  349. "(Status 0x%x)\n", status);
  350. timeout = ata_deadline(timer_start, tmout);
  351. while (status != 0xff && (status & ATA_BUSY) &&
  352. time_before(jiffies, timeout)) {
  353. msleep(50);
  354. status = ap->ops->sff_check_status(ap);
  355. }
  356. if (status == 0xff)
  357. return -ENODEV;
  358. if (status & ATA_BUSY) {
  359. ata_port_printk(ap, KERN_ERR, "port failed to respond "
  360. "(%lu secs, Status 0x%x)\n",
  361. DIV_ROUND_UP(tmout, 1000), status);
  362. return -EBUSY;
  363. }
  364. return 0;
  365. }
  366. EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
  367. static int ata_sff_check_ready(struct ata_link *link)
  368. {
  369. u8 status = link->ap->ops->sff_check_status(link->ap);
  370. return ata_check_ready(status);
  371. }
  372. /**
  373. * ata_sff_wait_ready - sleep until BSY clears, or timeout
  374. * @link: SFF link to wait ready status for
  375. * @deadline: deadline jiffies for the operation
  376. *
  377. * Sleep until ATA Status register bit BSY clears, or timeout
  378. * occurs.
  379. *
  380. * LOCKING:
  381. * Kernel thread context (may sleep).
  382. *
  383. * RETURNS:
  384. * 0 on success, -errno otherwise.
  385. */
  386. int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
  387. {
  388. return ata_wait_ready(link, deadline, ata_sff_check_ready);
  389. }
  390. EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
  391. /**
  392. * ata_sff_dev_select - Select device 0/1 on ATA bus
  393. * @ap: ATA channel to manipulate
  394. * @device: ATA device (numbered from zero) to select
  395. *
  396. * Use the method defined in the ATA specification to
  397. * make either device 0, or device 1, active on the
  398. * ATA channel. Works with both PIO and MMIO.
  399. *
  400. * May be used as the dev_select() entry in ata_port_operations.
  401. *
  402. * LOCKING:
  403. * caller.
  404. */
  405. void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
  406. {
  407. u8 tmp;
  408. if (device == 0)
  409. tmp = ATA_DEVICE_OBS;
  410. else
  411. tmp = ATA_DEVICE_OBS | ATA_DEV1;
  412. iowrite8(tmp, ap->ioaddr.device_addr);
  413. ata_sff_pause(ap); /* needed; also flushes, for mmio */
  414. }
  415. EXPORT_SYMBOL_GPL(ata_sff_dev_select);
  416. /**
  417. * ata_dev_select - Select device 0/1 on ATA bus
  418. * @ap: ATA channel to manipulate
  419. * @device: ATA device (numbered from zero) to select
  420. * @wait: non-zero to wait for Status register BSY bit to clear
  421. * @can_sleep: non-zero if context allows sleeping
  422. *
  423. * Use the method defined in the ATA specification to
  424. * make either device 0, or device 1, active on the
  425. * ATA channel.
  426. *
  427. * This is a high-level version of ata_sff_dev_select(), which
  428. * additionally provides the services of inserting the proper
  429. * pauses and status polling, where needed.
  430. *
  431. * LOCKING:
  432. * caller.
  433. */
  434. void ata_dev_select(struct ata_port *ap, unsigned int device,
  435. unsigned int wait, unsigned int can_sleep)
  436. {
  437. if (ata_msg_probe(ap))
  438. ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
  439. "device %u, wait %u\n", device, wait);
  440. if (wait)
  441. ata_wait_idle(ap);
  442. ap->ops->sff_dev_select(ap, device);
  443. if (wait) {
  444. if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
  445. msleep(150);
  446. ata_wait_idle(ap);
  447. }
  448. }
  449. /**
  450. * ata_sff_irq_on - Enable interrupts on a port.
  451. * @ap: Port on which interrupts are enabled.
  452. *
  453. * Enable interrupts on a legacy IDE device using MMIO or PIO,
  454. * wait for idle, clear any pending interrupts.
  455. *
  456. * LOCKING:
  457. * Inherited from caller.
  458. */
  459. u8 ata_sff_irq_on(struct ata_port *ap)
  460. {
  461. struct ata_ioports *ioaddr = &ap->ioaddr;
  462. u8 tmp;
  463. ap->ctl &= ~ATA_NIEN;
  464. ap->last_ctl = ap->ctl;
  465. if (ioaddr->ctl_addr)
  466. iowrite8(ap->ctl, ioaddr->ctl_addr);
  467. tmp = ata_wait_idle(ap);
  468. ap->ops->sff_irq_clear(ap);
  469. return tmp;
  470. }
  471. EXPORT_SYMBOL_GPL(ata_sff_irq_on);
  472. /**
  473. * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
  474. * @ap: Port associated with this ATA transaction.
  475. *
  476. * Clear interrupt and error flags in DMA status register.
  477. *
  478. * May be used as the irq_clear() entry in ata_port_operations.
  479. *
  480. * LOCKING:
  481. * spin_lock_irqsave(host lock)
  482. */
  483. void ata_sff_irq_clear(struct ata_port *ap)
  484. {
  485. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  486. if (!mmio)
  487. return;
  488. iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
  489. }
  490. EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
  491. /**
  492. * ata_sff_tf_load - send taskfile registers to host controller
  493. * @ap: Port to which output is sent
  494. * @tf: ATA taskfile register set
  495. *
  496. * Outputs ATA taskfile to standard ATA host controller.
  497. *
  498. * LOCKING:
  499. * Inherited from caller.
  500. */
  501. void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  502. {
  503. struct ata_ioports *ioaddr = &ap->ioaddr;
  504. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  505. if (tf->ctl != ap->last_ctl) {
  506. if (ioaddr->ctl_addr)
  507. iowrite8(tf->ctl, ioaddr->ctl_addr);
  508. ap->last_ctl = tf->ctl;
  509. ata_wait_idle(ap);
  510. }
  511. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  512. WARN_ON_ONCE(!ioaddr->ctl_addr);
  513. iowrite8(tf->hob_feature, ioaddr->feature_addr);
  514. iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
  515. iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
  516. iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
  517. iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
  518. VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
  519. tf->hob_feature,
  520. tf->hob_nsect,
  521. tf->hob_lbal,
  522. tf->hob_lbam,
  523. tf->hob_lbah);
  524. }
  525. if (is_addr) {
  526. iowrite8(tf->feature, ioaddr->feature_addr);
  527. iowrite8(tf->nsect, ioaddr->nsect_addr);
  528. iowrite8(tf->lbal, ioaddr->lbal_addr);
  529. iowrite8(tf->lbam, ioaddr->lbam_addr);
  530. iowrite8(tf->lbah, ioaddr->lbah_addr);
  531. VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
  532. tf->feature,
  533. tf->nsect,
  534. tf->lbal,
  535. tf->lbam,
  536. tf->lbah);
  537. }
  538. if (tf->flags & ATA_TFLAG_DEVICE) {
  539. iowrite8(tf->device, ioaddr->device_addr);
  540. VPRINTK("device 0x%X\n", tf->device);
  541. }
  542. ata_wait_idle(ap);
  543. }
  544. EXPORT_SYMBOL_GPL(ata_sff_tf_load);
  545. /**
  546. * ata_sff_tf_read - input device's ATA taskfile shadow registers
  547. * @ap: Port from which input is read
  548. * @tf: ATA taskfile register set for storing input
  549. *
  550. * Reads ATA taskfile registers for currently-selected device
  551. * into @tf. Assumes the device has a fully SFF compliant task file
  552. * layout and behaviour. If you device does not (eg has a different
  553. * status method) then you will need to provide a replacement tf_read
  554. *
  555. * LOCKING:
  556. * Inherited from caller.
  557. */
  558. void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  559. {
  560. struct ata_ioports *ioaddr = &ap->ioaddr;
  561. tf->command = ata_sff_check_status(ap);
  562. tf->feature = ioread8(ioaddr->error_addr);
  563. tf->nsect = ioread8(ioaddr->nsect_addr);
  564. tf->lbal = ioread8(ioaddr->lbal_addr);
  565. tf->lbam = ioread8(ioaddr->lbam_addr);
  566. tf->lbah = ioread8(ioaddr->lbah_addr);
  567. tf->device = ioread8(ioaddr->device_addr);
  568. if (tf->flags & ATA_TFLAG_LBA48) {
  569. if (likely(ioaddr->ctl_addr)) {
  570. iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  571. tf->hob_feature = ioread8(ioaddr->error_addr);
  572. tf->hob_nsect = ioread8(ioaddr->nsect_addr);
  573. tf->hob_lbal = ioread8(ioaddr->lbal_addr);
  574. tf->hob_lbam = ioread8(ioaddr->lbam_addr);
  575. tf->hob_lbah = ioread8(ioaddr->lbah_addr);
  576. iowrite8(tf->ctl, ioaddr->ctl_addr);
  577. ap->last_ctl = tf->ctl;
  578. } else
  579. WARN_ON_ONCE(1);
  580. }
  581. }
  582. EXPORT_SYMBOL_GPL(ata_sff_tf_read);
  583. /**
  584. * ata_sff_exec_command - issue ATA command to host controller
  585. * @ap: port to which command is being issued
  586. * @tf: ATA taskfile register set
  587. *
  588. * Issues ATA command, with proper synchronization with interrupt
  589. * handler / other threads.
  590. *
  591. * LOCKING:
  592. * spin_lock_irqsave(host lock)
  593. */
  594. void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
  595. {
  596. DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
  597. iowrite8(tf->command, ap->ioaddr.command_addr);
  598. ata_sff_pause(ap);
  599. }
  600. EXPORT_SYMBOL_GPL(ata_sff_exec_command);
  601. /**
  602. * ata_tf_to_host - issue ATA taskfile to host controller
  603. * @ap: port to which command is being issued
  604. * @tf: ATA taskfile register set
  605. *
  606. * Issues ATA taskfile register set to ATA host controller,
  607. * with proper synchronization with interrupt handler and
  608. * other threads.
  609. *
  610. * LOCKING:
  611. * spin_lock_irqsave(host lock)
  612. */
  613. static inline void ata_tf_to_host(struct ata_port *ap,
  614. const struct ata_taskfile *tf)
  615. {
  616. ap->ops->sff_tf_load(ap, tf);
  617. ap->ops->sff_exec_command(ap, tf);
  618. }
  619. /**
  620. * ata_sff_data_xfer - Transfer data by PIO
  621. * @dev: device to target
  622. * @buf: data buffer
  623. * @buflen: buffer length
  624. * @rw: read/write
  625. *
  626. * Transfer data from/to the device data register by PIO.
  627. *
  628. * LOCKING:
  629. * Inherited from caller.
  630. *
  631. * RETURNS:
  632. * Bytes consumed.
  633. */
  634. unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
  635. unsigned int buflen, int rw)
  636. {
  637. struct ata_port *ap = dev->link->ap;
  638. void __iomem *data_addr = ap->ioaddr.data_addr;
  639. unsigned int words = buflen >> 1;
  640. /* Transfer multiple of 2 bytes */
  641. if (rw == READ)
  642. ioread16_rep(data_addr, buf, words);
  643. else
  644. iowrite16_rep(data_addr, buf, words);
  645. /* Transfer trailing 1 byte, if any. */
  646. if (unlikely(buflen & 0x01)) {
  647. __le16 align_buf[1] = { 0 };
  648. unsigned char *trailing_buf = buf + buflen - 1;
  649. if (rw == READ) {
  650. align_buf[0] = cpu_to_le16(ioread16(data_addr));
  651. memcpy(trailing_buf, align_buf, 1);
  652. } else {
  653. memcpy(align_buf, trailing_buf, 1);
  654. iowrite16(le16_to_cpu(align_buf[0]), data_addr);
  655. }
  656. words++;
  657. }
  658. return words << 1;
  659. }
  660. EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
  661. /**
  662. * ata_sff_data_xfer32 - Transfer data by PIO
  663. * @dev: device to target
  664. * @buf: data buffer
  665. * @buflen: buffer length
  666. * @rw: read/write
  667. *
  668. * Transfer data from/to the device data register by PIO using 32bit
  669. * I/O operations.
  670. *
  671. * LOCKING:
  672. * Inherited from caller.
  673. *
  674. * RETURNS:
  675. * Bytes consumed.
  676. */
  677. unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
  678. unsigned int buflen, int rw)
  679. {
  680. struct ata_port *ap = dev->link->ap;
  681. void __iomem *data_addr = ap->ioaddr.data_addr;
  682. unsigned int words = buflen >> 2;
  683. int slop = buflen & 3;
  684. /* Transfer multiple of 4 bytes */
  685. if (rw == READ)
  686. ioread32_rep(data_addr, buf, words);
  687. else
  688. iowrite32_rep(data_addr, buf, words);
  689. /* Transfer trailing bytes, if any */
  690. if (unlikely(slop)) {
  691. unsigned char pad[4];
  692. /* Point buf to the tail of buffer */
  693. buf += buflen - slop;
  694. /*
  695. * Use io*_rep() accessors here as well to avoid pointlessly
  696. * swapping bytes to and fro on the big endian machines...
  697. */
  698. if (rw == READ) {
  699. if (slop < 3)
  700. ioread16_rep(data_addr, pad, 1);
  701. else
  702. ioread32_rep(data_addr, pad, 1);
  703. memcpy(buf, pad, slop);
  704. } else {
  705. memcpy(pad, buf, slop);
  706. if (slop < 3)
  707. iowrite16_rep(data_addr, pad, 1);
  708. else
  709. iowrite32_rep(data_addr, pad, 1);
  710. }
  711. }
  712. return (buflen + 1) & ~1;
  713. }
  714. EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
  715. /**
  716. * ata_sff_data_xfer_noirq - Transfer data by PIO
  717. * @dev: device to target
  718. * @buf: data buffer
  719. * @buflen: buffer length
  720. * @rw: read/write
  721. *
  722. * Transfer data from/to the device data register by PIO. Do the
  723. * transfer with interrupts disabled.
  724. *
  725. * LOCKING:
  726. * Inherited from caller.
  727. *
  728. * RETURNS:
  729. * Bytes consumed.
  730. */
  731. unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
  732. unsigned int buflen, int rw)
  733. {
  734. unsigned long flags;
  735. unsigned int consumed;
  736. local_irq_save(flags);
  737. consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
  738. local_irq_restore(flags);
  739. return consumed;
  740. }
  741. EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
  742. /**
  743. * ata_pio_sector - Transfer a sector of data.
  744. * @qc: Command on going
  745. *
  746. * Transfer qc->sect_size bytes of data from/to the ATA device.
  747. *
  748. * LOCKING:
  749. * Inherited from caller.
  750. */
  751. static void ata_pio_sector(struct ata_queued_cmd *qc)
  752. {
  753. int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
  754. struct ata_port *ap = qc->ap;
  755. struct page *page;
  756. unsigned int offset;
  757. unsigned char *buf;
  758. if (qc->curbytes == qc->nbytes - qc->sect_size)
  759. ap->hsm_task_state = HSM_ST_LAST;
  760. page = sg_page(qc->cursg);
  761. offset = qc->cursg->offset + qc->cursg_ofs;
  762. /* get the current page and offset */
  763. page = nth_page(page, (offset >> PAGE_SHIFT));
  764. offset %= PAGE_SIZE;
  765. DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
  766. if (PageHighMem(page)) {
  767. unsigned long flags;
  768. /* FIXME: use a bounce buffer */
  769. local_irq_save(flags);
  770. buf = kmap_atomic(page, KM_IRQ0);
  771. /* do the actual data transfer */
  772. ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
  773. do_write);
  774. kunmap_atomic(buf, KM_IRQ0);
  775. local_irq_restore(flags);
  776. } else {
  777. buf = page_address(page);
  778. ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
  779. do_write);
  780. }
  781. qc->curbytes += qc->sect_size;
  782. qc->cursg_ofs += qc->sect_size;
  783. if (qc->cursg_ofs == qc->cursg->length) {
  784. qc->cursg = sg_next(qc->cursg);
  785. qc->cursg_ofs = 0;
  786. }
  787. }
  788. /**
  789. * ata_pio_sectors - Transfer one or many sectors.
  790. * @qc: Command on going
  791. *
  792. * Transfer one or many sectors of data from/to the
  793. * ATA device for the DRQ request.
  794. *
  795. * LOCKING:
  796. * Inherited from caller.
  797. */
  798. static void ata_pio_sectors(struct ata_queued_cmd *qc)
  799. {
  800. if (is_multi_taskfile(&qc->tf)) {
  801. /* READ/WRITE MULTIPLE */
  802. unsigned int nsect;
  803. WARN_ON_ONCE(qc->dev->multi_count == 0);
  804. nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
  805. qc->dev->multi_count);
  806. while (nsect--)
  807. ata_pio_sector(qc);
  808. } else
  809. ata_pio_sector(qc);
  810. ata_sff_sync(qc->ap); /* flush */
  811. }
  812. /**
  813. * atapi_send_cdb - Write CDB bytes to hardware
  814. * @ap: Port to which ATAPI device is attached.
  815. * @qc: Taskfile currently active
  816. *
  817. * When device has indicated its readiness to accept
  818. * a CDB, this function is called. Send the CDB.
  819. *
  820. * LOCKING:
  821. * caller.
  822. */
  823. static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
  824. {
  825. /* send SCSI cdb */
  826. DPRINTK("send cdb\n");
  827. WARN_ON_ONCE(qc->dev->cdb_len < 12);
  828. ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
  829. ata_sff_sync(ap);
  830. /* FIXME: If the CDB is for DMA do we need to do the transition delay
  831. or is bmdma_start guaranteed to do it ? */
  832. switch (qc->tf.protocol) {
  833. case ATAPI_PROT_PIO:
  834. ap->hsm_task_state = HSM_ST;
  835. break;
  836. case ATAPI_PROT_NODATA:
  837. ap->hsm_task_state = HSM_ST_LAST;
  838. break;
  839. case ATAPI_PROT_DMA:
  840. ap->hsm_task_state = HSM_ST_LAST;
  841. /* initiate bmdma */
  842. ap->ops->bmdma_start(qc);
  843. break;
  844. }
  845. }
  846. /**
  847. * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
  848. * @qc: Command on going
  849. * @bytes: number of bytes
  850. *
  851. * Transfer Transfer data from/to the ATAPI device.
  852. *
  853. * LOCKING:
  854. * Inherited from caller.
  855. *
  856. */
  857. static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
  858. {
  859. int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
  860. struct ata_port *ap = qc->ap;
  861. struct ata_device *dev = qc->dev;
  862. struct ata_eh_info *ehi = &dev->link->eh_info;
  863. struct scatterlist *sg;
  864. struct page *page;
  865. unsigned char *buf;
  866. unsigned int offset, count, consumed;
  867. next_sg:
  868. sg = qc->cursg;
  869. if (unlikely(!sg)) {
  870. ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
  871. "buf=%u cur=%u bytes=%u",
  872. qc->nbytes, qc->curbytes, bytes);
  873. return -1;
  874. }
  875. page = sg_page(sg);
  876. offset = sg->offset + qc->cursg_ofs;
  877. /* get the current page and offset */
  878. page = nth_page(page, (offset >> PAGE_SHIFT));
  879. offset %= PAGE_SIZE;
  880. /* don't overrun current sg */
  881. count = min(sg->length - qc->cursg_ofs, bytes);
  882. /* don't cross page boundaries */
  883. count = min(count, (unsigned int)PAGE_SIZE - offset);
  884. DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
  885. if (PageHighMem(page)) {
  886. unsigned long flags;
  887. /* FIXME: use bounce buffer */
  888. local_irq_save(flags);
  889. buf = kmap_atomic(page, KM_IRQ0);
  890. /* do the actual data transfer */
  891. consumed = ap->ops->sff_data_xfer(dev, buf + offset,
  892. count, rw);
  893. kunmap_atomic(buf, KM_IRQ0);
  894. local_irq_restore(flags);
  895. } else {
  896. buf = page_address(page);
  897. consumed = ap->ops->sff_data_xfer(dev, buf + offset,
  898. count, rw);
  899. }
  900. bytes -= min(bytes, consumed);
  901. qc->curbytes += count;
  902. qc->cursg_ofs += count;
  903. if (qc->cursg_ofs == sg->length) {
  904. qc->cursg = sg_next(qc->cursg);
  905. qc->cursg_ofs = 0;
  906. }
  907. /*
  908. * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
  909. * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
  910. * check correctly as it doesn't know if it is the last request being
  911. * made. Somebody should implement a proper sanity check.
  912. */
  913. if (bytes)
  914. goto next_sg;
  915. return 0;
  916. }
  917. /**
  918. * atapi_pio_bytes - Transfer data from/to the ATAPI device.
  919. * @qc: Command on going
  920. *
  921. * Transfer Transfer data from/to the ATAPI device.
  922. *
  923. * LOCKING:
  924. * Inherited from caller.
  925. */
  926. static void atapi_pio_bytes(struct ata_queued_cmd *qc)
  927. {
  928. struct ata_port *ap = qc->ap;
  929. struct ata_device *dev = qc->dev;
  930. struct ata_eh_info *ehi = &dev->link->eh_info;
  931. unsigned int ireason, bc_lo, bc_hi, bytes;
  932. int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
  933. /* Abuse qc->result_tf for temp storage of intermediate TF
  934. * here to save some kernel stack usage.
  935. * For normal completion, qc->result_tf is not relevant. For
  936. * error, qc->result_tf is later overwritten by ata_qc_complete().
  937. * So, the correctness of qc->result_tf is not affected.
  938. */
  939. ap->ops->sff_tf_read(ap, &qc->result_tf);
  940. ireason = qc->result_tf.nsect;
  941. bc_lo = qc->result_tf.lbam;
  942. bc_hi = qc->result_tf.lbah;
  943. bytes = (bc_hi << 8) | bc_lo;
  944. /* shall be cleared to zero, indicating xfer of data */
  945. if (unlikely(ireason & (1 << 0)))
  946. goto atapi_check;
  947. /* make sure transfer direction matches expected */
  948. i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
  949. if (unlikely(do_write != i_write))
  950. goto atapi_check;
  951. if (unlikely(!bytes))
  952. goto atapi_check;
  953. VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
  954. if (unlikely(__atapi_pio_bytes(qc, bytes)))
  955. goto err_out;
  956. ata_sff_sync(ap); /* flush */
  957. return;
  958. atapi_check:
  959. ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
  960. ireason, bytes);
  961. err_out:
  962. qc->err_mask |= AC_ERR_HSM;
  963. ap->hsm_task_state = HSM_ST_ERR;
  964. }
  965. /**
  966. * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
  967. * @ap: the target ata_port
  968. * @qc: qc on going
  969. *
  970. * RETURNS:
  971. * 1 if ok in workqueue, 0 otherwise.
  972. */
  973. static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
  974. struct ata_queued_cmd *qc)
  975. {
  976. if (qc->tf.flags & ATA_TFLAG_POLLING)
  977. return 1;
  978. if (ap->hsm_task_state == HSM_ST_FIRST) {
  979. if (qc->tf.protocol == ATA_PROT_PIO &&
  980. (qc->tf.flags & ATA_TFLAG_WRITE))
  981. return 1;
  982. if (ata_is_atapi(qc->tf.protocol) &&
  983. !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  984. return 1;
  985. }
  986. return 0;
  987. }
  988. /**
  989. * ata_hsm_qc_complete - finish a qc running on standard HSM
  990. * @qc: Command to complete
  991. * @in_wq: 1 if called from workqueue, 0 otherwise
  992. *
  993. * Finish @qc which is running on standard HSM.
  994. *
  995. * LOCKING:
  996. * If @in_wq is zero, spin_lock_irqsave(host lock).
  997. * Otherwise, none on entry and grabs host lock.
  998. */
  999. static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
  1000. {
  1001. struct ata_port *ap = qc->ap;
  1002. unsigned long flags;
  1003. if (ap->ops->error_handler) {
  1004. if (in_wq) {
  1005. spin_lock_irqsave(ap->lock, flags);
  1006. /* EH might have kicked in while host lock is
  1007. * released.
  1008. */
  1009. qc = ata_qc_from_tag(ap, qc->tag);
  1010. if (qc) {
  1011. if (likely(!(qc->err_mask & AC_ERR_HSM))) {
  1012. ap->ops->sff_irq_on(ap);
  1013. ata_qc_complete(qc);
  1014. } else
  1015. ata_port_freeze(ap);
  1016. }
  1017. spin_unlock_irqrestore(ap->lock, flags);
  1018. } else {
  1019. if (likely(!(qc->err_mask & AC_ERR_HSM)))
  1020. ata_qc_complete(qc);
  1021. else
  1022. ata_port_freeze(ap);
  1023. }
  1024. } else {
  1025. if (in_wq) {
  1026. spin_lock_irqsave(ap->lock, flags);
  1027. ap->ops->sff_irq_on(ap);
  1028. ata_qc_complete(qc);
  1029. spin_unlock_irqrestore(ap->lock, flags);
  1030. } else
  1031. ata_qc_complete(qc);
  1032. }
  1033. }
  1034. /**
  1035. * ata_sff_hsm_move - move the HSM to the next state.
  1036. * @ap: the target ata_port
  1037. * @qc: qc on going
  1038. * @status: current device status
  1039. * @in_wq: 1 if called from workqueue, 0 otherwise
  1040. *
  1041. * RETURNS:
  1042. * 1 when poll next status needed, 0 otherwise.
  1043. */
  1044. int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
  1045. u8 status, int in_wq)
  1046. {
  1047. struct ata_eh_info *ehi = &ap->link.eh_info;
  1048. unsigned long flags = 0;
  1049. int poll_next;
  1050. WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
  1051. /* Make sure ata_sff_qc_issue() does not throw things
  1052. * like DMA polling into the workqueue. Notice that
  1053. * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
  1054. */
  1055. WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
  1056. fsm_start:
  1057. DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
  1058. ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
  1059. switch (ap->hsm_task_state) {
  1060. case HSM_ST_FIRST:
  1061. /* Send first data block or PACKET CDB */
  1062. /* If polling, we will stay in the work queue after
  1063. * sending the data. Otherwise, interrupt handler
  1064. * takes over after sending the data.
  1065. */
  1066. poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
  1067. /* check device status */
  1068. if (unlikely((status & ATA_DRQ) == 0)) {
  1069. /* handle BSY=0, DRQ=0 as error */
  1070. if (likely(status & (ATA_ERR | ATA_DF)))
  1071. /* device stops HSM for abort/error */
  1072. qc->err_mask |= AC_ERR_DEV;
  1073. else {
  1074. /* HSM violation. Let EH handle this */
  1075. ata_ehi_push_desc(ehi,
  1076. "ST_FIRST: !(DRQ|ERR|DF)");
  1077. qc->err_mask |= AC_ERR_HSM;
  1078. }
  1079. ap->hsm_task_state = HSM_ST_ERR;
  1080. goto fsm_start;
  1081. }
  1082. /* Device should not ask for data transfer (DRQ=1)
  1083. * when it finds something wrong.
  1084. * We ignore DRQ here and stop the HSM by
  1085. * changing hsm_task_state to HSM_ST_ERR and
  1086. * let the EH abort the command or reset the device.
  1087. */
  1088. if (unlikely(status & (ATA_ERR | ATA_DF))) {
  1089. /* Some ATAPI tape drives forget to clear the ERR bit
  1090. * when doing the next command (mostly request sense).
  1091. * We ignore ERR here to workaround and proceed sending
  1092. * the CDB.
  1093. */
  1094. if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
  1095. ata_ehi_push_desc(ehi, "ST_FIRST: "
  1096. "DRQ=1 with device error, "
  1097. "dev_stat 0x%X", status);
  1098. qc->err_mask |= AC_ERR_HSM;
  1099. ap->hsm_task_state = HSM_ST_ERR;
  1100. goto fsm_start;
  1101. }
  1102. }
  1103. /* Send the CDB (atapi) or the first data block (ata pio out).
  1104. * During the state transition, interrupt handler shouldn't
  1105. * be invoked before the data transfer is complete and
  1106. * hsm_task_state is changed. Hence, the following locking.
  1107. */
  1108. if (in_wq)
  1109. spin_lock_irqsave(ap->lock, flags);
  1110. if (qc->tf.protocol == ATA_PROT_PIO) {
  1111. /* PIO data out protocol.
  1112. * send first data block.
  1113. */
  1114. /* ata_pio_sectors() might change the state
  1115. * to HSM_ST_LAST. so, the state is changed here
  1116. * before ata_pio_sectors().
  1117. */
  1118. ap->hsm_task_state = HSM_ST;
  1119. ata_pio_sectors(qc);
  1120. } else
  1121. /* send CDB */
  1122. atapi_send_cdb(ap, qc);
  1123. if (in_wq)
  1124. spin_unlock_irqrestore(ap->lock, flags);
  1125. /* if polling, ata_pio_task() handles the rest.
  1126. * otherwise, interrupt handler takes over from here.
  1127. */
  1128. break;
  1129. case HSM_ST:
  1130. /* complete command or read/write the data register */
  1131. if (qc->tf.protocol == ATAPI_PROT_PIO) {
  1132. /* ATAPI PIO protocol */
  1133. if ((status & ATA_DRQ) == 0) {
  1134. /* No more data to transfer or device error.
  1135. * Device error will be tagged in HSM_ST_LAST.
  1136. */
  1137. ap->hsm_task_state = HSM_ST_LAST;
  1138. goto fsm_start;
  1139. }
  1140. /* Device should not ask for data transfer (DRQ=1)
  1141. * when it finds something wrong.
  1142. * We ignore DRQ here and stop the HSM by
  1143. * changing hsm_task_state to HSM_ST_ERR and
  1144. * let the EH abort the command or reset the device.
  1145. */
  1146. if (unlikely(status & (ATA_ERR | ATA_DF))) {
  1147. ata_ehi_push_desc(ehi, "ST-ATAPI: "
  1148. "DRQ=1 with device error, "
  1149. "dev_stat 0x%X", status);
  1150. qc->err_mask |= AC_ERR_HSM;
  1151. ap->hsm_task_state = HSM_ST_ERR;
  1152. goto fsm_start;
  1153. }
  1154. atapi_pio_bytes(qc);
  1155. if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
  1156. /* bad ireason reported by device */
  1157. goto fsm_start;
  1158. } else {
  1159. /* ATA PIO protocol */
  1160. if (unlikely((status & ATA_DRQ) == 0)) {
  1161. /* handle BSY=0, DRQ=0 as error */
  1162. if (likely(status & (ATA_ERR | ATA_DF))) {
  1163. /* device stops HSM for abort/error */
  1164. qc->err_mask |= AC_ERR_DEV;
  1165. /* If diagnostic failed and this is
  1166. * IDENTIFY, it's likely a phantom
  1167. * device. Mark hint.
  1168. */
  1169. if (qc->dev->horkage &
  1170. ATA_HORKAGE_DIAGNOSTIC)
  1171. qc->err_mask |=
  1172. AC_ERR_NODEV_HINT;
  1173. } else {
  1174. /* HSM violation. Let EH handle this.
  1175. * Phantom devices also trigger this
  1176. * condition. Mark hint.
  1177. */
  1178. ata_ehi_push_desc(ehi, "ST-ATA: "
  1179. "DRQ=0 without device error, "
  1180. "dev_stat 0x%X", status);
  1181. qc->err_mask |= AC_ERR_HSM |
  1182. AC_ERR_NODEV_HINT;
  1183. }
  1184. ap->hsm_task_state = HSM_ST_ERR;
  1185. goto fsm_start;
  1186. }
  1187. /* For PIO reads, some devices may ask for
  1188. * data transfer (DRQ=1) alone with ERR=1.
  1189. * We respect DRQ here and transfer one
  1190. * block of junk data before changing the
  1191. * hsm_task_state to HSM_ST_ERR.
  1192. *
  1193. * For PIO writes, ERR=1 DRQ=1 doesn't make
  1194. * sense since the data block has been
  1195. * transferred to the device.
  1196. */
  1197. if (unlikely(status & (ATA_ERR | ATA_DF))) {
  1198. /* data might be corrputed */
  1199. qc->err_mask |= AC_ERR_DEV;
  1200. if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
  1201. ata_pio_sectors(qc);
  1202. status = ata_wait_idle(ap);
  1203. }
  1204. if (status & (ATA_BUSY | ATA_DRQ)) {
  1205. ata_ehi_push_desc(ehi, "ST-ATA: "
  1206. "BUSY|DRQ persists on ERR|DF, "
  1207. "dev_stat 0x%X", status);
  1208. qc->err_mask |= AC_ERR_HSM;
  1209. }
  1210. /* There are oddball controllers with
  1211. * status register stuck at 0x7f and
  1212. * lbal/m/h at zero which makes it
  1213. * pass all other presence detection
  1214. * mechanisms we have. Set NODEV_HINT
  1215. * for it. Kernel bz#7241.
  1216. */
  1217. if (status == 0x7f)
  1218. qc->err_mask |= AC_ERR_NODEV_HINT;
  1219. /* ata_pio_sectors() might change the
  1220. * state to HSM_ST_LAST. so, the state
  1221. * is changed after ata_pio_sectors().
  1222. */
  1223. ap->hsm_task_state = HSM_ST_ERR;
  1224. goto fsm_start;
  1225. }
  1226. ata_pio_sectors(qc);
  1227. if (ap->hsm_task_state == HSM_ST_LAST &&
  1228. (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
  1229. /* all data read */
  1230. status = ata_wait_idle(ap);
  1231. goto fsm_start;
  1232. }
  1233. }
  1234. poll_next = 1;
  1235. break;
  1236. case HSM_ST_LAST:
  1237. if (unlikely(!ata_ok(status))) {
  1238. qc->err_mask |= __ac_err_mask(status);
  1239. ap->hsm_task_state = HSM_ST_ERR;
  1240. goto fsm_start;
  1241. }
  1242. /* no more data to transfer */
  1243. DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
  1244. ap->print_id, qc->dev->devno, status);
  1245. WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
  1246. ap->hsm_task_state = HSM_ST_IDLE;
  1247. /* complete taskfile transaction */
  1248. ata_hsm_qc_complete(qc, in_wq);
  1249. poll_next = 0;
  1250. break;
  1251. case HSM_ST_ERR:
  1252. ap->hsm_task_state = HSM_ST_IDLE;
  1253. /* complete taskfile transaction */
  1254. ata_hsm_qc_complete(qc, in_wq);
  1255. poll_next = 0;
  1256. break;
  1257. default:
  1258. poll_next = 0;
  1259. BUG();
  1260. }
  1261. return poll_next;
  1262. }
  1263. EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
  1264. void ata_pio_task(struct work_struct *work)
  1265. {
  1266. struct ata_port *ap =
  1267. container_of(work, struct ata_port, port_task.work);
  1268. struct ata_queued_cmd *qc = ap->port_task_data;
  1269. u8 status;
  1270. int poll_next;
  1271. fsm_start:
  1272. WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
  1273. /*
  1274. * This is purely heuristic. This is a fast path.
  1275. * Sometimes when we enter, BSY will be cleared in
  1276. * a chk-status or two. If not, the drive is probably seeking
  1277. * or something. Snooze for a couple msecs, then
  1278. * chk-status again. If still busy, queue delayed work.
  1279. */
  1280. status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
  1281. if (status & ATA_BUSY) {
  1282. msleep(2);
  1283. status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
  1284. if (status & ATA_BUSY) {
  1285. ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
  1286. return;
  1287. }
  1288. }
  1289. /* move the HSM */
  1290. poll_next = ata_sff_hsm_move(ap, qc, status, 1);
  1291. /* another command or interrupt handler
  1292. * may be running at this point.
  1293. */
  1294. if (poll_next)
  1295. goto fsm_start;
  1296. }
  1297. /**
  1298. * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
  1299. * @qc: command to issue to device
  1300. *
  1301. * Using various libata functions and hooks, this function
  1302. * starts an ATA command. ATA commands are grouped into
  1303. * classes called "protocols", and issuing each type of protocol
  1304. * is slightly different.
  1305. *
  1306. * May be used as the qc_issue() entry in ata_port_operations.
  1307. *
  1308. * LOCKING:
  1309. * spin_lock_irqsave(host lock)
  1310. *
  1311. * RETURNS:
  1312. * Zero on success, AC_ERR_* mask on failure
  1313. */
  1314. unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
  1315. {
  1316. struct ata_port *ap = qc->ap;
  1317. /* Use polling pio if the LLD doesn't handle
  1318. * interrupt driven pio and atapi CDB interrupt.
  1319. */
  1320. if (ap->flags & ATA_FLAG_PIO_POLLING) {
  1321. switch (qc->tf.protocol) {
  1322. case ATA_PROT_PIO:
  1323. case ATA_PROT_NODATA:
  1324. case ATAPI_PROT_PIO:
  1325. case ATAPI_PROT_NODATA:
  1326. qc->tf.flags |= ATA_TFLAG_POLLING;
  1327. break;
  1328. case ATAPI_PROT_DMA:
  1329. if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
  1330. /* see ata_dma_blacklisted() */
  1331. BUG();
  1332. break;
  1333. default:
  1334. break;
  1335. }
  1336. }
  1337. /* select the device */
  1338. ata_dev_select(ap, qc->dev->devno, 1, 0);
  1339. /* start the command */
  1340. switch (qc->tf.protocol) {
  1341. case ATA_PROT_NODATA:
  1342. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1343. ata_qc_set_polling(qc);
  1344. ata_tf_to_host(ap, &qc->tf);
  1345. ap->hsm_task_state = HSM_ST_LAST;
  1346. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1347. ata_pio_queue_task(ap, qc, 0);
  1348. break;
  1349. case ATA_PROT_DMA:
  1350. WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
  1351. ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
  1352. ap->ops->bmdma_setup(qc); /* set up bmdma */
  1353. ap->ops->bmdma_start(qc); /* initiate bmdma */
  1354. ap->hsm_task_state = HSM_ST_LAST;
  1355. break;
  1356. case ATA_PROT_PIO:
  1357. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1358. ata_qc_set_polling(qc);
  1359. ata_tf_to_host(ap, &qc->tf);
  1360. if (qc->tf.flags & ATA_TFLAG_WRITE) {
  1361. /* PIO data out protocol */
  1362. ap->hsm_task_state = HSM_ST_FIRST;
  1363. ata_pio_queue_task(ap, qc, 0);
  1364. /* always send first data block using
  1365. * the ata_pio_task() codepath.
  1366. */
  1367. } else {
  1368. /* PIO data in protocol */
  1369. ap->hsm_task_state = HSM_ST;
  1370. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1371. ata_pio_queue_task(ap, qc, 0);
  1372. /* if polling, ata_pio_task() handles the rest.
  1373. * otherwise, interrupt handler takes over from here.
  1374. */
  1375. }
  1376. break;
  1377. case ATAPI_PROT_PIO:
  1378. case ATAPI_PROT_NODATA:
  1379. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1380. ata_qc_set_polling(qc);
  1381. ata_tf_to_host(ap, &qc->tf);
  1382. ap->hsm_task_state = HSM_ST_FIRST;
  1383. /* send cdb by polling if no cdb interrupt */
  1384. if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
  1385. (qc->tf.flags & ATA_TFLAG_POLLING))
  1386. ata_pio_queue_task(ap, qc, 0);
  1387. break;
  1388. case ATAPI_PROT_DMA:
  1389. WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
  1390. ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
  1391. ap->ops->bmdma_setup(qc); /* set up bmdma */
  1392. ap->hsm_task_state = HSM_ST_FIRST;
  1393. /* send cdb by polling if no cdb interrupt */
  1394. if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  1395. ata_pio_queue_task(ap, qc, 0);
  1396. break;
  1397. default:
  1398. WARN_ON_ONCE(1);
  1399. return AC_ERR_SYSTEM;
  1400. }
  1401. return 0;
  1402. }
  1403. EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
  1404. /**
  1405. * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
  1406. * @qc: qc to fill result TF for
  1407. *
  1408. * @qc is finished and result TF needs to be filled. Fill it
  1409. * using ->sff_tf_read.
  1410. *
  1411. * LOCKING:
  1412. * spin_lock_irqsave(host lock)
  1413. *
  1414. * RETURNS:
  1415. * true indicating that result TF is successfully filled.
  1416. */
  1417. bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
  1418. {
  1419. qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
  1420. return true;
  1421. }
  1422. EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
  1423. /**
  1424. * ata_sff_host_intr - Handle host interrupt for given (port, task)
  1425. * @ap: Port on which interrupt arrived (possibly...)
  1426. * @qc: Taskfile currently active in engine
  1427. *
  1428. * Handle host interrupt for given queued command. Currently,
  1429. * only DMA interrupts are handled. All other commands are
  1430. * handled via polling with interrupts disabled (nIEN bit).
  1431. *
  1432. * LOCKING:
  1433. * spin_lock_irqsave(host lock)
  1434. *
  1435. * RETURNS:
  1436. * One if interrupt was handled, zero if not (shared irq).
  1437. */
  1438. inline unsigned int ata_sff_host_intr(struct ata_port *ap,
  1439. struct ata_queued_cmd *qc)
  1440. {
  1441. struct ata_eh_info *ehi = &ap->link.eh_info;
  1442. u8 status, host_stat = 0;
  1443. VPRINTK("ata%u: protocol %d task_state %d\n",
  1444. ap->print_id, qc->tf.protocol, ap->hsm_task_state);
  1445. /* Check whether we are expecting interrupt in this state */
  1446. switch (ap->hsm_task_state) {
  1447. case HSM_ST_FIRST:
  1448. /* Some pre-ATAPI-4 devices assert INTRQ
  1449. * at this state when ready to receive CDB.
  1450. */
  1451. /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
  1452. * The flag was turned on only for atapi devices. No
  1453. * need to check ata_is_atapi(qc->tf.protocol) again.
  1454. */
  1455. if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
  1456. goto idle_irq;
  1457. break;
  1458. case HSM_ST_LAST:
  1459. if (qc->tf.protocol == ATA_PROT_DMA ||
  1460. qc->tf.protocol == ATAPI_PROT_DMA) {
  1461. /* check status of DMA engine */
  1462. host_stat = ap->ops->bmdma_status(ap);
  1463. VPRINTK("ata%u: host_stat 0x%X\n",
  1464. ap->print_id, host_stat);
  1465. /* if it's not our irq... */
  1466. if (!(host_stat & ATA_DMA_INTR))
  1467. goto idle_irq;
  1468. /* before we do anything else, clear DMA-Start bit */
  1469. ap->ops->bmdma_stop(qc);
  1470. if (unlikely(host_stat & ATA_DMA_ERR)) {
  1471. /* error when transfering data to/from memory */
  1472. qc->err_mask |= AC_ERR_HOST_BUS;
  1473. ap->hsm_task_state = HSM_ST_ERR;
  1474. }
  1475. }
  1476. break;
  1477. case HSM_ST:
  1478. break;
  1479. default:
  1480. goto idle_irq;
  1481. }
  1482. /* check main status, clearing INTRQ if needed */
  1483. status = ata_sff_irq_status(ap);
  1484. if (status & ATA_BUSY)
  1485. goto idle_irq;
  1486. /* ack bmdma irq events */
  1487. ap->ops->sff_irq_clear(ap);
  1488. ata_sff_hsm_move(ap, qc, status, 0);
  1489. if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
  1490. qc->tf.protocol == ATAPI_PROT_DMA))
  1491. ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
  1492. return 1; /* irq handled */
  1493. idle_irq:
  1494. ap->stats.idle_irq++;
  1495. #ifdef ATA_IRQ_TRAP
  1496. if ((ap->stats.idle_irq % 1000) == 0) {
  1497. ap->ops->sff_check_status(ap);
  1498. ap->ops->sff_irq_clear(ap);
  1499. ata_port_printk(ap, KERN_WARNING, "irq trap\n");
  1500. return 1;
  1501. }
  1502. #endif
  1503. return 0; /* irq not handled */
  1504. }
  1505. EXPORT_SYMBOL_GPL(ata_sff_host_intr);
  1506. /**
  1507. * ata_sff_interrupt - Default ATA host interrupt handler
  1508. * @irq: irq line (unused)
  1509. * @dev_instance: pointer to our ata_host information structure
  1510. *
  1511. * Default interrupt handler for PCI IDE devices. Calls
  1512. * ata_sff_host_intr() for each port that is not disabled.
  1513. *
  1514. * LOCKING:
  1515. * Obtains host lock during operation.
  1516. *
  1517. * RETURNS:
  1518. * IRQ_NONE or IRQ_HANDLED.
  1519. */
  1520. irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
  1521. {
  1522. struct ata_host *host = dev_instance;
  1523. unsigned int i;
  1524. unsigned int handled = 0;
  1525. unsigned long flags;
  1526. /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
  1527. spin_lock_irqsave(&host->lock, flags);
  1528. for (i = 0; i < host->n_ports; i++) {
  1529. struct ata_port *ap;
  1530. ap = host->ports[i];
  1531. if (ap &&
  1532. !(ap->flags & ATA_FLAG_DISABLED)) {
  1533. struct ata_queued_cmd *qc;
  1534. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1535. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
  1536. (qc->flags & ATA_QCFLAG_ACTIVE))
  1537. handled |= ata_sff_host_intr(ap, qc);
  1538. }
  1539. }
  1540. spin_unlock_irqrestore(&host->lock, flags);
  1541. return IRQ_RETVAL(handled);
  1542. }
  1543. EXPORT_SYMBOL_GPL(ata_sff_interrupt);
  1544. /**
  1545. * ata_sff_freeze - Freeze SFF controller port
  1546. * @ap: port to freeze
  1547. *
  1548. * Freeze BMDMA controller port.
  1549. *
  1550. * LOCKING:
  1551. * Inherited from caller.
  1552. */
  1553. void ata_sff_freeze(struct ata_port *ap)
  1554. {
  1555. struct ata_ioports *ioaddr = &ap->ioaddr;
  1556. ap->ctl |= ATA_NIEN;
  1557. ap->last_ctl = ap->ctl;
  1558. if (ioaddr->ctl_addr)
  1559. iowrite8(ap->ctl, ioaddr->ctl_addr);
  1560. /* Under certain circumstances, some controllers raise IRQ on
  1561. * ATA_NIEN manipulation. Also, many controllers fail to mask
  1562. * previously pending IRQ on ATA_NIEN assertion. Clear it.
  1563. */
  1564. ap->ops->sff_check_status(ap);
  1565. ap->ops->sff_irq_clear(ap);
  1566. }
  1567. EXPORT_SYMBOL_GPL(ata_sff_freeze);
  1568. /**
  1569. * ata_sff_thaw - Thaw SFF controller port
  1570. * @ap: port to thaw
  1571. *
  1572. * Thaw SFF controller port.
  1573. *
  1574. * LOCKING:
  1575. * Inherited from caller.
  1576. */
  1577. void ata_sff_thaw(struct ata_port *ap)
  1578. {
  1579. /* clear & re-enable interrupts */
  1580. ap->ops->sff_check_status(ap);
  1581. ap->ops->sff_irq_clear(ap);
  1582. ap->ops->sff_irq_on(ap);
  1583. }
  1584. EXPORT_SYMBOL_GPL(ata_sff_thaw);
  1585. /**
  1586. * ata_sff_prereset - prepare SFF link for reset
  1587. * @link: SFF link to be reset
  1588. * @deadline: deadline jiffies for the operation
  1589. *
  1590. * SFF link @link is about to be reset. Initialize it. It first
  1591. * calls ata_std_prereset() and wait for !BSY if the port is
  1592. * being softreset.
  1593. *
  1594. * LOCKING:
  1595. * Kernel thread context (may sleep)
  1596. *
  1597. * RETURNS:
  1598. * 0 on success, -errno otherwise.
  1599. */
  1600. int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
  1601. {
  1602. struct ata_eh_context *ehc = &link->eh_context;
  1603. int rc;
  1604. rc = ata_std_prereset(link, deadline);
  1605. if (rc)
  1606. return rc;
  1607. /* if we're about to do hardreset, nothing more to do */
  1608. if (ehc->i.action & ATA_EH_HARDRESET)
  1609. return 0;
  1610. /* wait for !BSY if we don't know that no device is attached */
  1611. if (!ata_link_offline(link)) {
  1612. rc = ata_sff_wait_ready(link, deadline);
  1613. if (rc && rc != -ENODEV) {
  1614. ata_link_printk(link, KERN_WARNING, "device not ready "
  1615. "(errno=%d), forcing hardreset\n", rc);
  1616. ehc->i.action |= ATA_EH_HARDRESET;
  1617. }
  1618. }
  1619. return 0;
  1620. }
  1621. EXPORT_SYMBOL_GPL(ata_sff_prereset);
  1622. /**
  1623. * ata_devchk - PATA device presence detection
  1624. * @ap: ATA channel to examine
  1625. * @device: Device to examine (starting at zero)
  1626. *
  1627. * This technique was originally described in
  1628. * Hale Landis's ATADRVR (www.ata-atapi.com), and
  1629. * later found its way into the ATA/ATAPI spec.
  1630. *
  1631. * Write a pattern to the ATA shadow registers,
  1632. * and if a device is present, it will respond by
  1633. * correctly storing and echoing back the
  1634. * ATA shadow register contents.
  1635. *
  1636. * LOCKING:
  1637. * caller.
  1638. */
  1639. static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
  1640. {
  1641. struct ata_ioports *ioaddr = &ap->ioaddr;
  1642. u8 nsect, lbal;
  1643. ap->ops->sff_dev_select(ap, device);
  1644. iowrite8(0x55, ioaddr->nsect_addr);
  1645. iowrite8(0xaa, ioaddr->lbal_addr);
  1646. iowrite8(0xaa, ioaddr->nsect_addr);
  1647. iowrite8(0x55, ioaddr->lbal_addr);
  1648. iowrite8(0x55, ioaddr->nsect_addr);
  1649. iowrite8(0xaa, ioaddr->lbal_addr);
  1650. nsect = ioread8(ioaddr->nsect_addr);
  1651. lbal = ioread8(ioaddr->lbal_addr);
  1652. if ((nsect == 0x55) && (lbal == 0xaa))
  1653. return 1; /* we found a device */
  1654. return 0; /* nothing found */
  1655. }
  1656. /**
  1657. * ata_sff_dev_classify - Parse returned ATA device signature
  1658. * @dev: ATA device to classify (starting at zero)
  1659. * @present: device seems present
  1660. * @r_err: Value of error register on completion
  1661. *
  1662. * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
  1663. * an ATA/ATAPI-defined set of values is placed in the ATA
  1664. * shadow registers, indicating the results of device detection
  1665. * and diagnostics.
  1666. *
  1667. * Select the ATA device, and read the values from the ATA shadow
  1668. * registers. Then parse according to the Error register value,
  1669. * and the spec-defined values examined by ata_dev_classify().
  1670. *
  1671. * LOCKING:
  1672. * caller.
  1673. *
  1674. * RETURNS:
  1675. * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
  1676. */
  1677. unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
  1678. u8 *r_err)
  1679. {
  1680. struct ata_port *ap = dev->link->ap;
  1681. struct ata_taskfile tf;
  1682. unsigned int class;
  1683. u8 err;
  1684. ap->ops->sff_dev_select(ap, dev->devno);
  1685. memset(&tf, 0, sizeof(tf));
  1686. ap->ops->sff_tf_read(ap, &tf);
  1687. err = tf.feature;
  1688. if (r_err)
  1689. *r_err = err;
  1690. /* see if device passed diags: continue and warn later */
  1691. if (err == 0)
  1692. /* diagnostic fail : do nothing _YET_ */
  1693. dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
  1694. else if (err == 1)
  1695. /* do nothing */ ;
  1696. else if ((dev->devno == 0) && (err == 0x81))
  1697. /* do nothing */ ;
  1698. else
  1699. return ATA_DEV_NONE;
  1700. /* determine if device is ATA or ATAPI */
  1701. class = ata_dev_classify(&tf);
  1702. if (class == ATA_DEV_UNKNOWN) {
  1703. /* If the device failed diagnostic, it's likely to
  1704. * have reported incorrect device signature too.
  1705. * Assume ATA device if the device seems present but
  1706. * device signature is invalid with diagnostic
  1707. * failure.
  1708. */
  1709. if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
  1710. class = ATA_DEV_ATA;
  1711. else
  1712. class = ATA_DEV_NONE;
  1713. } else if ((class == ATA_DEV_ATA) &&
  1714. (ap->ops->sff_check_status(ap) == 0))
  1715. class = ATA_DEV_NONE;
  1716. return class;
  1717. }
  1718. EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
  1719. /**
  1720. * ata_sff_wait_after_reset - wait for devices to become ready after reset
  1721. * @link: SFF link which is just reset
  1722. * @devmask: mask of present devices
  1723. * @deadline: deadline jiffies for the operation
  1724. *
  1725. * Wait devices attached to SFF @link to become ready after
  1726. * reset. It contains preceding 150ms wait to avoid accessing TF
  1727. * status register too early.
  1728. *
  1729. * LOCKING:
  1730. * Kernel thread context (may sleep).
  1731. *
  1732. * RETURNS:
  1733. * 0 on success, -ENODEV if some or all of devices in @devmask
  1734. * don't seem to exist. -errno on other errors.
  1735. */
  1736. int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
  1737. unsigned long deadline)
  1738. {
  1739. struct ata_port *ap = link->ap;
  1740. struct ata_ioports *ioaddr = &ap->ioaddr;
  1741. unsigned int dev0 = devmask & (1 << 0);
  1742. unsigned int dev1 = devmask & (1 << 1);
  1743. int rc, ret = 0;
  1744. msleep(ATA_WAIT_AFTER_RESET);
  1745. /* always check readiness of the master device */
  1746. rc = ata_sff_wait_ready(link, deadline);
  1747. /* -ENODEV means the odd clown forgot the D7 pulldown resistor
  1748. * and TF status is 0xff, bail out on it too.
  1749. */
  1750. if (rc)
  1751. return rc;
  1752. /* if device 1 was found in ata_devchk, wait for register
  1753. * access briefly, then wait for BSY to clear.
  1754. */
  1755. if (dev1) {
  1756. int i;
  1757. ap->ops->sff_dev_select(ap, 1);
  1758. /* Wait for register access. Some ATAPI devices fail
  1759. * to set nsect/lbal after reset, so don't waste too
  1760. * much time on it. We're gonna wait for !BSY anyway.
  1761. */
  1762. for (i = 0; i < 2; i++) {
  1763. u8 nsect, lbal;
  1764. nsect = ioread8(ioaddr->nsect_addr);
  1765. lbal = ioread8(ioaddr->lbal_addr);
  1766. if ((nsect == 1) && (lbal == 1))
  1767. break;
  1768. msleep(50); /* give drive a breather */
  1769. }
  1770. rc = ata_sff_wait_ready(link, deadline);
  1771. if (rc) {
  1772. if (rc != -ENODEV)
  1773. return rc;
  1774. ret = rc;
  1775. }
  1776. }
  1777. /* is all this really necessary? */
  1778. ap->ops->sff_dev_select(ap, 0);
  1779. if (dev1)
  1780. ap->ops->sff_dev_select(ap, 1);
  1781. if (dev0)
  1782. ap->ops->sff_dev_select(ap, 0);
  1783. return ret;
  1784. }
  1785. EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
  1786. static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
  1787. unsigned long deadline)
  1788. {
  1789. struct ata_ioports *ioaddr = &ap->ioaddr;
  1790. DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
  1791. /* software reset. causes dev0 to be selected */
  1792. iowrite8(ap->ctl, ioaddr->ctl_addr);
  1793. udelay(20); /* FIXME: flush */
  1794. iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
  1795. udelay(20); /* FIXME: flush */
  1796. iowrite8(ap->ctl, ioaddr->ctl_addr);
  1797. ap->last_ctl = ap->ctl;
  1798. /* wait the port to become ready */
  1799. return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
  1800. }
  1801. /**
  1802. * ata_sff_softreset - reset host port via ATA SRST
  1803. * @link: ATA link to reset
  1804. * @classes: resulting classes of attached devices
  1805. * @deadline: deadline jiffies for the operation
  1806. *
  1807. * Reset host port using ATA SRST.
  1808. *
  1809. * LOCKING:
  1810. * Kernel thread context (may sleep)
  1811. *
  1812. * RETURNS:
  1813. * 0 on success, -errno otherwise.
  1814. */
  1815. int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
  1816. unsigned long deadline)
  1817. {
  1818. struct ata_port *ap = link->ap;
  1819. unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
  1820. unsigned int devmask = 0;
  1821. int rc;
  1822. u8 err;
  1823. DPRINTK("ENTER\n");
  1824. /* determine if device 0/1 are present */
  1825. if (ata_devchk(ap, 0))
  1826. devmask |= (1 << 0);
  1827. if (slave_possible && ata_devchk(ap, 1))
  1828. devmask |= (1 << 1);
  1829. /* select device 0 again */
  1830. ap->ops->sff_dev_select(ap, 0);
  1831. /* issue bus reset */
  1832. DPRINTK("about to softreset, devmask=%x\n", devmask);
  1833. rc = ata_bus_softreset(ap, devmask, deadline);
  1834. /* if link is occupied, -ENODEV too is an error */
  1835. if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
  1836. ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
  1837. return rc;
  1838. }
  1839. /* determine by signature whether we have ATA or ATAPI devices */
  1840. classes[0] = ata_sff_dev_classify(&link->device[0],
  1841. devmask & (1 << 0), &err);
  1842. if (slave_possible && err != 0x81)
  1843. classes[1] = ata_sff_dev_classify(&link->device[1],
  1844. devmask & (1 << 1), &err);
  1845. DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
  1846. return 0;
  1847. }
  1848. EXPORT_SYMBOL_GPL(ata_sff_softreset);
  1849. /**
  1850. * sata_sff_hardreset - reset host port via SATA phy reset
  1851. * @link: link to reset
  1852. * @class: resulting class of attached device
  1853. * @deadline: deadline jiffies for the operation
  1854. *
  1855. * SATA phy-reset host port using DET bits of SControl register,
  1856. * wait for !BSY and classify the attached device.
  1857. *
  1858. * LOCKING:
  1859. * Kernel thread context (may sleep)
  1860. *
  1861. * RETURNS:
  1862. * 0 on success, -errno otherwise.
  1863. */
  1864. int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
  1865. unsigned long deadline)
  1866. {
  1867. struct ata_eh_context *ehc = &link->eh_context;
  1868. const unsigned long *timing = sata_ehc_deb_timing(ehc);
  1869. bool online;
  1870. int rc;
  1871. rc = sata_link_hardreset(link, timing, deadline, &online,
  1872. ata_sff_check_ready);
  1873. if (online)
  1874. *class = ata_sff_dev_classify(link->device, 1, NULL);
  1875. DPRINTK("EXIT, class=%u\n", *class);
  1876. return rc;
  1877. }
  1878. EXPORT_SYMBOL_GPL(sata_sff_hardreset);
  1879. /**
  1880. * ata_sff_postreset - SFF postreset callback
  1881. * @link: the target SFF ata_link
  1882. * @classes: classes of attached devices
  1883. *
  1884. * This function is invoked after a successful reset. It first
  1885. * calls ata_std_postreset() and performs SFF specific postreset
  1886. * processing.
  1887. *
  1888. * LOCKING:
  1889. * Kernel thread context (may sleep)
  1890. */
  1891. void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
  1892. {
  1893. struct ata_port *ap = link->ap;
  1894. ata_std_postreset(link, classes);
  1895. /* is double-select really necessary? */
  1896. if (classes[0] != ATA_DEV_NONE)
  1897. ap->ops->sff_dev_select(ap, 1);
  1898. if (classes[1] != ATA_DEV_NONE)
  1899. ap->ops->sff_dev_select(ap, 0);
  1900. /* bail out if no device is present */
  1901. if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
  1902. DPRINTK("EXIT, no device\n");
  1903. return;
  1904. }
  1905. /* set up device control */
  1906. if (ap->ioaddr.ctl_addr) {
  1907. iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
  1908. ap->last_ctl = ap->ctl;
  1909. }
  1910. }
  1911. EXPORT_SYMBOL_GPL(ata_sff_postreset);
  1912. /**
  1913. * ata_sff_error_handler - Stock error handler for BMDMA controller
  1914. * @ap: port to handle error for
  1915. *
  1916. * Stock error handler for SFF controller. It can handle both
  1917. * PATA and SATA controllers. Many controllers should be able to
  1918. * use this EH as-is or with some added handling before and
  1919. * after.
  1920. *
  1921. * LOCKING:
  1922. * Kernel thread context (may sleep)
  1923. */
  1924. void ata_sff_error_handler(struct ata_port *ap)
  1925. {
  1926. ata_reset_fn_t softreset = ap->ops->softreset;
  1927. ata_reset_fn_t hardreset = ap->ops->hardreset;
  1928. struct ata_queued_cmd *qc;
  1929. unsigned long flags;
  1930. int thaw = 0;
  1931. qc = __ata_qc_from_tag(ap, ap->link.active_tag);
  1932. if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
  1933. qc = NULL;
  1934. /* reset PIO HSM and stop DMA engine */
  1935. spin_lock_irqsave(ap->lock, flags);
  1936. ap->hsm_task_state = HSM_ST_IDLE;
  1937. if (ap->ioaddr.bmdma_addr &&
  1938. qc && (qc->tf.protocol == ATA_PROT_DMA ||
  1939. qc->tf.protocol == ATAPI_PROT_DMA)) {
  1940. u8 host_stat;
  1941. host_stat = ap->ops->bmdma_status(ap);
  1942. /* BMDMA controllers indicate host bus error by
  1943. * setting DMA_ERR bit and timing out. As it wasn't
  1944. * really a timeout event, adjust error mask and
  1945. * cancel frozen state.
  1946. */
  1947. if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
  1948. qc->err_mask = AC_ERR_HOST_BUS;
  1949. thaw = 1;
  1950. }
  1951. ap->ops->bmdma_stop(qc);
  1952. }
  1953. ata_sff_sync(ap); /* FIXME: We don't need this */
  1954. ap->ops->sff_check_status(ap);
  1955. ap->ops->sff_irq_clear(ap);
  1956. spin_unlock_irqrestore(ap->lock, flags);
  1957. if (thaw)
  1958. ata_eh_thaw_port(ap);
  1959. /* PIO and DMA engines have been stopped, perform recovery */
  1960. /* Ignore ata_sff_softreset if ctl isn't accessible and
  1961. * built-in hardresets if SCR access isn't available.
  1962. */
  1963. if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
  1964. softreset = NULL;
  1965. if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
  1966. hardreset = NULL;
  1967. ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
  1968. ap->ops->postreset);
  1969. }
  1970. EXPORT_SYMBOL_GPL(ata_sff_error_handler);
  1971. /**
  1972. * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
  1973. * @qc: internal command to clean up
  1974. *
  1975. * LOCKING:
  1976. * Kernel thread context (may sleep)
  1977. */
  1978. void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
  1979. {
  1980. struct ata_port *ap = qc->ap;
  1981. unsigned long flags;
  1982. spin_lock_irqsave(ap->lock, flags);
  1983. ap->hsm_task_state = HSM_ST_IDLE;
  1984. if (ap->ioaddr.bmdma_addr)
  1985. ata_bmdma_stop(qc);
  1986. spin_unlock_irqrestore(ap->lock, flags);
  1987. }
  1988. EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
  1989. /**
  1990. * ata_sff_port_start - Set port up for dma.
  1991. * @ap: Port to initialize
  1992. *
  1993. * Called just after data structures for each port are
  1994. * initialized. Allocates space for PRD table if the device
  1995. * is DMA capable SFF.
  1996. *
  1997. * May be used as the port_start() entry in ata_port_operations.
  1998. *
  1999. * LOCKING:
  2000. * Inherited from caller.
  2001. */
  2002. int ata_sff_port_start(struct ata_port *ap)
  2003. {
  2004. if (ap->ioaddr.bmdma_addr)
  2005. return ata_port_start(ap);
  2006. return 0;
  2007. }
  2008. EXPORT_SYMBOL_GPL(ata_sff_port_start);
  2009. /**
  2010. * ata_sff_std_ports - initialize ioaddr with standard port offsets.
  2011. * @ioaddr: IO address structure to be initialized
  2012. *
  2013. * Utility function which initializes data_addr, error_addr,
  2014. * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
  2015. * device_addr, status_addr, and command_addr to standard offsets
  2016. * relative to cmd_addr.
  2017. *
  2018. * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
  2019. */
  2020. void ata_sff_std_ports(struct ata_ioports *ioaddr)
  2021. {
  2022. ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
  2023. ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
  2024. ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
  2025. ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
  2026. ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
  2027. ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
  2028. ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
  2029. ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
  2030. ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
  2031. ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
  2032. }
  2033. EXPORT_SYMBOL_GPL(ata_sff_std_ports);
  2034. unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
  2035. unsigned long xfer_mask)
  2036. {
  2037. /* Filter out DMA modes if the device has been configured by
  2038. the BIOS as PIO only */
  2039. if (adev->link->ap->ioaddr.bmdma_addr == NULL)
  2040. xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
  2041. return xfer_mask;
  2042. }
  2043. EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
  2044. /**
  2045. * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
  2046. * @qc: Info associated with this ATA transaction.
  2047. *
  2048. * LOCKING:
  2049. * spin_lock_irqsave(host lock)
  2050. */
  2051. void ata_bmdma_setup(struct ata_queued_cmd *qc)
  2052. {
  2053. struct ata_port *ap = qc->ap;
  2054. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  2055. u8 dmactl;
  2056. /* load PRD table addr. */
  2057. mb(); /* make sure PRD table writes are visible to controller */
  2058. iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
  2059. /* specify data direction, triple-check start bit is clear */
  2060. dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2061. dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
  2062. if (!rw)
  2063. dmactl |= ATA_DMA_WR;
  2064. iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2065. /* issue r/w command */
  2066. ap->ops->sff_exec_command(ap, &qc->tf);
  2067. }
  2068. EXPORT_SYMBOL_GPL(ata_bmdma_setup);
  2069. /**
  2070. * ata_bmdma_start - Start a PCI IDE BMDMA transaction
  2071. * @qc: Info associated with this ATA transaction.
  2072. *
  2073. * LOCKING:
  2074. * spin_lock_irqsave(host lock)
  2075. */
  2076. void ata_bmdma_start(struct ata_queued_cmd *qc)
  2077. {
  2078. struct ata_port *ap = qc->ap;
  2079. u8 dmactl;
  2080. /* start host DMA transaction */
  2081. dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2082. iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  2083. /* Strictly, one may wish to issue an ioread8() here, to
  2084. * flush the mmio write. However, control also passes
  2085. * to the hardware at this point, and it will interrupt
  2086. * us when we are to resume control. So, in effect,
  2087. * we don't care when the mmio write flushes.
  2088. * Further, a read of the DMA status register _immediately_
  2089. * following the write may not be what certain flaky hardware
  2090. * is expected, so I think it is best to not add a readb()
  2091. * without first all the MMIO ATA cards/mobos.
  2092. * Or maybe I'm just being paranoid.
  2093. *
  2094. * FIXME: The posting of this write means I/O starts are
  2095. * unneccessarily delayed for MMIO
  2096. */
  2097. }
  2098. EXPORT_SYMBOL_GPL(ata_bmdma_start);
  2099. /**
  2100. * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
  2101. * @qc: Command we are ending DMA for
  2102. *
  2103. * Clears the ATA_DMA_START flag in the dma control register
  2104. *
  2105. * May be used as the bmdma_stop() entry in ata_port_operations.
  2106. *
  2107. * LOCKING:
  2108. * spin_lock_irqsave(host lock)
  2109. */
  2110. void ata_bmdma_stop(struct ata_queued_cmd *qc)
  2111. {
  2112. struct ata_port *ap = qc->ap;
  2113. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  2114. /* clear start/stop bit */
  2115. iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
  2116. mmio + ATA_DMA_CMD);
  2117. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  2118. ata_sff_dma_pause(ap);
  2119. }
  2120. EXPORT_SYMBOL_GPL(ata_bmdma_stop);
  2121. /**
  2122. * ata_bmdma_status - Read PCI IDE BMDMA status
  2123. * @ap: Port associated with this ATA transaction.
  2124. *
  2125. * Read and return BMDMA status register.
  2126. *
  2127. * May be used as the bmdma_status() entry in ata_port_operations.
  2128. *
  2129. * LOCKING:
  2130. * spin_lock_irqsave(host lock)
  2131. */
  2132. u8 ata_bmdma_status(struct ata_port *ap)
  2133. {
  2134. return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  2135. }
  2136. EXPORT_SYMBOL_GPL(ata_bmdma_status);
  2137. /**
  2138. * ata_bus_reset - reset host port and associated ATA channel
  2139. * @ap: port to reset
  2140. *
  2141. * This is typically the first time we actually start issuing
  2142. * commands to the ATA channel. We wait for BSY to clear, then
  2143. * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
  2144. * result. Determine what devices, if any, are on the channel
  2145. * by looking at the device 0/1 error register. Look at the signature
  2146. * stored in each device's taskfile registers, to determine if
  2147. * the device is ATA or ATAPI.
  2148. *
  2149. * LOCKING:
  2150. * PCI/etc. bus probe sem.
  2151. * Obtains host lock.
  2152. *
  2153. * SIDE EFFECTS:
  2154. * Sets ATA_FLAG_DISABLED if bus reset fails.
  2155. *
  2156. * DEPRECATED:
  2157. * This function is only for drivers which still use old EH and
  2158. * will be removed soon.
  2159. */
  2160. void ata_bus_reset(struct ata_port *ap)
  2161. {
  2162. struct ata_device *device = ap->link.device;
  2163. struct ata_ioports *ioaddr = &ap->ioaddr;
  2164. unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
  2165. u8 err;
  2166. unsigned int dev0, dev1 = 0, devmask = 0;
  2167. int rc;
  2168. DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
  2169. /* determine if device 0/1 are present */
  2170. if (ap->flags & ATA_FLAG_SATA_RESET)
  2171. dev0 = 1;
  2172. else {
  2173. dev0 = ata_devchk(ap, 0);
  2174. if (slave_possible)
  2175. dev1 = ata_devchk(ap, 1);
  2176. }
  2177. if (dev0)
  2178. devmask |= (1 << 0);
  2179. if (dev1)
  2180. devmask |= (1 << 1);
  2181. /* select device 0 again */
  2182. ap->ops->sff_dev_select(ap, 0);
  2183. /* issue bus reset */
  2184. if (ap->flags & ATA_FLAG_SRST) {
  2185. rc = ata_bus_softreset(ap, devmask,
  2186. ata_deadline(jiffies, 40000));
  2187. if (rc && rc != -ENODEV)
  2188. goto err_out;
  2189. }
  2190. /*
  2191. * determine by signature whether we have ATA or ATAPI devices
  2192. */
  2193. device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
  2194. if ((slave_possible) && (err != 0x81))
  2195. device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
  2196. /* is double-select really necessary? */
  2197. if (device[1].class != ATA_DEV_NONE)
  2198. ap->ops->sff_dev_select(ap, 1);
  2199. if (device[0].class != ATA_DEV_NONE)
  2200. ap->ops->sff_dev_select(ap, 0);
  2201. /* if no devices were detected, disable this port */
  2202. if ((device[0].class == ATA_DEV_NONE) &&
  2203. (device[1].class == ATA_DEV_NONE))
  2204. goto err_out;
  2205. if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
  2206. /* set up device control for ATA_FLAG_SATA_RESET */
  2207. iowrite8(ap->ctl, ioaddr->ctl_addr);
  2208. ap->last_ctl = ap->ctl;
  2209. }
  2210. DPRINTK("EXIT\n");
  2211. return;
  2212. err_out:
  2213. ata_port_printk(ap, KERN_ERR, "disabling port\n");
  2214. ata_port_disable(ap);
  2215. DPRINTK("EXIT\n");
  2216. }
  2217. EXPORT_SYMBOL_GPL(ata_bus_reset);
  2218. #ifdef CONFIG_PCI
  2219. /**
  2220. * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
  2221. * @pdev: PCI device
  2222. *
  2223. * Some PCI ATA devices report simplex mode but in fact can be told to
  2224. * enter non simplex mode. This implements the necessary logic to
  2225. * perform the task on such devices. Calling it on other devices will
  2226. * have -undefined- behaviour.
  2227. */
  2228. int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
  2229. {
  2230. unsigned long bmdma = pci_resource_start(pdev, 4);
  2231. u8 simplex;
  2232. if (bmdma == 0)
  2233. return -ENOENT;
  2234. simplex = inb(bmdma + 0x02);
  2235. outb(simplex & 0x60, bmdma + 0x02);
  2236. simplex = inb(bmdma + 0x02);
  2237. if (simplex & 0x80)
  2238. return -EOPNOTSUPP;
  2239. return 0;
  2240. }
  2241. EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
  2242. /**
  2243. * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
  2244. * @host: target ATA host
  2245. *
  2246. * Acquire PCI BMDMA resources and initialize @host accordingly.
  2247. *
  2248. * LOCKING:
  2249. * Inherited from calling layer (may sleep).
  2250. *
  2251. * RETURNS:
  2252. * 0 on success, -errno otherwise.
  2253. */
  2254. int ata_pci_bmdma_init(struct ata_host *host)
  2255. {
  2256. struct device *gdev = host->dev;
  2257. struct pci_dev *pdev = to_pci_dev(gdev);
  2258. int i, rc;
  2259. /* No BAR4 allocation: No DMA */
  2260. if (pci_resource_start(pdev, 4) == 0)
  2261. return 0;
  2262. /* TODO: If we get no DMA mask we should fall back to PIO */
  2263. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  2264. if (rc)
  2265. return rc;
  2266. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  2267. if (rc)
  2268. return rc;
  2269. /* request and iomap DMA region */
  2270. rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
  2271. if (rc) {
  2272. dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
  2273. return -ENOMEM;
  2274. }
  2275. host->iomap = pcim_iomap_table(pdev);
  2276. for (i = 0; i < 2; i++) {
  2277. struct ata_port *ap = host->ports[i];
  2278. void __iomem *bmdma = host->iomap[4] + 8 * i;
  2279. if (ata_port_is_dummy(ap))
  2280. continue;
  2281. ap->ioaddr.bmdma_addr = bmdma;
  2282. if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
  2283. (ioread8(bmdma + 2) & 0x80))
  2284. host->flags |= ATA_HOST_SIMPLEX;
  2285. ata_port_desc(ap, "bmdma 0x%llx",
  2286. (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
  2287. }
  2288. return 0;
  2289. }
  2290. EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
  2291. static int ata_resources_present(struct pci_dev *pdev, int port)
  2292. {
  2293. int i;
  2294. /* Check the PCI resources for this channel are enabled */
  2295. port = port * 2;
  2296. for (i = 0; i < 2; i++) {
  2297. if (pci_resource_start(pdev, port + i) == 0 ||
  2298. pci_resource_len(pdev, port + i) == 0)
  2299. return 0;
  2300. }
  2301. return 1;
  2302. }
  2303. /**
  2304. * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
  2305. * @host: target ATA host
  2306. *
  2307. * Acquire native PCI ATA resources for @host and initialize the
  2308. * first two ports of @host accordingly. Ports marked dummy are
  2309. * skipped and allocation failure makes the port dummy.
  2310. *
  2311. * Note that native PCI resources are valid even for legacy hosts
  2312. * as we fix up pdev resources array early in boot, so this
  2313. * function can be used for both native and legacy SFF hosts.
  2314. *
  2315. * LOCKING:
  2316. * Inherited from calling layer (may sleep).
  2317. *
  2318. * RETURNS:
  2319. * 0 if at least one port is initialized, -ENODEV if no port is
  2320. * available.
  2321. */
  2322. int ata_pci_sff_init_host(struct ata_host *host)
  2323. {
  2324. struct device *gdev = host->dev;
  2325. struct pci_dev *pdev = to_pci_dev(gdev);
  2326. unsigned int mask = 0;
  2327. int i, rc;
  2328. /* request, iomap BARs and init port addresses accordingly */
  2329. for (i = 0; i < 2; i++) {
  2330. struct ata_port *ap = host->ports[i];
  2331. int base = i * 2;
  2332. void __iomem * const *iomap;
  2333. if (ata_port_is_dummy(ap))
  2334. continue;
  2335. /* Discard disabled ports. Some controllers show
  2336. * their unused channels this way. Disabled ports are
  2337. * made dummy.
  2338. */
  2339. if (!ata_resources_present(pdev, i)) {
  2340. ap->ops = &ata_dummy_port_ops;
  2341. continue;
  2342. }
  2343. rc = pcim_iomap_regions(pdev, 0x3 << base,
  2344. dev_driver_string(gdev));
  2345. if (rc) {
  2346. dev_printk(KERN_WARNING, gdev,
  2347. "failed to request/iomap BARs for port %d "
  2348. "(errno=%d)\n", i, rc);
  2349. if (rc == -EBUSY)
  2350. pcim_pin_device(pdev);
  2351. ap->ops = &ata_dummy_port_ops;
  2352. continue;
  2353. }
  2354. host->iomap = iomap = pcim_iomap_table(pdev);
  2355. ap->ioaddr.cmd_addr = iomap[base];
  2356. ap->ioaddr.altstatus_addr =
  2357. ap->ioaddr.ctl_addr = (void __iomem *)
  2358. ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
  2359. ata_sff_std_ports(&ap->ioaddr);
  2360. ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
  2361. (unsigned long long)pci_resource_start(pdev, base),
  2362. (unsigned long long)pci_resource_start(pdev, base + 1));
  2363. mask |= 1 << i;
  2364. }
  2365. if (!mask) {
  2366. dev_printk(KERN_ERR, gdev, "no available native port\n");
  2367. return -ENODEV;
  2368. }
  2369. return 0;
  2370. }
  2371. EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
  2372. /**
  2373. * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
  2374. * @pdev: target PCI device
  2375. * @ppi: array of port_info, must be enough for two ports
  2376. * @r_host: out argument for the initialized ATA host
  2377. *
  2378. * Helper to allocate ATA host for @pdev, acquire all native PCI
  2379. * resources and initialize it accordingly in one go.
  2380. *
  2381. * LOCKING:
  2382. * Inherited from calling layer (may sleep).
  2383. *
  2384. * RETURNS:
  2385. * 0 on success, -errno otherwise.
  2386. */
  2387. int ata_pci_sff_prepare_host(struct pci_dev *pdev,
  2388. const struct ata_port_info * const *ppi,
  2389. struct ata_host **r_host)
  2390. {
  2391. struct ata_host *host;
  2392. int rc;
  2393. if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
  2394. return -ENOMEM;
  2395. host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
  2396. if (!host) {
  2397. dev_printk(KERN_ERR, &pdev->dev,
  2398. "failed to allocate ATA host\n");
  2399. rc = -ENOMEM;
  2400. goto err_out;
  2401. }
  2402. rc = ata_pci_sff_init_host(host);
  2403. if (rc)
  2404. goto err_out;
  2405. /* init DMA related stuff */
  2406. rc = ata_pci_bmdma_init(host);
  2407. if (rc)
  2408. goto err_bmdma;
  2409. devres_remove_group(&pdev->dev, NULL);
  2410. *r_host = host;
  2411. return 0;
  2412. err_bmdma:
  2413. /* This is necessary because PCI and iomap resources are
  2414. * merged and releasing the top group won't release the
  2415. * acquired resources if some of those have been acquired
  2416. * before entering this function.
  2417. */
  2418. pcim_iounmap_regions(pdev, 0xf);
  2419. err_out:
  2420. devres_release_group(&pdev->dev, NULL);
  2421. return rc;
  2422. }
  2423. EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
  2424. /**
  2425. * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
  2426. * @host: target SFF ATA host
  2427. * @irq_handler: irq_handler used when requesting IRQ(s)
  2428. * @sht: scsi_host_template to use when registering the host
  2429. *
  2430. * This is the counterpart of ata_host_activate() for SFF ATA
  2431. * hosts. This separate helper is necessary because SFF hosts
  2432. * use two separate interrupts in legacy mode.
  2433. *
  2434. * LOCKING:
  2435. * Inherited from calling layer (may sleep).
  2436. *
  2437. * RETURNS:
  2438. * 0 on success, -errno otherwise.
  2439. */
  2440. int ata_pci_sff_activate_host(struct ata_host *host,
  2441. irq_handler_t irq_handler,
  2442. struct scsi_host_template *sht)
  2443. {
  2444. struct device *dev = host->dev;
  2445. struct pci_dev *pdev = to_pci_dev(dev);
  2446. const char *drv_name = dev_driver_string(host->dev);
  2447. int legacy_mode = 0, rc;
  2448. rc = ata_host_start(host);
  2449. if (rc)
  2450. return rc;
  2451. if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
  2452. u8 tmp8, mask;
  2453. /* TODO: What if one channel is in native mode ... */
  2454. pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
  2455. mask = (1 << 2) | (1 << 0);
  2456. if ((tmp8 & mask) != mask)
  2457. legacy_mode = 1;
  2458. #if defined(CONFIG_NO_ATA_LEGACY)
  2459. /* Some platforms with PCI limits cannot address compat
  2460. port space. In that case we punt if their firmware has
  2461. left a device in compatibility mode */
  2462. if (legacy_mode) {
  2463. printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
  2464. return -EOPNOTSUPP;
  2465. }
  2466. #endif
  2467. }
  2468. if (!devres_open_group(dev, NULL, GFP_KERNEL))
  2469. return -ENOMEM;
  2470. if (!legacy_mode && pdev->irq) {
  2471. rc = devm_request_irq(dev, pdev->irq, irq_handler,
  2472. IRQF_SHARED, drv_name, host);
  2473. if (rc)
  2474. goto out;
  2475. ata_port_desc(host->ports[0], "irq %d", pdev->irq);
  2476. ata_port_desc(host->ports[1], "irq %d", pdev->irq);
  2477. } else if (legacy_mode) {
  2478. if (!ata_port_is_dummy(host->ports[0])) {
  2479. rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
  2480. irq_handler, IRQF_SHARED,
  2481. drv_name, host);
  2482. if (rc)
  2483. goto out;
  2484. ata_port_desc(host->ports[0], "irq %d",
  2485. ATA_PRIMARY_IRQ(pdev));
  2486. }
  2487. if (!ata_port_is_dummy(host->ports[1])) {
  2488. rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
  2489. irq_handler, IRQF_SHARED,
  2490. drv_name, host);
  2491. if (rc)
  2492. goto out;
  2493. ata_port_desc(host->ports[1], "irq %d",
  2494. ATA_SECONDARY_IRQ(pdev));
  2495. }
  2496. }
  2497. rc = ata_host_register(host, sht);
  2498. out:
  2499. if (rc == 0)
  2500. devres_remove_group(dev, NULL);
  2501. else
  2502. devres_release_group(dev, NULL);
  2503. return rc;
  2504. }
  2505. EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
  2506. /**
  2507. * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
  2508. * @pdev: Controller to be initialized
  2509. * @ppi: array of port_info, must be enough for two ports
  2510. * @sht: scsi_host_template to use when registering the host
  2511. * @host_priv: host private_data
  2512. *
  2513. * This is a helper function which can be called from a driver's
  2514. * xxx_init_one() probe function if the hardware uses traditional
  2515. * IDE taskfile registers.
  2516. *
  2517. * This function calls pci_enable_device(), reserves its register
  2518. * regions, sets the dma mask, enables bus master mode, and calls
  2519. * ata_device_add()
  2520. *
  2521. * ASSUMPTION:
  2522. * Nobody makes a single channel controller that appears solely as
  2523. * the secondary legacy port on PCI.
  2524. *
  2525. * LOCKING:
  2526. * Inherited from PCI layer (may sleep).
  2527. *
  2528. * RETURNS:
  2529. * Zero on success, negative on errno-based value on error.
  2530. */
  2531. int ata_pci_sff_init_one(struct pci_dev *pdev,
  2532. const struct ata_port_info * const *ppi,
  2533. struct scsi_host_template *sht, void *host_priv)
  2534. {
  2535. struct device *dev = &pdev->dev;
  2536. const struct ata_port_info *pi = NULL;
  2537. struct ata_host *host = NULL;
  2538. int i, rc;
  2539. DPRINTK("ENTER\n");
  2540. /* look up the first valid port_info */
  2541. for (i = 0; i < 2 && ppi[i]; i++) {
  2542. if (ppi[i]->port_ops != &ata_dummy_port_ops) {
  2543. pi = ppi[i];
  2544. break;
  2545. }
  2546. }
  2547. if (!pi) {
  2548. dev_printk(KERN_ERR, &pdev->dev,
  2549. "no valid port_info specified\n");
  2550. return -EINVAL;
  2551. }
  2552. if (!devres_open_group(dev, NULL, GFP_KERNEL))
  2553. return -ENOMEM;
  2554. rc = pcim_enable_device(pdev);
  2555. if (rc)
  2556. goto out;
  2557. /* prepare and activate SFF host */
  2558. rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
  2559. if (rc)
  2560. goto out;
  2561. host->private_data = host_priv;
  2562. pci_set_master(pdev);
  2563. rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
  2564. out:
  2565. if (rc == 0)
  2566. devres_remove_group(&pdev->dev, NULL);
  2567. else
  2568. devres_release_group(&pdev->dev, NULL);
  2569. return rc;
  2570. }
  2571. EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
  2572. #endif /* CONFIG_PCI */