mpc832x_rdb.c 4.5 KB

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  1. /*
  2. * arch/powerpc/platforms/83xx/mpc832x_rdb.c
  3. *
  4. * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
  5. *
  6. * Description:
  7. * MPC832x RDB board specific routines.
  8. * This file is based on mpc832x_mds.c and mpc8313_rdb.c
  9. * Author: Michael Barkowski <michael.barkowski@freescale.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. #include <linux/pci.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/mmc_spi.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/of_platform.h>
  22. #include <asm/time.h>
  23. #include <asm/ipic.h>
  24. #include <asm/udbg.h>
  25. #include <asm/qe.h>
  26. #include <asm/qe_ic.h>
  27. #include <sysdev/fsl_soc.h>
  28. #include <sysdev/fsl_pci.h>
  29. #include "mpc83xx.h"
  30. #undef DEBUG
  31. #ifdef DEBUG
  32. #define DBG(fmt...) udbg_printf(fmt)
  33. #else
  34. #define DBG(fmt...)
  35. #endif
  36. #ifdef CONFIG_QUICC_ENGINE
  37. static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity)
  38. {
  39. pr_debug("%s %d %d\n", __func__, cs, polarity);
  40. par_io_data_set(3, 13, polarity);
  41. }
  42. static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity)
  43. {
  44. pr_debug("%s %d %d\n", __func__, cs, polarity);
  45. par_io_data_set(3, 13, !polarity);
  46. }
  47. static struct mmc_spi_platform_data mpc832x_mmc_pdata = {
  48. .ocr_mask = MMC_VDD_33_34,
  49. };
  50. static struct spi_board_info mpc832x_spi_boardinfo = {
  51. .bus_num = 0x4c0,
  52. .chip_select = 0,
  53. .max_speed_hz = 50000000,
  54. .modalias = "mmc_spi",
  55. .platform_data = &mpc832x_mmc_pdata,
  56. };
  57. static int __init mpc832x_spi_init(void)
  58. {
  59. par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
  60. par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
  61. par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
  62. par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
  63. par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
  64. par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
  65. par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
  66. return fsl_spi_init(&mpc832x_spi_boardinfo, 1,
  67. mpc83xx_spi_activate_cs,
  68. mpc83xx_spi_deactivate_cs);
  69. }
  70. machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
  71. #endif /* CONFIG_QUICC_ENGINE */
  72. /* ************************************************************************
  73. *
  74. * Setup the architecture
  75. *
  76. */
  77. static void __init mpc832x_rdb_setup_arch(void)
  78. {
  79. #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
  80. struct device_node *np;
  81. #endif
  82. if (ppc_md.progress)
  83. ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
  84. #ifdef CONFIG_PCI
  85. for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  86. mpc83xx_add_bridge(np);
  87. #endif
  88. #ifdef CONFIG_QUICC_ENGINE
  89. qe_reset();
  90. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  91. par_io_init(np);
  92. of_node_put(np);
  93. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  94. par_io_of_config(np);
  95. }
  96. #endif /* CONFIG_QUICC_ENGINE */
  97. }
  98. static struct of_device_id mpc832x_ids[] = {
  99. { .type = "soc", },
  100. { .compatible = "soc", },
  101. { .compatible = "simple-bus", },
  102. { .type = "qe", },
  103. { .compatible = "fsl,qe", },
  104. {},
  105. };
  106. static int __init mpc832x_declare_of_platform_devices(void)
  107. {
  108. /* Publish the QE devices */
  109. of_platform_bus_probe(NULL, mpc832x_ids, NULL);
  110. return 0;
  111. }
  112. machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices);
  113. static void __init mpc832x_rdb_init_IRQ(void)
  114. {
  115. struct device_node *np;
  116. np = of_find_node_by_type(NULL, "ipic");
  117. if (!np)
  118. return;
  119. ipic_init(np, 0);
  120. /* Initialize the default interrupt mapping priorities,
  121. * in case the boot rom changed something on us.
  122. */
  123. ipic_set_default_priority();
  124. of_node_put(np);
  125. #ifdef CONFIG_QUICC_ENGINE
  126. np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  127. if (!np) {
  128. np = of_find_node_by_type(NULL, "qeic");
  129. if (!np)
  130. return;
  131. }
  132. qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
  133. of_node_put(np);
  134. #endif /* CONFIG_QUICC_ENGINE */
  135. }
  136. /*
  137. * Called very early, MMU is off, device-tree isn't unflattened
  138. */
  139. static int __init mpc832x_rdb_probe(void)
  140. {
  141. unsigned long root = of_get_flat_dt_root();
  142. return of_flat_dt_is_compatible(root, "MPC832xRDB");
  143. }
  144. define_machine(mpc832x_rdb) {
  145. .name = "MPC832x RDB",
  146. .probe = mpc832x_rdb_probe,
  147. .setup_arch = mpc832x_rdb_setup_arch,
  148. .init_IRQ = mpc832x_rdb_init_IRQ,
  149. .get_irq = ipic_get_irq,
  150. .restart = mpc83xx_restart,
  151. .time_init = mpc83xx_time_init,
  152. .calibrate_decr = generic_calibrate_decr,
  153. .progress = udbg_progress,
  154. };