devices.c 8.2 KB

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  1. /*
  2. * RouterBoard 500 Platform devices
  3. *
  4. * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  5. * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/ctype.h>
  20. #include <linux/string.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/mtd/nand.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/gpio_keys.h>
  26. #include <linux/input.h>
  27. #include <linux/serial_8250.h>
  28. #include <asm/bootinfo.h>
  29. #include <asm/mach-rc32434/rc32434.h>
  30. #include <asm/mach-rc32434/dma.h>
  31. #include <asm/mach-rc32434/dma_v.h>
  32. #include <asm/mach-rc32434/eth.h>
  33. #include <asm/mach-rc32434/rb.h>
  34. #include <asm/mach-rc32434/integ.h>
  35. #include <asm/mach-rc32434/gpio.h>
  36. #include <asm/mach-rc32434/irq.h>
  37. #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
  38. #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
  39. extern unsigned int idt_cpu_freq;
  40. static struct mpmc_device dev3;
  41. void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
  42. {
  43. unsigned long flags;
  44. spin_lock_irqsave(&dev3.lock, flags);
  45. dev3.state = (dev3.state | or_mask) & ~nand_mask;
  46. writeb(dev3.state, dev3.base);
  47. spin_unlock_irqrestore(&dev3.lock, flags);
  48. }
  49. EXPORT_SYMBOL(set_latch_u5);
  50. unsigned char get_latch_u5(void)
  51. {
  52. return dev3.state;
  53. }
  54. EXPORT_SYMBOL(get_latch_u5);
  55. static struct resource korina_dev0_res[] = {
  56. {
  57. .name = "korina_regs",
  58. .start = ETH0_BASE_ADDR,
  59. .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
  60. .flags = IORESOURCE_MEM,
  61. }, {
  62. .name = "korina_rx",
  63. .start = ETH0_DMA_RX_IRQ,
  64. .end = ETH0_DMA_RX_IRQ,
  65. .flags = IORESOURCE_IRQ
  66. }, {
  67. .name = "korina_tx",
  68. .start = ETH0_DMA_TX_IRQ,
  69. .end = ETH0_DMA_TX_IRQ,
  70. .flags = IORESOURCE_IRQ
  71. }, {
  72. .name = "korina_ovr",
  73. .start = ETH0_RX_OVR_IRQ,
  74. .end = ETH0_RX_OVR_IRQ,
  75. .flags = IORESOURCE_IRQ
  76. }, {
  77. .name = "korina_und",
  78. .start = ETH0_TX_UND_IRQ,
  79. .end = ETH0_TX_UND_IRQ,
  80. .flags = IORESOURCE_IRQ
  81. }, {
  82. .name = "korina_dma_rx",
  83. .start = ETH0_RX_DMA_ADDR,
  84. .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  85. .flags = IORESOURCE_MEM,
  86. }, {
  87. .name = "korina_dma_tx",
  88. .start = ETH0_TX_DMA_ADDR,
  89. .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  90. .flags = IORESOURCE_MEM,
  91. }
  92. };
  93. static struct korina_device korina_dev0_data = {
  94. .name = "korina0",
  95. .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
  96. };
  97. static struct platform_device korina_dev0 = {
  98. .id = -1,
  99. .name = "korina",
  100. .dev.driver_data = &korina_dev0_data,
  101. .resource = korina_dev0_res,
  102. .num_resources = ARRAY_SIZE(korina_dev0_res),
  103. };
  104. static struct resource cf_slot0_res[] = {
  105. {
  106. .name = "cf_membase",
  107. .flags = IORESOURCE_MEM
  108. }, {
  109. .name = "cf_irq",
  110. .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
  111. .end = (8 + 4 * 32 + CF_GPIO_NUM),
  112. .flags = IORESOURCE_IRQ
  113. }
  114. };
  115. static struct cf_device cf_slot0_data = {
  116. .gpio_pin = CF_GPIO_NUM
  117. };
  118. static struct platform_device cf_slot0 = {
  119. .id = -1,
  120. .name = "pata-rb532-cf",
  121. .dev.platform_data = &cf_slot0_data,
  122. .resource = cf_slot0_res,
  123. .num_resources = ARRAY_SIZE(cf_slot0_res),
  124. };
  125. /* Resources and device for NAND */
  126. static int rb532_dev_ready(struct mtd_info *mtd)
  127. {
  128. return gpio_get_value(GPIO_RDY);
  129. }
  130. static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  131. {
  132. struct nand_chip *chip = mtd->priv;
  133. unsigned char orbits, nandbits;
  134. if (ctrl & NAND_CTRL_CHANGE) {
  135. orbits = (ctrl & NAND_CLE) << 1;
  136. orbits |= (ctrl & NAND_ALE) >> 1;
  137. nandbits = (~ctrl & NAND_CLE) << 1;
  138. nandbits |= (~ctrl & NAND_ALE) >> 1;
  139. set_latch_u5(orbits, nandbits);
  140. }
  141. if (cmd != NAND_CMD_NONE)
  142. writeb(cmd, chip->IO_ADDR_W);
  143. }
  144. static struct resource nand_slot0_res[] = {
  145. [0] = {
  146. .name = "nand_membase",
  147. .flags = IORESOURCE_MEM
  148. }
  149. };
  150. static struct platform_nand_data rb532_nand_data = {
  151. .ctrl.dev_ready = rb532_dev_ready,
  152. .ctrl.cmd_ctrl = rb532_cmd_ctrl,
  153. };
  154. static struct platform_device nand_slot0 = {
  155. .name = "gen_nand",
  156. .id = -1,
  157. .resource = nand_slot0_res,
  158. .num_resources = ARRAY_SIZE(nand_slot0_res),
  159. .dev.platform_data = &rb532_nand_data,
  160. };
  161. static struct mtd_partition rb532_partition_info[] = {
  162. {
  163. .name = "Routerboard NAND boot",
  164. .offset = 0,
  165. .size = 4 * 1024 * 1024,
  166. }, {
  167. .name = "rootfs",
  168. .offset = MTDPART_OFS_NXTBLK,
  169. .size = MTDPART_SIZ_FULL,
  170. }
  171. };
  172. static struct platform_device rb532_led = {
  173. .name = "rb532-led",
  174. .id = -1,
  175. };
  176. static struct gpio_keys_button rb532_gpio_btn[] = {
  177. {
  178. .gpio = 1,
  179. .code = BTN_0,
  180. .desc = "S1",
  181. .active_low = 1,
  182. }
  183. };
  184. static struct gpio_keys_platform_data rb532_gpio_btn_data = {
  185. .buttons = rb532_gpio_btn,
  186. .nbuttons = ARRAY_SIZE(rb532_gpio_btn),
  187. };
  188. static struct platform_device rb532_button = {
  189. .name = "gpio-keys",
  190. .id = -1,
  191. .dev = {
  192. .platform_data = &rb532_gpio_btn_data,
  193. }
  194. };
  195. static struct resource rb532_wdt_res[] = {
  196. {
  197. .name = "rb532_wdt_res",
  198. .start = INTEG0_BASE_ADDR,
  199. .end = INTEG0_BASE_ADDR + sizeof(struct integ),
  200. .flags = IORESOURCE_MEM,
  201. }
  202. };
  203. static struct platform_device rb532_wdt = {
  204. .name = "rc32434_wdt",
  205. .id = -1,
  206. .resource = rb532_wdt_res,
  207. .num_resources = ARRAY_SIZE(rb532_wdt_res),
  208. };
  209. static struct plat_serial8250_port rb532_uart_res[] = {
  210. {
  211. .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
  212. .irq = UART0_IRQ,
  213. .regshift = 2,
  214. .iotype = UPIO_MEM,
  215. .flags = UPF_BOOT_AUTOCONF,
  216. },
  217. {
  218. .flags = 0,
  219. }
  220. };
  221. static struct platform_device rb532_uart = {
  222. .name = "serial8250",
  223. .id = PLAT8250_DEV_PLATFORM,
  224. .dev.platform_data = &rb532_uart_res,
  225. };
  226. static struct platform_device *rb532_devs[] = {
  227. &korina_dev0,
  228. &nand_slot0,
  229. &cf_slot0,
  230. &rb532_led,
  231. &rb532_button,
  232. &rb532_uart,
  233. &rb532_wdt
  234. };
  235. static void __init parse_mac_addr(char *macstr)
  236. {
  237. int i, j;
  238. unsigned char result, value;
  239. for (i = 0; i < 6; i++) {
  240. result = 0;
  241. if (i != 5 && *(macstr + 2) != ':')
  242. return;
  243. for (j = 0; j < 2; j++) {
  244. if (isxdigit(*macstr)
  245. && (value =
  246. isdigit(*macstr) ? *macstr -
  247. '0' : toupper(*macstr) - 'A' + 10) < 16) {
  248. result = result * 16 + value;
  249. macstr++;
  250. } else
  251. return;
  252. }
  253. macstr++;
  254. korina_dev0_data.mac[i] = result;
  255. }
  256. }
  257. /* NAND definitions */
  258. #define NAND_CHIP_DELAY 25
  259. static void __init rb532_nand_setup(void)
  260. {
  261. switch (mips_machtype) {
  262. case MACH_MIKROTIK_RB532A:
  263. set_latch_u5(LO_FOFF | LO_CEX,
  264. LO_ULED | LO_ALE | LO_CLE | LO_WPX);
  265. break;
  266. default:
  267. set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
  268. LO_ULED | LO_ALE | LO_CLE);
  269. break;
  270. }
  271. /* Setup NAND specific settings */
  272. rb532_nand_data.chip.nr_chips = 1;
  273. rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
  274. rb532_nand_data.chip.partitions = rb532_partition_info;
  275. rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
  276. rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
  277. }
  278. static int __init plat_setup_devices(void)
  279. {
  280. /* Look for the CF card reader */
  281. if (!readl(IDT434_REG_BASE + DEV1MASK))
  282. rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
  283. else {
  284. cf_slot0_res[0].start =
  285. readl(IDT434_REG_BASE + DEV1BASE);
  286. cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
  287. }
  288. /* Read the NAND resources from the device controller */
  289. nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
  290. nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
  291. /* Read and map device controller 3 */
  292. dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
  293. if (!dev3.base) {
  294. printk(KERN_ERR "rb532: cannot remap device controller 3\n");
  295. return -ENXIO;
  296. }
  297. /* Initialise the NAND device */
  298. rb532_nand_setup();
  299. /* set the uart clock to the current cpu frequency */
  300. rb532_uart_res[0].uartclk = idt_cpu_freq;
  301. return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
  302. }
  303. static int __init setup_kmac(char *s)
  304. {
  305. printk(KERN_INFO "korina mac = %s\n", s);
  306. parse_mac_addr(s);
  307. return 0;
  308. }
  309. __setup("kmac=", setup_kmac);
  310. arch_initcall(plat_setup_devices);