intel_pm.c 113 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125
  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. *
  26. */
  27. #include <linux/cpufreq.h>
  28. #include "i915_drv.h"
  29. #include "intel_drv.h"
  30. #include "../../../platform/x86/intel_ips.h"
  31. #include <linux/module.h>
  32. /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  33. * framebuffer contents in-memory, aiming at reducing the required bandwidth
  34. * during in-memory transfers and, therefore, reduce the power packet.
  35. *
  36. * The benefits of FBC are mostly visible with solid backgrounds and
  37. * variation-less patterns.
  38. *
  39. * FBC-related functionality can be enabled by the means of the
  40. * i915.i915_enable_fbc parameter
  41. */
  42. static void i8xx_disable_fbc(struct drm_device *dev)
  43. {
  44. struct drm_i915_private *dev_priv = dev->dev_private;
  45. u32 fbc_ctl;
  46. /* Disable compression */
  47. fbc_ctl = I915_READ(FBC_CONTROL);
  48. if ((fbc_ctl & FBC_CTL_EN) == 0)
  49. return;
  50. fbc_ctl &= ~FBC_CTL_EN;
  51. I915_WRITE(FBC_CONTROL, fbc_ctl);
  52. /* Wait for compressing bit to clear */
  53. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  54. DRM_DEBUG_KMS("FBC idle timed out\n");
  55. return;
  56. }
  57. DRM_DEBUG_KMS("disabled FBC\n");
  58. }
  59. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  60. {
  61. struct drm_device *dev = crtc->dev;
  62. struct drm_i915_private *dev_priv = dev->dev_private;
  63. struct drm_framebuffer *fb = crtc->fb;
  64. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  65. struct drm_i915_gem_object *obj = intel_fb->obj;
  66. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  67. int cfb_pitch;
  68. int plane, i;
  69. u32 fbc_ctl, fbc_ctl2;
  70. cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  71. if (fb->pitches[0] < cfb_pitch)
  72. cfb_pitch = fb->pitches[0];
  73. /* FBC_CTL wants 64B units */
  74. cfb_pitch = (cfb_pitch / 64) - 1;
  75. plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  76. /* Clear old tags */
  77. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  78. I915_WRITE(FBC_TAG + (i * 4), 0);
  79. /* Set it up... */
  80. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  81. fbc_ctl2 |= plane;
  82. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  83. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  84. /* enable it... */
  85. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  86. if (IS_I945GM(dev))
  87. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  88. fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  89. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  90. fbc_ctl |= obj->fence_reg;
  91. I915_WRITE(FBC_CONTROL, fbc_ctl);
  92. DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
  93. cfb_pitch, crtc->y, intel_crtc->plane);
  94. }
  95. static bool i8xx_fbc_enabled(struct drm_device *dev)
  96. {
  97. struct drm_i915_private *dev_priv = dev->dev_private;
  98. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  99. }
  100. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  101. {
  102. struct drm_device *dev = crtc->dev;
  103. struct drm_i915_private *dev_priv = dev->dev_private;
  104. struct drm_framebuffer *fb = crtc->fb;
  105. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  106. struct drm_i915_gem_object *obj = intel_fb->obj;
  107. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  108. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  109. unsigned long stall_watermark = 200;
  110. u32 dpfc_ctl;
  111. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  112. dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  113. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  114. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  115. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  116. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  117. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  118. /* enable it... */
  119. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  120. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  121. }
  122. static void g4x_disable_fbc(struct drm_device *dev)
  123. {
  124. struct drm_i915_private *dev_priv = dev->dev_private;
  125. u32 dpfc_ctl;
  126. /* Disable compression */
  127. dpfc_ctl = I915_READ(DPFC_CONTROL);
  128. if (dpfc_ctl & DPFC_CTL_EN) {
  129. dpfc_ctl &= ~DPFC_CTL_EN;
  130. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  131. DRM_DEBUG_KMS("disabled FBC\n");
  132. }
  133. }
  134. static bool g4x_fbc_enabled(struct drm_device *dev)
  135. {
  136. struct drm_i915_private *dev_priv = dev->dev_private;
  137. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  138. }
  139. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  140. {
  141. struct drm_i915_private *dev_priv = dev->dev_private;
  142. u32 blt_ecoskpd;
  143. /* Make sure blitter notifies FBC of writes */
  144. gen6_gt_force_wake_get(dev_priv);
  145. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  146. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  147. GEN6_BLITTER_LOCK_SHIFT;
  148. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  149. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  150. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  151. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  152. GEN6_BLITTER_LOCK_SHIFT);
  153. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  154. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  155. gen6_gt_force_wake_put(dev_priv);
  156. }
  157. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  158. {
  159. struct drm_device *dev = crtc->dev;
  160. struct drm_i915_private *dev_priv = dev->dev_private;
  161. struct drm_framebuffer *fb = crtc->fb;
  162. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  163. struct drm_i915_gem_object *obj = intel_fb->obj;
  164. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  165. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  166. unsigned long stall_watermark = 200;
  167. u32 dpfc_ctl;
  168. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  169. dpfc_ctl &= DPFC_RESERVED;
  170. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  171. /* Set persistent mode for front-buffer rendering, ala X. */
  172. dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  173. dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  174. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  175. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  176. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  177. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  178. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  179. I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  180. /* enable it... */
  181. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  182. if (IS_GEN6(dev)) {
  183. I915_WRITE(SNB_DPFC_CTL_SA,
  184. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  185. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  186. sandybridge_blit_fbc_update(dev);
  187. }
  188. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  189. }
  190. static void ironlake_disable_fbc(struct drm_device *dev)
  191. {
  192. struct drm_i915_private *dev_priv = dev->dev_private;
  193. u32 dpfc_ctl;
  194. /* Disable compression */
  195. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  196. if (dpfc_ctl & DPFC_CTL_EN) {
  197. dpfc_ctl &= ~DPFC_CTL_EN;
  198. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  199. DRM_DEBUG_KMS("disabled FBC\n");
  200. }
  201. }
  202. static bool ironlake_fbc_enabled(struct drm_device *dev)
  203. {
  204. struct drm_i915_private *dev_priv = dev->dev_private;
  205. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  206. }
  207. bool intel_fbc_enabled(struct drm_device *dev)
  208. {
  209. struct drm_i915_private *dev_priv = dev->dev_private;
  210. if (!dev_priv->display.fbc_enabled)
  211. return false;
  212. return dev_priv->display.fbc_enabled(dev);
  213. }
  214. static void intel_fbc_work_fn(struct work_struct *__work)
  215. {
  216. struct intel_fbc_work *work =
  217. container_of(to_delayed_work(__work),
  218. struct intel_fbc_work, work);
  219. struct drm_device *dev = work->crtc->dev;
  220. struct drm_i915_private *dev_priv = dev->dev_private;
  221. mutex_lock(&dev->struct_mutex);
  222. if (work == dev_priv->fbc_work) {
  223. /* Double check that we haven't switched fb without cancelling
  224. * the prior work.
  225. */
  226. if (work->crtc->fb == work->fb) {
  227. dev_priv->display.enable_fbc(work->crtc,
  228. work->interval);
  229. dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
  230. dev_priv->cfb_fb = work->crtc->fb->base.id;
  231. dev_priv->cfb_y = work->crtc->y;
  232. }
  233. dev_priv->fbc_work = NULL;
  234. }
  235. mutex_unlock(&dev->struct_mutex);
  236. kfree(work);
  237. }
  238. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  239. {
  240. if (dev_priv->fbc_work == NULL)
  241. return;
  242. DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  243. /* Synchronisation is provided by struct_mutex and checking of
  244. * dev_priv->fbc_work, so we can perform the cancellation
  245. * entirely asynchronously.
  246. */
  247. if (cancel_delayed_work(&dev_priv->fbc_work->work))
  248. /* tasklet was killed before being run, clean up */
  249. kfree(dev_priv->fbc_work);
  250. /* Mark the work as no longer wanted so that if it does
  251. * wake-up (because the work was already running and waiting
  252. * for our mutex), it will discover that is no longer
  253. * necessary to run.
  254. */
  255. dev_priv->fbc_work = NULL;
  256. }
  257. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  258. {
  259. struct intel_fbc_work *work;
  260. struct drm_device *dev = crtc->dev;
  261. struct drm_i915_private *dev_priv = dev->dev_private;
  262. if (!dev_priv->display.enable_fbc)
  263. return;
  264. intel_cancel_fbc_work(dev_priv);
  265. work = kzalloc(sizeof *work, GFP_KERNEL);
  266. if (work == NULL) {
  267. dev_priv->display.enable_fbc(crtc, interval);
  268. return;
  269. }
  270. work->crtc = crtc;
  271. work->fb = crtc->fb;
  272. work->interval = interval;
  273. INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  274. dev_priv->fbc_work = work;
  275. DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
  276. /* Delay the actual enabling to let pageflipping cease and the
  277. * display to settle before starting the compression. Note that
  278. * this delay also serves a second purpose: it allows for a
  279. * vblank to pass after disabling the FBC before we attempt
  280. * to modify the control registers.
  281. *
  282. * A more complicated solution would involve tracking vblanks
  283. * following the termination of the page-flipping sequence
  284. * and indeed performing the enable as a co-routine and not
  285. * waiting synchronously upon the vblank.
  286. */
  287. schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  288. }
  289. void intel_disable_fbc(struct drm_device *dev)
  290. {
  291. struct drm_i915_private *dev_priv = dev->dev_private;
  292. intel_cancel_fbc_work(dev_priv);
  293. if (!dev_priv->display.disable_fbc)
  294. return;
  295. dev_priv->display.disable_fbc(dev);
  296. dev_priv->cfb_plane = -1;
  297. }
  298. /**
  299. * intel_update_fbc - enable/disable FBC as needed
  300. * @dev: the drm_device
  301. *
  302. * Set up the framebuffer compression hardware at mode set time. We
  303. * enable it if possible:
  304. * - plane A only (on pre-965)
  305. * - no pixel mulitply/line duplication
  306. * - no alpha buffer discard
  307. * - no dual wide
  308. * - framebuffer <= 2048 in width, 1536 in height
  309. *
  310. * We can't assume that any compression will take place (worst case),
  311. * so the compressed buffer has to be the same size as the uncompressed
  312. * one. It also must reside (along with the line length buffer) in
  313. * stolen memory.
  314. *
  315. * We need to enable/disable FBC on a global basis.
  316. */
  317. void intel_update_fbc(struct drm_device *dev)
  318. {
  319. struct drm_i915_private *dev_priv = dev->dev_private;
  320. struct drm_crtc *crtc = NULL, *tmp_crtc;
  321. struct intel_crtc *intel_crtc;
  322. struct drm_framebuffer *fb;
  323. struct intel_framebuffer *intel_fb;
  324. struct drm_i915_gem_object *obj;
  325. int enable_fbc;
  326. if (!i915_powersave)
  327. return;
  328. if (!I915_HAS_FBC(dev))
  329. return;
  330. /*
  331. * If FBC is already on, we just have to verify that we can
  332. * keep it that way...
  333. * Need to disable if:
  334. * - more than one pipe is active
  335. * - changing FBC params (stride, fence, mode)
  336. * - new fb is too large to fit in compressed buffer
  337. * - going to an unsupported config (interlace, pixel multiply, etc.)
  338. */
  339. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  340. if (tmp_crtc->enabled &&
  341. !to_intel_crtc(tmp_crtc)->primary_disabled &&
  342. tmp_crtc->fb) {
  343. if (crtc) {
  344. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  345. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  346. goto out_disable;
  347. }
  348. crtc = tmp_crtc;
  349. }
  350. }
  351. if (!crtc || crtc->fb == NULL) {
  352. DRM_DEBUG_KMS("no output, disabling\n");
  353. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  354. goto out_disable;
  355. }
  356. intel_crtc = to_intel_crtc(crtc);
  357. fb = crtc->fb;
  358. intel_fb = to_intel_framebuffer(fb);
  359. obj = intel_fb->obj;
  360. enable_fbc = i915_enable_fbc;
  361. if (enable_fbc < 0) {
  362. DRM_DEBUG_KMS("fbc set to per-chip default\n");
  363. enable_fbc = 1;
  364. if (INTEL_INFO(dev)->gen <= 6)
  365. enable_fbc = 0;
  366. }
  367. if (!enable_fbc) {
  368. DRM_DEBUG_KMS("fbc disabled per module param\n");
  369. dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  370. goto out_disable;
  371. }
  372. if (intel_fb->obj->base.size > dev_priv->cfb_size) {
  373. DRM_DEBUG_KMS("framebuffer too large, disabling "
  374. "compression\n");
  375. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  376. goto out_disable;
  377. }
  378. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  379. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  380. DRM_DEBUG_KMS("mode incompatible with compression, "
  381. "disabling\n");
  382. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  383. goto out_disable;
  384. }
  385. if ((crtc->mode.hdisplay > 2048) ||
  386. (crtc->mode.vdisplay > 1536)) {
  387. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  388. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  389. goto out_disable;
  390. }
  391. if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  392. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  393. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  394. goto out_disable;
  395. }
  396. /* The use of a CPU fence is mandatory in order to detect writes
  397. * by the CPU to the scanout and trigger updates to the FBC.
  398. */
  399. if (obj->tiling_mode != I915_TILING_X ||
  400. obj->fence_reg == I915_FENCE_REG_NONE) {
  401. DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  402. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  403. goto out_disable;
  404. }
  405. /* If the kernel debugger is active, always disable compression */
  406. if (in_dbg_master())
  407. goto out_disable;
  408. /* If the scanout has not changed, don't modify the FBC settings.
  409. * Note that we make the fundamental assumption that the fb->obj
  410. * cannot be unpinned (and have its GTT offset and fence revoked)
  411. * without first being decoupled from the scanout and FBC disabled.
  412. */
  413. if (dev_priv->cfb_plane == intel_crtc->plane &&
  414. dev_priv->cfb_fb == fb->base.id &&
  415. dev_priv->cfb_y == crtc->y)
  416. return;
  417. if (intel_fbc_enabled(dev)) {
  418. /* We update FBC along two paths, after changing fb/crtc
  419. * configuration (modeswitching) and after page-flipping
  420. * finishes. For the latter, we know that not only did
  421. * we disable the FBC at the start of the page-flip
  422. * sequence, but also more than one vblank has passed.
  423. *
  424. * For the former case of modeswitching, it is possible
  425. * to switch between two FBC valid configurations
  426. * instantaneously so we do need to disable the FBC
  427. * before we can modify its control registers. We also
  428. * have to wait for the next vblank for that to take
  429. * effect. However, since we delay enabling FBC we can
  430. * assume that a vblank has passed since disabling and
  431. * that we can safely alter the registers in the deferred
  432. * callback.
  433. *
  434. * In the scenario that we go from a valid to invalid
  435. * and then back to valid FBC configuration we have
  436. * no strict enforcement that a vblank occurred since
  437. * disabling the FBC. However, along all current pipe
  438. * disabling paths we do need to wait for a vblank at
  439. * some point. And we wait before enabling FBC anyway.
  440. */
  441. DRM_DEBUG_KMS("disabling active FBC for update\n");
  442. intel_disable_fbc(dev);
  443. }
  444. intel_enable_fbc(crtc, 500);
  445. return;
  446. out_disable:
  447. /* Multiple disables should be harmless */
  448. if (intel_fbc_enabled(dev)) {
  449. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  450. intel_disable_fbc(dev);
  451. }
  452. }
  453. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  454. {
  455. drm_i915_private_t *dev_priv = dev->dev_private;
  456. u32 tmp;
  457. tmp = I915_READ(CLKCFG);
  458. switch (tmp & CLKCFG_FSB_MASK) {
  459. case CLKCFG_FSB_533:
  460. dev_priv->fsb_freq = 533; /* 133*4 */
  461. break;
  462. case CLKCFG_FSB_800:
  463. dev_priv->fsb_freq = 800; /* 200*4 */
  464. break;
  465. case CLKCFG_FSB_667:
  466. dev_priv->fsb_freq = 667; /* 167*4 */
  467. break;
  468. case CLKCFG_FSB_400:
  469. dev_priv->fsb_freq = 400; /* 100*4 */
  470. break;
  471. }
  472. switch (tmp & CLKCFG_MEM_MASK) {
  473. case CLKCFG_MEM_533:
  474. dev_priv->mem_freq = 533;
  475. break;
  476. case CLKCFG_MEM_667:
  477. dev_priv->mem_freq = 667;
  478. break;
  479. case CLKCFG_MEM_800:
  480. dev_priv->mem_freq = 800;
  481. break;
  482. }
  483. /* detect pineview DDR3 setting */
  484. tmp = I915_READ(CSHRDDR3CTL);
  485. dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  486. }
  487. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  488. {
  489. drm_i915_private_t *dev_priv = dev->dev_private;
  490. u16 ddrpll, csipll;
  491. ddrpll = I915_READ16(DDRMPLL1);
  492. csipll = I915_READ16(CSIPLL0);
  493. switch (ddrpll & 0xff) {
  494. case 0xc:
  495. dev_priv->mem_freq = 800;
  496. break;
  497. case 0x10:
  498. dev_priv->mem_freq = 1066;
  499. break;
  500. case 0x14:
  501. dev_priv->mem_freq = 1333;
  502. break;
  503. case 0x18:
  504. dev_priv->mem_freq = 1600;
  505. break;
  506. default:
  507. DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  508. ddrpll & 0xff);
  509. dev_priv->mem_freq = 0;
  510. break;
  511. }
  512. dev_priv->r_t = dev_priv->mem_freq;
  513. switch (csipll & 0x3ff) {
  514. case 0x00c:
  515. dev_priv->fsb_freq = 3200;
  516. break;
  517. case 0x00e:
  518. dev_priv->fsb_freq = 3733;
  519. break;
  520. case 0x010:
  521. dev_priv->fsb_freq = 4266;
  522. break;
  523. case 0x012:
  524. dev_priv->fsb_freq = 4800;
  525. break;
  526. case 0x014:
  527. dev_priv->fsb_freq = 5333;
  528. break;
  529. case 0x016:
  530. dev_priv->fsb_freq = 5866;
  531. break;
  532. case 0x018:
  533. dev_priv->fsb_freq = 6400;
  534. break;
  535. default:
  536. DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  537. csipll & 0x3ff);
  538. dev_priv->fsb_freq = 0;
  539. break;
  540. }
  541. if (dev_priv->fsb_freq == 3200) {
  542. dev_priv->c_m = 0;
  543. } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  544. dev_priv->c_m = 1;
  545. } else {
  546. dev_priv->c_m = 2;
  547. }
  548. }
  549. static const struct cxsr_latency cxsr_latency_table[] = {
  550. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  551. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  552. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  553. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  554. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  555. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  556. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  557. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  558. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  559. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  560. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  561. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  562. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  563. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  564. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  565. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  566. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  567. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  568. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  569. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  570. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  571. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  572. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  573. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  574. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  575. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  576. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  577. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  578. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  579. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  580. };
  581. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  582. int is_ddr3,
  583. int fsb,
  584. int mem)
  585. {
  586. const struct cxsr_latency *latency;
  587. int i;
  588. if (fsb == 0 || mem == 0)
  589. return NULL;
  590. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  591. latency = &cxsr_latency_table[i];
  592. if (is_desktop == latency->is_desktop &&
  593. is_ddr3 == latency->is_ddr3 &&
  594. fsb == latency->fsb_freq && mem == latency->mem_freq)
  595. return latency;
  596. }
  597. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  598. return NULL;
  599. }
  600. static void pineview_disable_cxsr(struct drm_device *dev)
  601. {
  602. struct drm_i915_private *dev_priv = dev->dev_private;
  603. /* deactivate cxsr */
  604. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  605. }
  606. /*
  607. * Latency for FIFO fetches is dependent on several factors:
  608. * - memory configuration (speed, channels)
  609. * - chipset
  610. * - current MCH state
  611. * It can be fairly high in some situations, so here we assume a fairly
  612. * pessimal value. It's a tradeoff between extra memory fetches (if we
  613. * set this value too high, the FIFO will fetch frequently to stay full)
  614. * and power consumption (set it too low to save power and we might see
  615. * FIFO underruns and display "flicker").
  616. *
  617. * A value of 5us seems to be a good balance; safe for very low end
  618. * platforms but not overly aggressive on lower latency configs.
  619. */
  620. static const int latency_ns = 5000;
  621. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  622. {
  623. struct drm_i915_private *dev_priv = dev->dev_private;
  624. uint32_t dsparb = I915_READ(DSPARB);
  625. int size;
  626. size = dsparb & 0x7f;
  627. if (plane)
  628. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  629. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  630. plane ? "B" : "A", size);
  631. return size;
  632. }
  633. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  634. {
  635. struct drm_i915_private *dev_priv = dev->dev_private;
  636. uint32_t dsparb = I915_READ(DSPARB);
  637. int size;
  638. size = dsparb & 0x1ff;
  639. if (plane)
  640. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  641. size >>= 1; /* Convert to cachelines */
  642. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  643. plane ? "B" : "A", size);
  644. return size;
  645. }
  646. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  647. {
  648. struct drm_i915_private *dev_priv = dev->dev_private;
  649. uint32_t dsparb = I915_READ(DSPARB);
  650. int size;
  651. size = dsparb & 0x7f;
  652. size >>= 2; /* Convert to cachelines */
  653. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  654. plane ? "B" : "A",
  655. size);
  656. return size;
  657. }
  658. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  659. {
  660. struct drm_i915_private *dev_priv = dev->dev_private;
  661. uint32_t dsparb = I915_READ(DSPARB);
  662. int size;
  663. size = dsparb & 0x7f;
  664. size >>= 1; /* Convert to cachelines */
  665. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  666. plane ? "B" : "A", size);
  667. return size;
  668. }
  669. /* Pineview has different values for various configs */
  670. static const struct intel_watermark_params pineview_display_wm = {
  671. PINEVIEW_DISPLAY_FIFO,
  672. PINEVIEW_MAX_WM,
  673. PINEVIEW_DFT_WM,
  674. PINEVIEW_GUARD_WM,
  675. PINEVIEW_FIFO_LINE_SIZE
  676. };
  677. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  678. PINEVIEW_DISPLAY_FIFO,
  679. PINEVIEW_MAX_WM,
  680. PINEVIEW_DFT_HPLLOFF_WM,
  681. PINEVIEW_GUARD_WM,
  682. PINEVIEW_FIFO_LINE_SIZE
  683. };
  684. static const struct intel_watermark_params pineview_cursor_wm = {
  685. PINEVIEW_CURSOR_FIFO,
  686. PINEVIEW_CURSOR_MAX_WM,
  687. PINEVIEW_CURSOR_DFT_WM,
  688. PINEVIEW_CURSOR_GUARD_WM,
  689. PINEVIEW_FIFO_LINE_SIZE,
  690. };
  691. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  692. PINEVIEW_CURSOR_FIFO,
  693. PINEVIEW_CURSOR_MAX_WM,
  694. PINEVIEW_CURSOR_DFT_WM,
  695. PINEVIEW_CURSOR_GUARD_WM,
  696. PINEVIEW_FIFO_LINE_SIZE
  697. };
  698. static const struct intel_watermark_params g4x_wm_info = {
  699. G4X_FIFO_SIZE,
  700. G4X_MAX_WM,
  701. G4X_MAX_WM,
  702. 2,
  703. G4X_FIFO_LINE_SIZE,
  704. };
  705. static const struct intel_watermark_params g4x_cursor_wm_info = {
  706. I965_CURSOR_FIFO,
  707. I965_CURSOR_MAX_WM,
  708. I965_CURSOR_DFT_WM,
  709. 2,
  710. G4X_FIFO_LINE_SIZE,
  711. };
  712. static const struct intel_watermark_params valleyview_wm_info = {
  713. VALLEYVIEW_FIFO_SIZE,
  714. VALLEYVIEW_MAX_WM,
  715. VALLEYVIEW_MAX_WM,
  716. 2,
  717. G4X_FIFO_LINE_SIZE,
  718. };
  719. static const struct intel_watermark_params valleyview_cursor_wm_info = {
  720. I965_CURSOR_FIFO,
  721. VALLEYVIEW_CURSOR_MAX_WM,
  722. I965_CURSOR_DFT_WM,
  723. 2,
  724. G4X_FIFO_LINE_SIZE,
  725. };
  726. static const struct intel_watermark_params i965_cursor_wm_info = {
  727. I965_CURSOR_FIFO,
  728. I965_CURSOR_MAX_WM,
  729. I965_CURSOR_DFT_WM,
  730. 2,
  731. I915_FIFO_LINE_SIZE,
  732. };
  733. static const struct intel_watermark_params i945_wm_info = {
  734. I945_FIFO_SIZE,
  735. I915_MAX_WM,
  736. 1,
  737. 2,
  738. I915_FIFO_LINE_SIZE
  739. };
  740. static const struct intel_watermark_params i915_wm_info = {
  741. I915_FIFO_SIZE,
  742. I915_MAX_WM,
  743. 1,
  744. 2,
  745. I915_FIFO_LINE_SIZE
  746. };
  747. static const struct intel_watermark_params i855_wm_info = {
  748. I855GM_FIFO_SIZE,
  749. I915_MAX_WM,
  750. 1,
  751. 2,
  752. I830_FIFO_LINE_SIZE
  753. };
  754. static const struct intel_watermark_params i830_wm_info = {
  755. I830_FIFO_SIZE,
  756. I915_MAX_WM,
  757. 1,
  758. 2,
  759. I830_FIFO_LINE_SIZE
  760. };
  761. static const struct intel_watermark_params ironlake_display_wm_info = {
  762. ILK_DISPLAY_FIFO,
  763. ILK_DISPLAY_MAXWM,
  764. ILK_DISPLAY_DFTWM,
  765. 2,
  766. ILK_FIFO_LINE_SIZE
  767. };
  768. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  769. ILK_CURSOR_FIFO,
  770. ILK_CURSOR_MAXWM,
  771. ILK_CURSOR_DFTWM,
  772. 2,
  773. ILK_FIFO_LINE_SIZE
  774. };
  775. static const struct intel_watermark_params ironlake_display_srwm_info = {
  776. ILK_DISPLAY_SR_FIFO,
  777. ILK_DISPLAY_MAX_SRWM,
  778. ILK_DISPLAY_DFT_SRWM,
  779. 2,
  780. ILK_FIFO_LINE_SIZE
  781. };
  782. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  783. ILK_CURSOR_SR_FIFO,
  784. ILK_CURSOR_MAX_SRWM,
  785. ILK_CURSOR_DFT_SRWM,
  786. 2,
  787. ILK_FIFO_LINE_SIZE
  788. };
  789. static const struct intel_watermark_params sandybridge_display_wm_info = {
  790. SNB_DISPLAY_FIFO,
  791. SNB_DISPLAY_MAXWM,
  792. SNB_DISPLAY_DFTWM,
  793. 2,
  794. SNB_FIFO_LINE_SIZE
  795. };
  796. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  797. SNB_CURSOR_FIFO,
  798. SNB_CURSOR_MAXWM,
  799. SNB_CURSOR_DFTWM,
  800. 2,
  801. SNB_FIFO_LINE_SIZE
  802. };
  803. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  804. SNB_DISPLAY_SR_FIFO,
  805. SNB_DISPLAY_MAX_SRWM,
  806. SNB_DISPLAY_DFT_SRWM,
  807. 2,
  808. SNB_FIFO_LINE_SIZE
  809. };
  810. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  811. SNB_CURSOR_SR_FIFO,
  812. SNB_CURSOR_MAX_SRWM,
  813. SNB_CURSOR_DFT_SRWM,
  814. 2,
  815. SNB_FIFO_LINE_SIZE
  816. };
  817. /**
  818. * intel_calculate_wm - calculate watermark level
  819. * @clock_in_khz: pixel clock
  820. * @wm: chip FIFO params
  821. * @pixel_size: display pixel size
  822. * @latency_ns: memory latency for the platform
  823. *
  824. * Calculate the watermark level (the level at which the display plane will
  825. * start fetching from memory again). Each chip has a different display
  826. * FIFO size and allocation, so the caller needs to figure that out and pass
  827. * in the correct intel_watermark_params structure.
  828. *
  829. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  830. * on the pixel size. When it reaches the watermark level, it'll start
  831. * fetching FIFO line sized based chunks from memory until the FIFO fills
  832. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  833. * will occur, and a display engine hang could result.
  834. */
  835. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  836. const struct intel_watermark_params *wm,
  837. int fifo_size,
  838. int pixel_size,
  839. unsigned long latency_ns)
  840. {
  841. long entries_required, wm_size;
  842. /*
  843. * Note: we need to make sure we don't overflow for various clock &
  844. * latency values.
  845. * clocks go from a few thousand to several hundred thousand.
  846. * latency is usually a few thousand
  847. */
  848. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  849. 1000;
  850. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  851. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  852. wm_size = fifo_size - (entries_required + wm->guard_size);
  853. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  854. /* Don't promote wm_size to unsigned... */
  855. if (wm_size > (long)wm->max_wm)
  856. wm_size = wm->max_wm;
  857. if (wm_size <= 0)
  858. wm_size = wm->default_wm;
  859. return wm_size;
  860. }
  861. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  862. {
  863. struct drm_crtc *crtc, *enabled = NULL;
  864. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  865. if (crtc->enabled && crtc->fb) {
  866. if (enabled)
  867. return NULL;
  868. enabled = crtc;
  869. }
  870. }
  871. return enabled;
  872. }
  873. static void pineview_update_wm(struct drm_device *dev)
  874. {
  875. struct drm_i915_private *dev_priv = dev->dev_private;
  876. struct drm_crtc *crtc;
  877. const struct cxsr_latency *latency;
  878. u32 reg;
  879. unsigned long wm;
  880. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  881. dev_priv->fsb_freq, dev_priv->mem_freq);
  882. if (!latency) {
  883. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  884. pineview_disable_cxsr(dev);
  885. return;
  886. }
  887. crtc = single_enabled_crtc(dev);
  888. if (crtc) {
  889. int clock = crtc->mode.clock;
  890. int pixel_size = crtc->fb->bits_per_pixel / 8;
  891. /* Display SR */
  892. wm = intel_calculate_wm(clock, &pineview_display_wm,
  893. pineview_display_wm.fifo_size,
  894. pixel_size, latency->display_sr);
  895. reg = I915_READ(DSPFW1);
  896. reg &= ~DSPFW_SR_MASK;
  897. reg |= wm << DSPFW_SR_SHIFT;
  898. I915_WRITE(DSPFW1, reg);
  899. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  900. /* cursor SR */
  901. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  902. pineview_display_wm.fifo_size,
  903. pixel_size, latency->cursor_sr);
  904. reg = I915_READ(DSPFW3);
  905. reg &= ~DSPFW_CURSOR_SR_MASK;
  906. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  907. I915_WRITE(DSPFW3, reg);
  908. /* Display HPLL off SR */
  909. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  910. pineview_display_hplloff_wm.fifo_size,
  911. pixel_size, latency->display_hpll_disable);
  912. reg = I915_READ(DSPFW3);
  913. reg &= ~DSPFW_HPLL_SR_MASK;
  914. reg |= wm & DSPFW_HPLL_SR_MASK;
  915. I915_WRITE(DSPFW3, reg);
  916. /* cursor HPLL off SR */
  917. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  918. pineview_display_hplloff_wm.fifo_size,
  919. pixel_size, latency->cursor_hpll_disable);
  920. reg = I915_READ(DSPFW3);
  921. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  922. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  923. I915_WRITE(DSPFW3, reg);
  924. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  925. /* activate cxsr */
  926. I915_WRITE(DSPFW3,
  927. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  928. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  929. } else {
  930. pineview_disable_cxsr(dev);
  931. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  932. }
  933. }
  934. static bool g4x_compute_wm0(struct drm_device *dev,
  935. int plane,
  936. const struct intel_watermark_params *display,
  937. int display_latency_ns,
  938. const struct intel_watermark_params *cursor,
  939. int cursor_latency_ns,
  940. int *plane_wm,
  941. int *cursor_wm)
  942. {
  943. struct drm_crtc *crtc;
  944. int htotal, hdisplay, clock, pixel_size;
  945. int line_time_us, line_count;
  946. int entries, tlb_miss;
  947. crtc = intel_get_crtc_for_plane(dev, plane);
  948. if (crtc->fb == NULL || !crtc->enabled) {
  949. *cursor_wm = cursor->guard_size;
  950. *plane_wm = display->guard_size;
  951. return false;
  952. }
  953. htotal = crtc->mode.htotal;
  954. hdisplay = crtc->mode.hdisplay;
  955. clock = crtc->mode.clock;
  956. pixel_size = crtc->fb->bits_per_pixel / 8;
  957. /* Use the small buffer method to calculate plane watermark */
  958. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  959. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  960. if (tlb_miss > 0)
  961. entries += tlb_miss;
  962. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  963. *plane_wm = entries + display->guard_size;
  964. if (*plane_wm > (int)display->max_wm)
  965. *plane_wm = display->max_wm;
  966. /* Use the large buffer method to calculate cursor watermark */
  967. line_time_us = ((htotal * 1000) / clock);
  968. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  969. entries = line_count * 64 * pixel_size;
  970. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  971. if (tlb_miss > 0)
  972. entries += tlb_miss;
  973. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  974. *cursor_wm = entries + cursor->guard_size;
  975. if (*cursor_wm > (int)cursor->max_wm)
  976. *cursor_wm = (int)cursor->max_wm;
  977. return true;
  978. }
  979. /*
  980. * Check the wm result.
  981. *
  982. * If any calculated watermark values is larger than the maximum value that
  983. * can be programmed into the associated watermark register, that watermark
  984. * must be disabled.
  985. */
  986. static bool g4x_check_srwm(struct drm_device *dev,
  987. int display_wm, int cursor_wm,
  988. const struct intel_watermark_params *display,
  989. const struct intel_watermark_params *cursor)
  990. {
  991. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  992. display_wm, cursor_wm);
  993. if (display_wm > display->max_wm) {
  994. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  995. display_wm, display->max_wm);
  996. return false;
  997. }
  998. if (cursor_wm > cursor->max_wm) {
  999. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  1000. cursor_wm, cursor->max_wm);
  1001. return false;
  1002. }
  1003. if (!(display_wm || cursor_wm)) {
  1004. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  1005. return false;
  1006. }
  1007. return true;
  1008. }
  1009. static bool g4x_compute_srwm(struct drm_device *dev,
  1010. int plane,
  1011. int latency_ns,
  1012. const struct intel_watermark_params *display,
  1013. const struct intel_watermark_params *cursor,
  1014. int *display_wm, int *cursor_wm)
  1015. {
  1016. struct drm_crtc *crtc;
  1017. int hdisplay, htotal, pixel_size, clock;
  1018. unsigned long line_time_us;
  1019. int line_count, line_size;
  1020. int small, large;
  1021. int entries;
  1022. if (!latency_ns) {
  1023. *display_wm = *cursor_wm = 0;
  1024. return false;
  1025. }
  1026. crtc = intel_get_crtc_for_plane(dev, plane);
  1027. hdisplay = crtc->mode.hdisplay;
  1028. htotal = crtc->mode.htotal;
  1029. clock = crtc->mode.clock;
  1030. pixel_size = crtc->fb->bits_per_pixel / 8;
  1031. line_time_us = (htotal * 1000) / clock;
  1032. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1033. line_size = hdisplay * pixel_size;
  1034. /* Use the minimum of the small and large buffer method for primary */
  1035. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1036. large = line_count * line_size;
  1037. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1038. *display_wm = entries + display->guard_size;
  1039. /* calculate the self-refresh watermark for display cursor */
  1040. entries = line_count * pixel_size * 64;
  1041. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1042. *cursor_wm = entries + cursor->guard_size;
  1043. return g4x_check_srwm(dev,
  1044. *display_wm, *cursor_wm,
  1045. display, cursor);
  1046. }
  1047. static bool vlv_compute_drain_latency(struct drm_device *dev,
  1048. int plane,
  1049. int *plane_prec_mult,
  1050. int *plane_dl,
  1051. int *cursor_prec_mult,
  1052. int *cursor_dl)
  1053. {
  1054. struct drm_crtc *crtc;
  1055. int clock, pixel_size;
  1056. int entries;
  1057. crtc = intel_get_crtc_for_plane(dev, plane);
  1058. if (crtc->fb == NULL || !crtc->enabled)
  1059. return false;
  1060. clock = crtc->mode.clock; /* VESA DOT Clock */
  1061. pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
  1062. entries = (clock / 1000) * pixel_size;
  1063. *plane_prec_mult = (entries > 256) ?
  1064. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1065. *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
  1066. pixel_size);
  1067. entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
  1068. *cursor_prec_mult = (entries > 256) ?
  1069. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1070. *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
  1071. return true;
  1072. }
  1073. /*
  1074. * Update drain latency registers of memory arbiter
  1075. *
  1076. * Valleyview SoC has a new memory arbiter and needs drain latency registers
  1077. * to be programmed. Each plane has a drain latency multiplier and a drain
  1078. * latency value.
  1079. */
  1080. static void vlv_update_drain_latency(struct drm_device *dev)
  1081. {
  1082. struct drm_i915_private *dev_priv = dev->dev_private;
  1083. int planea_prec, planea_dl, planeb_prec, planeb_dl;
  1084. int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
  1085. int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
  1086. either 16 or 32 */
  1087. /* For plane A, Cursor A */
  1088. if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
  1089. &cursor_prec_mult, &cursora_dl)) {
  1090. cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1091. DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
  1092. planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1093. DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
  1094. I915_WRITE(VLV_DDL1, cursora_prec |
  1095. (cursora_dl << DDL_CURSORA_SHIFT) |
  1096. planea_prec | planea_dl);
  1097. }
  1098. /* For plane B, Cursor B */
  1099. if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
  1100. &cursor_prec_mult, &cursorb_dl)) {
  1101. cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1102. DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
  1103. planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1104. DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
  1105. I915_WRITE(VLV_DDL2, cursorb_prec |
  1106. (cursorb_dl << DDL_CURSORB_SHIFT) |
  1107. planeb_prec | planeb_dl);
  1108. }
  1109. }
  1110. #define single_plane_enabled(mask) is_power_of_2(mask)
  1111. static void valleyview_update_wm(struct drm_device *dev)
  1112. {
  1113. static const int sr_latency_ns = 12000;
  1114. struct drm_i915_private *dev_priv = dev->dev_private;
  1115. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1116. int plane_sr, cursor_sr;
  1117. unsigned int enabled = 0;
  1118. vlv_update_drain_latency(dev);
  1119. if (g4x_compute_wm0(dev, 0,
  1120. &valleyview_wm_info, latency_ns,
  1121. &valleyview_cursor_wm_info, latency_ns,
  1122. &planea_wm, &cursora_wm))
  1123. enabled |= 1;
  1124. if (g4x_compute_wm0(dev, 1,
  1125. &valleyview_wm_info, latency_ns,
  1126. &valleyview_cursor_wm_info, latency_ns,
  1127. &planeb_wm, &cursorb_wm))
  1128. enabled |= 2;
  1129. plane_sr = cursor_sr = 0;
  1130. if (single_plane_enabled(enabled) &&
  1131. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1132. sr_latency_ns,
  1133. &valleyview_wm_info,
  1134. &valleyview_cursor_wm_info,
  1135. &plane_sr, &cursor_sr))
  1136. I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
  1137. else
  1138. I915_WRITE(FW_BLC_SELF_VLV,
  1139. I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
  1140. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1141. planea_wm, cursora_wm,
  1142. planeb_wm, cursorb_wm,
  1143. plane_sr, cursor_sr);
  1144. I915_WRITE(DSPFW1,
  1145. (plane_sr << DSPFW_SR_SHIFT) |
  1146. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1147. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1148. planea_wm);
  1149. I915_WRITE(DSPFW2,
  1150. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  1151. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1152. I915_WRITE(DSPFW3,
  1153. (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
  1154. }
  1155. static void g4x_update_wm(struct drm_device *dev)
  1156. {
  1157. static const int sr_latency_ns = 12000;
  1158. struct drm_i915_private *dev_priv = dev->dev_private;
  1159. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1160. int plane_sr, cursor_sr;
  1161. unsigned int enabled = 0;
  1162. if (g4x_compute_wm0(dev, 0,
  1163. &g4x_wm_info, latency_ns,
  1164. &g4x_cursor_wm_info, latency_ns,
  1165. &planea_wm, &cursora_wm))
  1166. enabled |= 1;
  1167. if (g4x_compute_wm0(dev, 1,
  1168. &g4x_wm_info, latency_ns,
  1169. &g4x_cursor_wm_info, latency_ns,
  1170. &planeb_wm, &cursorb_wm))
  1171. enabled |= 2;
  1172. plane_sr = cursor_sr = 0;
  1173. if (single_plane_enabled(enabled) &&
  1174. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1175. sr_latency_ns,
  1176. &g4x_wm_info,
  1177. &g4x_cursor_wm_info,
  1178. &plane_sr, &cursor_sr))
  1179. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1180. else
  1181. I915_WRITE(FW_BLC_SELF,
  1182. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  1183. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1184. planea_wm, cursora_wm,
  1185. planeb_wm, cursorb_wm,
  1186. plane_sr, cursor_sr);
  1187. I915_WRITE(DSPFW1,
  1188. (plane_sr << DSPFW_SR_SHIFT) |
  1189. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1190. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1191. planea_wm);
  1192. I915_WRITE(DSPFW2,
  1193. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  1194. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1195. /* HPLL off in SR has some issues on G4x... disable it */
  1196. I915_WRITE(DSPFW3,
  1197. (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  1198. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1199. }
  1200. static void i965_update_wm(struct drm_device *dev)
  1201. {
  1202. struct drm_i915_private *dev_priv = dev->dev_private;
  1203. struct drm_crtc *crtc;
  1204. int srwm = 1;
  1205. int cursor_sr = 16;
  1206. /* Calc sr entries for one plane configs */
  1207. crtc = single_enabled_crtc(dev);
  1208. if (crtc) {
  1209. /* self-refresh has much higher latency */
  1210. static const int sr_latency_ns = 12000;
  1211. int clock = crtc->mode.clock;
  1212. int htotal = crtc->mode.htotal;
  1213. int hdisplay = crtc->mode.hdisplay;
  1214. int pixel_size = crtc->fb->bits_per_pixel / 8;
  1215. unsigned long line_time_us;
  1216. int entries;
  1217. line_time_us = ((htotal * 1000) / clock);
  1218. /* Use ns/us then divide to preserve precision */
  1219. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1220. pixel_size * hdisplay;
  1221. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  1222. srwm = I965_FIFO_SIZE - entries;
  1223. if (srwm < 0)
  1224. srwm = 1;
  1225. srwm &= 0x1ff;
  1226. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  1227. entries, srwm);
  1228. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1229. pixel_size * 64;
  1230. entries = DIV_ROUND_UP(entries,
  1231. i965_cursor_wm_info.cacheline_size);
  1232. cursor_sr = i965_cursor_wm_info.fifo_size -
  1233. (entries + i965_cursor_wm_info.guard_size);
  1234. if (cursor_sr > i965_cursor_wm_info.max_wm)
  1235. cursor_sr = i965_cursor_wm_info.max_wm;
  1236. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  1237. "cursor %d\n", srwm, cursor_sr);
  1238. if (IS_CRESTLINE(dev))
  1239. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1240. } else {
  1241. /* Turn off self refresh if both pipes are enabled */
  1242. if (IS_CRESTLINE(dev))
  1243. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  1244. & ~FW_BLC_SELF_EN);
  1245. }
  1246. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  1247. srwm);
  1248. /* 965 has limitations... */
  1249. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  1250. (8 << 16) | (8 << 8) | (8 << 0));
  1251. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  1252. /* update cursor SR watermark */
  1253. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1254. }
  1255. static void i9xx_update_wm(struct drm_device *dev)
  1256. {
  1257. struct drm_i915_private *dev_priv = dev->dev_private;
  1258. const struct intel_watermark_params *wm_info;
  1259. uint32_t fwater_lo;
  1260. uint32_t fwater_hi;
  1261. int cwm, srwm = 1;
  1262. int fifo_size;
  1263. int planea_wm, planeb_wm;
  1264. struct drm_crtc *crtc, *enabled = NULL;
  1265. if (IS_I945GM(dev))
  1266. wm_info = &i945_wm_info;
  1267. else if (!IS_GEN2(dev))
  1268. wm_info = &i915_wm_info;
  1269. else
  1270. wm_info = &i855_wm_info;
  1271. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  1272. crtc = intel_get_crtc_for_plane(dev, 0);
  1273. if (crtc->enabled && crtc->fb) {
  1274. planea_wm = intel_calculate_wm(crtc->mode.clock,
  1275. wm_info, fifo_size,
  1276. crtc->fb->bits_per_pixel / 8,
  1277. latency_ns);
  1278. enabled = crtc;
  1279. } else
  1280. planea_wm = fifo_size - wm_info->guard_size;
  1281. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  1282. crtc = intel_get_crtc_for_plane(dev, 1);
  1283. if (crtc->enabled && crtc->fb) {
  1284. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  1285. wm_info, fifo_size,
  1286. crtc->fb->bits_per_pixel / 8,
  1287. latency_ns);
  1288. if (enabled == NULL)
  1289. enabled = crtc;
  1290. else
  1291. enabled = NULL;
  1292. } else
  1293. planeb_wm = fifo_size - wm_info->guard_size;
  1294. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  1295. /*
  1296. * Overlay gets an aggressive default since video jitter is bad.
  1297. */
  1298. cwm = 2;
  1299. /* Play safe and disable self-refresh before adjusting watermarks. */
  1300. if (IS_I945G(dev) || IS_I945GM(dev))
  1301. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  1302. else if (IS_I915GM(dev))
  1303. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  1304. /* Calc sr entries for one plane configs */
  1305. if (HAS_FW_BLC(dev) && enabled) {
  1306. /* self-refresh has much higher latency */
  1307. static const int sr_latency_ns = 6000;
  1308. int clock = enabled->mode.clock;
  1309. int htotal = enabled->mode.htotal;
  1310. int hdisplay = enabled->mode.hdisplay;
  1311. int pixel_size = enabled->fb->bits_per_pixel / 8;
  1312. unsigned long line_time_us;
  1313. int entries;
  1314. line_time_us = (htotal * 1000) / clock;
  1315. /* Use ns/us then divide to preserve precision */
  1316. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1317. pixel_size * hdisplay;
  1318. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  1319. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  1320. srwm = wm_info->fifo_size - entries;
  1321. if (srwm < 0)
  1322. srwm = 1;
  1323. if (IS_I945G(dev) || IS_I945GM(dev))
  1324. I915_WRITE(FW_BLC_SELF,
  1325. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  1326. else if (IS_I915GM(dev))
  1327. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  1328. }
  1329. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  1330. planea_wm, planeb_wm, cwm, srwm);
  1331. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  1332. fwater_hi = (cwm & 0x1f);
  1333. /* Set request length to 8 cachelines per fetch */
  1334. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  1335. fwater_hi = fwater_hi | (1 << 8);
  1336. I915_WRITE(FW_BLC, fwater_lo);
  1337. I915_WRITE(FW_BLC2, fwater_hi);
  1338. if (HAS_FW_BLC(dev)) {
  1339. if (enabled) {
  1340. if (IS_I945G(dev) || IS_I945GM(dev))
  1341. I915_WRITE(FW_BLC_SELF,
  1342. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  1343. else if (IS_I915GM(dev))
  1344. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  1345. DRM_DEBUG_KMS("memory self refresh enabled\n");
  1346. } else
  1347. DRM_DEBUG_KMS("memory self refresh disabled\n");
  1348. }
  1349. }
  1350. static void i830_update_wm(struct drm_device *dev)
  1351. {
  1352. struct drm_i915_private *dev_priv = dev->dev_private;
  1353. struct drm_crtc *crtc;
  1354. uint32_t fwater_lo;
  1355. int planea_wm;
  1356. crtc = single_enabled_crtc(dev);
  1357. if (crtc == NULL)
  1358. return;
  1359. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  1360. dev_priv->display.get_fifo_size(dev, 0),
  1361. crtc->fb->bits_per_pixel / 8,
  1362. latency_ns);
  1363. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  1364. fwater_lo |= (3<<8) | planea_wm;
  1365. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  1366. I915_WRITE(FW_BLC, fwater_lo);
  1367. }
  1368. #define ILK_LP0_PLANE_LATENCY 700
  1369. #define ILK_LP0_CURSOR_LATENCY 1300
  1370. /*
  1371. * Check the wm result.
  1372. *
  1373. * If any calculated watermark values is larger than the maximum value that
  1374. * can be programmed into the associated watermark register, that watermark
  1375. * must be disabled.
  1376. */
  1377. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  1378. int fbc_wm, int display_wm, int cursor_wm,
  1379. const struct intel_watermark_params *display,
  1380. const struct intel_watermark_params *cursor)
  1381. {
  1382. struct drm_i915_private *dev_priv = dev->dev_private;
  1383. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  1384. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  1385. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  1386. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  1387. fbc_wm, SNB_FBC_MAX_SRWM, level);
  1388. /* fbc has it's own way to disable FBC WM */
  1389. I915_WRITE(DISP_ARB_CTL,
  1390. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  1391. return false;
  1392. }
  1393. if (display_wm > display->max_wm) {
  1394. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  1395. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  1396. return false;
  1397. }
  1398. if (cursor_wm > cursor->max_wm) {
  1399. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  1400. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  1401. return false;
  1402. }
  1403. if (!(fbc_wm || display_wm || cursor_wm)) {
  1404. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  1405. return false;
  1406. }
  1407. return true;
  1408. }
  1409. /*
  1410. * Compute watermark values of WM[1-3],
  1411. */
  1412. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  1413. int latency_ns,
  1414. const struct intel_watermark_params *display,
  1415. const struct intel_watermark_params *cursor,
  1416. int *fbc_wm, int *display_wm, int *cursor_wm)
  1417. {
  1418. struct drm_crtc *crtc;
  1419. unsigned long line_time_us;
  1420. int hdisplay, htotal, pixel_size, clock;
  1421. int line_count, line_size;
  1422. int small, large;
  1423. int entries;
  1424. if (!latency_ns) {
  1425. *fbc_wm = *display_wm = *cursor_wm = 0;
  1426. return false;
  1427. }
  1428. crtc = intel_get_crtc_for_plane(dev, plane);
  1429. hdisplay = crtc->mode.hdisplay;
  1430. htotal = crtc->mode.htotal;
  1431. clock = crtc->mode.clock;
  1432. pixel_size = crtc->fb->bits_per_pixel / 8;
  1433. line_time_us = (htotal * 1000) / clock;
  1434. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1435. line_size = hdisplay * pixel_size;
  1436. /* Use the minimum of the small and large buffer method for primary */
  1437. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1438. large = line_count * line_size;
  1439. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1440. *display_wm = entries + display->guard_size;
  1441. /*
  1442. * Spec says:
  1443. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  1444. */
  1445. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  1446. /* calculate the self-refresh watermark for display cursor */
  1447. entries = line_count * pixel_size * 64;
  1448. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1449. *cursor_wm = entries + cursor->guard_size;
  1450. return ironlake_check_srwm(dev, level,
  1451. *fbc_wm, *display_wm, *cursor_wm,
  1452. display, cursor);
  1453. }
  1454. static void ironlake_update_wm(struct drm_device *dev)
  1455. {
  1456. struct drm_i915_private *dev_priv = dev->dev_private;
  1457. int fbc_wm, plane_wm, cursor_wm;
  1458. unsigned int enabled;
  1459. enabled = 0;
  1460. if (g4x_compute_wm0(dev, 0,
  1461. &ironlake_display_wm_info,
  1462. ILK_LP0_PLANE_LATENCY,
  1463. &ironlake_cursor_wm_info,
  1464. ILK_LP0_CURSOR_LATENCY,
  1465. &plane_wm, &cursor_wm)) {
  1466. I915_WRITE(WM0_PIPEA_ILK,
  1467. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1468. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1469. " plane %d, " "cursor: %d\n",
  1470. plane_wm, cursor_wm);
  1471. enabled |= 1;
  1472. }
  1473. if (g4x_compute_wm0(dev, 1,
  1474. &ironlake_display_wm_info,
  1475. ILK_LP0_PLANE_LATENCY,
  1476. &ironlake_cursor_wm_info,
  1477. ILK_LP0_CURSOR_LATENCY,
  1478. &plane_wm, &cursor_wm)) {
  1479. I915_WRITE(WM0_PIPEB_ILK,
  1480. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1481. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1482. " plane %d, cursor: %d\n",
  1483. plane_wm, cursor_wm);
  1484. enabled |= 2;
  1485. }
  1486. /*
  1487. * Calculate and update the self-refresh watermark only when one
  1488. * display plane is used.
  1489. */
  1490. I915_WRITE(WM3_LP_ILK, 0);
  1491. I915_WRITE(WM2_LP_ILK, 0);
  1492. I915_WRITE(WM1_LP_ILK, 0);
  1493. if (!single_plane_enabled(enabled))
  1494. return;
  1495. enabled = ffs(enabled) - 1;
  1496. /* WM1 */
  1497. if (!ironlake_compute_srwm(dev, 1, enabled,
  1498. ILK_READ_WM1_LATENCY() * 500,
  1499. &ironlake_display_srwm_info,
  1500. &ironlake_cursor_srwm_info,
  1501. &fbc_wm, &plane_wm, &cursor_wm))
  1502. return;
  1503. I915_WRITE(WM1_LP_ILK,
  1504. WM1_LP_SR_EN |
  1505. (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1506. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1507. (plane_wm << WM1_LP_SR_SHIFT) |
  1508. cursor_wm);
  1509. /* WM2 */
  1510. if (!ironlake_compute_srwm(dev, 2, enabled,
  1511. ILK_READ_WM2_LATENCY() * 500,
  1512. &ironlake_display_srwm_info,
  1513. &ironlake_cursor_srwm_info,
  1514. &fbc_wm, &plane_wm, &cursor_wm))
  1515. return;
  1516. I915_WRITE(WM2_LP_ILK,
  1517. WM2_LP_EN |
  1518. (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1519. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1520. (plane_wm << WM1_LP_SR_SHIFT) |
  1521. cursor_wm);
  1522. /*
  1523. * WM3 is unsupported on ILK, probably because we don't have latency
  1524. * data for that power state
  1525. */
  1526. }
  1527. static void sandybridge_update_wm(struct drm_device *dev)
  1528. {
  1529. struct drm_i915_private *dev_priv = dev->dev_private;
  1530. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  1531. u32 val;
  1532. int fbc_wm, plane_wm, cursor_wm;
  1533. unsigned int enabled;
  1534. enabled = 0;
  1535. if (g4x_compute_wm0(dev, 0,
  1536. &sandybridge_display_wm_info, latency,
  1537. &sandybridge_cursor_wm_info, latency,
  1538. &plane_wm, &cursor_wm)) {
  1539. val = I915_READ(WM0_PIPEA_ILK);
  1540. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1541. I915_WRITE(WM0_PIPEA_ILK, val |
  1542. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1543. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1544. " plane %d, " "cursor: %d\n",
  1545. plane_wm, cursor_wm);
  1546. enabled |= 1;
  1547. }
  1548. if (g4x_compute_wm0(dev, 1,
  1549. &sandybridge_display_wm_info, latency,
  1550. &sandybridge_cursor_wm_info, latency,
  1551. &plane_wm, &cursor_wm)) {
  1552. val = I915_READ(WM0_PIPEB_ILK);
  1553. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1554. I915_WRITE(WM0_PIPEB_ILK, val |
  1555. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1556. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1557. " plane %d, cursor: %d\n",
  1558. plane_wm, cursor_wm);
  1559. enabled |= 2;
  1560. }
  1561. if ((dev_priv->num_pipe == 3) &&
  1562. g4x_compute_wm0(dev, 2,
  1563. &sandybridge_display_wm_info, latency,
  1564. &sandybridge_cursor_wm_info, latency,
  1565. &plane_wm, &cursor_wm)) {
  1566. val = I915_READ(WM0_PIPEC_IVB);
  1567. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1568. I915_WRITE(WM0_PIPEC_IVB, val |
  1569. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1570. DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  1571. " plane %d, cursor: %d\n",
  1572. plane_wm, cursor_wm);
  1573. enabled |= 3;
  1574. }
  1575. /*
  1576. * Calculate and update the self-refresh watermark only when one
  1577. * display plane is used.
  1578. *
  1579. * SNB support 3 levels of watermark.
  1580. *
  1581. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1582. * and disabled in the descending order
  1583. *
  1584. */
  1585. I915_WRITE(WM3_LP_ILK, 0);
  1586. I915_WRITE(WM2_LP_ILK, 0);
  1587. I915_WRITE(WM1_LP_ILK, 0);
  1588. if (!single_plane_enabled(enabled) ||
  1589. dev_priv->sprite_scaling_enabled)
  1590. return;
  1591. enabled = ffs(enabled) - 1;
  1592. /* WM1 */
  1593. if (!ironlake_compute_srwm(dev, 1, enabled,
  1594. SNB_READ_WM1_LATENCY() * 500,
  1595. &sandybridge_display_srwm_info,
  1596. &sandybridge_cursor_srwm_info,
  1597. &fbc_wm, &plane_wm, &cursor_wm))
  1598. return;
  1599. I915_WRITE(WM1_LP_ILK,
  1600. WM1_LP_SR_EN |
  1601. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1602. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1603. (plane_wm << WM1_LP_SR_SHIFT) |
  1604. cursor_wm);
  1605. /* WM2 */
  1606. if (!ironlake_compute_srwm(dev, 2, enabled,
  1607. SNB_READ_WM2_LATENCY() * 500,
  1608. &sandybridge_display_srwm_info,
  1609. &sandybridge_cursor_srwm_info,
  1610. &fbc_wm, &plane_wm, &cursor_wm))
  1611. return;
  1612. I915_WRITE(WM2_LP_ILK,
  1613. WM2_LP_EN |
  1614. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1615. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1616. (plane_wm << WM1_LP_SR_SHIFT) |
  1617. cursor_wm);
  1618. /* WM3 */
  1619. if (!ironlake_compute_srwm(dev, 3, enabled,
  1620. SNB_READ_WM3_LATENCY() * 500,
  1621. &sandybridge_display_srwm_info,
  1622. &sandybridge_cursor_srwm_info,
  1623. &fbc_wm, &plane_wm, &cursor_wm))
  1624. return;
  1625. I915_WRITE(WM3_LP_ILK,
  1626. WM3_LP_EN |
  1627. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1628. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1629. (plane_wm << WM1_LP_SR_SHIFT) |
  1630. cursor_wm);
  1631. }
  1632. static void
  1633. haswell_update_linetime_wm(struct drm_device *dev, int pipe,
  1634. struct drm_display_mode *mode)
  1635. {
  1636. struct drm_i915_private *dev_priv = dev->dev_private;
  1637. u32 temp;
  1638. temp = I915_READ(PIPE_WM_LINETIME(pipe));
  1639. temp &= ~PIPE_WM_LINETIME_MASK;
  1640. /* The WM are computed with base on how long it takes to fill a single
  1641. * row at the given clock rate, multiplied by 8.
  1642. * */
  1643. temp |= PIPE_WM_LINETIME_TIME(
  1644. ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
  1645. /* IPS watermarks are only used by pipe A, and are ignored by
  1646. * pipes B and C. They are calculated similarly to the common
  1647. * linetime values, except that we are using CD clock frequency
  1648. * in MHz instead of pixel rate for the division.
  1649. *
  1650. * This is a placeholder for the IPS watermark calculation code.
  1651. */
  1652. I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
  1653. }
  1654. static bool
  1655. sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
  1656. uint32_t sprite_width, int pixel_size,
  1657. const struct intel_watermark_params *display,
  1658. int display_latency_ns, int *sprite_wm)
  1659. {
  1660. struct drm_crtc *crtc;
  1661. int clock;
  1662. int entries, tlb_miss;
  1663. crtc = intel_get_crtc_for_plane(dev, plane);
  1664. if (crtc->fb == NULL || !crtc->enabled) {
  1665. *sprite_wm = display->guard_size;
  1666. return false;
  1667. }
  1668. clock = crtc->mode.clock;
  1669. /* Use the small buffer method to calculate the sprite watermark */
  1670. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  1671. tlb_miss = display->fifo_size*display->cacheline_size -
  1672. sprite_width * 8;
  1673. if (tlb_miss > 0)
  1674. entries += tlb_miss;
  1675. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  1676. *sprite_wm = entries + display->guard_size;
  1677. if (*sprite_wm > (int)display->max_wm)
  1678. *sprite_wm = display->max_wm;
  1679. return true;
  1680. }
  1681. static bool
  1682. sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
  1683. uint32_t sprite_width, int pixel_size,
  1684. const struct intel_watermark_params *display,
  1685. int latency_ns, int *sprite_wm)
  1686. {
  1687. struct drm_crtc *crtc;
  1688. unsigned long line_time_us;
  1689. int clock;
  1690. int line_count, line_size;
  1691. int small, large;
  1692. int entries;
  1693. if (!latency_ns) {
  1694. *sprite_wm = 0;
  1695. return false;
  1696. }
  1697. crtc = intel_get_crtc_for_plane(dev, plane);
  1698. clock = crtc->mode.clock;
  1699. if (!clock) {
  1700. *sprite_wm = 0;
  1701. return false;
  1702. }
  1703. line_time_us = (sprite_width * 1000) / clock;
  1704. if (!line_time_us) {
  1705. *sprite_wm = 0;
  1706. return false;
  1707. }
  1708. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1709. line_size = sprite_width * pixel_size;
  1710. /* Use the minimum of the small and large buffer method for primary */
  1711. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1712. large = line_count * line_size;
  1713. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1714. *sprite_wm = entries + display->guard_size;
  1715. return *sprite_wm > 0x3ff ? false : true;
  1716. }
  1717. static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
  1718. uint32_t sprite_width, int pixel_size)
  1719. {
  1720. struct drm_i915_private *dev_priv = dev->dev_private;
  1721. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  1722. u32 val;
  1723. int sprite_wm, reg;
  1724. int ret;
  1725. switch (pipe) {
  1726. case 0:
  1727. reg = WM0_PIPEA_ILK;
  1728. break;
  1729. case 1:
  1730. reg = WM0_PIPEB_ILK;
  1731. break;
  1732. case 2:
  1733. reg = WM0_PIPEC_IVB;
  1734. break;
  1735. default:
  1736. return; /* bad pipe */
  1737. }
  1738. ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
  1739. &sandybridge_display_wm_info,
  1740. latency, &sprite_wm);
  1741. if (!ret) {
  1742. DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
  1743. pipe);
  1744. return;
  1745. }
  1746. val = I915_READ(reg);
  1747. val &= ~WM0_PIPE_SPRITE_MASK;
  1748. I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
  1749. DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
  1750. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  1751. pixel_size,
  1752. &sandybridge_display_srwm_info,
  1753. SNB_READ_WM1_LATENCY() * 500,
  1754. &sprite_wm);
  1755. if (!ret) {
  1756. DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
  1757. pipe);
  1758. return;
  1759. }
  1760. I915_WRITE(WM1S_LP_ILK, sprite_wm);
  1761. /* Only IVB has two more LP watermarks for sprite */
  1762. if (!IS_IVYBRIDGE(dev))
  1763. return;
  1764. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  1765. pixel_size,
  1766. &sandybridge_display_srwm_info,
  1767. SNB_READ_WM2_LATENCY() * 500,
  1768. &sprite_wm);
  1769. if (!ret) {
  1770. DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
  1771. pipe);
  1772. return;
  1773. }
  1774. I915_WRITE(WM2S_LP_IVB, sprite_wm);
  1775. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  1776. pixel_size,
  1777. &sandybridge_display_srwm_info,
  1778. SNB_READ_WM3_LATENCY() * 500,
  1779. &sprite_wm);
  1780. if (!ret) {
  1781. DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
  1782. pipe);
  1783. return;
  1784. }
  1785. I915_WRITE(WM3S_LP_IVB, sprite_wm);
  1786. }
  1787. /**
  1788. * intel_update_watermarks - update FIFO watermark values based on current modes
  1789. *
  1790. * Calculate watermark values for the various WM regs based on current mode
  1791. * and plane configuration.
  1792. *
  1793. * There are several cases to deal with here:
  1794. * - normal (i.e. non-self-refresh)
  1795. * - self-refresh (SR) mode
  1796. * - lines are large relative to FIFO size (buffer can hold up to 2)
  1797. * - lines are small relative to FIFO size (buffer can hold more than 2
  1798. * lines), so need to account for TLB latency
  1799. *
  1800. * The normal calculation is:
  1801. * watermark = dotclock * bytes per pixel * latency
  1802. * where latency is platform & configuration dependent (we assume pessimal
  1803. * values here).
  1804. *
  1805. * The SR calculation is:
  1806. * watermark = (trunc(latency/line time)+1) * surface width *
  1807. * bytes per pixel
  1808. * where
  1809. * line time = htotal / dotclock
  1810. * surface width = hdisplay for normal plane and 64 for cursor
  1811. * and latency is assumed to be high, as above.
  1812. *
  1813. * The final value programmed to the register should always be rounded up,
  1814. * and include an extra 2 entries to account for clock crossings.
  1815. *
  1816. * We don't use the sprite, so we can ignore that. And on Crestline we have
  1817. * to set the non-SR watermarks to 8.
  1818. */
  1819. void intel_update_watermarks(struct drm_device *dev)
  1820. {
  1821. struct drm_i915_private *dev_priv = dev->dev_private;
  1822. if (dev_priv->display.update_wm)
  1823. dev_priv->display.update_wm(dev);
  1824. }
  1825. void intel_update_linetime_watermarks(struct drm_device *dev,
  1826. int pipe, struct drm_display_mode *mode)
  1827. {
  1828. struct drm_i915_private *dev_priv = dev->dev_private;
  1829. if (dev_priv->display.update_linetime_wm)
  1830. dev_priv->display.update_linetime_wm(dev, pipe, mode);
  1831. }
  1832. void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  1833. uint32_t sprite_width, int pixel_size)
  1834. {
  1835. struct drm_i915_private *dev_priv = dev->dev_private;
  1836. if (dev_priv->display.update_sprite_wm)
  1837. dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
  1838. pixel_size);
  1839. }
  1840. static struct drm_i915_gem_object *
  1841. intel_alloc_context_page(struct drm_device *dev)
  1842. {
  1843. struct drm_i915_gem_object *ctx;
  1844. int ret;
  1845. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  1846. ctx = i915_gem_alloc_object(dev, 4096);
  1847. if (!ctx) {
  1848. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  1849. return NULL;
  1850. }
  1851. ret = i915_gem_object_pin(ctx, 4096, true);
  1852. if (ret) {
  1853. DRM_ERROR("failed to pin power context: %d\n", ret);
  1854. goto err_unref;
  1855. }
  1856. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  1857. if (ret) {
  1858. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  1859. goto err_unpin;
  1860. }
  1861. return ctx;
  1862. err_unpin:
  1863. i915_gem_object_unpin(ctx);
  1864. err_unref:
  1865. drm_gem_object_unreference(&ctx->base);
  1866. mutex_unlock(&dev->struct_mutex);
  1867. return NULL;
  1868. }
  1869. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  1870. {
  1871. struct drm_i915_private *dev_priv = dev->dev_private;
  1872. u16 rgvswctl;
  1873. rgvswctl = I915_READ16(MEMSWCTL);
  1874. if (rgvswctl & MEMCTL_CMD_STS) {
  1875. DRM_DEBUG("gpu busy, RCS change rejected\n");
  1876. return false; /* still busy with another command */
  1877. }
  1878. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  1879. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  1880. I915_WRITE16(MEMSWCTL, rgvswctl);
  1881. POSTING_READ16(MEMSWCTL);
  1882. rgvswctl |= MEMCTL_CMD_STS;
  1883. I915_WRITE16(MEMSWCTL, rgvswctl);
  1884. return true;
  1885. }
  1886. static void ironlake_enable_drps(struct drm_device *dev)
  1887. {
  1888. struct drm_i915_private *dev_priv = dev->dev_private;
  1889. u32 rgvmodectl = I915_READ(MEMMODECTL);
  1890. u8 fmax, fmin, fstart, vstart;
  1891. /* Enable temp reporting */
  1892. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  1893. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  1894. /* 100ms RC evaluation intervals */
  1895. I915_WRITE(RCUPEI, 100000);
  1896. I915_WRITE(RCDNEI, 100000);
  1897. /* Set max/min thresholds to 90ms and 80ms respectively */
  1898. I915_WRITE(RCBMAXAVG, 90000);
  1899. I915_WRITE(RCBMINAVG, 80000);
  1900. I915_WRITE(MEMIHYST, 1);
  1901. /* Set up min, max, and cur for interrupt handling */
  1902. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  1903. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  1904. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  1905. MEMMODE_FSTART_SHIFT;
  1906. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  1907. PXVFREQ_PX_SHIFT;
  1908. dev_priv->fmax = fmax; /* IPS callback will increase this */
  1909. dev_priv->fstart = fstart;
  1910. dev_priv->max_delay = fstart;
  1911. dev_priv->min_delay = fmin;
  1912. dev_priv->cur_delay = fstart;
  1913. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  1914. fmax, fmin, fstart);
  1915. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  1916. /*
  1917. * Interrupts will be enabled in ironlake_irq_postinstall
  1918. */
  1919. I915_WRITE(VIDSTART, vstart);
  1920. POSTING_READ(VIDSTART);
  1921. rgvmodectl |= MEMMODE_SWMODE_EN;
  1922. I915_WRITE(MEMMODECTL, rgvmodectl);
  1923. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  1924. DRM_ERROR("stuck trying to change perf mode\n");
  1925. msleep(1);
  1926. ironlake_set_drps(dev, fstart);
  1927. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  1928. I915_READ(0x112e0);
  1929. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  1930. dev_priv->last_count2 = I915_READ(0x112f4);
  1931. getrawmonotonic(&dev_priv->last_time2);
  1932. }
  1933. static void ironlake_disable_drps(struct drm_device *dev)
  1934. {
  1935. struct drm_i915_private *dev_priv = dev->dev_private;
  1936. u16 rgvswctl = I915_READ16(MEMSWCTL);
  1937. /* Ack interrupts, disable EFC interrupt */
  1938. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  1939. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  1940. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  1941. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1942. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  1943. /* Go back to the starting frequency */
  1944. ironlake_set_drps(dev, dev_priv->fstart);
  1945. msleep(1);
  1946. rgvswctl |= MEMCTL_CMD_STS;
  1947. I915_WRITE(MEMSWCTL, rgvswctl);
  1948. msleep(1);
  1949. }
  1950. void gen6_set_rps(struct drm_device *dev, u8 val)
  1951. {
  1952. struct drm_i915_private *dev_priv = dev->dev_private;
  1953. u32 limits;
  1954. limits = 0;
  1955. if (val >= dev_priv->max_delay)
  1956. val = dev_priv->max_delay;
  1957. else
  1958. limits |= dev_priv->max_delay << 24;
  1959. if (val <= dev_priv->min_delay)
  1960. val = dev_priv->min_delay;
  1961. else
  1962. limits |= dev_priv->min_delay << 16;
  1963. if (val == dev_priv->cur_delay)
  1964. return;
  1965. I915_WRITE(GEN6_RPNSWREQ,
  1966. GEN6_FREQUENCY(val) |
  1967. GEN6_OFFSET(0) |
  1968. GEN6_AGGRESSIVE_TURBO);
  1969. /* Make sure we continue to get interrupts
  1970. * until we hit the minimum or maximum frequencies.
  1971. */
  1972. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  1973. dev_priv->cur_delay = val;
  1974. }
  1975. static void gen6_disable_rps(struct drm_device *dev)
  1976. {
  1977. struct drm_i915_private *dev_priv = dev->dev_private;
  1978. I915_WRITE(GEN6_RC_CONTROL, 0);
  1979. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  1980. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  1981. I915_WRITE(GEN6_PMIER, 0);
  1982. /* Complete PM interrupt masking here doesn't race with the rps work
  1983. * item again unmasking PM interrupts because that is using a different
  1984. * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  1985. * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  1986. spin_lock_irq(&dev_priv->rps_lock);
  1987. dev_priv->pm_iir = 0;
  1988. spin_unlock_irq(&dev_priv->rps_lock);
  1989. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  1990. }
  1991. int intel_enable_rc6(const struct drm_device *dev)
  1992. {
  1993. /*
  1994. * Respect the kernel parameter if it is set
  1995. */
  1996. if (i915_enable_rc6 >= 0)
  1997. return i915_enable_rc6;
  1998. /*
  1999. * Disable RC6 on Ironlake
  2000. */
  2001. if (INTEL_INFO(dev)->gen == 5)
  2002. return 0;
  2003. /* On Haswell, only RC6 is available. So let's enable it by default to
  2004. * provide better testing and coverage since the beginning.
  2005. */
  2006. if (IS_HASWELL(dev))
  2007. return INTEL_RC6_ENABLE;
  2008. /*
  2009. * Disable rc6 on Sandybridge
  2010. */
  2011. if (INTEL_INFO(dev)->gen == 6) {
  2012. DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
  2013. return INTEL_RC6_ENABLE;
  2014. }
  2015. DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
  2016. return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
  2017. }
  2018. static void gen6_enable_rps(struct drm_device *dev)
  2019. {
  2020. struct drm_i915_private *dev_priv = dev->dev_private;
  2021. struct intel_ring_buffer *ring;
  2022. u32 rp_state_cap;
  2023. u32 gt_perf_status;
  2024. u32 pcu_mbox, rc6_mask = 0;
  2025. u32 gtfifodbg;
  2026. int rc6_mode;
  2027. int i;
  2028. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2029. /* Here begins a magic sequence of register writes to enable
  2030. * auto-downclocking.
  2031. *
  2032. * Perhaps there might be some value in exposing these to
  2033. * userspace...
  2034. */
  2035. I915_WRITE(GEN6_RC_STATE, 0);
  2036. /* Clear the DBG now so we don't confuse earlier errors */
  2037. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  2038. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  2039. I915_WRITE(GTFIFODBG, gtfifodbg);
  2040. }
  2041. gen6_gt_force_wake_get(dev_priv);
  2042. rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  2043. gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  2044. /* In units of 100MHz */
  2045. dev_priv->max_delay = rp_state_cap & 0xff;
  2046. dev_priv->min_delay = (rp_state_cap & 0xff0000) >> 16;
  2047. dev_priv->cur_delay = 0;
  2048. /* disable the counters and set deterministic thresholds */
  2049. I915_WRITE(GEN6_RC_CONTROL, 0);
  2050. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  2051. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  2052. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  2053. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  2054. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  2055. for_each_ring(ring, dev_priv, i)
  2056. I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
  2057. I915_WRITE(GEN6_RC_SLEEP, 0);
  2058. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  2059. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  2060. I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
  2061. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  2062. /* Check if we are enabling RC6 */
  2063. rc6_mode = intel_enable_rc6(dev_priv->dev);
  2064. if (rc6_mode & INTEL_RC6_ENABLE)
  2065. rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
  2066. /* We don't use those on Haswell */
  2067. if (!IS_HASWELL(dev)) {
  2068. if (rc6_mode & INTEL_RC6p_ENABLE)
  2069. rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
  2070. if (rc6_mode & INTEL_RC6pp_ENABLE)
  2071. rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
  2072. }
  2073. DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
  2074. (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
  2075. (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
  2076. (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
  2077. I915_WRITE(GEN6_RC_CONTROL,
  2078. rc6_mask |
  2079. GEN6_RC_CTL_EI_MODE(1) |
  2080. GEN6_RC_CTL_HW_ENABLE);
  2081. I915_WRITE(GEN6_RPNSWREQ,
  2082. GEN6_FREQUENCY(10) |
  2083. GEN6_OFFSET(0) |
  2084. GEN6_AGGRESSIVE_TURBO);
  2085. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2086. GEN6_FREQUENCY(12));
  2087. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  2088. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  2089. dev_priv->max_delay << 24 |
  2090. dev_priv->min_delay << 16);
  2091. I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
  2092. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
  2093. I915_WRITE(GEN6_RP_UP_EI, 66000);
  2094. I915_WRITE(GEN6_RP_DOWN_EI, 350000);
  2095. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  2096. I915_WRITE(GEN6_RP_CONTROL,
  2097. GEN6_RP_MEDIA_TURBO |
  2098. GEN6_RP_MEDIA_HW_NORMAL_MODE |
  2099. GEN6_RP_MEDIA_IS_GFX |
  2100. GEN6_RP_ENABLE |
  2101. GEN6_RP_UP_BUSY_AVG |
  2102. (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
  2103. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2104. 500))
  2105. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  2106. I915_WRITE(GEN6_PCODE_DATA, 0);
  2107. I915_WRITE(GEN6_PCODE_MAILBOX,
  2108. GEN6_PCODE_READY |
  2109. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  2110. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2111. 500))
  2112. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  2113. /* Check for overclock support */
  2114. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2115. 500))
  2116. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  2117. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
  2118. pcu_mbox = I915_READ(GEN6_PCODE_DATA);
  2119. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  2120. 500))
  2121. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  2122. if (pcu_mbox & (1<<31)) { /* OC supported */
  2123. dev_priv->max_delay = pcu_mbox & 0xff;
  2124. DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
  2125. }
  2126. gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
  2127. /* requires MSI enabled */
  2128. I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
  2129. spin_lock_irq(&dev_priv->rps_lock);
  2130. WARN_ON(dev_priv->pm_iir != 0);
  2131. I915_WRITE(GEN6_PMIMR, 0);
  2132. spin_unlock_irq(&dev_priv->rps_lock);
  2133. /* enable all PM interrupts */
  2134. I915_WRITE(GEN6_PMINTRMSK, 0);
  2135. gen6_gt_force_wake_put(dev_priv);
  2136. }
  2137. static void gen6_update_ring_freq(struct drm_device *dev)
  2138. {
  2139. struct drm_i915_private *dev_priv = dev->dev_private;
  2140. int min_freq = 15;
  2141. int gpu_freq, ia_freq, max_ia_freq;
  2142. int scaling_factor = 180;
  2143. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2144. max_ia_freq = cpufreq_quick_get_max(0);
  2145. /*
  2146. * Default to measured freq if none found, PCU will ensure we don't go
  2147. * over
  2148. */
  2149. if (!max_ia_freq)
  2150. max_ia_freq = tsc_khz;
  2151. /* Convert from kHz to MHz */
  2152. max_ia_freq /= 1000;
  2153. /*
  2154. * For each potential GPU frequency, load a ring frequency we'd like
  2155. * to use for memory access. We do this by specifying the IA frequency
  2156. * the PCU should use as a reference to determine the ring frequency.
  2157. */
  2158. for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
  2159. gpu_freq--) {
  2160. int diff = dev_priv->max_delay - gpu_freq;
  2161. /*
  2162. * For GPU frequencies less than 750MHz, just use the lowest
  2163. * ring freq.
  2164. */
  2165. if (gpu_freq < min_freq)
  2166. ia_freq = 800;
  2167. else
  2168. ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  2169. ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  2170. I915_WRITE(GEN6_PCODE_DATA,
  2171. (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
  2172. gpu_freq);
  2173. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  2174. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  2175. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  2176. GEN6_PCODE_READY) == 0, 10)) {
  2177. DRM_ERROR("pcode write of freq table timed out\n");
  2178. continue;
  2179. }
  2180. }
  2181. }
  2182. void ironlake_teardown_rc6(struct drm_device *dev)
  2183. {
  2184. struct drm_i915_private *dev_priv = dev->dev_private;
  2185. if (dev_priv->renderctx) {
  2186. i915_gem_object_unpin(dev_priv->renderctx);
  2187. drm_gem_object_unreference(&dev_priv->renderctx->base);
  2188. dev_priv->renderctx = NULL;
  2189. }
  2190. if (dev_priv->pwrctx) {
  2191. i915_gem_object_unpin(dev_priv->pwrctx);
  2192. drm_gem_object_unreference(&dev_priv->pwrctx->base);
  2193. dev_priv->pwrctx = NULL;
  2194. }
  2195. }
  2196. static void ironlake_disable_rc6(struct drm_device *dev)
  2197. {
  2198. struct drm_i915_private *dev_priv = dev->dev_private;
  2199. if (I915_READ(PWRCTXA)) {
  2200. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  2201. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  2202. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  2203. 50);
  2204. I915_WRITE(PWRCTXA, 0);
  2205. POSTING_READ(PWRCTXA);
  2206. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  2207. POSTING_READ(RSTDBYCTL);
  2208. }
  2209. }
  2210. static int ironlake_setup_rc6(struct drm_device *dev)
  2211. {
  2212. struct drm_i915_private *dev_priv = dev->dev_private;
  2213. if (dev_priv->renderctx == NULL)
  2214. dev_priv->renderctx = intel_alloc_context_page(dev);
  2215. if (!dev_priv->renderctx)
  2216. return -ENOMEM;
  2217. if (dev_priv->pwrctx == NULL)
  2218. dev_priv->pwrctx = intel_alloc_context_page(dev);
  2219. if (!dev_priv->pwrctx) {
  2220. ironlake_teardown_rc6(dev);
  2221. return -ENOMEM;
  2222. }
  2223. return 0;
  2224. }
  2225. static void ironlake_enable_rc6(struct drm_device *dev)
  2226. {
  2227. struct drm_i915_private *dev_priv = dev->dev_private;
  2228. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  2229. int ret;
  2230. /* rc6 disabled by default due to repeated reports of hanging during
  2231. * boot and resume.
  2232. */
  2233. if (!intel_enable_rc6(dev))
  2234. return;
  2235. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2236. ret = ironlake_setup_rc6(dev);
  2237. if (ret)
  2238. return;
  2239. /*
  2240. * GPU can automatically power down the render unit if given a page
  2241. * to save state.
  2242. */
  2243. ret = intel_ring_begin(ring, 6);
  2244. if (ret) {
  2245. ironlake_teardown_rc6(dev);
  2246. return;
  2247. }
  2248. intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  2249. intel_ring_emit(ring, MI_SET_CONTEXT);
  2250. intel_ring_emit(ring, dev_priv->renderctx->gtt_offset |
  2251. MI_MM_SPACE_GTT |
  2252. MI_SAVE_EXT_STATE_EN |
  2253. MI_RESTORE_EXT_STATE_EN |
  2254. MI_RESTORE_INHIBIT);
  2255. intel_ring_emit(ring, MI_SUSPEND_FLUSH);
  2256. intel_ring_emit(ring, MI_NOOP);
  2257. intel_ring_emit(ring, MI_FLUSH);
  2258. intel_ring_advance(ring);
  2259. /*
  2260. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  2261. * does an implicit flush, combined with MI_FLUSH above, it should be
  2262. * safe to assume that renderctx is valid
  2263. */
  2264. ret = intel_wait_ring_idle(ring);
  2265. if (ret) {
  2266. DRM_ERROR("failed to enable ironlake power power savings\n");
  2267. ironlake_teardown_rc6(dev);
  2268. return;
  2269. }
  2270. I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
  2271. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  2272. }
  2273. static unsigned long intel_pxfreq(u32 vidfreq)
  2274. {
  2275. unsigned long freq;
  2276. int div = (vidfreq & 0x3f0000) >> 16;
  2277. int post = (vidfreq & 0x3000) >> 12;
  2278. int pre = (vidfreq & 0x7);
  2279. if (!pre)
  2280. return 0;
  2281. freq = ((div * 133333) / ((1<<post) * pre));
  2282. return freq;
  2283. }
  2284. static const struct cparams {
  2285. u16 i;
  2286. u16 t;
  2287. u16 m;
  2288. u16 c;
  2289. } cparams[] = {
  2290. { 1, 1333, 301, 28664 },
  2291. { 1, 1066, 294, 24460 },
  2292. { 1, 800, 294, 25192 },
  2293. { 0, 1333, 276, 27605 },
  2294. { 0, 1066, 276, 27605 },
  2295. { 0, 800, 231, 23784 },
  2296. };
  2297. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  2298. {
  2299. u64 total_count, diff, ret;
  2300. u32 count1, count2, count3, m = 0, c = 0;
  2301. unsigned long now = jiffies_to_msecs(jiffies), diff1;
  2302. int i;
  2303. diff1 = now - dev_priv->last_time1;
  2304. /* Prevent division-by-zero if we are asking too fast.
  2305. * Also, we don't get interesting results if we are polling
  2306. * faster than once in 10ms, so just return the saved value
  2307. * in such cases.
  2308. */
  2309. if (diff1 <= 10)
  2310. return dev_priv->chipset_power;
  2311. count1 = I915_READ(DMIEC);
  2312. count2 = I915_READ(DDREC);
  2313. count3 = I915_READ(CSIEC);
  2314. total_count = count1 + count2 + count3;
  2315. /* FIXME: handle per-counter overflow */
  2316. if (total_count < dev_priv->last_count1) {
  2317. diff = ~0UL - dev_priv->last_count1;
  2318. diff += total_count;
  2319. } else {
  2320. diff = total_count - dev_priv->last_count1;
  2321. }
  2322. for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  2323. if (cparams[i].i == dev_priv->c_m &&
  2324. cparams[i].t == dev_priv->r_t) {
  2325. m = cparams[i].m;
  2326. c = cparams[i].c;
  2327. break;
  2328. }
  2329. }
  2330. diff = div_u64(diff, diff1);
  2331. ret = ((m * diff) + c);
  2332. ret = div_u64(ret, 10);
  2333. dev_priv->last_count1 = total_count;
  2334. dev_priv->last_time1 = now;
  2335. dev_priv->chipset_power = ret;
  2336. return ret;
  2337. }
  2338. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  2339. {
  2340. unsigned long m, x, b;
  2341. u32 tsfs;
  2342. tsfs = I915_READ(TSFS);
  2343. m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  2344. x = I915_READ8(TR1);
  2345. b = tsfs & TSFS_INTR_MASK;
  2346. return ((m * x) / 127) - b;
  2347. }
  2348. static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  2349. {
  2350. static const struct v_table {
  2351. u16 vd; /* in .1 mil */
  2352. u16 vm; /* in .1 mil */
  2353. } v_table[] = {
  2354. { 0, 0, },
  2355. { 375, 0, },
  2356. { 500, 0, },
  2357. { 625, 0, },
  2358. { 750, 0, },
  2359. { 875, 0, },
  2360. { 1000, 0, },
  2361. { 1125, 0, },
  2362. { 4125, 3000, },
  2363. { 4125, 3000, },
  2364. { 4125, 3000, },
  2365. { 4125, 3000, },
  2366. { 4125, 3000, },
  2367. { 4125, 3000, },
  2368. { 4125, 3000, },
  2369. { 4125, 3000, },
  2370. { 4125, 3000, },
  2371. { 4125, 3000, },
  2372. { 4125, 3000, },
  2373. { 4125, 3000, },
  2374. { 4125, 3000, },
  2375. { 4125, 3000, },
  2376. { 4125, 3000, },
  2377. { 4125, 3000, },
  2378. { 4125, 3000, },
  2379. { 4125, 3000, },
  2380. { 4125, 3000, },
  2381. { 4125, 3000, },
  2382. { 4125, 3000, },
  2383. { 4125, 3000, },
  2384. { 4125, 3000, },
  2385. { 4125, 3000, },
  2386. { 4250, 3125, },
  2387. { 4375, 3250, },
  2388. { 4500, 3375, },
  2389. { 4625, 3500, },
  2390. { 4750, 3625, },
  2391. { 4875, 3750, },
  2392. { 5000, 3875, },
  2393. { 5125, 4000, },
  2394. { 5250, 4125, },
  2395. { 5375, 4250, },
  2396. { 5500, 4375, },
  2397. { 5625, 4500, },
  2398. { 5750, 4625, },
  2399. { 5875, 4750, },
  2400. { 6000, 4875, },
  2401. { 6125, 5000, },
  2402. { 6250, 5125, },
  2403. { 6375, 5250, },
  2404. { 6500, 5375, },
  2405. { 6625, 5500, },
  2406. { 6750, 5625, },
  2407. { 6875, 5750, },
  2408. { 7000, 5875, },
  2409. { 7125, 6000, },
  2410. { 7250, 6125, },
  2411. { 7375, 6250, },
  2412. { 7500, 6375, },
  2413. { 7625, 6500, },
  2414. { 7750, 6625, },
  2415. { 7875, 6750, },
  2416. { 8000, 6875, },
  2417. { 8125, 7000, },
  2418. { 8250, 7125, },
  2419. { 8375, 7250, },
  2420. { 8500, 7375, },
  2421. { 8625, 7500, },
  2422. { 8750, 7625, },
  2423. { 8875, 7750, },
  2424. { 9000, 7875, },
  2425. { 9125, 8000, },
  2426. { 9250, 8125, },
  2427. { 9375, 8250, },
  2428. { 9500, 8375, },
  2429. { 9625, 8500, },
  2430. { 9750, 8625, },
  2431. { 9875, 8750, },
  2432. { 10000, 8875, },
  2433. { 10125, 9000, },
  2434. { 10250, 9125, },
  2435. { 10375, 9250, },
  2436. { 10500, 9375, },
  2437. { 10625, 9500, },
  2438. { 10750, 9625, },
  2439. { 10875, 9750, },
  2440. { 11000, 9875, },
  2441. { 11125, 10000, },
  2442. { 11250, 10125, },
  2443. { 11375, 10250, },
  2444. { 11500, 10375, },
  2445. { 11625, 10500, },
  2446. { 11750, 10625, },
  2447. { 11875, 10750, },
  2448. { 12000, 10875, },
  2449. { 12125, 11000, },
  2450. { 12250, 11125, },
  2451. { 12375, 11250, },
  2452. { 12500, 11375, },
  2453. { 12625, 11500, },
  2454. { 12750, 11625, },
  2455. { 12875, 11750, },
  2456. { 13000, 11875, },
  2457. { 13125, 12000, },
  2458. { 13250, 12125, },
  2459. { 13375, 12250, },
  2460. { 13500, 12375, },
  2461. { 13625, 12500, },
  2462. { 13750, 12625, },
  2463. { 13875, 12750, },
  2464. { 14000, 12875, },
  2465. { 14125, 13000, },
  2466. { 14250, 13125, },
  2467. { 14375, 13250, },
  2468. { 14500, 13375, },
  2469. { 14625, 13500, },
  2470. { 14750, 13625, },
  2471. { 14875, 13750, },
  2472. { 15000, 13875, },
  2473. { 15125, 14000, },
  2474. { 15250, 14125, },
  2475. { 15375, 14250, },
  2476. { 15500, 14375, },
  2477. { 15625, 14500, },
  2478. { 15750, 14625, },
  2479. { 15875, 14750, },
  2480. { 16000, 14875, },
  2481. { 16125, 15000, },
  2482. };
  2483. if (dev_priv->info->is_mobile)
  2484. return v_table[pxvid].vm;
  2485. else
  2486. return v_table[pxvid].vd;
  2487. }
  2488. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  2489. {
  2490. struct timespec now, diff1;
  2491. u64 diff;
  2492. unsigned long diffms;
  2493. u32 count;
  2494. if (dev_priv->info->gen != 5)
  2495. return;
  2496. getrawmonotonic(&now);
  2497. diff1 = timespec_sub(now, dev_priv->last_time2);
  2498. /* Don't divide by 0 */
  2499. diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  2500. if (!diffms)
  2501. return;
  2502. count = I915_READ(GFXEC);
  2503. if (count < dev_priv->last_count2) {
  2504. diff = ~0UL - dev_priv->last_count2;
  2505. diff += count;
  2506. } else {
  2507. diff = count - dev_priv->last_count2;
  2508. }
  2509. dev_priv->last_count2 = count;
  2510. dev_priv->last_time2 = now;
  2511. /* More magic constants... */
  2512. diff = diff * 1181;
  2513. diff = div_u64(diff, diffms * 10);
  2514. dev_priv->gfx_power = diff;
  2515. }
  2516. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  2517. {
  2518. unsigned long t, corr, state1, corr2, state2;
  2519. u32 pxvid, ext_v;
  2520. pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
  2521. pxvid = (pxvid >> 24) & 0x7f;
  2522. ext_v = pvid_to_extvid(dev_priv, pxvid);
  2523. state1 = ext_v;
  2524. t = i915_mch_val(dev_priv);
  2525. /* Revel in the empirically derived constants */
  2526. /* Correction factor in 1/100000 units */
  2527. if (t > 80)
  2528. corr = ((t * 2349) + 135940);
  2529. else if (t >= 50)
  2530. corr = ((t * 964) + 29317);
  2531. else /* < 50 */
  2532. corr = ((t * 301) + 1004);
  2533. corr = corr * ((150142 * state1) / 10000 - 78642);
  2534. corr /= 100000;
  2535. corr2 = (corr * dev_priv->corr);
  2536. state2 = (corr2 * state1) / 10000;
  2537. state2 /= 100; /* convert to mW */
  2538. i915_update_gfx_val(dev_priv);
  2539. return dev_priv->gfx_power + state2;
  2540. }
  2541. /* Global for IPS driver to get at the current i915 device */
  2542. static struct drm_i915_private *i915_mch_dev;
  2543. /*
  2544. * Lock protecting IPS related data structures
  2545. * - i915_mch_dev
  2546. * - dev_priv->max_delay
  2547. * - dev_priv->min_delay
  2548. * - dev_priv->fmax
  2549. * - dev_priv->gpu_busy
  2550. */
  2551. static DEFINE_SPINLOCK(mchdev_lock);
  2552. /**
  2553. * i915_read_mch_val - return value for IPS use
  2554. *
  2555. * Calculate and return a value for the IPS driver to use when deciding whether
  2556. * we have thermal and power headroom to increase CPU or GPU power budget.
  2557. */
  2558. unsigned long i915_read_mch_val(void)
  2559. {
  2560. struct drm_i915_private *dev_priv;
  2561. unsigned long chipset_val, graphics_val, ret = 0;
  2562. spin_lock(&mchdev_lock);
  2563. if (!i915_mch_dev)
  2564. goto out_unlock;
  2565. dev_priv = i915_mch_dev;
  2566. chipset_val = i915_chipset_val(dev_priv);
  2567. graphics_val = i915_gfx_val(dev_priv);
  2568. ret = chipset_val + graphics_val;
  2569. out_unlock:
  2570. spin_unlock(&mchdev_lock);
  2571. return ret;
  2572. }
  2573. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  2574. /**
  2575. * i915_gpu_raise - raise GPU frequency limit
  2576. *
  2577. * Raise the limit; IPS indicates we have thermal headroom.
  2578. */
  2579. bool i915_gpu_raise(void)
  2580. {
  2581. struct drm_i915_private *dev_priv;
  2582. bool ret = true;
  2583. spin_lock(&mchdev_lock);
  2584. if (!i915_mch_dev) {
  2585. ret = false;
  2586. goto out_unlock;
  2587. }
  2588. dev_priv = i915_mch_dev;
  2589. if (dev_priv->max_delay > dev_priv->fmax)
  2590. dev_priv->max_delay--;
  2591. out_unlock:
  2592. spin_unlock(&mchdev_lock);
  2593. return ret;
  2594. }
  2595. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  2596. /**
  2597. * i915_gpu_lower - lower GPU frequency limit
  2598. *
  2599. * IPS indicates we're close to a thermal limit, so throttle back the GPU
  2600. * frequency maximum.
  2601. */
  2602. bool i915_gpu_lower(void)
  2603. {
  2604. struct drm_i915_private *dev_priv;
  2605. bool ret = true;
  2606. spin_lock(&mchdev_lock);
  2607. if (!i915_mch_dev) {
  2608. ret = false;
  2609. goto out_unlock;
  2610. }
  2611. dev_priv = i915_mch_dev;
  2612. if (dev_priv->max_delay < dev_priv->min_delay)
  2613. dev_priv->max_delay++;
  2614. out_unlock:
  2615. spin_unlock(&mchdev_lock);
  2616. return ret;
  2617. }
  2618. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  2619. /**
  2620. * i915_gpu_busy - indicate GPU business to IPS
  2621. *
  2622. * Tell the IPS driver whether or not the GPU is busy.
  2623. */
  2624. bool i915_gpu_busy(void)
  2625. {
  2626. struct drm_i915_private *dev_priv;
  2627. bool ret = false;
  2628. spin_lock(&mchdev_lock);
  2629. if (!i915_mch_dev)
  2630. goto out_unlock;
  2631. dev_priv = i915_mch_dev;
  2632. ret = dev_priv->busy;
  2633. out_unlock:
  2634. spin_unlock(&mchdev_lock);
  2635. return ret;
  2636. }
  2637. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  2638. /**
  2639. * i915_gpu_turbo_disable - disable graphics turbo
  2640. *
  2641. * Disable graphics turbo by resetting the max frequency and setting the
  2642. * current frequency to the default.
  2643. */
  2644. bool i915_gpu_turbo_disable(void)
  2645. {
  2646. struct drm_i915_private *dev_priv;
  2647. bool ret = true;
  2648. spin_lock(&mchdev_lock);
  2649. if (!i915_mch_dev) {
  2650. ret = false;
  2651. goto out_unlock;
  2652. }
  2653. dev_priv = i915_mch_dev;
  2654. dev_priv->max_delay = dev_priv->fstart;
  2655. if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
  2656. ret = false;
  2657. out_unlock:
  2658. spin_unlock(&mchdev_lock);
  2659. return ret;
  2660. }
  2661. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  2662. /**
  2663. * Tells the intel_ips driver that the i915 driver is now loaded, if
  2664. * IPS got loaded first.
  2665. *
  2666. * This awkward dance is so that neither module has to depend on the
  2667. * other in order for IPS to do the appropriate communication of
  2668. * GPU turbo limits to i915.
  2669. */
  2670. static void
  2671. ips_ping_for_i915_load(void)
  2672. {
  2673. void (*link)(void);
  2674. link = symbol_get(ips_link_to_i915_driver);
  2675. if (link) {
  2676. link();
  2677. symbol_put(ips_link_to_i915_driver);
  2678. }
  2679. }
  2680. void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
  2681. {
  2682. spin_lock(&mchdev_lock);
  2683. i915_mch_dev = dev_priv;
  2684. dev_priv->mchdev_lock = &mchdev_lock;
  2685. spin_unlock(&mchdev_lock);
  2686. ips_ping_for_i915_load();
  2687. }
  2688. void intel_gpu_ips_teardown(void)
  2689. {
  2690. spin_lock(&mchdev_lock);
  2691. i915_mch_dev = NULL;
  2692. spin_unlock(&mchdev_lock);
  2693. }
  2694. static void intel_init_emon(struct drm_device *dev)
  2695. {
  2696. struct drm_i915_private *dev_priv = dev->dev_private;
  2697. u32 lcfuse;
  2698. u8 pxw[16];
  2699. int i;
  2700. /* Disable to program */
  2701. I915_WRITE(ECR, 0);
  2702. POSTING_READ(ECR);
  2703. /* Program energy weights for various events */
  2704. I915_WRITE(SDEW, 0x15040d00);
  2705. I915_WRITE(CSIEW0, 0x007f0000);
  2706. I915_WRITE(CSIEW1, 0x1e220004);
  2707. I915_WRITE(CSIEW2, 0x04000004);
  2708. for (i = 0; i < 5; i++)
  2709. I915_WRITE(PEW + (i * 4), 0);
  2710. for (i = 0; i < 3; i++)
  2711. I915_WRITE(DEW + (i * 4), 0);
  2712. /* Program P-state weights to account for frequency power adjustment */
  2713. for (i = 0; i < 16; i++) {
  2714. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  2715. unsigned long freq = intel_pxfreq(pxvidfreq);
  2716. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  2717. PXVFREQ_PX_SHIFT;
  2718. unsigned long val;
  2719. val = vid * vid;
  2720. val *= (freq / 1000);
  2721. val *= 255;
  2722. val /= (127*127*900);
  2723. if (val > 0xff)
  2724. DRM_ERROR("bad pxval: %ld\n", val);
  2725. pxw[i] = val;
  2726. }
  2727. /* Render standby states get 0 weight */
  2728. pxw[14] = 0;
  2729. pxw[15] = 0;
  2730. for (i = 0; i < 4; i++) {
  2731. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  2732. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  2733. I915_WRITE(PXW + (i * 4), val);
  2734. }
  2735. /* Adjust magic regs to magic values (more experimental results) */
  2736. I915_WRITE(OGW0, 0);
  2737. I915_WRITE(OGW1, 0);
  2738. I915_WRITE(EG0, 0x00007f00);
  2739. I915_WRITE(EG1, 0x0000000e);
  2740. I915_WRITE(EG2, 0x000e0000);
  2741. I915_WRITE(EG3, 0x68000300);
  2742. I915_WRITE(EG4, 0x42000000);
  2743. I915_WRITE(EG5, 0x00140031);
  2744. I915_WRITE(EG6, 0);
  2745. I915_WRITE(EG7, 0);
  2746. for (i = 0; i < 8; i++)
  2747. I915_WRITE(PXWL + (i * 4), 0);
  2748. /* Enable PMON + select events */
  2749. I915_WRITE(ECR, 0x80000019);
  2750. lcfuse = I915_READ(LCFUSE02);
  2751. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  2752. }
  2753. void intel_disable_gt_powersave(struct drm_device *dev)
  2754. {
  2755. if (IS_IRONLAKE_M(dev)) {
  2756. ironlake_disable_drps(dev);
  2757. ironlake_disable_rc6(dev);
  2758. } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
  2759. gen6_disable_rps(dev);
  2760. }
  2761. }
  2762. void intel_enable_gt_powersave(struct drm_device *dev)
  2763. {
  2764. if (IS_IRONLAKE_M(dev)) {
  2765. ironlake_enable_drps(dev);
  2766. ironlake_enable_rc6(dev);
  2767. intel_init_emon(dev);
  2768. } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
  2769. gen6_enable_rps(dev);
  2770. gen6_update_ring_freq(dev);
  2771. }
  2772. }
  2773. static void ironlake_init_clock_gating(struct drm_device *dev)
  2774. {
  2775. struct drm_i915_private *dev_priv = dev->dev_private;
  2776. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2777. /* Required for FBC */
  2778. dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
  2779. DPFCRUNIT_CLOCK_GATE_DISABLE |
  2780. DPFDUNIT_CLOCK_GATE_DISABLE;
  2781. /* Required for CxSR */
  2782. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  2783. I915_WRITE(PCH_3DCGDIS0,
  2784. MARIUNIT_CLOCK_GATE_DISABLE |
  2785. SVSMUNIT_CLOCK_GATE_DISABLE);
  2786. I915_WRITE(PCH_3DCGDIS1,
  2787. VFMUNIT_CLOCK_GATE_DISABLE);
  2788. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2789. /*
  2790. * According to the spec the following bits should be set in
  2791. * order to enable memory self-refresh
  2792. * The bit 22/21 of 0x42004
  2793. * The bit 5 of 0x42020
  2794. * The bit 15 of 0x45000
  2795. */
  2796. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2797. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  2798. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  2799. I915_WRITE(ILK_DSPCLK_GATE,
  2800. (I915_READ(ILK_DSPCLK_GATE) |
  2801. ILK_DPARB_CLK_GATE));
  2802. I915_WRITE(DISP_ARB_CTL,
  2803. (I915_READ(DISP_ARB_CTL) |
  2804. DISP_FBC_WM_DIS));
  2805. I915_WRITE(WM3_LP_ILK, 0);
  2806. I915_WRITE(WM2_LP_ILK, 0);
  2807. I915_WRITE(WM1_LP_ILK, 0);
  2808. /*
  2809. * Based on the document from hardware guys the following bits
  2810. * should be set unconditionally in order to enable FBC.
  2811. * The bit 22 of 0x42000
  2812. * The bit 22 of 0x42004
  2813. * The bit 7,8,9 of 0x42020.
  2814. */
  2815. if (IS_IRONLAKE_M(dev)) {
  2816. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  2817. I915_READ(ILK_DISPLAY_CHICKEN1) |
  2818. ILK_FBCQ_DIS);
  2819. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2820. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2821. ILK_DPARB_GATE);
  2822. I915_WRITE(ILK_DSPCLK_GATE,
  2823. I915_READ(ILK_DSPCLK_GATE) |
  2824. ILK_DPFC_DIS1 |
  2825. ILK_DPFC_DIS2 |
  2826. ILK_CLK_FBC);
  2827. }
  2828. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2829. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2830. ILK_ELPIN_409_SELECT);
  2831. I915_WRITE(_3D_CHICKEN2,
  2832. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  2833. _3D_CHICKEN2_WM_READ_PIPELINED);
  2834. }
  2835. static void gen6_init_clock_gating(struct drm_device *dev)
  2836. {
  2837. struct drm_i915_private *dev_priv = dev->dev_private;
  2838. int pipe;
  2839. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2840. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2841. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2842. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2843. ILK_ELPIN_409_SELECT);
  2844. I915_WRITE(WM3_LP_ILK, 0);
  2845. I915_WRITE(WM2_LP_ILK, 0);
  2846. I915_WRITE(WM1_LP_ILK, 0);
  2847. I915_WRITE(CACHE_MODE_0,
  2848. _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
  2849. I915_WRITE(GEN6_UCGCTL1,
  2850. I915_READ(GEN6_UCGCTL1) |
  2851. GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
  2852. GEN6_CSUNIT_CLOCK_GATE_DISABLE);
  2853. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  2854. * gating disable must be set. Failure to set it results in
  2855. * flickering pixels due to Z write ordering failures after
  2856. * some amount of runtime in the Mesa "fire" demo, and Unigine
  2857. * Sanctuary and Tropics, and apparently anything else with
  2858. * alpha test or pixel discard.
  2859. *
  2860. * According to the spec, bit 11 (RCCUNIT) must also be set,
  2861. * but we didn't debug actual testcases to find it out.
  2862. *
  2863. * Also apply WaDisableVDSUnitClockGating and
  2864. * WaDisableRCPBUnitClockGating.
  2865. */
  2866. I915_WRITE(GEN6_UCGCTL2,
  2867. GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  2868. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  2869. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  2870. /* Bspec says we need to always set all mask bits. */
  2871. I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
  2872. _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
  2873. /*
  2874. * According to the spec the following bits should be
  2875. * set in order to enable memory self-refresh and fbc:
  2876. * The bit21 and bit22 of 0x42000
  2877. * The bit21 and bit22 of 0x42004
  2878. * The bit5 and bit7 of 0x42020
  2879. * The bit14 of 0x70180
  2880. * The bit14 of 0x71180
  2881. */
  2882. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  2883. I915_READ(ILK_DISPLAY_CHICKEN1) |
  2884. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  2885. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  2886. I915_READ(ILK_DISPLAY_CHICKEN2) |
  2887. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  2888. I915_WRITE(ILK_DSPCLK_GATE,
  2889. I915_READ(ILK_DSPCLK_GATE) |
  2890. ILK_DPARB_CLK_GATE |
  2891. ILK_DPFD_CLK_GATE);
  2892. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  2893. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  2894. for_each_pipe(pipe) {
  2895. I915_WRITE(DSPCNTR(pipe),
  2896. I915_READ(DSPCNTR(pipe)) |
  2897. DISPPLANE_TRICKLE_FEED_DISABLE);
  2898. intel_flush_display_plane(dev_priv, pipe);
  2899. }
  2900. }
  2901. static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
  2902. {
  2903. uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
  2904. reg &= ~GEN7_FF_SCHED_MASK;
  2905. reg |= GEN7_FF_TS_SCHED_HW;
  2906. reg |= GEN7_FF_VS_SCHED_HW;
  2907. reg |= GEN7_FF_DS_SCHED_HW;
  2908. I915_WRITE(GEN7_FF_THREAD_MODE, reg);
  2909. }
  2910. static void haswell_init_clock_gating(struct drm_device *dev)
  2911. {
  2912. struct drm_i915_private *dev_priv = dev->dev_private;
  2913. int pipe;
  2914. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2915. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2916. I915_WRITE(WM3_LP_ILK, 0);
  2917. I915_WRITE(WM2_LP_ILK, 0);
  2918. I915_WRITE(WM1_LP_ILK, 0);
  2919. /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  2920. * This implements the WaDisableRCZUnitClockGating workaround.
  2921. */
  2922. I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
  2923. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  2924. I915_WRITE(IVB_CHICKEN3,
  2925. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  2926. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  2927. /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  2928. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  2929. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  2930. /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  2931. I915_WRITE(GEN7_L3CNTLREG1,
  2932. GEN7_WA_FOR_GEN7_L3_CONTROL);
  2933. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  2934. GEN7_WA_L3_CHICKEN_MODE);
  2935. /* This is required by WaCatErrorRejectionIssue */
  2936. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  2937. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  2938. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  2939. for_each_pipe(pipe) {
  2940. I915_WRITE(DSPCNTR(pipe),
  2941. I915_READ(DSPCNTR(pipe)) |
  2942. DISPPLANE_TRICKLE_FEED_DISABLE);
  2943. intel_flush_display_plane(dev_priv, pipe);
  2944. }
  2945. gen7_setup_fixed_func_scheduler(dev_priv);
  2946. /* WaDisable4x2SubspanOptimization */
  2947. I915_WRITE(CACHE_MODE_1,
  2948. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  2949. /* XXX: This is a workaround for early silicon revisions and should be
  2950. * removed later.
  2951. */
  2952. I915_WRITE(WM_DBG,
  2953. I915_READ(WM_DBG) |
  2954. WM_DBG_DISALLOW_MULTIPLE_LP |
  2955. WM_DBG_DISALLOW_SPRITE |
  2956. WM_DBG_DISALLOW_MAXFIFO);
  2957. }
  2958. static void ivybridge_init_clock_gating(struct drm_device *dev)
  2959. {
  2960. struct drm_i915_private *dev_priv = dev->dev_private;
  2961. int pipe;
  2962. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  2963. uint32_t snpcr;
  2964. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  2965. I915_WRITE(WM3_LP_ILK, 0);
  2966. I915_WRITE(WM2_LP_ILK, 0);
  2967. I915_WRITE(WM1_LP_ILK, 0);
  2968. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  2969. I915_WRITE(IVB_CHICKEN3,
  2970. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  2971. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  2972. /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  2973. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  2974. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  2975. /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  2976. I915_WRITE(GEN7_L3CNTLREG1,
  2977. GEN7_WA_FOR_GEN7_L3_CONTROL);
  2978. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  2979. GEN7_WA_L3_CHICKEN_MODE);
  2980. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  2981. * gating disable must be set. Failure to set it results in
  2982. * flickering pixels due to Z write ordering failures after
  2983. * some amount of runtime in the Mesa "fire" demo, and Unigine
  2984. * Sanctuary and Tropics, and apparently anything else with
  2985. * alpha test or pixel discard.
  2986. *
  2987. * According to the spec, bit 11 (RCCUNIT) must also be set,
  2988. * but we didn't debug actual testcases to find it out.
  2989. *
  2990. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  2991. * This implements the WaDisableRCZUnitClockGating workaround.
  2992. */
  2993. I915_WRITE(GEN6_UCGCTL2,
  2994. GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  2995. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  2996. /* This is required by WaCatErrorRejectionIssue */
  2997. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  2998. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  2999. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  3000. for_each_pipe(pipe) {
  3001. I915_WRITE(DSPCNTR(pipe),
  3002. I915_READ(DSPCNTR(pipe)) |
  3003. DISPPLANE_TRICKLE_FEED_DISABLE);
  3004. intel_flush_display_plane(dev_priv, pipe);
  3005. }
  3006. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3007. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3008. gen7_setup_fixed_func_scheduler(dev_priv);
  3009. /* WaDisable4x2SubspanOptimization */
  3010. I915_WRITE(CACHE_MODE_1,
  3011. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  3012. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  3013. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  3014. snpcr |= GEN6_MBC_SNPCR_MED;
  3015. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  3016. }
  3017. static void valleyview_init_clock_gating(struct drm_device *dev)
  3018. {
  3019. struct drm_i915_private *dev_priv = dev->dev_private;
  3020. int pipe;
  3021. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  3022. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  3023. I915_WRITE(WM3_LP_ILK, 0);
  3024. I915_WRITE(WM2_LP_ILK, 0);
  3025. I915_WRITE(WM1_LP_ILK, 0);
  3026. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  3027. I915_WRITE(IVB_CHICKEN3,
  3028. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  3029. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  3030. /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  3031. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  3032. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  3033. /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
  3034. I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
  3035. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
  3036. /* This is required by WaCatErrorRejectionIssue */
  3037. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  3038. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  3039. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  3040. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3041. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3042. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  3043. * gating disable must be set. Failure to set it results in
  3044. * flickering pixels due to Z write ordering failures after
  3045. * some amount of runtime in the Mesa "fire" demo, and Unigine
  3046. * Sanctuary and Tropics, and apparently anything else with
  3047. * alpha test or pixel discard.
  3048. *
  3049. * According to the spec, bit 11 (RCCUNIT) must also be set,
  3050. * but we didn't debug actual testcases to find it out.
  3051. *
  3052. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  3053. * This implements the WaDisableRCZUnitClockGating workaround.
  3054. *
  3055. * Also apply WaDisableVDSUnitClockGating and
  3056. * WaDisableRCPBUnitClockGating.
  3057. */
  3058. I915_WRITE(GEN6_UCGCTL2,
  3059. GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  3060. GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
  3061. GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  3062. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  3063. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  3064. I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
  3065. for_each_pipe(pipe) {
  3066. I915_WRITE(DSPCNTR(pipe),
  3067. I915_READ(DSPCNTR(pipe)) |
  3068. DISPPLANE_TRICKLE_FEED_DISABLE);
  3069. intel_flush_display_plane(dev_priv, pipe);
  3070. }
  3071. I915_WRITE(CACHE_MODE_1,
  3072. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  3073. /*
  3074. * On ValleyView, the GUnit needs to signal the GT
  3075. * when flip and other events complete. So enable
  3076. * all the GUnit->GT interrupts here
  3077. */
  3078. I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
  3079. PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
  3080. SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
  3081. PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
  3082. PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
  3083. SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
  3084. PLANEA_FLIPDONE_INT_EN);
  3085. }
  3086. static void g4x_init_clock_gating(struct drm_device *dev)
  3087. {
  3088. struct drm_i915_private *dev_priv = dev->dev_private;
  3089. uint32_t dspclk_gate;
  3090. I915_WRITE(RENCLK_GATE_D1, 0);
  3091. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  3092. GS_UNIT_CLOCK_GATE_DISABLE |
  3093. CL_UNIT_CLOCK_GATE_DISABLE);
  3094. I915_WRITE(RAMCLK_GATE_D, 0);
  3095. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  3096. OVRUNIT_CLOCK_GATE_DISABLE |
  3097. OVCUNIT_CLOCK_GATE_DISABLE;
  3098. if (IS_GM45(dev))
  3099. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  3100. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  3101. }
  3102. static void crestline_init_clock_gating(struct drm_device *dev)
  3103. {
  3104. struct drm_i915_private *dev_priv = dev->dev_private;
  3105. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  3106. I915_WRITE(RENCLK_GATE_D2, 0);
  3107. I915_WRITE(DSPCLK_GATE_D, 0);
  3108. I915_WRITE(RAMCLK_GATE_D, 0);
  3109. I915_WRITE16(DEUC, 0);
  3110. }
  3111. static void broadwater_init_clock_gating(struct drm_device *dev)
  3112. {
  3113. struct drm_i915_private *dev_priv = dev->dev_private;
  3114. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  3115. I965_RCC_CLOCK_GATE_DISABLE |
  3116. I965_RCPB_CLOCK_GATE_DISABLE |
  3117. I965_ISC_CLOCK_GATE_DISABLE |
  3118. I965_FBC_CLOCK_GATE_DISABLE);
  3119. I915_WRITE(RENCLK_GATE_D2, 0);
  3120. }
  3121. static void gen3_init_clock_gating(struct drm_device *dev)
  3122. {
  3123. struct drm_i915_private *dev_priv = dev->dev_private;
  3124. u32 dstate = I915_READ(D_STATE);
  3125. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  3126. DSTATE_DOT_CLOCK_GATING;
  3127. I915_WRITE(D_STATE, dstate);
  3128. if (IS_PINEVIEW(dev))
  3129. I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
  3130. /* IIR "flip pending" means done if this bit is set */
  3131. I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
  3132. }
  3133. static void i85x_init_clock_gating(struct drm_device *dev)
  3134. {
  3135. struct drm_i915_private *dev_priv = dev->dev_private;
  3136. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  3137. }
  3138. static void i830_init_clock_gating(struct drm_device *dev)
  3139. {
  3140. struct drm_i915_private *dev_priv = dev->dev_private;
  3141. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  3142. }
  3143. static void ibx_init_clock_gating(struct drm_device *dev)
  3144. {
  3145. struct drm_i915_private *dev_priv = dev->dev_private;
  3146. /*
  3147. * On Ibex Peak and Cougar Point, we need to disable clock
  3148. * gating for the panel power sequencer or it will fail to
  3149. * start up when no ports are active.
  3150. */
  3151. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3152. }
  3153. static void cpt_init_clock_gating(struct drm_device *dev)
  3154. {
  3155. struct drm_i915_private *dev_priv = dev->dev_private;
  3156. int pipe;
  3157. /*
  3158. * On Ibex Peak and Cougar Point, we need to disable clock
  3159. * gating for the panel power sequencer or it will fail to
  3160. * start up when no ports are active.
  3161. */
  3162. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3163. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  3164. DPLS_EDP_PPS_FIX_DIS);
  3165. /* Without this, mode sets may fail silently on FDI */
  3166. for_each_pipe(pipe)
  3167. I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
  3168. }
  3169. void intel_init_clock_gating(struct drm_device *dev)
  3170. {
  3171. struct drm_i915_private *dev_priv = dev->dev_private;
  3172. dev_priv->display.init_clock_gating(dev);
  3173. if (dev_priv->display.init_pch_clock_gating)
  3174. dev_priv->display.init_pch_clock_gating(dev);
  3175. }
  3176. static void gen6_sanitize_pm(struct drm_device *dev)
  3177. {
  3178. struct drm_i915_private *dev_priv = dev->dev_private;
  3179. u32 limits, delay, old;
  3180. gen6_gt_force_wake_get(dev_priv);
  3181. old = limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
  3182. /* Make sure we continue to get interrupts
  3183. * until we hit the minimum or maximum frequencies.
  3184. */
  3185. limits &= ~(0x3f << 16 | 0x3f << 24);
  3186. delay = dev_priv->cur_delay;
  3187. if (delay < dev_priv->max_delay)
  3188. limits |= (dev_priv->max_delay & 0x3f) << 24;
  3189. if (delay > dev_priv->min_delay)
  3190. limits |= (dev_priv->min_delay & 0x3f) << 16;
  3191. if (old != limits) {
  3192. /* Note that the known failure case is to read back 0. */
  3193. DRM_DEBUG_DRIVER("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS "
  3194. "expected %08x, was %08x\n", limits, old);
  3195. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  3196. }
  3197. gen6_gt_force_wake_put(dev_priv);
  3198. }
  3199. void intel_sanitize_pm(struct drm_device *dev)
  3200. {
  3201. struct drm_i915_private *dev_priv = dev->dev_private;
  3202. if (dev_priv->display.sanitize_pm)
  3203. dev_priv->display.sanitize_pm(dev);
  3204. }
  3205. /* Starting with Haswell, we have different power wells for
  3206. * different parts of the GPU. This attempts to enable them all.
  3207. */
  3208. void intel_init_power_wells(struct drm_device *dev)
  3209. {
  3210. struct drm_i915_private *dev_priv = dev->dev_private;
  3211. unsigned long power_wells[] = {
  3212. HSW_PWR_WELL_CTL1,
  3213. HSW_PWR_WELL_CTL2,
  3214. HSW_PWR_WELL_CTL4
  3215. };
  3216. int i;
  3217. if (!IS_HASWELL(dev))
  3218. return;
  3219. mutex_lock(&dev->struct_mutex);
  3220. for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
  3221. int well = I915_READ(power_wells[i]);
  3222. if ((well & HSW_PWR_WELL_STATE) == 0) {
  3223. I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
  3224. if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
  3225. DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
  3226. }
  3227. }
  3228. mutex_unlock(&dev->struct_mutex);
  3229. }
  3230. /* Set up chip specific power management-related functions */
  3231. void intel_init_pm(struct drm_device *dev)
  3232. {
  3233. struct drm_i915_private *dev_priv = dev->dev_private;
  3234. if (I915_HAS_FBC(dev)) {
  3235. if (HAS_PCH_SPLIT(dev)) {
  3236. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  3237. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  3238. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  3239. } else if (IS_GM45(dev)) {
  3240. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  3241. dev_priv->display.enable_fbc = g4x_enable_fbc;
  3242. dev_priv->display.disable_fbc = g4x_disable_fbc;
  3243. } else if (IS_CRESTLINE(dev)) {
  3244. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  3245. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  3246. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  3247. }
  3248. /* 855GM needs testing */
  3249. }
  3250. /* For cxsr */
  3251. if (IS_PINEVIEW(dev))
  3252. i915_pineview_get_mem_freq(dev);
  3253. else if (IS_GEN5(dev))
  3254. i915_ironlake_get_mem_freq(dev);
  3255. /* For FIFO watermark updates */
  3256. if (HAS_PCH_SPLIT(dev)) {
  3257. if (HAS_PCH_IBX(dev))
  3258. dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
  3259. else if (HAS_PCH_CPT(dev))
  3260. dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
  3261. if (IS_GEN5(dev)) {
  3262. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  3263. dev_priv->display.update_wm = ironlake_update_wm;
  3264. else {
  3265. DRM_DEBUG_KMS("Failed to get proper latency. "
  3266. "Disable CxSR\n");
  3267. dev_priv->display.update_wm = NULL;
  3268. }
  3269. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  3270. } else if (IS_GEN6(dev)) {
  3271. if (SNB_READ_WM0_LATENCY()) {
  3272. dev_priv->display.update_wm = sandybridge_update_wm;
  3273. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3274. } else {
  3275. DRM_DEBUG_KMS("Failed to read display plane latency. "
  3276. "Disable CxSR\n");
  3277. dev_priv->display.update_wm = NULL;
  3278. }
  3279. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  3280. dev_priv->display.sanitize_pm = gen6_sanitize_pm;
  3281. } else if (IS_IVYBRIDGE(dev)) {
  3282. /* FIXME: detect B0+ stepping and use auto training */
  3283. if (SNB_READ_WM0_LATENCY()) {
  3284. dev_priv->display.update_wm = sandybridge_update_wm;
  3285. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3286. } else {
  3287. DRM_DEBUG_KMS("Failed to read display plane latency. "
  3288. "Disable CxSR\n");
  3289. dev_priv->display.update_wm = NULL;
  3290. }
  3291. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  3292. dev_priv->display.sanitize_pm = gen6_sanitize_pm;
  3293. } else if (IS_HASWELL(dev)) {
  3294. if (SNB_READ_WM0_LATENCY()) {
  3295. dev_priv->display.update_wm = sandybridge_update_wm;
  3296. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  3297. dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
  3298. } else {
  3299. DRM_DEBUG_KMS("Failed to read display plane latency. "
  3300. "Disable CxSR\n");
  3301. dev_priv->display.update_wm = NULL;
  3302. }
  3303. dev_priv->display.init_clock_gating = haswell_init_clock_gating;
  3304. dev_priv->display.sanitize_pm = gen6_sanitize_pm;
  3305. } else
  3306. dev_priv->display.update_wm = NULL;
  3307. } else if (IS_VALLEYVIEW(dev)) {
  3308. dev_priv->display.update_wm = valleyview_update_wm;
  3309. dev_priv->display.init_clock_gating =
  3310. valleyview_init_clock_gating;
  3311. } else if (IS_PINEVIEW(dev)) {
  3312. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  3313. dev_priv->is_ddr3,
  3314. dev_priv->fsb_freq,
  3315. dev_priv->mem_freq)) {
  3316. DRM_INFO("failed to find known CxSR latency "
  3317. "(found ddr%s fsb freq %d, mem freq %d), "
  3318. "disabling CxSR\n",
  3319. (dev_priv->is_ddr3 == 1) ? "3" : "2",
  3320. dev_priv->fsb_freq, dev_priv->mem_freq);
  3321. /* Disable CxSR and never update its watermark again */
  3322. pineview_disable_cxsr(dev);
  3323. dev_priv->display.update_wm = NULL;
  3324. } else
  3325. dev_priv->display.update_wm = pineview_update_wm;
  3326. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  3327. } else if (IS_G4X(dev)) {
  3328. dev_priv->display.update_wm = g4x_update_wm;
  3329. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  3330. } else if (IS_GEN4(dev)) {
  3331. dev_priv->display.update_wm = i965_update_wm;
  3332. if (IS_CRESTLINE(dev))
  3333. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  3334. else if (IS_BROADWATER(dev))
  3335. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  3336. } else if (IS_GEN3(dev)) {
  3337. dev_priv->display.update_wm = i9xx_update_wm;
  3338. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  3339. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  3340. } else if (IS_I865G(dev)) {
  3341. dev_priv->display.update_wm = i830_update_wm;
  3342. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  3343. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3344. } else if (IS_I85X(dev)) {
  3345. dev_priv->display.update_wm = i9xx_update_wm;
  3346. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  3347. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  3348. } else {
  3349. dev_priv->display.update_wm = i830_update_wm;
  3350. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  3351. if (IS_845G(dev))
  3352. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  3353. else
  3354. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3355. }
  3356. }
  3357. static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  3358. {
  3359. u32 gt_thread_status_mask;
  3360. if (IS_HASWELL(dev_priv->dev))
  3361. gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
  3362. else
  3363. gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
  3364. /* w/a for a sporadic read returning 0 by waiting for the GT
  3365. * thread to wake up.
  3366. */
  3367. if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
  3368. DRM_ERROR("GT thread status wait timed out\n");
  3369. }
  3370. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  3371. {
  3372. u32 forcewake_ack;
  3373. if (IS_HASWELL(dev_priv->dev))
  3374. forcewake_ack = FORCEWAKE_ACK_HSW;
  3375. else
  3376. forcewake_ack = FORCEWAKE_ACK;
  3377. if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500))
  3378. DRM_ERROR("Force wake wait timed out\n");
  3379. I915_WRITE_NOTRACE(FORCEWAKE, 1);
  3380. POSTING_READ(FORCEWAKE);
  3381. if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
  3382. DRM_ERROR("Force wake wait timed out\n");
  3383. __gen6_gt_wait_for_thread_c0(dev_priv);
  3384. }
  3385. static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
  3386. {
  3387. u32 forcewake_ack;
  3388. if (IS_HASWELL(dev_priv->dev))
  3389. forcewake_ack = FORCEWAKE_ACK_HSW;
  3390. else
  3391. forcewake_ack = FORCEWAKE_MT_ACK;
  3392. if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 500))
  3393. DRM_ERROR("Force wake wait timed out\n");
  3394. I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
  3395. POSTING_READ(FORCEWAKE_MT);
  3396. if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
  3397. DRM_ERROR("Force wake wait timed out\n");
  3398. __gen6_gt_wait_for_thread_c0(dev_priv);
  3399. }
  3400. /*
  3401. * Generally this is called implicitly by the register read function. However,
  3402. * if some sequence requires the GT to not power down then this function should
  3403. * be called at the beginning of the sequence followed by a call to
  3404. * gen6_gt_force_wake_put() at the end of the sequence.
  3405. */
  3406. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  3407. {
  3408. unsigned long irqflags;
  3409. spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  3410. if (dev_priv->forcewake_count++ == 0)
  3411. dev_priv->gt.force_wake_get(dev_priv);
  3412. spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  3413. }
  3414. void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
  3415. {
  3416. u32 gtfifodbg;
  3417. gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
  3418. if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
  3419. "MMIO read or write has been dropped %x\n", gtfifodbg))
  3420. I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
  3421. }
  3422. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  3423. {
  3424. I915_WRITE_NOTRACE(FORCEWAKE, 0);
  3425. POSTING_READ(FORCEWAKE);
  3426. gen6_gt_check_fifodbg(dev_priv);
  3427. }
  3428. static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
  3429. {
  3430. I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
  3431. POSTING_READ(FORCEWAKE_MT);
  3432. gen6_gt_check_fifodbg(dev_priv);
  3433. }
  3434. /*
  3435. * see gen6_gt_force_wake_get()
  3436. */
  3437. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  3438. {
  3439. unsigned long irqflags;
  3440. spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  3441. if (--dev_priv->forcewake_count == 0)
  3442. dev_priv->gt.force_wake_put(dev_priv);
  3443. spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  3444. }
  3445. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  3446. {
  3447. int ret = 0;
  3448. if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
  3449. int loop = 500;
  3450. u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  3451. while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  3452. udelay(10);
  3453. fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  3454. }
  3455. if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
  3456. ++ret;
  3457. dev_priv->gt_fifo_count = fifo;
  3458. }
  3459. dev_priv->gt_fifo_count--;
  3460. return ret;
  3461. }
  3462. static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
  3463. {
  3464. /* Already awake? */
  3465. if ((I915_READ(0x130094) & 0xa1) == 0xa1)
  3466. return;
  3467. I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
  3468. POSTING_READ(FORCEWAKE_VLV);
  3469. if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500))
  3470. DRM_ERROR("Force wake wait timed out\n");
  3471. __gen6_gt_wait_for_thread_c0(dev_priv);
  3472. }
  3473. static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
  3474. {
  3475. I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
  3476. /* FIXME: confirm VLV behavior with Punit folks */
  3477. POSTING_READ(FORCEWAKE_VLV);
  3478. }
  3479. void intel_gt_init(struct drm_device *dev)
  3480. {
  3481. struct drm_i915_private *dev_priv = dev->dev_private;
  3482. spin_lock_init(&dev_priv->gt_lock);
  3483. if (IS_VALLEYVIEW(dev)) {
  3484. dev_priv->gt.force_wake_get = vlv_force_wake_get;
  3485. dev_priv->gt.force_wake_put = vlv_force_wake_put;
  3486. } else if (INTEL_INFO(dev)->gen >= 6) {
  3487. dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
  3488. dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
  3489. /* IVB configs may use multi-threaded forcewake */
  3490. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  3491. u32 ecobus;
  3492. /* A small trick here - if the bios hasn't configured
  3493. * MT forcewake, and if the device is in RC6, then
  3494. * force_wake_mt_get will not wake the device and the
  3495. * ECOBUS read will return zero. Which will be
  3496. * (correctly) interpreted by the test below as MT
  3497. * forcewake being disabled.
  3498. */
  3499. mutex_lock(&dev->struct_mutex);
  3500. __gen6_gt_force_wake_mt_get(dev_priv);
  3501. ecobus = I915_READ_NOTRACE(ECOBUS);
  3502. __gen6_gt_force_wake_mt_put(dev_priv);
  3503. mutex_unlock(&dev->struct_mutex);
  3504. if (ecobus & FORCEWAKE_MT_ENABLE) {
  3505. DRM_DEBUG_KMS("Using MT version of forcewake\n");
  3506. dev_priv->gt.force_wake_get =
  3507. __gen6_gt_force_wake_mt_get;
  3508. dev_priv->gt.force_wake_put =
  3509. __gen6_gt_force_wake_mt_put;
  3510. }
  3511. }
  3512. }
  3513. }