wm8350-core.c 38 KB

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  1. /*
  2. * wm8350-core.c -- Device access for Wolfson WM8350
  3. *
  4. * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Liam Girdwood, Mark Brown
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/bug.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/mfd/wm8350/core.h>
  23. #include <linux/mfd/wm8350/audio.h>
  24. #include <linux/mfd/wm8350/comparator.h>
  25. #include <linux/mfd/wm8350/gpio.h>
  26. #include <linux/mfd/wm8350/pmic.h>
  27. #include <linux/mfd/wm8350/rtc.h>
  28. #include <linux/mfd/wm8350/supply.h>
  29. #include <linux/mfd/wm8350/wdt.h>
  30. #define WM8350_UNLOCK_KEY 0x0013
  31. #define WM8350_LOCK_KEY 0x0000
  32. #define WM8350_CLOCK_CONTROL_1 0x28
  33. #define WM8350_AIF_TEST 0x74
  34. /* debug */
  35. #define WM8350_BUS_DEBUG 0
  36. #if WM8350_BUS_DEBUG
  37. #define dump(regs, src) do { \
  38. int i_; \
  39. u16 *src_ = src; \
  40. printk(KERN_DEBUG); \
  41. for (i_ = 0; i_ < regs; i_++) \
  42. printk(" 0x%4.4x", *src_++); \
  43. printk("\n"); \
  44. } while (0);
  45. #else
  46. #define dump(bytes, src)
  47. #endif
  48. #define WM8350_LOCK_DEBUG 0
  49. #if WM8350_LOCK_DEBUG
  50. #define ldbg(format, arg...) printk(format, ## arg)
  51. #else
  52. #define ldbg(format, arg...)
  53. #endif
  54. /*
  55. * WM8350 Device IO
  56. */
  57. static DEFINE_MUTEX(io_mutex);
  58. static DEFINE_MUTEX(reg_lock_mutex);
  59. static DEFINE_MUTEX(auxadc_mutex);
  60. /* Perform a physical read from the device.
  61. */
  62. static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
  63. u16 *dest)
  64. {
  65. int i, ret;
  66. int bytes = num_regs * 2;
  67. dev_dbg(wm8350->dev, "volatile read\n");
  68. ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
  69. for (i = reg; i < reg + num_regs; i++) {
  70. /* Cache is CPU endian */
  71. dest[i - reg] = be16_to_cpu(dest[i - reg]);
  72. /* Satisfy non-volatile bits from cache */
  73. dest[i - reg] &= wm8350_reg_io_map[i].vol;
  74. dest[i - reg] |= wm8350->reg_cache[i];
  75. /* Mask out non-readable bits */
  76. dest[i - reg] &= wm8350_reg_io_map[i].readable;
  77. }
  78. dump(num_regs, dest);
  79. return ret;
  80. }
  81. static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
  82. {
  83. int i;
  84. int end = reg + num_regs;
  85. int ret = 0;
  86. int bytes = num_regs * 2;
  87. if (wm8350->read_dev == NULL)
  88. return -ENODEV;
  89. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  90. dev_err(wm8350->dev, "invalid reg %x\n",
  91. reg + num_regs - 1);
  92. return -EINVAL;
  93. }
  94. dev_dbg(wm8350->dev,
  95. "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
  96. #if WM8350_BUS_DEBUG
  97. /* we can _safely_ read any register, but warn if read not supported */
  98. for (i = reg; i < end; i++) {
  99. if (!wm8350_reg_io_map[i].readable)
  100. dev_warn(wm8350->dev,
  101. "reg R%d is not readable\n", i);
  102. }
  103. #endif
  104. /* if any volatile registers are required, then read back all */
  105. for (i = reg; i < end; i++)
  106. if (wm8350_reg_io_map[i].vol)
  107. return wm8350_phys_read(wm8350, reg, num_regs, dest);
  108. /* no volatiles, then cache is good */
  109. dev_dbg(wm8350->dev, "cache read\n");
  110. memcpy(dest, &wm8350->reg_cache[reg], bytes);
  111. dump(num_regs, dest);
  112. return ret;
  113. }
  114. static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
  115. {
  116. if (reg == WM8350_SECURITY ||
  117. wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
  118. return 0;
  119. if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
  120. (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
  121. reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
  122. (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
  123. reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
  124. return 1;
  125. return 0;
  126. }
  127. static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
  128. {
  129. int i;
  130. int end = reg + num_regs;
  131. int bytes = num_regs * 2;
  132. if (wm8350->write_dev == NULL)
  133. return -ENODEV;
  134. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  135. dev_err(wm8350->dev, "invalid reg %x\n",
  136. reg + num_regs - 1);
  137. return -EINVAL;
  138. }
  139. /* it's generally not a good idea to write to RO or locked registers */
  140. for (i = reg; i < end; i++) {
  141. if (!wm8350_reg_io_map[i].writable) {
  142. dev_err(wm8350->dev,
  143. "attempted write to read only reg R%d\n", i);
  144. return -EINVAL;
  145. }
  146. if (is_reg_locked(wm8350, i)) {
  147. dev_err(wm8350->dev,
  148. "attempted write to locked reg R%d\n", i);
  149. return -EINVAL;
  150. }
  151. src[i - reg] &= wm8350_reg_io_map[i].writable;
  152. wm8350->reg_cache[i] =
  153. (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
  154. | src[i - reg];
  155. /* Don't store volatile bits */
  156. wm8350->reg_cache[i] &= ~wm8350_reg_io_map[i].vol;
  157. src[i - reg] = cpu_to_be16(src[i - reg]);
  158. }
  159. /* Actually write it out */
  160. return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
  161. }
  162. /*
  163. * Safe read, modify, write methods
  164. */
  165. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  166. {
  167. u16 data;
  168. int err;
  169. mutex_lock(&io_mutex);
  170. err = wm8350_read(wm8350, reg, 1, &data);
  171. if (err) {
  172. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  173. goto out;
  174. }
  175. data &= ~mask;
  176. err = wm8350_write(wm8350, reg, 1, &data);
  177. if (err)
  178. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  179. out:
  180. mutex_unlock(&io_mutex);
  181. return err;
  182. }
  183. EXPORT_SYMBOL_GPL(wm8350_clear_bits);
  184. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  185. {
  186. u16 data;
  187. int err;
  188. mutex_lock(&io_mutex);
  189. err = wm8350_read(wm8350, reg, 1, &data);
  190. if (err) {
  191. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  192. goto out;
  193. }
  194. data |= mask;
  195. err = wm8350_write(wm8350, reg, 1, &data);
  196. if (err)
  197. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  198. out:
  199. mutex_unlock(&io_mutex);
  200. return err;
  201. }
  202. EXPORT_SYMBOL_GPL(wm8350_set_bits);
  203. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
  204. {
  205. u16 data;
  206. int err;
  207. mutex_lock(&io_mutex);
  208. err = wm8350_read(wm8350, reg, 1, &data);
  209. if (err)
  210. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  211. mutex_unlock(&io_mutex);
  212. return data;
  213. }
  214. EXPORT_SYMBOL_GPL(wm8350_reg_read);
  215. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
  216. {
  217. int ret;
  218. u16 data = val;
  219. mutex_lock(&io_mutex);
  220. ret = wm8350_write(wm8350, reg, 1, &data);
  221. if (ret)
  222. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  223. mutex_unlock(&io_mutex);
  224. return ret;
  225. }
  226. EXPORT_SYMBOL_GPL(wm8350_reg_write);
  227. int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
  228. u16 *dest)
  229. {
  230. int err = 0;
  231. mutex_lock(&io_mutex);
  232. err = wm8350_read(wm8350, start_reg, regs, dest);
  233. if (err)
  234. dev_err(wm8350->dev, "block read starting from R%d failed\n",
  235. start_reg);
  236. mutex_unlock(&io_mutex);
  237. return err;
  238. }
  239. EXPORT_SYMBOL_GPL(wm8350_block_read);
  240. int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
  241. u16 *src)
  242. {
  243. int ret = 0;
  244. mutex_lock(&io_mutex);
  245. ret = wm8350_write(wm8350, start_reg, regs, src);
  246. if (ret)
  247. dev_err(wm8350->dev, "block write starting at R%d failed\n",
  248. start_reg);
  249. mutex_unlock(&io_mutex);
  250. return ret;
  251. }
  252. EXPORT_SYMBOL_GPL(wm8350_block_write);
  253. /**
  254. * wm8350_reg_lock()
  255. *
  256. * The WM8350 has a hardware lock which can be used to prevent writes to
  257. * some registers (generally those which can cause particularly serious
  258. * problems if misused). This function enables that lock.
  259. */
  260. int wm8350_reg_lock(struct wm8350 *wm8350)
  261. {
  262. u16 key = WM8350_LOCK_KEY;
  263. int ret;
  264. ldbg(__func__);
  265. mutex_lock(&io_mutex);
  266. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  267. if (ret)
  268. dev_err(wm8350->dev, "lock failed\n");
  269. mutex_unlock(&io_mutex);
  270. return ret;
  271. }
  272. EXPORT_SYMBOL_GPL(wm8350_reg_lock);
  273. /**
  274. * wm8350_reg_unlock()
  275. *
  276. * The WM8350 has a hardware lock which can be used to prevent writes to
  277. * some registers (generally those which can cause particularly serious
  278. * problems if misused). This function disables that lock so updates
  279. * can be performed. For maximum safety this should be done only when
  280. * required.
  281. */
  282. int wm8350_reg_unlock(struct wm8350 *wm8350)
  283. {
  284. u16 key = WM8350_UNLOCK_KEY;
  285. int ret;
  286. ldbg(__func__);
  287. mutex_lock(&io_mutex);
  288. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  289. if (ret)
  290. dev_err(wm8350->dev, "unlock failed\n");
  291. mutex_unlock(&io_mutex);
  292. return ret;
  293. }
  294. EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
  295. static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
  296. {
  297. mutex_lock(&wm8350->irq_mutex);
  298. if (wm8350->irq[irq].handler)
  299. wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
  300. else {
  301. dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
  302. irq);
  303. wm8350_mask_irq(wm8350, irq);
  304. }
  305. mutex_unlock(&wm8350->irq_mutex);
  306. }
  307. /*
  308. * wm8350_irq_worker actually handles the interrupts. Since all
  309. * interrupts are clear on read the IRQ line will be reasserted and
  310. * the physical IRQ will be handled again if another interrupt is
  311. * asserted while we run - in the normal course of events this is a
  312. * rare occurrence so we save I2C/SPI reads.
  313. */
  314. static void wm8350_irq_worker(struct work_struct *work)
  315. {
  316. struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
  317. u16 level_one, status1, status2, comp;
  318. /* TODO: Use block reads to improve performance? */
  319. level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
  320. & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
  321. status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
  322. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
  323. status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
  324. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
  325. comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
  326. & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
  327. /* over current */
  328. if (level_one & WM8350_OC_INT) {
  329. u16 oc;
  330. oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
  331. oc &= ~wm8350_reg_read(wm8350,
  332. WM8350_OVER_CURRENT_INT_STATUS_MASK);
  333. if (oc & WM8350_OC_LS_EINT) /* limit switch */
  334. wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
  335. }
  336. /* under voltage */
  337. if (level_one & WM8350_UV_INT) {
  338. u16 uv;
  339. uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
  340. uv &= ~wm8350_reg_read(wm8350,
  341. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
  342. if (uv & WM8350_UV_DC1_EINT)
  343. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
  344. if (uv & WM8350_UV_DC2_EINT)
  345. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
  346. if (uv & WM8350_UV_DC3_EINT)
  347. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
  348. if (uv & WM8350_UV_DC4_EINT)
  349. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
  350. if (uv & WM8350_UV_DC5_EINT)
  351. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
  352. if (uv & WM8350_UV_DC6_EINT)
  353. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
  354. if (uv & WM8350_UV_LDO1_EINT)
  355. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
  356. if (uv & WM8350_UV_LDO2_EINT)
  357. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
  358. if (uv & WM8350_UV_LDO3_EINT)
  359. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
  360. if (uv & WM8350_UV_LDO4_EINT)
  361. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
  362. }
  363. /* charger, RTC */
  364. if (status1) {
  365. if (status1 & WM8350_CHG_BAT_HOT_EINT)
  366. wm8350_irq_call_handler(wm8350,
  367. WM8350_IRQ_CHG_BAT_HOT);
  368. if (status1 & WM8350_CHG_BAT_COLD_EINT)
  369. wm8350_irq_call_handler(wm8350,
  370. WM8350_IRQ_CHG_BAT_COLD);
  371. if (status1 & WM8350_CHG_BAT_FAIL_EINT)
  372. wm8350_irq_call_handler(wm8350,
  373. WM8350_IRQ_CHG_BAT_FAIL);
  374. if (status1 & WM8350_CHG_TO_EINT)
  375. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
  376. if (status1 & WM8350_CHG_END_EINT)
  377. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
  378. if (status1 & WM8350_CHG_START_EINT)
  379. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
  380. if (status1 & WM8350_CHG_FAST_RDY_EINT)
  381. wm8350_irq_call_handler(wm8350,
  382. WM8350_IRQ_CHG_FAST_RDY);
  383. if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
  384. wm8350_irq_call_handler(wm8350,
  385. WM8350_IRQ_CHG_VBATT_LT_3P9);
  386. if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
  387. wm8350_irq_call_handler(wm8350,
  388. WM8350_IRQ_CHG_VBATT_LT_3P1);
  389. if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
  390. wm8350_irq_call_handler(wm8350,
  391. WM8350_IRQ_CHG_VBATT_LT_2P85);
  392. if (status1 & WM8350_RTC_ALM_EINT)
  393. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
  394. if (status1 & WM8350_RTC_SEC_EINT)
  395. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
  396. if (status1 & WM8350_RTC_PER_EINT)
  397. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
  398. }
  399. /* current sink, system, aux adc */
  400. if (status2) {
  401. if (status2 & WM8350_CS1_EINT)
  402. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
  403. if (status2 & WM8350_CS2_EINT)
  404. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
  405. if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
  406. wm8350_irq_call_handler(wm8350,
  407. WM8350_IRQ_SYS_HYST_COMP_FAIL);
  408. if (status2 & WM8350_SYS_CHIP_GT115_EINT)
  409. wm8350_irq_call_handler(wm8350,
  410. WM8350_IRQ_SYS_CHIP_GT115);
  411. if (status2 & WM8350_SYS_CHIP_GT140_EINT)
  412. wm8350_irq_call_handler(wm8350,
  413. WM8350_IRQ_SYS_CHIP_GT140);
  414. if (status2 & WM8350_SYS_WDOG_TO_EINT)
  415. wm8350_irq_call_handler(wm8350,
  416. WM8350_IRQ_SYS_WDOG_TO);
  417. if (status2 & WM8350_AUXADC_DATARDY_EINT)
  418. wm8350_irq_call_handler(wm8350,
  419. WM8350_IRQ_AUXADC_DATARDY);
  420. if (status2 & WM8350_AUXADC_DCOMP4_EINT)
  421. wm8350_irq_call_handler(wm8350,
  422. WM8350_IRQ_AUXADC_DCOMP4);
  423. if (status2 & WM8350_AUXADC_DCOMP3_EINT)
  424. wm8350_irq_call_handler(wm8350,
  425. WM8350_IRQ_AUXADC_DCOMP3);
  426. if (status2 & WM8350_AUXADC_DCOMP2_EINT)
  427. wm8350_irq_call_handler(wm8350,
  428. WM8350_IRQ_AUXADC_DCOMP2);
  429. if (status2 & WM8350_AUXADC_DCOMP1_EINT)
  430. wm8350_irq_call_handler(wm8350,
  431. WM8350_IRQ_AUXADC_DCOMP1);
  432. if (status2 & WM8350_USB_LIMIT_EINT)
  433. wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
  434. }
  435. /* wake, codec, ext */
  436. if (comp) {
  437. if (comp & WM8350_WKUP_OFF_STATE_EINT)
  438. wm8350_irq_call_handler(wm8350,
  439. WM8350_IRQ_WKUP_OFF_STATE);
  440. if (comp & WM8350_WKUP_HIB_STATE_EINT)
  441. wm8350_irq_call_handler(wm8350,
  442. WM8350_IRQ_WKUP_HIB_STATE);
  443. if (comp & WM8350_WKUP_CONV_FAULT_EINT)
  444. wm8350_irq_call_handler(wm8350,
  445. WM8350_IRQ_WKUP_CONV_FAULT);
  446. if (comp & WM8350_WKUP_WDOG_RST_EINT)
  447. wm8350_irq_call_handler(wm8350,
  448. WM8350_IRQ_WKUP_WDOG_RST);
  449. if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
  450. wm8350_irq_call_handler(wm8350,
  451. WM8350_IRQ_WKUP_GP_PWR_ON);
  452. if (comp & WM8350_WKUP_ONKEY_EINT)
  453. wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
  454. if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
  455. wm8350_irq_call_handler(wm8350,
  456. WM8350_IRQ_WKUP_GP_WAKEUP);
  457. if (comp & WM8350_CODEC_JCK_DET_L_EINT)
  458. wm8350_irq_call_handler(wm8350,
  459. WM8350_IRQ_CODEC_JCK_DET_L);
  460. if (comp & WM8350_CODEC_JCK_DET_R_EINT)
  461. wm8350_irq_call_handler(wm8350,
  462. WM8350_IRQ_CODEC_JCK_DET_R);
  463. if (comp & WM8350_CODEC_MICSCD_EINT)
  464. wm8350_irq_call_handler(wm8350,
  465. WM8350_IRQ_CODEC_MICSCD);
  466. if (comp & WM8350_CODEC_MICD_EINT)
  467. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
  468. if (comp & WM8350_EXT_USB_FB_EINT)
  469. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
  470. if (comp & WM8350_EXT_WALL_FB_EINT)
  471. wm8350_irq_call_handler(wm8350,
  472. WM8350_IRQ_EXT_WALL_FB);
  473. if (comp & WM8350_EXT_BAT_FB_EINT)
  474. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
  475. }
  476. if (level_one & WM8350_GP_INT) {
  477. int i;
  478. u16 gpio;
  479. gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
  480. gpio &= ~wm8350_reg_read(wm8350,
  481. WM8350_GPIO_INT_STATUS_MASK);
  482. for (i = 0; i < 12; i++) {
  483. if (gpio & (1 << i))
  484. wm8350_irq_call_handler(wm8350,
  485. WM8350_IRQ_GPIO(i));
  486. }
  487. }
  488. enable_irq(wm8350->chip_irq);
  489. }
  490. static irqreturn_t wm8350_irq(int irq, void *data)
  491. {
  492. struct wm8350 *wm8350 = data;
  493. disable_irq_nosync(irq);
  494. schedule_work(&wm8350->irq_work);
  495. return IRQ_HANDLED;
  496. }
  497. int wm8350_register_irq(struct wm8350 *wm8350, int irq,
  498. void (*handler) (struct wm8350 *, int, void *),
  499. void *data)
  500. {
  501. if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
  502. return -EINVAL;
  503. if (wm8350->irq[irq].handler)
  504. return -EBUSY;
  505. mutex_lock(&wm8350->irq_mutex);
  506. wm8350->irq[irq].handler = handler;
  507. wm8350->irq[irq].data = data;
  508. mutex_unlock(&wm8350->irq_mutex);
  509. return 0;
  510. }
  511. EXPORT_SYMBOL_GPL(wm8350_register_irq);
  512. int wm8350_free_irq(struct wm8350 *wm8350, int irq)
  513. {
  514. if (irq < 0 || irq > WM8350_NUM_IRQ)
  515. return -EINVAL;
  516. mutex_lock(&wm8350->irq_mutex);
  517. wm8350->irq[irq].handler = NULL;
  518. mutex_unlock(&wm8350->irq_mutex);
  519. return 0;
  520. }
  521. EXPORT_SYMBOL_GPL(wm8350_free_irq);
  522. int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
  523. {
  524. switch (irq) {
  525. case WM8350_IRQ_CHG_BAT_HOT:
  526. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  527. WM8350_IM_CHG_BAT_HOT_EINT);
  528. case WM8350_IRQ_CHG_BAT_COLD:
  529. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  530. WM8350_IM_CHG_BAT_COLD_EINT);
  531. case WM8350_IRQ_CHG_BAT_FAIL:
  532. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  533. WM8350_IM_CHG_BAT_FAIL_EINT);
  534. case WM8350_IRQ_CHG_TO:
  535. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  536. WM8350_IM_CHG_TO_EINT);
  537. case WM8350_IRQ_CHG_END:
  538. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  539. WM8350_IM_CHG_END_EINT);
  540. case WM8350_IRQ_CHG_START:
  541. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  542. WM8350_IM_CHG_START_EINT);
  543. case WM8350_IRQ_CHG_FAST_RDY:
  544. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  545. WM8350_IM_CHG_FAST_RDY_EINT);
  546. case WM8350_IRQ_RTC_PER:
  547. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  548. WM8350_IM_RTC_PER_EINT);
  549. case WM8350_IRQ_RTC_SEC:
  550. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  551. WM8350_IM_RTC_SEC_EINT);
  552. case WM8350_IRQ_RTC_ALM:
  553. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  554. WM8350_IM_RTC_ALM_EINT);
  555. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  556. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  557. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  558. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  559. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  560. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  561. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  562. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  563. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  564. case WM8350_IRQ_CS1:
  565. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  566. WM8350_IM_CS1_EINT);
  567. case WM8350_IRQ_CS2:
  568. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  569. WM8350_IM_CS2_EINT);
  570. case WM8350_IRQ_USB_LIMIT:
  571. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  572. WM8350_IM_USB_LIMIT_EINT);
  573. case WM8350_IRQ_AUXADC_DATARDY:
  574. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  575. WM8350_IM_AUXADC_DATARDY_EINT);
  576. case WM8350_IRQ_AUXADC_DCOMP4:
  577. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  578. WM8350_IM_AUXADC_DCOMP4_EINT);
  579. case WM8350_IRQ_AUXADC_DCOMP3:
  580. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  581. WM8350_IM_AUXADC_DCOMP3_EINT);
  582. case WM8350_IRQ_AUXADC_DCOMP2:
  583. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  584. WM8350_IM_AUXADC_DCOMP2_EINT);
  585. case WM8350_IRQ_AUXADC_DCOMP1:
  586. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  587. WM8350_IM_AUXADC_DCOMP1_EINT);
  588. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  589. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  590. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  591. case WM8350_IRQ_SYS_CHIP_GT115:
  592. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  593. WM8350_IM_SYS_CHIP_GT115_EINT);
  594. case WM8350_IRQ_SYS_CHIP_GT140:
  595. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  596. WM8350_IM_SYS_CHIP_GT140_EINT);
  597. case WM8350_IRQ_SYS_WDOG_TO:
  598. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  599. WM8350_IM_SYS_WDOG_TO_EINT);
  600. case WM8350_IRQ_UV_LDO4:
  601. return wm8350_set_bits(wm8350,
  602. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  603. WM8350_IM_UV_LDO4_EINT);
  604. case WM8350_IRQ_UV_LDO3:
  605. return wm8350_set_bits(wm8350,
  606. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  607. WM8350_IM_UV_LDO3_EINT);
  608. case WM8350_IRQ_UV_LDO2:
  609. return wm8350_set_bits(wm8350,
  610. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  611. WM8350_IM_UV_LDO2_EINT);
  612. case WM8350_IRQ_UV_LDO1:
  613. return wm8350_set_bits(wm8350,
  614. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  615. WM8350_IM_UV_LDO1_EINT);
  616. case WM8350_IRQ_UV_DC6:
  617. return wm8350_set_bits(wm8350,
  618. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  619. WM8350_IM_UV_DC6_EINT);
  620. case WM8350_IRQ_UV_DC5:
  621. return wm8350_set_bits(wm8350,
  622. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  623. WM8350_IM_UV_DC5_EINT);
  624. case WM8350_IRQ_UV_DC4:
  625. return wm8350_set_bits(wm8350,
  626. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  627. WM8350_IM_UV_DC4_EINT);
  628. case WM8350_IRQ_UV_DC3:
  629. return wm8350_set_bits(wm8350,
  630. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  631. WM8350_IM_UV_DC3_EINT);
  632. case WM8350_IRQ_UV_DC2:
  633. return wm8350_set_bits(wm8350,
  634. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  635. WM8350_IM_UV_DC2_EINT);
  636. case WM8350_IRQ_UV_DC1:
  637. return wm8350_set_bits(wm8350,
  638. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  639. WM8350_IM_UV_DC1_EINT);
  640. case WM8350_IRQ_OC_LS:
  641. return wm8350_set_bits(wm8350,
  642. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  643. WM8350_IM_OC_LS_EINT);
  644. case WM8350_IRQ_EXT_USB_FB:
  645. return wm8350_set_bits(wm8350,
  646. WM8350_COMPARATOR_INT_STATUS_MASK,
  647. WM8350_IM_EXT_USB_FB_EINT);
  648. case WM8350_IRQ_EXT_WALL_FB:
  649. return wm8350_set_bits(wm8350,
  650. WM8350_COMPARATOR_INT_STATUS_MASK,
  651. WM8350_IM_EXT_WALL_FB_EINT);
  652. case WM8350_IRQ_EXT_BAT_FB:
  653. return wm8350_set_bits(wm8350,
  654. WM8350_COMPARATOR_INT_STATUS_MASK,
  655. WM8350_IM_EXT_BAT_FB_EINT);
  656. case WM8350_IRQ_CODEC_JCK_DET_L:
  657. return wm8350_set_bits(wm8350,
  658. WM8350_COMPARATOR_INT_STATUS_MASK,
  659. WM8350_IM_CODEC_JCK_DET_L_EINT);
  660. case WM8350_IRQ_CODEC_JCK_DET_R:
  661. return wm8350_set_bits(wm8350,
  662. WM8350_COMPARATOR_INT_STATUS_MASK,
  663. WM8350_IM_CODEC_JCK_DET_R_EINT);
  664. case WM8350_IRQ_CODEC_MICSCD:
  665. return wm8350_set_bits(wm8350,
  666. WM8350_COMPARATOR_INT_STATUS_MASK,
  667. WM8350_IM_CODEC_MICSCD_EINT);
  668. case WM8350_IRQ_CODEC_MICD:
  669. return wm8350_set_bits(wm8350,
  670. WM8350_COMPARATOR_INT_STATUS_MASK,
  671. WM8350_IM_CODEC_MICD_EINT);
  672. case WM8350_IRQ_WKUP_OFF_STATE:
  673. return wm8350_set_bits(wm8350,
  674. WM8350_COMPARATOR_INT_STATUS_MASK,
  675. WM8350_IM_WKUP_OFF_STATE_EINT);
  676. case WM8350_IRQ_WKUP_HIB_STATE:
  677. return wm8350_set_bits(wm8350,
  678. WM8350_COMPARATOR_INT_STATUS_MASK,
  679. WM8350_IM_WKUP_HIB_STATE_EINT);
  680. case WM8350_IRQ_WKUP_CONV_FAULT:
  681. return wm8350_set_bits(wm8350,
  682. WM8350_COMPARATOR_INT_STATUS_MASK,
  683. WM8350_IM_WKUP_CONV_FAULT_EINT);
  684. case WM8350_IRQ_WKUP_WDOG_RST:
  685. return wm8350_set_bits(wm8350,
  686. WM8350_COMPARATOR_INT_STATUS_MASK,
  687. WM8350_IM_WKUP_OFF_STATE_EINT);
  688. case WM8350_IRQ_WKUP_GP_PWR_ON:
  689. return wm8350_set_bits(wm8350,
  690. WM8350_COMPARATOR_INT_STATUS_MASK,
  691. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  692. case WM8350_IRQ_WKUP_ONKEY:
  693. return wm8350_set_bits(wm8350,
  694. WM8350_COMPARATOR_INT_STATUS_MASK,
  695. WM8350_IM_WKUP_ONKEY_EINT);
  696. case WM8350_IRQ_WKUP_GP_WAKEUP:
  697. return wm8350_set_bits(wm8350,
  698. WM8350_COMPARATOR_INT_STATUS_MASK,
  699. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  700. case WM8350_IRQ_GPIO(0):
  701. return wm8350_set_bits(wm8350,
  702. WM8350_GPIO_INT_STATUS_MASK,
  703. WM8350_IM_GP0_EINT);
  704. case WM8350_IRQ_GPIO(1):
  705. return wm8350_set_bits(wm8350,
  706. WM8350_GPIO_INT_STATUS_MASK,
  707. WM8350_IM_GP1_EINT);
  708. case WM8350_IRQ_GPIO(2):
  709. return wm8350_set_bits(wm8350,
  710. WM8350_GPIO_INT_STATUS_MASK,
  711. WM8350_IM_GP2_EINT);
  712. case WM8350_IRQ_GPIO(3):
  713. return wm8350_set_bits(wm8350,
  714. WM8350_GPIO_INT_STATUS_MASK,
  715. WM8350_IM_GP3_EINT);
  716. case WM8350_IRQ_GPIO(4):
  717. return wm8350_set_bits(wm8350,
  718. WM8350_GPIO_INT_STATUS_MASK,
  719. WM8350_IM_GP4_EINT);
  720. case WM8350_IRQ_GPIO(5):
  721. return wm8350_set_bits(wm8350,
  722. WM8350_GPIO_INT_STATUS_MASK,
  723. WM8350_IM_GP5_EINT);
  724. case WM8350_IRQ_GPIO(6):
  725. return wm8350_set_bits(wm8350,
  726. WM8350_GPIO_INT_STATUS_MASK,
  727. WM8350_IM_GP6_EINT);
  728. case WM8350_IRQ_GPIO(7):
  729. return wm8350_set_bits(wm8350,
  730. WM8350_GPIO_INT_STATUS_MASK,
  731. WM8350_IM_GP7_EINT);
  732. case WM8350_IRQ_GPIO(8):
  733. return wm8350_set_bits(wm8350,
  734. WM8350_GPIO_INT_STATUS_MASK,
  735. WM8350_IM_GP8_EINT);
  736. case WM8350_IRQ_GPIO(9):
  737. return wm8350_set_bits(wm8350,
  738. WM8350_GPIO_INT_STATUS_MASK,
  739. WM8350_IM_GP9_EINT);
  740. case WM8350_IRQ_GPIO(10):
  741. return wm8350_set_bits(wm8350,
  742. WM8350_GPIO_INT_STATUS_MASK,
  743. WM8350_IM_GP10_EINT);
  744. case WM8350_IRQ_GPIO(11):
  745. return wm8350_set_bits(wm8350,
  746. WM8350_GPIO_INT_STATUS_MASK,
  747. WM8350_IM_GP11_EINT);
  748. case WM8350_IRQ_GPIO(12):
  749. return wm8350_set_bits(wm8350,
  750. WM8350_GPIO_INT_STATUS_MASK,
  751. WM8350_IM_GP12_EINT);
  752. default:
  753. dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
  754. irq);
  755. return -EINVAL;
  756. }
  757. return 0;
  758. }
  759. EXPORT_SYMBOL_GPL(wm8350_mask_irq);
  760. int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
  761. {
  762. switch (irq) {
  763. case WM8350_IRQ_CHG_BAT_HOT:
  764. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  765. WM8350_IM_CHG_BAT_HOT_EINT);
  766. case WM8350_IRQ_CHG_BAT_COLD:
  767. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  768. WM8350_IM_CHG_BAT_COLD_EINT);
  769. case WM8350_IRQ_CHG_BAT_FAIL:
  770. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  771. WM8350_IM_CHG_BAT_FAIL_EINT);
  772. case WM8350_IRQ_CHG_TO:
  773. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  774. WM8350_IM_CHG_TO_EINT);
  775. case WM8350_IRQ_CHG_END:
  776. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  777. WM8350_IM_CHG_END_EINT);
  778. case WM8350_IRQ_CHG_START:
  779. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  780. WM8350_IM_CHG_START_EINT);
  781. case WM8350_IRQ_CHG_FAST_RDY:
  782. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  783. WM8350_IM_CHG_FAST_RDY_EINT);
  784. case WM8350_IRQ_RTC_PER:
  785. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  786. WM8350_IM_RTC_PER_EINT);
  787. case WM8350_IRQ_RTC_SEC:
  788. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  789. WM8350_IM_RTC_SEC_EINT);
  790. case WM8350_IRQ_RTC_ALM:
  791. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  792. WM8350_IM_RTC_ALM_EINT);
  793. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  794. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  795. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  796. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  797. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  798. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  799. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  800. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  801. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  802. case WM8350_IRQ_CS1:
  803. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  804. WM8350_IM_CS1_EINT);
  805. case WM8350_IRQ_CS2:
  806. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  807. WM8350_IM_CS2_EINT);
  808. case WM8350_IRQ_USB_LIMIT:
  809. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  810. WM8350_IM_USB_LIMIT_EINT);
  811. case WM8350_IRQ_AUXADC_DATARDY:
  812. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  813. WM8350_IM_AUXADC_DATARDY_EINT);
  814. case WM8350_IRQ_AUXADC_DCOMP4:
  815. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  816. WM8350_IM_AUXADC_DCOMP4_EINT);
  817. case WM8350_IRQ_AUXADC_DCOMP3:
  818. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  819. WM8350_IM_AUXADC_DCOMP3_EINT);
  820. case WM8350_IRQ_AUXADC_DCOMP2:
  821. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  822. WM8350_IM_AUXADC_DCOMP2_EINT);
  823. case WM8350_IRQ_AUXADC_DCOMP1:
  824. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  825. WM8350_IM_AUXADC_DCOMP1_EINT);
  826. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  827. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  828. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  829. case WM8350_IRQ_SYS_CHIP_GT115:
  830. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  831. WM8350_IM_SYS_CHIP_GT115_EINT);
  832. case WM8350_IRQ_SYS_CHIP_GT140:
  833. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  834. WM8350_IM_SYS_CHIP_GT140_EINT);
  835. case WM8350_IRQ_SYS_WDOG_TO:
  836. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  837. WM8350_IM_SYS_WDOG_TO_EINT);
  838. case WM8350_IRQ_UV_LDO4:
  839. return wm8350_clear_bits(wm8350,
  840. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  841. WM8350_IM_UV_LDO4_EINT);
  842. case WM8350_IRQ_UV_LDO3:
  843. return wm8350_clear_bits(wm8350,
  844. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  845. WM8350_IM_UV_LDO3_EINT);
  846. case WM8350_IRQ_UV_LDO2:
  847. return wm8350_clear_bits(wm8350,
  848. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  849. WM8350_IM_UV_LDO2_EINT);
  850. case WM8350_IRQ_UV_LDO1:
  851. return wm8350_clear_bits(wm8350,
  852. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  853. WM8350_IM_UV_LDO1_EINT);
  854. case WM8350_IRQ_UV_DC6:
  855. return wm8350_clear_bits(wm8350,
  856. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  857. WM8350_IM_UV_DC6_EINT);
  858. case WM8350_IRQ_UV_DC5:
  859. return wm8350_clear_bits(wm8350,
  860. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  861. WM8350_IM_UV_DC5_EINT);
  862. case WM8350_IRQ_UV_DC4:
  863. return wm8350_clear_bits(wm8350,
  864. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  865. WM8350_IM_UV_DC4_EINT);
  866. case WM8350_IRQ_UV_DC3:
  867. return wm8350_clear_bits(wm8350,
  868. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  869. WM8350_IM_UV_DC3_EINT);
  870. case WM8350_IRQ_UV_DC2:
  871. return wm8350_clear_bits(wm8350,
  872. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  873. WM8350_IM_UV_DC2_EINT);
  874. case WM8350_IRQ_UV_DC1:
  875. return wm8350_clear_bits(wm8350,
  876. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  877. WM8350_IM_UV_DC1_EINT);
  878. case WM8350_IRQ_OC_LS:
  879. return wm8350_clear_bits(wm8350,
  880. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  881. WM8350_IM_OC_LS_EINT);
  882. case WM8350_IRQ_EXT_USB_FB:
  883. return wm8350_clear_bits(wm8350,
  884. WM8350_COMPARATOR_INT_STATUS_MASK,
  885. WM8350_IM_EXT_USB_FB_EINT);
  886. case WM8350_IRQ_EXT_WALL_FB:
  887. return wm8350_clear_bits(wm8350,
  888. WM8350_COMPARATOR_INT_STATUS_MASK,
  889. WM8350_IM_EXT_WALL_FB_EINT);
  890. case WM8350_IRQ_EXT_BAT_FB:
  891. return wm8350_clear_bits(wm8350,
  892. WM8350_COMPARATOR_INT_STATUS_MASK,
  893. WM8350_IM_EXT_BAT_FB_EINT);
  894. case WM8350_IRQ_CODEC_JCK_DET_L:
  895. return wm8350_clear_bits(wm8350,
  896. WM8350_COMPARATOR_INT_STATUS_MASK,
  897. WM8350_IM_CODEC_JCK_DET_L_EINT);
  898. case WM8350_IRQ_CODEC_JCK_DET_R:
  899. return wm8350_clear_bits(wm8350,
  900. WM8350_COMPARATOR_INT_STATUS_MASK,
  901. WM8350_IM_CODEC_JCK_DET_R_EINT);
  902. case WM8350_IRQ_CODEC_MICSCD:
  903. return wm8350_clear_bits(wm8350,
  904. WM8350_COMPARATOR_INT_STATUS_MASK,
  905. WM8350_IM_CODEC_MICSCD_EINT);
  906. case WM8350_IRQ_CODEC_MICD:
  907. return wm8350_clear_bits(wm8350,
  908. WM8350_COMPARATOR_INT_STATUS_MASK,
  909. WM8350_IM_CODEC_MICD_EINT);
  910. case WM8350_IRQ_WKUP_OFF_STATE:
  911. return wm8350_clear_bits(wm8350,
  912. WM8350_COMPARATOR_INT_STATUS_MASK,
  913. WM8350_IM_WKUP_OFF_STATE_EINT);
  914. case WM8350_IRQ_WKUP_HIB_STATE:
  915. return wm8350_clear_bits(wm8350,
  916. WM8350_COMPARATOR_INT_STATUS_MASK,
  917. WM8350_IM_WKUP_HIB_STATE_EINT);
  918. case WM8350_IRQ_WKUP_CONV_FAULT:
  919. return wm8350_clear_bits(wm8350,
  920. WM8350_COMPARATOR_INT_STATUS_MASK,
  921. WM8350_IM_WKUP_CONV_FAULT_EINT);
  922. case WM8350_IRQ_WKUP_WDOG_RST:
  923. return wm8350_clear_bits(wm8350,
  924. WM8350_COMPARATOR_INT_STATUS_MASK,
  925. WM8350_IM_WKUP_OFF_STATE_EINT);
  926. case WM8350_IRQ_WKUP_GP_PWR_ON:
  927. return wm8350_clear_bits(wm8350,
  928. WM8350_COMPARATOR_INT_STATUS_MASK,
  929. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  930. case WM8350_IRQ_WKUP_ONKEY:
  931. return wm8350_clear_bits(wm8350,
  932. WM8350_COMPARATOR_INT_STATUS_MASK,
  933. WM8350_IM_WKUP_ONKEY_EINT);
  934. case WM8350_IRQ_WKUP_GP_WAKEUP:
  935. return wm8350_clear_bits(wm8350,
  936. WM8350_COMPARATOR_INT_STATUS_MASK,
  937. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  938. case WM8350_IRQ_GPIO(0):
  939. return wm8350_clear_bits(wm8350,
  940. WM8350_GPIO_INT_STATUS_MASK,
  941. WM8350_IM_GP0_EINT);
  942. case WM8350_IRQ_GPIO(1):
  943. return wm8350_clear_bits(wm8350,
  944. WM8350_GPIO_INT_STATUS_MASK,
  945. WM8350_IM_GP1_EINT);
  946. case WM8350_IRQ_GPIO(2):
  947. return wm8350_clear_bits(wm8350,
  948. WM8350_GPIO_INT_STATUS_MASK,
  949. WM8350_IM_GP2_EINT);
  950. case WM8350_IRQ_GPIO(3):
  951. return wm8350_clear_bits(wm8350,
  952. WM8350_GPIO_INT_STATUS_MASK,
  953. WM8350_IM_GP3_EINT);
  954. case WM8350_IRQ_GPIO(4):
  955. return wm8350_clear_bits(wm8350,
  956. WM8350_GPIO_INT_STATUS_MASK,
  957. WM8350_IM_GP4_EINT);
  958. case WM8350_IRQ_GPIO(5):
  959. return wm8350_clear_bits(wm8350,
  960. WM8350_GPIO_INT_STATUS_MASK,
  961. WM8350_IM_GP5_EINT);
  962. case WM8350_IRQ_GPIO(6):
  963. return wm8350_clear_bits(wm8350,
  964. WM8350_GPIO_INT_STATUS_MASK,
  965. WM8350_IM_GP6_EINT);
  966. case WM8350_IRQ_GPIO(7):
  967. return wm8350_clear_bits(wm8350,
  968. WM8350_GPIO_INT_STATUS_MASK,
  969. WM8350_IM_GP7_EINT);
  970. case WM8350_IRQ_GPIO(8):
  971. return wm8350_clear_bits(wm8350,
  972. WM8350_GPIO_INT_STATUS_MASK,
  973. WM8350_IM_GP8_EINT);
  974. case WM8350_IRQ_GPIO(9):
  975. return wm8350_clear_bits(wm8350,
  976. WM8350_GPIO_INT_STATUS_MASK,
  977. WM8350_IM_GP9_EINT);
  978. case WM8350_IRQ_GPIO(10):
  979. return wm8350_clear_bits(wm8350,
  980. WM8350_GPIO_INT_STATUS_MASK,
  981. WM8350_IM_GP10_EINT);
  982. case WM8350_IRQ_GPIO(11):
  983. return wm8350_clear_bits(wm8350,
  984. WM8350_GPIO_INT_STATUS_MASK,
  985. WM8350_IM_GP11_EINT);
  986. case WM8350_IRQ_GPIO(12):
  987. return wm8350_clear_bits(wm8350,
  988. WM8350_GPIO_INT_STATUS_MASK,
  989. WM8350_IM_GP12_EINT);
  990. default:
  991. dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
  992. irq);
  993. return -EINVAL;
  994. }
  995. return 0;
  996. }
  997. EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
  998. /*
  999. * Cache is always host endian.
  1000. */
  1001. static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
  1002. {
  1003. int i, ret = 0;
  1004. u16 value;
  1005. const u16 *reg_map;
  1006. switch (mode) {
  1007. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
  1008. case 0:
  1009. reg_map = wm8350_mode0_defaults;
  1010. break;
  1011. #endif
  1012. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
  1013. case 1:
  1014. reg_map = wm8350_mode1_defaults;
  1015. break;
  1016. #endif
  1017. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
  1018. case 2:
  1019. reg_map = wm8350_mode2_defaults;
  1020. break;
  1021. #endif
  1022. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
  1023. case 3:
  1024. reg_map = wm8350_mode3_defaults;
  1025. break;
  1026. #endif
  1027. default:
  1028. dev_err(wm8350->dev, "Configuration mode %d not supported\n",
  1029. mode);
  1030. return -EINVAL;
  1031. }
  1032. wm8350->reg_cache =
  1033. kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
  1034. if (wm8350->reg_cache == NULL)
  1035. return -ENOMEM;
  1036. /* Read the initial cache state back from the device - this is
  1037. * a PMIC so the device many not be in a virgin state and we
  1038. * can't rely on the silicon values.
  1039. */
  1040. for (i = 0; i < WM8350_MAX_REGISTER; i++) {
  1041. /* audio register range */
  1042. if (wm8350_reg_io_map[i].readable &&
  1043. (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
  1044. ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
  1045. if (ret < 0) {
  1046. dev_err(wm8350->dev,
  1047. "failed to read initial cache value\n");
  1048. goto out;
  1049. }
  1050. value = be16_to_cpu(value);
  1051. value &= wm8350_reg_io_map[i].readable;
  1052. value &= ~wm8350_reg_io_map[i].vol;
  1053. wm8350->reg_cache[i] = value;
  1054. } else
  1055. wm8350->reg_cache[i] = reg_map[i];
  1056. }
  1057. out:
  1058. return ret;
  1059. }
  1060. /*
  1061. * Register a client device. This is non-fatal since there is no need to
  1062. * fail the entire device init due to a single platform device failing.
  1063. */
  1064. static void wm8350_client_dev_register(struct wm8350 *wm8350,
  1065. const char *name,
  1066. struct platform_device **pdev)
  1067. {
  1068. int ret;
  1069. *pdev = platform_device_alloc(name, -1);
  1070. if (pdev == NULL) {
  1071. dev_err(wm8350->dev, "Failed to allocate %s\n", name);
  1072. return;
  1073. }
  1074. (*pdev)->dev.parent = wm8350->dev;
  1075. platform_set_drvdata(*pdev, wm8350);
  1076. ret = platform_device_add(*pdev);
  1077. if (ret != 0) {
  1078. dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
  1079. platform_device_put(*pdev);
  1080. *pdev = NULL;
  1081. }
  1082. }
  1083. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  1084. struct wm8350_platform_data *pdata)
  1085. {
  1086. int ret = -EINVAL;
  1087. u16 id1, id2, mask, mode;
  1088. /* get WM8350 revision and config mode */
  1089. wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
  1090. wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
  1091. id1 = be16_to_cpu(id1);
  1092. id2 = be16_to_cpu(id2);
  1093. if (id1 == 0x6143) {
  1094. switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
  1095. case WM8350_REV_E:
  1096. dev_info(wm8350->dev, "Found Rev E device\n");
  1097. wm8350->rev = WM8350_REV_E;
  1098. break;
  1099. case WM8350_REV_F:
  1100. dev_info(wm8350->dev, "Found Rev F device\n");
  1101. wm8350->rev = WM8350_REV_F;
  1102. break;
  1103. case WM8350_REV_G:
  1104. dev_info(wm8350->dev, "Found Rev G device\n");
  1105. wm8350->rev = WM8350_REV_G;
  1106. break;
  1107. case WM8350_REV_H:
  1108. dev_info(wm8350->dev, "Found Rev H device\n");
  1109. wm8350->rev = WM8350_REV_H;
  1110. break;
  1111. default:
  1112. /* For safety we refuse to run on unknown hardware */
  1113. dev_info(wm8350->dev, "Found unknown rev %x\n",
  1114. (id2 & WM8350_CHIP_REV_MASK) >> 12);
  1115. ret = -ENODEV;
  1116. goto err;
  1117. }
  1118. } else {
  1119. dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
  1120. id1);
  1121. ret = -ENODEV;
  1122. goto err;
  1123. }
  1124. mode = id2 & WM8350_CONF_STS_MASK >> 10;
  1125. mask = id2 & WM8350_CUST_ID_MASK;
  1126. dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
  1127. ret = wm8350_create_cache(wm8350, mode);
  1128. if (ret < 0) {
  1129. printk(KERN_ERR "wm8350: failed to create register cache\n");
  1130. return ret;
  1131. }
  1132. if (pdata->init) {
  1133. ret = pdata->init(wm8350);
  1134. if (ret != 0) {
  1135. dev_err(wm8350->dev, "Platform init() failed: %d\n",
  1136. ret);
  1137. goto err;
  1138. }
  1139. }
  1140. mutex_init(&wm8350->irq_mutex);
  1141. INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
  1142. if (irq) {
  1143. ret = request_irq(irq, wm8350_irq, 0,
  1144. "wm8350", wm8350);
  1145. if (ret != 0) {
  1146. dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
  1147. ret);
  1148. goto err;
  1149. }
  1150. } else {
  1151. dev_err(wm8350->dev, "No IRQ configured\n");
  1152. goto err;
  1153. }
  1154. wm8350->chip_irq = irq;
  1155. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
  1156. wm8350_client_dev_register(wm8350, "wm8350-codec",
  1157. &(wm8350->codec.pdev));
  1158. wm8350_client_dev_register(wm8350, "wm8350-gpio",
  1159. &(wm8350->gpio.pdev));
  1160. wm8350_client_dev_register(wm8350, "wm8350-power",
  1161. &(wm8350->power.pdev));
  1162. wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
  1163. wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
  1164. return 0;
  1165. err:
  1166. kfree(wm8350->reg_cache);
  1167. return ret;
  1168. }
  1169. EXPORT_SYMBOL_GPL(wm8350_device_init);
  1170. void wm8350_device_exit(struct wm8350 *wm8350)
  1171. {
  1172. int i;
  1173. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
  1174. platform_device_unregister(wm8350->pmic.pdev[i]);
  1175. platform_device_unregister(wm8350->wdt.pdev);
  1176. platform_device_unregister(wm8350->rtc.pdev);
  1177. platform_device_unregister(wm8350->power.pdev);
  1178. platform_device_unregister(wm8350->gpio.pdev);
  1179. platform_device_unregister(wm8350->codec.pdev);
  1180. free_irq(wm8350->chip_irq, wm8350);
  1181. flush_work(&wm8350->irq_work);
  1182. kfree(wm8350->reg_cache);
  1183. }
  1184. EXPORT_SYMBOL_GPL(wm8350_device_exit);
  1185. MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
  1186. MODULE_LICENSE("GPL");