ad1848_lib.c 37 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of AD1848/AD1847/CS4248
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #define SNDRV_MAIN_OBJECT_FILE
  22. #include <linux/delay.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/slab.h>
  26. #include <linux/ioport.h>
  27. #include <sound/core.h>
  28. #include <sound/ad1848.h>
  29. #include <sound/control.h>
  30. #include <sound/tlv.h>
  31. #include <sound/pcm_params.h>
  32. #include <asm/io.h>
  33. #include <asm/dma.h>
  34. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  35. MODULE_DESCRIPTION("Routines for control of AD1848/AD1847/CS4248");
  36. MODULE_LICENSE("GPL");
  37. #if 0
  38. #define SNDRV_DEBUG_MCE
  39. #endif
  40. /*
  41. * Some variables
  42. */
  43. static unsigned char freq_bits[14] = {
  44. /* 5510 */ 0x00 | AD1848_XTAL2,
  45. /* 6620 */ 0x0E | AD1848_XTAL2,
  46. /* 8000 */ 0x00 | AD1848_XTAL1,
  47. /* 9600 */ 0x0E | AD1848_XTAL1,
  48. /* 11025 */ 0x02 | AD1848_XTAL2,
  49. /* 16000 */ 0x02 | AD1848_XTAL1,
  50. /* 18900 */ 0x04 | AD1848_XTAL2,
  51. /* 22050 */ 0x06 | AD1848_XTAL2,
  52. /* 27042 */ 0x04 | AD1848_XTAL1,
  53. /* 32000 */ 0x06 | AD1848_XTAL1,
  54. /* 33075 */ 0x0C | AD1848_XTAL2,
  55. /* 37800 */ 0x08 | AD1848_XTAL2,
  56. /* 44100 */ 0x0A | AD1848_XTAL2,
  57. /* 48000 */ 0x0C | AD1848_XTAL1
  58. };
  59. static unsigned int rates[14] = {
  60. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  61. 27042, 32000, 33075, 37800, 44100, 48000
  62. };
  63. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  64. .count = ARRAY_SIZE(rates),
  65. .list = rates,
  66. .mask = 0,
  67. };
  68. static unsigned char snd_ad1848_original_image[16] =
  69. {
  70. 0x00, /* 00 - lic */
  71. 0x00, /* 01 - ric */
  72. 0x9f, /* 02 - la1ic */
  73. 0x9f, /* 03 - ra1ic */
  74. 0x9f, /* 04 - la2ic */
  75. 0x9f, /* 05 - ra2ic */
  76. 0xbf, /* 06 - loc */
  77. 0xbf, /* 07 - roc */
  78. 0x20, /* 08 - dfr */
  79. AD1848_AUTOCALIB, /* 09 - ic */
  80. 0x00, /* 0a - pc */
  81. 0x00, /* 0b - ti */
  82. 0x00, /* 0c - mi */
  83. 0x00, /* 0d - lbc */
  84. 0x00, /* 0e - dru */
  85. 0x00, /* 0f - drl */
  86. };
  87. /*
  88. * Basic I/O functions
  89. */
  90. static void snd_ad1848_wait(struct snd_wss *chip)
  91. {
  92. int timeout;
  93. for (timeout = 250; timeout > 0; timeout--) {
  94. if ((inb(AD1848P(chip, REGSEL)) & AD1848_INIT) == 0)
  95. break;
  96. udelay(100);
  97. }
  98. }
  99. void snd_ad1848_out(struct snd_wss *chip,
  100. unsigned char reg,
  101. unsigned char value)
  102. {
  103. snd_ad1848_wait(chip);
  104. #ifdef CONFIG_SND_DEBUG
  105. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  106. snd_printk(KERN_WARNING "auto calibration time out - "
  107. "reg = 0x%x, value = 0x%x\n", reg, value);
  108. #endif
  109. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  110. outb(chip->image[reg] = value, AD1848P(chip, REG));
  111. mb();
  112. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  113. chip->mce_bit | reg, value);
  114. }
  115. EXPORT_SYMBOL(snd_ad1848_out);
  116. static void snd_ad1848_dout(struct snd_wss *chip,
  117. unsigned char reg, unsigned char value)
  118. {
  119. snd_ad1848_wait(chip);
  120. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  121. outb(value, AD1848P(chip, REG));
  122. mb();
  123. }
  124. static unsigned char snd_ad1848_in(struct snd_wss *chip, unsigned char reg)
  125. {
  126. snd_ad1848_wait(chip);
  127. #ifdef CONFIG_SND_DEBUG
  128. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  129. snd_printk(KERN_WARNING "auto calibration time out - "
  130. "reg = 0x%x\n", reg);
  131. #endif
  132. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  133. mb();
  134. return inb(AD1848P(chip, REG));
  135. }
  136. #if 0
  137. static void snd_ad1848_debug(struct snd_wss *chip)
  138. {
  139. printk("AD1848 REGS: INDEX = 0x%02x ", inb(AD1848P(chip, REGSEL)));
  140. printk(" STATUS = 0x%02x\n", inb(AD1848P(chip, STATUS)));
  141. printk(" 0x00: left input = 0x%02x ", snd_ad1848_in(chip, 0x00));
  142. printk(" 0x08: playback format = 0x%02x\n", snd_ad1848_in(chip, 0x08));
  143. printk(" 0x01: right input = 0x%02x ", snd_ad1848_in(chip, 0x01));
  144. printk(" 0x09: iface (CFIG 1) = 0x%02x\n", snd_ad1848_in(chip, 0x09));
  145. printk(" 0x02: AUXA left = 0x%02x ", snd_ad1848_in(chip, 0x02));
  146. printk(" 0x0a: pin control = 0x%02x\n", snd_ad1848_in(chip, 0x0a));
  147. printk(" 0x03: AUXA right = 0x%02x ", snd_ad1848_in(chip, 0x03));
  148. printk(" 0x0b: init & status = 0x%02x\n", snd_ad1848_in(chip, 0x0b));
  149. printk(" 0x04: AUXB left = 0x%02x ", snd_ad1848_in(chip, 0x04));
  150. printk(" 0x0c: revision & mode = 0x%02x\n", snd_ad1848_in(chip, 0x0c));
  151. printk(" 0x05: AUXB right = 0x%02x ", snd_ad1848_in(chip, 0x05));
  152. printk(" 0x0d: loopback = 0x%02x\n", snd_ad1848_in(chip, 0x0d));
  153. printk(" 0x06: left output = 0x%02x ", snd_ad1848_in(chip, 0x06));
  154. printk(" 0x0e: data upr count = 0x%02x\n", snd_ad1848_in(chip, 0x0e));
  155. printk(" 0x07: right output = 0x%02x ", snd_ad1848_in(chip, 0x07));
  156. printk(" 0x0f: data lwr count = 0x%02x\n", snd_ad1848_in(chip, 0x0f));
  157. }
  158. #endif
  159. /*
  160. * AD1848 detection / MCE routines
  161. */
  162. static void snd_ad1848_mce_up(struct snd_wss *chip)
  163. {
  164. unsigned long flags;
  165. int timeout;
  166. snd_ad1848_wait(chip);
  167. #ifdef CONFIG_SND_DEBUG
  168. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  169. snd_printk(KERN_WARNING "mce_up - auto calibration time out (0)\n");
  170. #endif
  171. spin_lock_irqsave(&chip->reg_lock, flags);
  172. chip->mce_bit |= AD1848_MCE;
  173. timeout = inb(AD1848P(chip, REGSEL));
  174. if (timeout == 0x80)
  175. snd_printk(KERN_WARNING "mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  176. if (!(timeout & AD1848_MCE))
  177. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  178. spin_unlock_irqrestore(&chip->reg_lock, flags);
  179. }
  180. static void snd_ad1848_mce_down(struct snd_wss *chip)
  181. {
  182. unsigned long flags, timeout;
  183. int reg;
  184. spin_lock_irqsave(&chip->reg_lock, flags);
  185. for (timeout = 5; timeout > 0; timeout--)
  186. inb(AD1848P(chip, REGSEL));
  187. /* end of cleanup sequence */
  188. for (timeout = 12000; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  189. udelay(100);
  190. snd_printdd("(1) timeout = %ld\n", timeout);
  191. #ifdef CONFIG_SND_DEBUG
  192. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  193. snd_printk(KERN_WARNING "mce_down [0x%lx] - auto calibration time out (0)\n", AD1848P(chip, REGSEL));
  194. #endif
  195. chip->mce_bit &= ~AD1848_MCE;
  196. reg = inb(AD1848P(chip, REGSEL));
  197. outb(chip->mce_bit | (reg & 0x1f), AD1848P(chip, REGSEL));
  198. if (reg == 0x80)
  199. snd_printk(KERN_WARNING "mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  200. if ((reg & AD1848_MCE) == 0) {
  201. spin_unlock_irqrestore(&chip->reg_lock, flags);
  202. return;
  203. }
  204. /*
  205. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  206. * It may take up to 5 sample periods (at most 907 us @ 5.5125 kHz) for
  207. * the process to _start_, so it is important to wait at least that long
  208. * before checking. Otherwise we might think AC has finished when it
  209. * has in fact not begun. It could take 128 (no AC) or 384 (AC) cycles
  210. * for ACI to drop. This gives a wait of at most 70 ms with a more
  211. * typical value of 3-9 ms.
  212. */
  213. timeout = jiffies + msecs_to_jiffies(250);
  214. do {
  215. spin_unlock_irqrestore(&chip->reg_lock, flags);
  216. msleep(1);
  217. spin_lock_irqsave(&chip->reg_lock, flags);
  218. reg = snd_ad1848_in(chip, AD1848_TEST_INIT) &
  219. AD1848_CALIB_IN_PROGRESS;
  220. } while (reg && time_before(jiffies, timeout));
  221. spin_unlock_irqrestore(&chip->reg_lock, flags);
  222. if (reg)
  223. snd_printk(KERN_ERR
  224. "mce_down - auto calibration time out (2)\n");
  225. snd_printdd("(4) jiffies = %lu\n", jiffies);
  226. snd_printd("mce_down - exit = 0x%x\n", inb(AD1848P(chip, REGSEL)));
  227. }
  228. static unsigned int snd_ad1848_get_count(unsigned char format,
  229. unsigned int size)
  230. {
  231. switch (format & 0xe0) {
  232. case AD1848_LINEAR_16:
  233. size >>= 1;
  234. break;
  235. }
  236. if (format & AD1848_STEREO)
  237. size >>= 1;
  238. return size;
  239. }
  240. static int snd_ad1848_trigger(struct snd_wss *chip, unsigned char what,
  241. int channel, int cmd)
  242. {
  243. int result = 0;
  244. #if 0
  245. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, inb(AD1848P(card, STATUS)));
  246. #endif
  247. spin_lock(&chip->reg_lock);
  248. if (cmd == SNDRV_PCM_TRIGGER_START) {
  249. if (chip->image[AD1848_IFACE_CTRL] & what) {
  250. spin_unlock(&chip->reg_lock);
  251. return 0;
  252. }
  253. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] |= what);
  254. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  255. if (!(chip->image[AD1848_IFACE_CTRL] & what)) {
  256. spin_unlock(&chip->reg_lock);
  257. return 0;
  258. }
  259. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] &= ~what);
  260. } else {
  261. result = -EINVAL;
  262. }
  263. spin_unlock(&chip->reg_lock);
  264. return result;
  265. }
  266. /*
  267. * CODEC I/O
  268. */
  269. static unsigned char snd_ad1848_get_rate(unsigned int rate)
  270. {
  271. int i;
  272. for (i = 0; i < ARRAY_SIZE(rates); i++)
  273. if (rate == rates[i])
  274. return freq_bits[i];
  275. snd_BUG();
  276. return freq_bits[ARRAY_SIZE(rates) - 1];
  277. }
  278. static int snd_ad1848_ioctl(struct snd_pcm_substream *substream,
  279. unsigned int cmd, void *arg)
  280. {
  281. return snd_pcm_lib_ioctl(substream, cmd, arg);
  282. }
  283. static unsigned char snd_ad1848_get_format(int format, int channels)
  284. {
  285. unsigned char rformat;
  286. rformat = AD1848_LINEAR_8;
  287. switch (format) {
  288. case SNDRV_PCM_FORMAT_A_LAW: rformat = AD1848_ALAW_8; break;
  289. case SNDRV_PCM_FORMAT_MU_LAW: rformat = AD1848_ULAW_8; break;
  290. case SNDRV_PCM_FORMAT_S16_LE: rformat = AD1848_LINEAR_16; break;
  291. }
  292. if (channels > 1)
  293. rformat |= AD1848_STEREO;
  294. #if 0
  295. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  296. #endif
  297. return rformat;
  298. }
  299. static void snd_ad1848_calibrate_mute(struct snd_wss *chip, int mute)
  300. {
  301. unsigned long flags;
  302. mute = mute ? 1 : 0;
  303. spin_lock_irqsave(&chip->reg_lock, flags);
  304. if (chip->calibrate_mute == mute) {
  305. spin_unlock_irqrestore(&chip->reg_lock, flags);
  306. return;
  307. }
  308. if (!mute) {
  309. snd_ad1848_dout(chip, AD1848_LEFT_INPUT, chip->image[AD1848_LEFT_INPUT]);
  310. snd_ad1848_dout(chip, AD1848_RIGHT_INPUT, chip->image[AD1848_RIGHT_INPUT]);
  311. }
  312. snd_ad1848_dout(chip, AD1848_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_LEFT_INPUT]);
  313. snd_ad1848_dout(chip, AD1848_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_RIGHT_INPUT]);
  314. snd_ad1848_dout(chip, AD1848_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_LEFT_INPUT]);
  315. snd_ad1848_dout(chip, AD1848_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_RIGHT_INPUT]);
  316. snd_ad1848_dout(chip, AD1848_LEFT_OUTPUT, mute ? 0x80 : chip->image[AD1848_LEFT_OUTPUT]);
  317. snd_ad1848_dout(chip, AD1848_RIGHT_OUTPUT, mute ? 0x80 : chip->image[AD1848_RIGHT_OUTPUT]);
  318. chip->calibrate_mute = mute;
  319. spin_unlock_irqrestore(&chip->reg_lock, flags);
  320. }
  321. static void snd_ad1848_set_data_format(struct snd_wss *chip,
  322. struct snd_pcm_hw_params *hw_params)
  323. {
  324. if (hw_params == NULL) {
  325. chip->image[AD1848_DATA_FORMAT] = 0x20;
  326. } else {
  327. chip->image[AD1848_DATA_FORMAT] =
  328. snd_ad1848_get_format(params_format(hw_params), params_channels(hw_params)) |
  329. snd_ad1848_get_rate(params_rate(hw_params));
  330. }
  331. // snd_printk(">>> pmode = 0x%x, dfr = 0x%x\n", pstr->mode, chip->image[AD1848_DATA_FORMAT]);
  332. }
  333. static int snd_ad1848_open(struct snd_wss *chip, unsigned int mode)
  334. {
  335. unsigned long flags;
  336. if (chip->mode & WSS_MODE_OPEN)
  337. return -EAGAIN;
  338. snd_ad1848_mce_down(chip);
  339. #ifdef SNDRV_DEBUG_MCE
  340. snd_printk("open: (1)\n");
  341. #endif
  342. snd_ad1848_mce_up(chip);
  343. spin_lock_irqsave(&chip->reg_lock, flags);
  344. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  345. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO |
  346. AD1848_CALIB_MODE);
  347. chip->image[AD1848_IFACE_CTRL] |= AD1848_AUTOCALIB;
  348. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  349. spin_unlock_irqrestore(&chip->reg_lock, flags);
  350. snd_ad1848_mce_down(chip);
  351. #ifdef SNDRV_DEBUG_MCE
  352. snd_printk("open: (2)\n");
  353. #endif
  354. snd_ad1848_set_data_format(chip, NULL);
  355. snd_ad1848_mce_up(chip);
  356. spin_lock_irqsave(&chip->reg_lock, flags);
  357. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  358. spin_unlock_irqrestore(&chip->reg_lock, flags);
  359. snd_ad1848_mce_down(chip);
  360. #ifdef SNDRV_DEBUG_MCE
  361. snd_printk("open: (3)\n");
  362. #endif
  363. /* ok. now enable and ack CODEC IRQ */
  364. spin_lock_irqsave(&chip->reg_lock, flags);
  365. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  366. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  367. chip->image[AD1848_PIN_CTRL] |= AD1848_IRQ_ENABLE;
  368. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  369. spin_unlock_irqrestore(&chip->reg_lock, flags);
  370. chip->mode = mode;
  371. return 0;
  372. }
  373. static void snd_ad1848_close(struct snd_wss *chip)
  374. {
  375. unsigned long flags;
  376. if (!chip->mode)
  377. return;
  378. /* disable IRQ */
  379. spin_lock_irqsave(&chip->reg_lock, flags);
  380. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  381. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  382. chip->image[AD1848_PIN_CTRL] &= ~AD1848_IRQ_ENABLE;
  383. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  384. spin_unlock_irqrestore(&chip->reg_lock, flags);
  385. /* now disable capture & playback */
  386. snd_ad1848_mce_up(chip);
  387. spin_lock_irqsave(&chip->reg_lock, flags);
  388. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  389. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  390. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  391. spin_unlock_irqrestore(&chip->reg_lock, flags);
  392. snd_ad1848_mce_down(chip);
  393. /* clear IRQ again */
  394. spin_lock_irqsave(&chip->reg_lock, flags);
  395. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  396. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  397. spin_unlock_irqrestore(&chip->reg_lock, flags);
  398. chip->mode = 0;
  399. }
  400. /*
  401. * ok.. exported functions..
  402. */
  403. static int snd_ad1848_playback_trigger(struct snd_pcm_substream *substream,
  404. int cmd)
  405. {
  406. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  407. return snd_ad1848_trigger(chip, AD1848_PLAYBACK_ENABLE, SNDRV_PCM_STREAM_PLAYBACK, cmd);
  408. }
  409. static int snd_ad1848_capture_trigger(struct snd_pcm_substream *substream,
  410. int cmd)
  411. {
  412. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  413. return snd_ad1848_trigger(chip, AD1848_CAPTURE_ENABLE, SNDRV_PCM_STREAM_CAPTURE, cmd);
  414. }
  415. static int snd_ad1848_playback_hw_params(struct snd_pcm_substream *substream,
  416. struct snd_pcm_hw_params *hw_params)
  417. {
  418. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  419. unsigned long flags;
  420. int err;
  421. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  422. return err;
  423. snd_ad1848_calibrate_mute(chip, 1);
  424. snd_ad1848_set_data_format(chip, hw_params);
  425. snd_ad1848_mce_up(chip);
  426. spin_lock_irqsave(&chip->reg_lock, flags);
  427. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  428. spin_unlock_irqrestore(&chip->reg_lock, flags);
  429. snd_ad1848_mce_down(chip);
  430. snd_ad1848_calibrate_mute(chip, 0);
  431. return 0;
  432. }
  433. static int snd_ad1848_playback_hw_free(struct snd_pcm_substream *substream)
  434. {
  435. return snd_pcm_lib_free_pages(substream);
  436. }
  437. static int snd_ad1848_playback_prepare(struct snd_pcm_substream *substream)
  438. {
  439. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  440. struct snd_pcm_runtime *runtime = substream->runtime;
  441. unsigned long flags;
  442. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  443. unsigned int count = snd_pcm_lib_period_bytes(substream);
  444. chip->p_dma_size = size;
  445. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO);
  446. snd_dma_program(chip->dma1, runtime->dma_addr, size,
  447. DMA_MODE_WRITE | DMA_AUTOINIT);
  448. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  449. spin_lock_irqsave(&chip->reg_lock, flags);
  450. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  451. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  452. spin_unlock_irqrestore(&chip->reg_lock, flags);
  453. return 0;
  454. }
  455. static int snd_ad1848_capture_hw_params(struct snd_pcm_substream *substream,
  456. struct snd_pcm_hw_params *hw_params)
  457. {
  458. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  459. unsigned long flags;
  460. int err;
  461. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  462. return err;
  463. snd_ad1848_calibrate_mute(chip, 1);
  464. snd_ad1848_set_data_format(chip, hw_params);
  465. snd_ad1848_mce_up(chip);
  466. spin_lock_irqsave(&chip->reg_lock, flags);
  467. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  468. spin_unlock_irqrestore(&chip->reg_lock, flags);
  469. snd_ad1848_mce_down(chip);
  470. snd_ad1848_calibrate_mute(chip, 0);
  471. return 0;
  472. }
  473. static int snd_ad1848_capture_hw_free(struct snd_pcm_substream *substream)
  474. {
  475. return snd_pcm_lib_free_pages(substream);
  476. }
  477. static int snd_ad1848_capture_prepare(struct snd_pcm_substream *substream)
  478. {
  479. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  480. struct snd_pcm_runtime *runtime = substream->runtime;
  481. unsigned long flags;
  482. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  483. unsigned int count = snd_pcm_lib_period_bytes(substream);
  484. chip->c_dma_size = size;
  485. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  486. snd_dma_program(chip->dma2, runtime->dma_addr, size,
  487. DMA_MODE_READ | DMA_AUTOINIT);
  488. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  489. spin_lock_irqsave(&chip->reg_lock, flags);
  490. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  491. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  492. spin_unlock_irqrestore(&chip->reg_lock, flags);
  493. return 0;
  494. }
  495. static irqreturn_t snd_ad1848_interrupt(int irq, void *dev_id)
  496. {
  497. struct snd_wss *chip = dev_id;
  498. if ((chip->mode & WSS_MODE_PLAY) && chip->playback_substream)
  499. snd_pcm_period_elapsed(chip->playback_substream);
  500. if ((chip->mode & WSS_MODE_RECORD) && chip->capture_substream)
  501. snd_pcm_period_elapsed(chip->capture_substream);
  502. outb(0, AD1848P(chip, STATUS)); /* clear global interrupt bit */
  503. return IRQ_HANDLED;
  504. }
  505. static snd_pcm_uframes_t snd_ad1848_playback_pointer(struct snd_pcm_substream *substream)
  506. {
  507. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  508. size_t ptr;
  509. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_PLAYBACK_ENABLE))
  510. return 0;
  511. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  512. return bytes_to_frames(substream->runtime, ptr);
  513. }
  514. static snd_pcm_uframes_t snd_ad1848_capture_pointer(struct snd_pcm_substream *substream)
  515. {
  516. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  517. size_t ptr;
  518. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_CAPTURE_ENABLE))
  519. return 0;
  520. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  521. return bytes_to_frames(substream->runtime, ptr);
  522. }
  523. /*
  524. */
  525. static void snd_ad1848_thinkpad_twiddle(struct snd_wss *chip, int on)
  526. {
  527. int tmp;
  528. if (!chip->thinkpad_flag) return;
  529. outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
  530. tmp = inb(AD1848_THINKPAD_CTL_PORT2);
  531. if (on)
  532. /* turn it on */
  533. tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
  534. else
  535. /* turn it off */
  536. tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
  537. outb(tmp, AD1848_THINKPAD_CTL_PORT2);
  538. }
  539. #ifdef CONFIG_PM
  540. static void snd_ad1848_suspend(struct snd_wss *chip)
  541. {
  542. snd_pcm_suspend_all(chip->pcm);
  543. if (chip->thinkpad_flag)
  544. snd_ad1848_thinkpad_twiddle(chip, 0);
  545. }
  546. static void snd_ad1848_resume(struct snd_wss *chip)
  547. {
  548. int i;
  549. if (chip->thinkpad_flag)
  550. snd_ad1848_thinkpad_twiddle(chip, 1);
  551. /* clear any pendings IRQ */
  552. inb(AD1848P(chip, STATUS));
  553. outb(0, AD1848P(chip, STATUS));
  554. mb();
  555. snd_ad1848_mce_down(chip);
  556. for (i = 0; i < 16; i++)
  557. snd_ad1848_out(chip, i, chip->image[i]);
  558. snd_ad1848_mce_up(chip);
  559. snd_ad1848_mce_down(chip);
  560. }
  561. #endif /* CONFIG_PM */
  562. static int snd_ad1848_probe(struct snd_wss *chip)
  563. {
  564. unsigned long flags;
  565. int i, id, rev, ad1847;
  566. unsigned char *ptr;
  567. #if 0
  568. snd_ad1848_debug(chip);
  569. #endif
  570. id = ad1847 = 0;
  571. for (i = 0; i < 1000; i++) {
  572. mb();
  573. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  574. udelay(500);
  575. else {
  576. spin_lock_irqsave(&chip->reg_lock, flags);
  577. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  578. snd_ad1848_out(chip, AD1848_LEFT_INPUT, 0xaa);
  579. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, 0x45);
  580. rev = snd_ad1848_in(chip, AD1848_RIGHT_INPUT);
  581. if (rev == 0x65) {
  582. spin_unlock_irqrestore(&chip->reg_lock, flags);
  583. id = 1;
  584. ad1847 = 1;
  585. break;
  586. }
  587. if (snd_ad1848_in(chip, AD1848_LEFT_INPUT) == 0xaa && rev == 0x45) {
  588. spin_unlock_irqrestore(&chip->reg_lock, flags);
  589. id = 1;
  590. break;
  591. }
  592. spin_unlock_irqrestore(&chip->reg_lock, flags);
  593. }
  594. }
  595. if (id != 1)
  596. return -ENODEV; /* no valid device found */
  597. if (chip->hardware == WSS_HW_DETECT) {
  598. if (ad1847) {
  599. chip->hardware = WSS_HW_AD1847;
  600. } else {
  601. chip->hardware = WSS_HW_AD1848;
  602. rev = snd_ad1848_in(chip, AD1848_MISC_INFO);
  603. if (rev & 0x80) {
  604. chip->hardware = WSS_HW_CS4248;
  605. } else if ((rev & 0x0f) == 0x0a) {
  606. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x40);
  607. for (i = 0; i < 16; ++i) {
  608. if (snd_ad1848_in(chip, i) != snd_ad1848_in(chip, i + 16)) {
  609. chip->hardware = WSS_HW_CMI8330;
  610. break;
  611. }
  612. }
  613. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  614. }
  615. }
  616. }
  617. spin_lock_irqsave(&chip->reg_lock, flags);
  618. inb(AD1848P(chip, STATUS)); /* clear any pendings IRQ */
  619. outb(0, AD1848P(chip, STATUS));
  620. mb();
  621. spin_unlock_irqrestore(&chip->reg_lock, flags);
  622. chip->image[AD1848_MISC_INFO] = 0x00;
  623. chip->image[AD1848_IFACE_CTRL] =
  624. (chip->image[AD1848_IFACE_CTRL] & ~AD1848_SINGLE_DMA) | AD1848_SINGLE_DMA;
  625. ptr = (unsigned char *) &chip->image;
  626. snd_ad1848_mce_down(chip);
  627. spin_lock_irqsave(&chip->reg_lock, flags);
  628. for (i = 0; i < 16; i++) /* ok.. fill all AD1848 registers */
  629. snd_ad1848_out(chip, i, *ptr++);
  630. spin_unlock_irqrestore(&chip->reg_lock, flags);
  631. snd_ad1848_mce_up(chip);
  632. snd_ad1848_mce_down(chip);
  633. return 0; /* all things are ok.. */
  634. }
  635. /*
  636. */
  637. static struct snd_pcm_hardware snd_ad1848_playback =
  638. {
  639. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  640. SNDRV_PCM_INFO_MMAP_VALID),
  641. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  642. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  643. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  644. .rate_min = 5510,
  645. .rate_max = 48000,
  646. .channels_min = 1,
  647. .channels_max = 2,
  648. .buffer_bytes_max = (128*1024),
  649. .period_bytes_min = 64,
  650. .period_bytes_max = (128*1024),
  651. .periods_min = 1,
  652. .periods_max = 1024,
  653. .fifo_size = 0,
  654. };
  655. static struct snd_pcm_hardware snd_ad1848_capture =
  656. {
  657. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  658. SNDRV_PCM_INFO_MMAP_VALID),
  659. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  660. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  661. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  662. .rate_min = 5510,
  663. .rate_max = 48000,
  664. .channels_min = 1,
  665. .channels_max = 2,
  666. .buffer_bytes_max = (128*1024),
  667. .period_bytes_min = 64,
  668. .period_bytes_max = (128*1024),
  669. .periods_min = 1,
  670. .periods_max = 1024,
  671. .fifo_size = 0,
  672. };
  673. /*
  674. */
  675. static int snd_ad1848_playback_open(struct snd_pcm_substream *substream)
  676. {
  677. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  678. struct snd_pcm_runtime *runtime = substream->runtime;
  679. int err;
  680. err = snd_ad1848_open(chip, WSS_MODE_PLAY);
  681. if (err < 0)
  682. return err;
  683. chip->playback_substream = substream;
  684. runtime->hw = snd_ad1848_playback;
  685. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  686. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  687. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  688. return 0;
  689. }
  690. static int snd_ad1848_capture_open(struct snd_pcm_substream *substream)
  691. {
  692. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  693. struct snd_pcm_runtime *runtime = substream->runtime;
  694. int err;
  695. err = snd_ad1848_open(chip, WSS_MODE_RECORD);
  696. if (err < 0)
  697. return err;
  698. chip->capture_substream = substream;
  699. runtime->hw = snd_ad1848_capture;
  700. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  701. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  702. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  703. return 0;
  704. }
  705. static int snd_ad1848_playback_close(struct snd_pcm_substream *substream)
  706. {
  707. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  708. chip->mode &= ~WSS_MODE_PLAY;
  709. chip->playback_substream = NULL;
  710. snd_ad1848_close(chip);
  711. return 0;
  712. }
  713. static int snd_ad1848_capture_close(struct snd_pcm_substream *substream)
  714. {
  715. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  716. chip->mode &= ~WSS_MODE_RECORD;
  717. chip->capture_substream = NULL;
  718. snd_ad1848_close(chip);
  719. return 0;
  720. }
  721. static int snd_ad1848_free(struct snd_wss *chip)
  722. {
  723. release_and_free_resource(chip->res_port);
  724. if (chip->irq >= 0)
  725. free_irq(chip->irq, (void *) chip);
  726. if (chip->dma1 >= 0) {
  727. snd_dma_disable(chip->dma1);
  728. free_dma(chip->dma1);
  729. }
  730. kfree(chip);
  731. return 0;
  732. }
  733. static int snd_ad1848_dev_free(struct snd_device *device)
  734. {
  735. struct snd_wss *chip = device->device_data;
  736. return snd_ad1848_free(chip);
  737. }
  738. static const char *snd_ad1848_chip_id(struct snd_wss *chip)
  739. {
  740. switch (chip->hardware) {
  741. case AD1848_HW_AD1847: return "AD1847";
  742. case AD1848_HW_AD1848: return "AD1848";
  743. case AD1848_HW_CS4248: return "CS4248";
  744. case AD1848_HW_CMI8330: return "CMI8330/C3D";
  745. default: return "???";
  746. }
  747. }
  748. int snd_ad1848_create(struct snd_card *card,
  749. unsigned long port,
  750. int irq, int dma,
  751. unsigned short hardware,
  752. struct snd_wss **rchip)
  753. {
  754. static struct snd_device_ops ops = {
  755. .dev_free = snd_ad1848_dev_free,
  756. };
  757. struct snd_wss *chip;
  758. int err;
  759. *rchip = NULL;
  760. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  761. if (chip == NULL)
  762. return -ENOMEM;
  763. spin_lock_init(&chip->reg_lock);
  764. chip->card = card;
  765. chip->port = port;
  766. chip->irq = -1;
  767. chip->dma1 = -1;
  768. chip->dma2 = -1;
  769. chip->single_dma = 1;
  770. chip->hardware = hardware;
  771. memcpy(&chip->image, &snd_ad1848_original_image, sizeof(snd_ad1848_original_image));
  772. if ((chip->res_port = request_region(port, 4, "AD1848")) == NULL) {
  773. snd_printk(KERN_ERR "ad1848: can't grab port 0x%lx\n", port);
  774. snd_ad1848_free(chip);
  775. return -EBUSY;
  776. }
  777. if (request_irq(irq, snd_ad1848_interrupt, IRQF_DISABLED, "AD1848", (void *) chip)) {
  778. snd_printk(KERN_ERR "ad1848: can't grab IRQ %d\n", irq);
  779. snd_ad1848_free(chip);
  780. return -EBUSY;
  781. }
  782. chip->irq = irq;
  783. if (request_dma(dma, "AD1848")) {
  784. snd_printk(KERN_ERR "ad1848: can't grab DMA %d\n", dma);
  785. snd_ad1848_free(chip);
  786. return -EBUSY;
  787. }
  788. chip->dma1 = dma;
  789. chip->dma2 = dma;
  790. if (hardware == WSS_HW_THINKPAD) {
  791. chip->thinkpad_flag = 1;
  792. chip->hardware = WSS_HW_DETECT; /* reset */
  793. snd_ad1848_thinkpad_twiddle(chip, 1);
  794. }
  795. if (snd_ad1848_probe(chip) < 0) {
  796. snd_ad1848_free(chip);
  797. return -ENODEV;
  798. }
  799. /* Register device */
  800. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  801. snd_ad1848_free(chip);
  802. return err;
  803. }
  804. #ifdef CONFIG_PM
  805. chip->suspend = snd_ad1848_suspend;
  806. chip->resume = snd_ad1848_resume;
  807. #endif
  808. *rchip = chip;
  809. return 0;
  810. }
  811. EXPORT_SYMBOL(snd_ad1848_create);
  812. static struct snd_pcm_ops snd_ad1848_playback_ops = {
  813. .open = snd_ad1848_playback_open,
  814. .close = snd_ad1848_playback_close,
  815. .ioctl = snd_ad1848_ioctl,
  816. .hw_params = snd_ad1848_playback_hw_params,
  817. .hw_free = snd_ad1848_playback_hw_free,
  818. .prepare = snd_ad1848_playback_prepare,
  819. .trigger = snd_ad1848_playback_trigger,
  820. .pointer = snd_ad1848_playback_pointer,
  821. };
  822. static struct snd_pcm_ops snd_ad1848_capture_ops = {
  823. .open = snd_ad1848_capture_open,
  824. .close = snd_ad1848_capture_close,
  825. .ioctl = snd_ad1848_ioctl,
  826. .hw_params = snd_ad1848_capture_hw_params,
  827. .hw_free = snd_ad1848_capture_hw_free,
  828. .prepare = snd_ad1848_capture_prepare,
  829. .trigger = snd_ad1848_capture_trigger,
  830. .pointer = snd_ad1848_capture_pointer,
  831. };
  832. int snd_ad1848_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
  833. {
  834. struct snd_pcm *pcm;
  835. int err;
  836. if ((err = snd_pcm_new(chip->card, "AD1848", device, 1, 1, &pcm)) < 0)
  837. return err;
  838. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1848_playback_ops);
  839. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1848_capture_ops);
  840. pcm->private_data = chip;
  841. pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  842. strcpy(pcm->name, snd_ad1848_chip_id(chip));
  843. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  844. snd_dma_isa_data(),
  845. 64 * 1024,
  846. chip->dma1 > 3 ?
  847. 128 * 1024 : 64 * 1024);
  848. chip->pcm = pcm;
  849. if (rpcm)
  850. *rpcm = pcm;
  851. return 0;
  852. }
  853. EXPORT_SYMBOL(snd_ad1848_pcm);
  854. const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction)
  855. {
  856. return direction == SNDRV_PCM_STREAM_PLAYBACK ?
  857. &snd_ad1848_playback_ops : &snd_ad1848_capture_ops;
  858. }
  859. EXPORT_SYMBOL(snd_ad1848_get_pcm_ops);
  860. /*
  861. * MIXER part
  862. */
  863. static int snd_ad1848_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  864. {
  865. static char *texts[4] = {
  866. "Line", "Aux", "Mic", "Mix"
  867. };
  868. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  869. uinfo->count = 2;
  870. uinfo->value.enumerated.items = 4;
  871. if (uinfo->value.enumerated.item > 3)
  872. uinfo->value.enumerated.item = 3;
  873. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  874. return 0;
  875. }
  876. static int snd_ad1848_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  877. {
  878. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  879. unsigned long flags;
  880. spin_lock_irqsave(&chip->reg_lock, flags);
  881. ucontrol->value.enumerated.item[0] = (chip->image[AD1848_LEFT_INPUT] & AD1848_MIXS_ALL) >> 6;
  882. ucontrol->value.enumerated.item[1] = (chip->image[AD1848_RIGHT_INPUT] & AD1848_MIXS_ALL) >> 6;
  883. spin_unlock_irqrestore(&chip->reg_lock, flags);
  884. return 0;
  885. }
  886. static int snd_ad1848_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  887. {
  888. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  889. unsigned long flags;
  890. unsigned short left, right;
  891. int change;
  892. if (ucontrol->value.enumerated.item[0] > 3 ||
  893. ucontrol->value.enumerated.item[1] > 3)
  894. return -EINVAL;
  895. left = ucontrol->value.enumerated.item[0] << 6;
  896. right = ucontrol->value.enumerated.item[1] << 6;
  897. spin_lock_irqsave(&chip->reg_lock, flags);
  898. left = (chip->image[AD1848_LEFT_INPUT] & ~AD1848_MIXS_ALL) | left;
  899. right = (chip->image[AD1848_RIGHT_INPUT] & ~AD1848_MIXS_ALL) | right;
  900. change = left != chip->image[AD1848_LEFT_INPUT] ||
  901. right != chip->image[AD1848_RIGHT_INPUT];
  902. snd_ad1848_out(chip, AD1848_LEFT_INPUT, left);
  903. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, right);
  904. spin_unlock_irqrestore(&chip->reg_lock, flags);
  905. return change;
  906. }
  907. static int snd_ad1848_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  908. {
  909. int mask = (kcontrol->private_value >> 16) & 0xff;
  910. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  911. uinfo->count = 1;
  912. uinfo->value.integer.min = 0;
  913. uinfo->value.integer.max = mask;
  914. return 0;
  915. }
  916. static int snd_ad1848_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  917. {
  918. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  919. unsigned long flags;
  920. int reg = kcontrol->private_value & 0xff;
  921. int shift = (kcontrol->private_value >> 8) & 0xff;
  922. int mask = (kcontrol->private_value >> 16) & 0xff;
  923. int invert = (kcontrol->private_value >> 24) & 0xff;
  924. spin_lock_irqsave(&chip->reg_lock, flags);
  925. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  926. spin_unlock_irqrestore(&chip->reg_lock, flags);
  927. if (invert)
  928. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  929. return 0;
  930. }
  931. static int snd_ad1848_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  932. {
  933. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  934. unsigned long flags;
  935. int reg = kcontrol->private_value & 0xff;
  936. int shift = (kcontrol->private_value >> 8) & 0xff;
  937. int mask = (kcontrol->private_value >> 16) & 0xff;
  938. int invert = (kcontrol->private_value >> 24) & 0xff;
  939. int change;
  940. unsigned short val;
  941. val = (ucontrol->value.integer.value[0] & mask);
  942. if (invert)
  943. val = mask - val;
  944. val <<= shift;
  945. spin_lock_irqsave(&chip->reg_lock, flags);
  946. val = (chip->image[reg] & ~(mask << shift)) | val;
  947. change = val != chip->image[reg];
  948. snd_ad1848_out(chip, reg, val);
  949. spin_unlock_irqrestore(&chip->reg_lock, flags);
  950. return change;
  951. }
  952. static int snd_ad1848_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  953. {
  954. int mask = (kcontrol->private_value >> 24) & 0xff;
  955. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  956. uinfo->count = 2;
  957. uinfo->value.integer.min = 0;
  958. uinfo->value.integer.max = mask;
  959. return 0;
  960. }
  961. static int snd_ad1848_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  962. {
  963. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  964. unsigned long flags;
  965. int left_reg = kcontrol->private_value & 0xff;
  966. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  967. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  968. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  969. int mask = (kcontrol->private_value >> 24) & 0xff;
  970. int invert = (kcontrol->private_value >> 22) & 1;
  971. spin_lock_irqsave(&chip->reg_lock, flags);
  972. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  973. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  974. spin_unlock_irqrestore(&chip->reg_lock, flags);
  975. if (invert) {
  976. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  977. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  978. }
  979. return 0;
  980. }
  981. static int snd_ad1848_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  982. {
  983. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  984. unsigned long flags;
  985. int left_reg = kcontrol->private_value & 0xff;
  986. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  987. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  988. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  989. int mask = (kcontrol->private_value >> 24) & 0xff;
  990. int invert = (kcontrol->private_value >> 22) & 1;
  991. int change;
  992. unsigned short val1, val2;
  993. val1 = ucontrol->value.integer.value[0] & mask;
  994. val2 = ucontrol->value.integer.value[1] & mask;
  995. if (invert) {
  996. val1 = mask - val1;
  997. val2 = mask - val2;
  998. }
  999. val1 <<= shift_left;
  1000. val2 <<= shift_right;
  1001. spin_lock_irqsave(&chip->reg_lock, flags);
  1002. if (left_reg != right_reg) {
  1003. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1004. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1005. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1006. snd_ad1848_out(chip, left_reg, val1);
  1007. snd_ad1848_out(chip, right_reg, val2);
  1008. } else {
  1009. val1 = (chip->image[left_reg] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1010. change = val1 != chip->image[left_reg];
  1011. snd_ad1848_out(chip, left_reg, val1);
  1012. }
  1013. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1014. return change;
  1015. }
  1016. static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
  1017. static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
  1018. static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
  1019. #define AD1848_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
  1020. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  1021. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1022. .name = xname, \
  1023. .index = xindex, \
  1024. .info = snd_ad1848_info_single, \
  1025. .get = snd_ad1848_get_single, \
  1026. .put = snd_ad1848_put_single, \
  1027. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
  1028. .tlv = { .p = (xtlv) } }
  1029. #define AD1848_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
  1030. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  1031. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1032. .name = xname, \
  1033. .index = xindex, \
  1034. .info = snd_ad1848_info_double, \
  1035. .get = snd_ad1848_get_double, \
  1036. .put = snd_ad1848_put_double, \
  1037. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
  1038. (shift_right << 19) | (mask << 24) | (invert << 22), \
  1039. .tlv = { .p = (xtlv) } }
  1040. static struct snd_kcontrol_new snd_ad1848_controls[] = {
  1041. WSS_DOUBLE("PCM Playback Switch", 0,
  1042. AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 7, 7, 1, 1),
  1043. AD1848_DOUBLE_TLV("PCM Playback Volume", 0,
  1044. AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 0, 0, 63, 1,
  1045. db_scale_6bit),
  1046. WSS_DOUBLE("Aux Playback Switch", 0,
  1047. AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1048. AD1848_DOUBLE_TLV("Aux Playback Volume", 0,
  1049. AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
  1050. db_scale_5bit_12db_max),
  1051. WSS_DOUBLE("Aux Playback Switch", 1,
  1052. AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1053. AD1848_DOUBLE_TLV("Aux Playback Volume", 1,
  1054. AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
  1055. db_scale_5bit_12db_max),
  1056. AD1848_DOUBLE_TLV("Capture Volume", 0,
  1057. AD1848_LEFT_INPUT, AD1848_RIGHT_INPUT, 0, 0, 15, 0,
  1058. db_scale_rec_gain),
  1059. {
  1060. .name = "Capture Source",
  1061. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1062. .info = snd_ad1848_info_mux,
  1063. .get = snd_ad1848_get_mux,
  1064. .put = snd_ad1848_put_mux,
  1065. },
  1066. WSS_SINGLE("Loopback Capture Switch", 0,
  1067. AD1848_LOOPBACK, 0, 1, 0),
  1068. AD1848_SINGLE_TLV("Loopback Capture Volume", 0,
  1069. AD1848_LOOPBACK, 1, 63, 0,
  1070. db_scale_6bit),
  1071. };
  1072. int snd_ad1848_mixer(struct snd_wss *chip)
  1073. {
  1074. struct snd_card *card;
  1075. struct snd_pcm *pcm;
  1076. unsigned int idx;
  1077. int err;
  1078. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1079. pcm = chip->pcm;
  1080. card = chip->card;
  1081. strcpy(card->mixername, pcm->name);
  1082. for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
  1083. err = snd_ctl_add(card,
  1084. snd_ctl_new1(&snd_ad1848_controls[idx], chip));
  1085. if (err < 0)
  1086. return err;
  1087. }
  1088. return 0;
  1089. }
  1090. EXPORT_SYMBOL(snd_ad1848_mixer);
  1091. /*
  1092. * INIT part
  1093. */
  1094. static int __init alsa_ad1848_init(void)
  1095. {
  1096. return 0;
  1097. }
  1098. static void __exit alsa_ad1848_exit(void)
  1099. {
  1100. }
  1101. module_init(alsa_ad1848_init)
  1102. module_exit(alsa_ad1848_exit)