processor.h 23 KB

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  1. #ifndef _ASM_X86_PROCESSOR_H
  2. #define _ASM_X86_PROCESSOR_H
  3. #include <asm/processor-flags.h>
  4. /* Forward declaration, a strange C thing */
  5. struct task_struct;
  6. struct mm_struct;
  7. #include <asm/vm86.h>
  8. #include <asm/math_emu.h>
  9. #include <asm/segment.h>
  10. #include <asm/types.h>
  11. #include <asm/sigcontext.h>
  12. #include <asm/current.h>
  13. #include <asm/cpufeature.h>
  14. #include <asm/system.h>
  15. #include <asm/page.h>
  16. #include <asm/pgtable_types.h>
  17. #include <asm/percpu.h>
  18. #include <asm/msr.h>
  19. #include <asm/desc_defs.h>
  20. #include <asm/nops.h>
  21. #include <asm/ds.h>
  22. #include <linux/personality.h>
  23. #include <linux/cpumask.h>
  24. #include <linux/cache.h>
  25. #include <linux/threads.h>
  26. #include <linux/init.h>
  27. /*
  28. * Default implementation of macro that returns current
  29. * instruction pointer ("program counter").
  30. */
  31. static inline void *current_text_addr(void)
  32. {
  33. void *pc;
  34. asm volatile("mov $1f, %0; 1:":"=r" (pc));
  35. return pc;
  36. }
  37. #ifdef CONFIG_X86_VSMP
  38. # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
  39. # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
  40. #else
  41. # define ARCH_MIN_TASKALIGN 16
  42. # define ARCH_MIN_MMSTRUCT_ALIGN 0
  43. #endif
  44. /*
  45. * CPU type and hardware bug flags. Kept separately for each CPU.
  46. * Members of this structure are referenced in head.S, so think twice
  47. * before touching them. [mj]
  48. */
  49. struct cpuinfo_x86 {
  50. __u8 x86; /* CPU family */
  51. __u8 x86_vendor; /* CPU vendor */
  52. __u8 x86_model;
  53. __u8 x86_mask;
  54. #ifdef CONFIG_X86_32
  55. char wp_works_ok; /* It doesn't on 386's */
  56. /* Problems on some 486Dx4's and old 386's: */
  57. char hlt_works_ok;
  58. char hard_math;
  59. char rfu;
  60. char fdiv_bug;
  61. char f00f_bug;
  62. char coma_bug;
  63. char pad0;
  64. #else
  65. /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  66. int x86_tlbsize;
  67. #endif
  68. __u8 x86_virt_bits;
  69. __u8 x86_phys_bits;
  70. /* CPUID returned core id bits: */
  71. __u8 x86_coreid_bits;
  72. /* Max extended CPUID function supported: */
  73. __u32 extended_cpuid_level;
  74. /* Maximum supported CPUID level, -1=no CPUID: */
  75. int cpuid_level;
  76. __u32 x86_capability[NCAPINTS];
  77. char x86_vendor_id[16];
  78. char x86_model_id[64];
  79. /* in KB - valid for CPUS which support this call: */
  80. int x86_cache_size;
  81. int x86_cache_alignment; /* In bytes */
  82. int x86_power;
  83. unsigned long loops_per_jiffy;
  84. #ifdef CONFIG_SMP
  85. /* cpus sharing the last level cache: */
  86. cpumask_var_t llc_shared_map;
  87. #endif
  88. /* cpuid returned max cores value: */
  89. u16 x86_max_cores;
  90. u16 apicid;
  91. u16 initial_apicid;
  92. u16 x86_clflush_size;
  93. #ifdef CONFIG_SMP
  94. /* number of cores as seen by the OS: */
  95. u16 booted_cores;
  96. /* Physical processor id: */
  97. u16 phys_proc_id;
  98. /* Core id: */
  99. u16 cpu_core_id;
  100. /* Index into per_cpu list: */
  101. u16 cpu_index;
  102. #endif
  103. unsigned int x86_hyper_vendor;
  104. } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  105. #define X86_VENDOR_INTEL 0
  106. #define X86_VENDOR_CYRIX 1
  107. #define X86_VENDOR_AMD 2
  108. #define X86_VENDOR_UMC 3
  109. #define X86_VENDOR_CENTAUR 5
  110. #define X86_VENDOR_TRANSMETA 7
  111. #define X86_VENDOR_NSC 8
  112. #define X86_VENDOR_NUM 9
  113. #define X86_VENDOR_UNKNOWN 0xff
  114. #define X86_HYPER_VENDOR_NONE 0
  115. #define X86_HYPER_VENDOR_VMWARE 1
  116. /*
  117. * capabilities of CPUs
  118. */
  119. extern struct cpuinfo_x86 boot_cpu_data;
  120. extern struct cpuinfo_x86 new_cpu_data;
  121. extern struct tss_struct doublefault_tss;
  122. extern __u32 cleared_cpu_caps[NCAPINTS];
  123. #ifdef CONFIG_SMP
  124. DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
  125. #define cpu_data(cpu) per_cpu(cpu_info, cpu)
  126. #define current_cpu_data __get_cpu_var(cpu_info)
  127. #else
  128. #define cpu_data(cpu) boot_cpu_data
  129. #define current_cpu_data boot_cpu_data
  130. #endif
  131. extern const struct seq_operations cpuinfo_op;
  132. static inline int hlt_works(int cpu)
  133. {
  134. #ifdef CONFIG_X86_32
  135. return cpu_data(cpu).hlt_works_ok;
  136. #else
  137. return 1;
  138. #endif
  139. }
  140. #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
  141. extern void cpu_detect(struct cpuinfo_x86 *c);
  142. extern struct pt_regs *idle_regs(struct pt_regs *);
  143. extern void early_cpu_init(void);
  144. extern void identify_boot_cpu(void);
  145. extern void identify_secondary_cpu(struct cpuinfo_x86 *);
  146. extern void print_cpu_info(struct cpuinfo_x86 *);
  147. extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
  148. extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
  149. extern unsigned short num_cache_leaves;
  150. extern void detect_extended_topology(struct cpuinfo_x86 *c);
  151. extern void detect_ht(struct cpuinfo_x86 *c);
  152. static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
  153. unsigned int *ecx, unsigned int *edx)
  154. {
  155. /* ecx is often an input as well as an output. */
  156. asm("cpuid"
  157. : "=a" (*eax),
  158. "=b" (*ebx),
  159. "=c" (*ecx),
  160. "=d" (*edx)
  161. : "0" (*eax), "2" (*ecx));
  162. }
  163. static inline void load_cr3(pgd_t *pgdir)
  164. {
  165. write_cr3(__pa(pgdir));
  166. }
  167. #ifdef CONFIG_X86_32
  168. /* This is the TSS defined by the hardware. */
  169. struct x86_hw_tss {
  170. unsigned short back_link, __blh;
  171. unsigned long sp0;
  172. unsigned short ss0, __ss0h;
  173. unsigned long sp1;
  174. /* ss1 caches MSR_IA32_SYSENTER_CS: */
  175. unsigned short ss1, __ss1h;
  176. unsigned long sp2;
  177. unsigned short ss2, __ss2h;
  178. unsigned long __cr3;
  179. unsigned long ip;
  180. unsigned long flags;
  181. unsigned long ax;
  182. unsigned long cx;
  183. unsigned long dx;
  184. unsigned long bx;
  185. unsigned long sp;
  186. unsigned long bp;
  187. unsigned long si;
  188. unsigned long di;
  189. unsigned short es, __esh;
  190. unsigned short cs, __csh;
  191. unsigned short ss, __ssh;
  192. unsigned short ds, __dsh;
  193. unsigned short fs, __fsh;
  194. unsigned short gs, __gsh;
  195. unsigned short ldt, __ldth;
  196. unsigned short trace;
  197. unsigned short io_bitmap_base;
  198. } __attribute__((packed));
  199. #else
  200. struct x86_hw_tss {
  201. u32 reserved1;
  202. u64 sp0;
  203. u64 sp1;
  204. u64 sp2;
  205. u64 reserved2;
  206. u64 ist[7];
  207. u32 reserved3;
  208. u32 reserved4;
  209. u16 reserved5;
  210. u16 io_bitmap_base;
  211. } __attribute__((packed)) ____cacheline_aligned;
  212. #endif
  213. /*
  214. * IO-bitmap sizes:
  215. */
  216. #define IO_BITMAP_BITS 65536
  217. #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
  218. #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
  219. #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
  220. #define INVALID_IO_BITMAP_OFFSET 0x8000
  221. struct tss_struct {
  222. /*
  223. * The hardware state:
  224. */
  225. struct x86_hw_tss x86_tss;
  226. /*
  227. * The extra 1 is there because the CPU will access an
  228. * additional byte beyond the end of the IO permission
  229. * bitmap. The extra byte must be all 1 bits, and must
  230. * be within the limit.
  231. */
  232. unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
  233. /*
  234. * .. and then another 0x100 bytes for the emergency kernel stack:
  235. */
  236. unsigned long stack[64];
  237. } ____cacheline_aligned;
  238. DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
  239. /*
  240. * Save the original ist values for checking stack pointers during debugging
  241. */
  242. struct orig_ist {
  243. unsigned long ist[7];
  244. };
  245. #define MXCSR_DEFAULT 0x1f80
  246. struct i387_fsave_struct {
  247. u32 cwd; /* FPU Control Word */
  248. u32 swd; /* FPU Status Word */
  249. u32 twd; /* FPU Tag Word */
  250. u32 fip; /* FPU IP Offset */
  251. u32 fcs; /* FPU IP Selector */
  252. u32 foo; /* FPU Operand Pointer Offset */
  253. u32 fos; /* FPU Operand Pointer Selector */
  254. /* 8*10 bytes for each FP-reg = 80 bytes: */
  255. u32 st_space[20];
  256. /* Software status information [not touched by FSAVE ]: */
  257. u32 status;
  258. };
  259. struct i387_fxsave_struct {
  260. u16 cwd; /* Control Word */
  261. u16 swd; /* Status Word */
  262. u16 twd; /* Tag Word */
  263. u16 fop; /* Last Instruction Opcode */
  264. union {
  265. struct {
  266. u64 rip; /* Instruction Pointer */
  267. u64 rdp; /* Data Pointer */
  268. };
  269. struct {
  270. u32 fip; /* FPU IP Offset */
  271. u32 fcs; /* FPU IP Selector */
  272. u32 foo; /* FPU Operand Offset */
  273. u32 fos; /* FPU Operand Selector */
  274. };
  275. };
  276. u32 mxcsr; /* MXCSR Register State */
  277. u32 mxcsr_mask; /* MXCSR Mask */
  278. /* 8*16 bytes for each FP-reg = 128 bytes: */
  279. u32 st_space[32];
  280. /* 16*16 bytes for each XMM-reg = 256 bytes: */
  281. u32 xmm_space[64];
  282. u32 padding[12];
  283. union {
  284. u32 padding1[12];
  285. u32 sw_reserved[12];
  286. };
  287. } __attribute__((aligned(16)));
  288. struct i387_soft_struct {
  289. u32 cwd;
  290. u32 swd;
  291. u32 twd;
  292. u32 fip;
  293. u32 fcs;
  294. u32 foo;
  295. u32 fos;
  296. /* 8*10 bytes for each FP-reg = 80 bytes: */
  297. u32 st_space[20];
  298. u8 ftop;
  299. u8 changed;
  300. u8 lookahead;
  301. u8 no_update;
  302. u8 rm;
  303. u8 alimit;
  304. struct math_emu_info *info;
  305. u32 entry_eip;
  306. };
  307. struct ymmh_struct {
  308. /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
  309. u32 ymmh_space[64];
  310. };
  311. struct xsave_hdr_struct {
  312. u64 xstate_bv;
  313. u64 reserved1[2];
  314. u64 reserved2[5];
  315. } __attribute__((packed));
  316. struct xsave_struct {
  317. struct i387_fxsave_struct i387;
  318. struct xsave_hdr_struct xsave_hdr;
  319. struct ymmh_struct ymmh;
  320. /* new processor state extensions will go here */
  321. } __attribute__ ((packed, aligned (64)));
  322. union thread_xstate {
  323. struct i387_fsave_struct fsave;
  324. struct i387_fxsave_struct fxsave;
  325. struct i387_soft_struct soft;
  326. struct xsave_struct xsave;
  327. };
  328. #ifdef CONFIG_X86_64
  329. DECLARE_PER_CPU(struct orig_ist, orig_ist);
  330. union irq_stack_union {
  331. char irq_stack[IRQ_STACK_SIZE];
  332. /*
  333. * GCC hardcodes the stack canary as %gs:40. Since the
  334. * irq_stack is the object at %gs:0, we reserve the bottom
  335. * 48 bytes of the irq stack for the canary.
  336. */
  337. struct {
  338. char gs_base[40];
  339. unsigned long stack_canary;
  340. };
  341. };
  342. DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
  343. DECLARE_INIT_PER_CPU(irq_stack_union);
  344. DECLARE_PER_CPU(char *, irq_stack_ptr);
  345. DECLARE_PER_CPU(unsigned int, irq_count);
  346. extern unsigned long kernel_eflags;
  347. extern asmlinkage void ignore_sysret(void);
  348. #else /* X86_64 */
  349. #ifdef CONFIG_CC_STACKPROTECTOR
  350. DECLARE_PER_CPU(unsigned long, stack_canary);
  351. #endif
  352. #endif /* X86_64 */
  353. extern unsigned int xstate_size;
  354. extern void free_thread_xstate(struct task_struct *);
  355. extern struct kmem_cache *task_xstate_cachep;
  356. extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
  357. extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
  358. extern unsigned short num_cache_leaves;
  359. struct thread_struct {
  360. /* Cached TLS descriptors: */
  361. struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
  362. unsigned long sp0;
  363. unsigned long sp;
  364. #ifdef CONFIG_X86_32
  365. unsigned long sysenter_cs;
  366. #else
  367. unsigned long usersp; /* Copy from PDA */
  368. unsigned short es;
  369. unsigned short ds;
  370. unsigned short fsindex;
  371. unsigned short gsindex;
  372. #endif
  373. #ifdef CONFIG_X86_32
  374. unsigned long ip;
  375. #endif
  376. #ifdef CONFIG_X86_64
  377. unsigned long fs;
  378. #endif
  379. unsigned long gs;
  380. /* Hardware debugging registers: */
  381. unsigned long debugreg0;
  382. unsigned long debugreg1;
  383. unsigned long debugreg2;
  384. unsigned long debugreg3;
  385. unsigned long debugreg6;
  386. unsigned long debugreg7;
  387. /* Fault info: */
  388. unsigned long cr2;
  389. unsigned long trap_no;
  390. unsigned long error_code;
  391. /* floating point and extended processor state */
  392. union thread_xstate *xstate;
  393. #ifdef CONFIG_X86_32
  394. /* Virtual 86 mode info */
  395. struct vm86_struct __user *vm86_info;
  396. unsigned long screen_bitmap;
  397. unsigned long v86flags;
  398. unsigned long v86mask;
  399. unsigned long saved_sp0;
  400. unsigned int saved_fs;
  401. unsigned int saved_gs;
  402. #endif
  403. /* IO permissions: */
  404. unsigned long *io_bitmap_ptr;
  405. unsigned long iopl;
  406. /* Max allowed port in the bitmap, in bytes: */
  407. unsigned io_bitmap_max;
  408. /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
  409. unsigned long debugctlmsr;
  410. #ifdef CONFIG_X86_DS
  411. /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
  412. struct ds_context *ds_ctx;
  413. #endif /* CONFIG_X86_DS */
  414. #ifdef CONFIG_X86_PTRACE_BTS
  415. /* the signal to send on a bts buffer overflow */
  416. unsigned int bts_ovfl_signal;
  417. #endif /* CONFIG_X86_PTRACE_BTS */
  418. };
  419. static inline unsigned long native_get_debugreg(int regno)
  420. {
  421. unsigned long val = 0; /* Damn you, gcc! */
  422. switch (regno) {
  423. case 0:
  424. asm("mov %%db0, %0" :"=r" (val));
  425. break;
  426. case 1:
  427. asm("mov %%db1, %0" :"=r" (val));
  428. break;
  429. case 2:
  430. asm("mov %%db2, %0" :"=r" (val));
  431. break;
  432. case 3:
  433. asm("mov %%db3, %0" :"=r" (val));
  434. break;
  435. case 6:
  436. asm("mov %%db6, %0" :"=r" (val));
  437. break;
  438. case 7:
  439. asm("mov %%db7, %0" :"=r" (val));
  440. break;
  441. default:
  442. BUG();
  443. }
  444. return val;
  445. }
  446. static inline void native_set_debugreg(int regno, unsigned long value)
  447. {
  448. switch (regno) {
  449. case 0:
  450. asm("mov %0, %%db0" ::"r" (value));
  451. break;
  452. case 1:
  453. asm("mov %0, %%db1" ::"r" (value));
  454. break;
  455. case 2:
  456. asm("mov %0, %%db2" ::"r" (value));
  457. break;
  458. case 3:
  459. asm("mov %0, %%db3" ::"r" (value));
  460. break;
  461. case 6:
  462. asm("mov %0, %%db6" ::"r" (value));
  463. break;
  464. case 7:
  465. asm("mov %0, %%db7" ::"r" (value));
  466. break;
  467. default:
  468. BUG();
  469. }
  470. }
  471. /*
  472. * Set IOPL bits in EFLAGS from given mask
  473. */
  474. static inline void native_set_iopl_mask(unsigned mask)
  475. {
  476. #ifdef CONFIG_X86_32
  477. unsigned int reg;
  478. asm volatile ("pushfl;"
  479. "popl %0;"
  480. "andl %1, %0;"
  481. "orl %2, %0;"
  482. "pushl %0;"
  483. "popfl"
  484. : "=&r" (reg)
  485. : "i" (~X86_EFLAGS_IOPL), "r" (mask));
  486. #endif
  487. }
  488. static inline void
  489. native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
  490. {
  491. tss->x86_tss.sp0 = thread->sp0;
  492. #ifdef CONFIG_X86_32
  493. /* Only happens when SEP is enabled, no need to test "SEP"arately: */
  494. if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
  495. tss->x86_tss.ss1 = thread->sysenter_cs;
  496. wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
  497. }
  498. #endif
  499. }
  500. static inline void native_swapgs(void)
  501. {
  502. #ifdef CONFIG_X86_64
  503. asm volatile("swapgs" ::: "memory");
  504. #endif
  505. }
  506. #ifdef CONFIG_PARAVIRT
  507. #include <asm/paravirt.h>
  508. #else
  509. #define __cpuid native_cpuid
  510. #define paravirt_enabled() 0
  511. /*
  512. * These special macros can be used to get or set a debugging register
  513. */
  514. #define get_debugreg(var, register) \
  515. (var) = native_get_debugreg(register)
  516. #define set_debugreg(value, register) \
  517. native_set_debugreg(register, value)
  518. static inline void load_sp0(struct tss_struct *tss,
  519. struct thread_struct *thread)
  520. {
  521. native_load_sp0(tss, thread);
  522. }
  523. #define set_iopl_mask native_set_iopl_mask
  524. #endif /* CONFIG_PARAVIRT */
  525. /*
  526. * Save the cr4 feature set we're using (ie
  527. * Pentium 4MB enable and PPro Global page
  528. * enable), so that any CPU's that boot up
  529. * after us can get the correct flags.
  530. */
  531. extern unsigned long mmu_cr4_features;
  532. static inline void set_in_cr4(unsigned long mask)
  533. {
  534. unsigned cr4;
  535. mmu_cr4_features |= mask;
  536. cr4 = read_cr4();
  537. cr4 |= mask;
  538. write_cr4(cr4);
  539. }
  540. static inline void clear_in_cr4(unsigned long mask)
  541. {
  542. unsigned cr4;
  543. mmu_cr4_features &= ~mask;
  544. cr4 = read_cr4();
  545. cr4 &= ~mask;
  546. write_cr4(cr4);
  547. }
  548. typedef struct {
  549. unsigned long seg;
  550. } mm_segment_t;
  551. /*
  552. * create a kernel thread without removing it from tasklists
  553. */
  554. extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
  555. /* Free all resources held by a thread. */
  556. extern void release_thread(struct task_struct *);
  557. /* Prepare to copy thread state - unlazy all lazy state */
  558. extern void prepare_to_copy(struct task_struct *tsk);
  559. unsigned long get_wchan(struct task_struct *p);
  560. /*
  561. * Generic CPUID function
  562. * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
  563. * resulting in stale register contents being returned.
  564. */
  565. static inline void cpuid(unsigned int op,
  566. unsigned int *eax, unsigned int *ebx,
  567. unsigned int *ecx, unsigned int *edx)
  568. {
  569. *eax = op;
  570. *ecx = 0;
  571. __cpuid(eax, ebx, ecx, edx);
  572. }
  573. /* Some CPUID calls want 'count' to be placed in ecx */
  574. static inline void cpuid_count(unsigned int op, int count,
  575. unsigned int *eax, unsigned int *ebx,
  576. unsigned int *ecx, unsigned int *edx)
  577. {
  578. *eax = op;
  579. *ecx = count;
  580. __cpuid(eax, ebx, ecx, edx);
  581. }
  582. /*
  583. * CPUID functions returning a single datum
  584. */
  585. static inline unsigned int cpuid_eax(unsigned int op)
  586. {
  587. unsigned int eax, ebx, ecx, edx;
  588. cpuid(op, &eax, &ebx, &ecx, &edx);
  589. return eax;
  590. }
  591. static inline unsigned int cpuid_ebx(unsigned int op)
  592. {
  593. unsigned int eax, ebx, ecx, edx;
  594. cpuid(op, &eax, &ebx, &ecx, &edx);
  595. return ebx;
  596. }
  597. static inline unsigned int cpuid_ecx(unsigned int op)
  598. {
  599. unsigned int eax, ebx, ecx, edx;
  600. cpuid(op, &eax, &ebx, &ecx, &edx);
  601. return ecx;
  602. }
  603. static inline unsigned int cpuid_edx(unsigned int op)
  604. {
  605. unsigned int eax, ebx, ecx, edx;
  606. cpuid(op, &eax, &ebx, &ecx, &edx);
  607. return edx;
  608. }
  609. /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
  610. static inline void rep_nop(void)
  611. {
  612. asm volatile("rep; nop" ::: "memory");
  613. }
  614. static inline void cpu_relax(void)
  615. {
  616. rep_nop();
  617. }
  618. /* Stop speculative execution: */
  619. static inline void sync_core(void)
  620. {
  621. int tmp;
  622. asm volatile("cpuid" : "=a" (tmp) : "0" (1)
  623. : "ebx", "ecx", "edx", "memory");
  624. }
  625. static inline void __monitor(const void *eax, unsigned long ecx,
  626. unsigned long edx)
  627. {
  628. /* "monitor %eax, %ecx, %edx;" */
  629. asm volatile(".byte 0x0f, 0x01, 0xc8;"
  630. :: "a" (eax), "c" (ecx), "d"(edx));
  631. }
  632. static inline void __mwait(unsigned long eax, unsigned long ecx)
  633. {
  634. /* "mwait %eax, %ecx;" */
  635. asm volatile(".byte 0x0f, 0x01, 0xc9;"
  636. :: "a" (eax), "c" (ecx));
  637. }
  638. static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
  639. {
  640. trace_hardirqs_on();
  641. /* "mwait %eax, %ecx;" */
  642. asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
  643. :: "a" (eax), "c" (ecx));
  644. }
  645. extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
  646. extern void select_idle_routine(const struct cpuinfo_x86 *c);
  647. extern void init_c1e_mask(void);
  648. extern unsigned long boot_option_idle_override;
  649. extern unsigned long idle_halt;
  650. extern unsigned long idle_nomwait;
  651. /*
  652. * on systems with caches, caches must be flashed as the absolute
  653. * last instruction before going into a suspended halt. Otherwise,
  654. * dirty data can linger in the cache and become stale on resume,
  655. * leading to strange errors.
  656. *
  657. * perform a variety of operations to guarantee that the compiler
  658. * will not reorder instructions. wbinvd itself is serializing
  659. * so the processor will not reorder.
  660. *
  661. * Systems without cache can just go into halt.
  662. */
  663. static inline void wbinvd_halt(void)
  664. {
  665. mb();
  666. /* check for clflush to determine if wbinvd is legal */
  667. if (cpu_has_clflush)
  668. asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
  669. else
  670. while (1)
  671. halt();
  672. }
  673. extern void enable_sep_cpu(void);
  674. extern int sysenter_setup(void);
  675. /* Defined in head.S */
  676. extern struct desc_ptr early_gdt_descr;
  677. extern void cpu_set_gdt(int);
  678. extern void switch_to_new_gdt(int);
  679. extern void load_percpu_segment(int);
  680. extern void cpu_init(void);
  681. static inline unsigned long get_debugctlmsr(void)
  682. {
  683. unsigned long debugctlmsr = 0;
  684. #ifndef CONFIG_X86_DEBUGCTLMSR
  685. if (boot_cpu_data.x86 < 6)
  686. return 0;
  687. #endif
  688. rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
  689. return debugctlmsr;
  690. }
  691. static inline void update_debugctlmsr(unsigned long debugctlmsr)
  692. {
  693. #ifndef CONFIG_X86_DEBUGCTLMSR
  694. if (boot_cpu_data.x86 < 6)
  695. return;
  696. #endif
  697. wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
  698. }
  699. /*
  700. * from system description table in BIOS. Mostly for MCA use, but
  701. * others may find it useful:
  702. */
  703. extern unsigned int machine_id;
  704. extern unsigned int machine_submodel_id;
  705. extern unsigned int BIOS_revision;
  706. /* Boot loader type from the setup header: */
  707. extern int bootloader_type;
  708. extern char ignore_fpu_irq;
  709. #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  710. #define ARCH_HAS_PREFETCHW
  711. #define ARCH_HAS_SPINLOCK_PREFETCH
  712. #ifdef CONFIG_X86_32
  713. # define BASE_PREFETCH ASM_NOP4
  714. # define ARCH_HAS_PREFETCH
  715. #else
  716. # define BASE_PREFETCH "prefetcht0 (%1)"
  717. #endif
  718. /*
  719. * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
  720. *
  721. * It's not worth to care about 3dnow prefetches for the K6
  722. * because they are microcoded there and very slow.
  723. */
  724. static inline void prefetch(const void *x)
  725. {
  726. alternative_input(BASE_PREFETCH,
  727. "prefetchnta (%1)",
  728. X86_FEATURE_XMM,
  729. "r" (x));
  730. }
  731. /*
  732. * 3dnow prefetch to get an exclusive cache line.
  733. * Useful for spinlocks to avoid one state transition in the
  734. * cache coherency protocol:
  735. */
  736. static inline void prefetchw(const void *x)
  737. {
  738. alternative_input(BASE_PREFETCH,
  739. "prefetchw (%1)",
  740. X86_FEATURE_3DNOW,
  741. "r" (x));
  742. }
  743. static inline void spin_lock_prefetch(const void *x)
  744. {
  745. prefetchw(x);
  746. }
  747. #ifdef CONFIG_X86_32
  748. /*
  749. * User space process size: 3GB (default).
  750. */
  751. #define TASK_SIZE PAGE_OFFSET
  752. #define TASK_SIZE_MAX TASK_SIZE
  753. #define STACK_TOP TASK_SIZE
  754. #define STACK_TOP_MAX STACK_TOP
  755. #define INIT_THREAD { \
  756. .sp0 = sizeof(init_stack) + (long)&init_stack, \
  757. .vm86_info = NULL, \
  758. .sysenter_cs = __KERNEL_CS, \
  759. .io_bitmap_ptr = NULL, \
  760. }
  761. /*
  762. * Note that the .io_bitmap member must be extra-big. This is because
  763. * the CPU will access an additional byte beyond the end of the IO
  764. * permission bitmap. The extra byte must be all 1 bits, and must
  765. * be within the limit.
  766. */
  767. #define INIT_TSS { \
  768. .x86_tss = { \
  769. .sp0 = sizeof(init_stack) + (long)&init_stack, \
  770. .ss0 = __KERNEL_DS, \
  771. .ss1 = __KERNEL_CS, \
  772. .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
  773. }, \
  774. .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
  775. }
  776. extern unsigned long thread_saved_pc(struct task_struct *tsk);
  777. #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
  778. #define KSTK_TOP(info) \
  779. ({ \
  780. unsigned long *__ptr = (unsigned long *)(info); \
  781. (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
  782. })
  783. /*
  784. * The below -8 is to reserve 8 bytes on top of the ring0 stack.
  785. * This is necessary to guarantee that the entire "struct pt_regs"
  786. * is accessable even if the CPU haven't stored the SS/ESP registers
  787. * on the stack (interrupt gate does not save these registers
  788. * when switching to the same priv ring).
  789. * Therefore beware: accessing the ss/esp fields of the
  790. * "struct pt_regs" is possible, but they may contain the
  791. * completely wrong values.
  792. */
  793. #define task_pt_regs(task) \
  794. ({ \
  795. struct pt_regs *__regs__; \
  796. __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
  797. __regs__ - 1; \
  798. })
  799. #define KSTK_ESP(task) (task_pt_regs(task)->sp)
  800. #else
  801. /*
  802. * User space process size. 47bits minus one guard page.
  803. */
  804. #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
  805. /* This decides where the kernel will search for a free chunk of vm
  806. * space during mmap's.
  807. */
  808. #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
  809. 0xc0000000 : 0xFFFFe000)
  810. #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
  811. IA32_PAGE_OFFSET : TASK_SIZE_MAX)
  812. #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
  813. IA32_PAGE_OFFSET : TASK_SIZE_MAX)
  814. #define STACK_TOP TASK_SIZE
  815. #define STACK_TOP_MAX TASK_SIZE_MAX
  816. #define INIT_THREAD { \
  817. .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
  818. }
  819. #define INIT_TSS { \
  820. .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
  821. }
  822. /*
  823. * Return saved PC of a blocked thread.
  824. * What is this good for? it will be always the scheduler or ret_from_fork.
  825. */
  826. #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
  827. #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
  828. #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
  829. #endif /* CONFIG_X86_64 */
  830. extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
  831. unsigned long new_sp);
  832. /*
  833. * This decides where the kernel will search for a free chunk of vm
  834. * space during mmap's.
  835. */
  836. #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
  837. #define KSTK_EIP(task) (task_pt_regs(task)->ip)
  838. /* Get/set a process' ability to use the timestamp counter instruction */
  839. #define GET_TSC_CTL(adr) get_tsc_mode((adr))
  840. #define SET_TSC_CTL(val) set_tsc_mode((val))
  841. extern int get_tsc_mode(unsigned long adr);
  842. extern int set_tsc_mode(unsigned int val);
  843. #endif /* _ASM_X86_PROCESSOR_H */