pwm-tiecap.c 8.8 KB

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  1. /*
  2. * ECAP PWM driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/io.h>
  23. #include <linux/err.h>
  24. #include <linux/clk.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/pwm.h>
  27. #include <linux/of_device.h>
  28. #include "pwm-tipwmss.h"
  29. /* ECAP registers and bits definitions */
  30. #define CAP1 0x08
  31. #define CAP2 0x0C
  32. #define CAP3 0x10
  33. #define CAP4 0x14
  34. #define ECCTL2 0x2A
  35. #define ECCTL2_APWM_POL_LOW BIT(10)
  36. #define ECCTL2_APWM_MODE BIT(9)
  37. #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
  38. #define ECCTL2_TSCTR_FREERUN BIT(4)
  39. struct ecap_context {
  40. u32 cap3;
  41. u32 cap4;
  42. u16 ecctl2;
  43. };
  44. struct ecap_pwm_chip {
  45. struct pwm_chip chip;
  46. unsigned int clk_rate;
  47. void __iomem *mmio_base;
  48. struct ecap_context ctx;
  49. };
  50. static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
  51. {
  52. return container_of(chip, struct ecap_pwm_chip, chip);
  53. }
  54. /*
  55. * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
  56. * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
  57. */
  58. static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  59. int duty_ns, int period_ns)
  60. {
  61. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  62. unsigned long long c;
  63. unsigned long period_cycles, duty_cycles;
  64. unsigned int reg_val;
  65. if (period_ns > NSEC_PER_SEC)
  66. return -ERANGE;
  67. c = pc->clk_rate;
  68. c = c * period_ns;
  69. do_div(c, NSEC_PER_SEC);
  70. period_cycles = (unsigned long)c;
  71. if (period_cycles < 1) {
  72. period_cycles = 1;
  73. duty_cycles = 1;
  74. } else {
  75. c = pc->clk_rate;
  76. c = c * duty_ns;
  77. do_div(c, NSEC_PER_SEC);
  78. duty_cycles = (unsigned long)c;
  79. }
  80. pm_runtime_get_sync(pc->chip.dev);
  81. reg_val = readw(pc->mmio_base + ECCTL2);
  82. /* Configure APWM mode & disable sync option */
  83. reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
  84. writew(reg_val, pc->mmio_base + ECCTL2);
  85. if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
  86. /* Update active registers if not running */
  87. writel(duty_cycles, pc->mmio_base + CAP2);
  88. writel(period_cycles, pc->mmio_base + CAP1);
  89. } else {
  90. /*
  91. * Update shadow registers to configure period and
  92. * compare values. This helps current PWM period to
  93. * complete on reconfiguring
  94. */
  95. writel(duty_cycles, pc->mmio_base + CAP4);
  96. writel(period_cycles, pc->mmio_base + CAP3);
  97. }
  98. if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
  99. reg_val = readw(pc->mmio_base + ECCTL2);
  100. /* Disable APWM mode to put APWM output Low */
  101. reg_val &= ~ECCTL2_APWM_MODE;
  102. writew(reg_val, pc->mmio_base + ECCTL2);
  103. }
  104. pm_runtime_put_sync(pc->chip.dev);
  105. return 0;
  106. }
  107. static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
  108. enum pwm_polarity polarity)
  109. {
  110. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  111. unsigned short reg_val;
  112. pm_runtime_get_sync(pc->chip.dev);
  113. reg_val = readw(pc->mmio_base + ECCTL2);
  114. if (polarity == PWM_POLARITY_INVERSED)
  115. /* Duty cycle defines LOW period of PWM */
  116. reg_val |= ECCTL2_APWM_POL_LOW;
  117. else
  118. /* Duty cycle defines HIGH period of PWM */
  119. reg_val &= ~ECCTL2_APWM_POL_LOW;
  120. writew(reg_val, pc->mmio_base + ECCTL2);
  121. pm_runtime_put_sync(pc->chip.dev);
  122. return 0;
  123. }
  124. static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  125. {
  126. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  127. unsigned int reg_val;
  128. /* Leave clock enabled on enabling PWM */
  129. pm_runtime_get_sync(pc->chip.dev);
  130. /*
  131. * Enable 'Free run Time stamp counter mode' to start counter
  132. * and 'APWM mode' to enable APWM output
  133. */
  134. reg_val = readw(pc->mmio_base + ECCTL2);
  135. reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
  136. writew(reg_val, pc->mmio_base + ECCTL2);
  137. return 0;
  138. }
  139. static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  140. {
  141. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  142. unsigned int reg_val;
  143. /*
  144. * Disable 'Free run Time stamp counter mode' to stop counter
  145. * and 'APWM mode' to put APWM output to low
  146. */
  147. reg_val = readw(pc->mmio_base + ECCTL2);
  148. reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
  149. writew(reg_val, pc->mmio_base + ECCTL2);
  150. /* Disable clock on PWM disable */
  151. pm_runtime_put_sync(pc->chip.dev);
  152. }
  153. static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  154. {
  155. if (test_bit(PWMF_ENABLED, &pwm->flags)) {
  156. dev_warn(chip->dev, "Removing PWM device without disabling\n");
  157. pm_runtime_put_sync(chip->dev);
  158. }
  159. }
  160. static const struct pwm_ops ecap_pwm_ops = {
  161. .free = ecap_pwm_free,
  162. .config = ecap_pwm_config,
  163. .set_polarity = ecap_pwm_set_polarity,
  164. .enable = ecap_pwm_enable,
  165. .disable = ecap_pwm_disable,
  166. .owner = THIS_MODULE,
  167. };
  168. static const struct of_device_id ecap_of_match[] = {
  169. { .compatible = "ti,am33xx-ecap" },
  170. {},
  171. };
  172. MODULE_DEVICE_TABLE(of, ecap_of_match);
  173. static int ecap_pwm_probe(struct platform_device *pdev)
  174. {
  175. int ret;
  176. struct resource *r;
  177. struct clk *clk;
  178. struct ecap_pwm_chip *pc;
  179. u16 status;
  180. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  181. if (!pc) {
  182. dev_err(&pdev->dev, "failed to allocate memory\n");
  183. return -ENOMEM;
  184. }
  185. clk = devm_clk_get(&pdev->dev, "fck");
  186. if (IS_ERR(clk)) {
  187. dev_err(&pdev->dev, "failed to get clock\n");
  188. return PTR_ERR(clk);
  189. }
  190. pc->clk_rate = clk_get_rate(clk);
  191. if (!pc->clk_rate) {
  192. dev_err(&pdev->dev, "failed to get clock rate\n");
  193. return -EINVAL;
  194. }
  195. pc->chip.dev = &pdev->dev;
  196. pc->chip.ops = &ecap_pwm_ops;
  197. pc->chip.of_xlate = of_pwm_xlate_with_flags;
  198. pc->chip.of_pwm_n_cells = 3;
  199. pc->chip.base = -1;
  200. pc->chip.npwm = 1;
  201. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  202. pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  203. if (IS_ERR(pc->mmio_base))
  204. return PTR_ERR(pc->mmio_base);
  205. ret = pwmchip_add(&pc->chip);
  206. if (ret < 0) {
  207. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  208. return ret;
  209. }
  210. pm_runtime_enable(&pdev->dev);
  211. pm_runtime_get_sync(&pdev->dev);
  212. status = pwmss_submodule_state_change(pdev->dev.parent,
  213. PWMSS_ECAPCLK_EN);
  214. if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
  215. dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
  216. ret = -EINVAL;
  217. goto pwmss_clk_failure;
  218. }
  219. pm_runtime_put_sync(&pdev->dev);
  220. platform_set_drvdata(pdev, pc);
  221. return 0;
  222. pwmss_clk_failure:
  223. pm_runtime_put_sync(&pdev->dev);
  224. pm_runtime_disable(&pdev->dev);
  225. pwmchip_remove(&pc->chip);
  226. return ret;
  227. }
  228. static int ecap_pwm_remove(struct platform_device *pdev)
  229. {
  230. struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
  231. pm_runtime_get_sync(&pdev->dev);
  232. /*
  233. * Due to hardware misbehaviour, acknowledge of the stop_req
  234. * is missing. Hence checking of the status bit skipped.
  235. */
  236. pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
  237. pm_runtime_put_sync(&pdev->dev);
  238. pm_runtime_put_sync(&pdev->dev);
  239. pm_runtime_disable(&pdev->dev);
  240. return pwmchip_remove(&pc->chip);
  241. }
  242. #ifdef CONFIG_PM_SLEEP
  243. static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
  244. {
  245. pm_runtime_get_sync(pc->chip.dev);
  246. pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
  247. pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
  248. pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
  249. pm_runtime_put_sync(pc->chip.dev);
  250. }
  251. static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
  252. {
  253. writel(pc->ctx.cap3, pc->mmio_base + CAP3);
  254. writel(pc->ctx.cap4, pc->mmio_base + CAP4);
  255. writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
  256. }
  257. static int ecap_pwm_suspend(struct device *dev)
  258. {
  259. struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
  260. struct pwm_device *pwm = pc->chip.pwms;
  261. ecap_pwm_save_context(pc);
  262. /* Disable explicitly if PWM is running */
  263. if (test_bit(PWMF_ENABLED, &pwm->flags))
  264. pm_runtime_put_sync(dev);
  265. return 0;
  266. }
  267. static int ecap_pwm_resume(struct device *dev)
  268. {
  269. struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
  270. struct pwm_device *pwm = pc->chip.pwms;
  271. /* Enable explicitly if PWM was running */
  272. if (test_bit(PWMF_ENABLED, &pwm->flags))
  273. pm_runtime_get_sync(dev);
  274. ecap_pwm_restore_context(pc);
  275. return 0;
  276. }
  277. #endif
  278. static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
  279. static struct platform_driver ecap_pwm_driver = {
  280. .driver = {
  281. .name = "ecap",
  282. .owner = THIS_MODULE,
  283. .of_match_table = ecap_of_match,
  284. .pm = &ecap_pwm_pm_ops,
  285. },
  286. .probe = ecap_pwm_probe,
  287. .remove = ecap_pwm_remove,
  288. };
  289. module_platform_driver(ecap_pwm_driver);
  290. MODULE_DESCRIPTION("ECAP PWM driver");
  291. MODULE_AUTHOR("Texas Instruments");
  292. MODULE_LICENSE("GPL");