smpboot.c 34 KB

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  1. /*
  2. * x86 SMP booting functions
  3. *
  4. * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  5. * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
  6. * Copyright 2001 Andi Kleen, SuSE Labs.
  7. *
  8. * Much of the core SMP work is based on previous work by Thomas Radke, to
  9. * whom a great many thanks are extended.
  10. *
  11. * Thanks to Intel for making available several different Pentium,
  12. * Pentium Pro and Pentium-II/Xeon MP machines.
  13. * Original development of Linux SMP code supported by Caldera.
  14. *
  15. * This code is released under the GNU General Public License version 2 or
  16. * later.
  17. *
  18. * Fixes
  19. * Felix Koop : NR_CPUS used properly
  20. * Jose Renau : Handle single CPU case.
  21. * Alan Cox : By repeated request 8) - Total BogoMIPS report.
  22. * Greg Wright : Fix for kernel stacks panic.
  23. * Erich Boleyn : MP v1.4 and additional changes.
  24. * Matthias Sattler : Changes for 2.1 kernel map.
  25. * Michel Lespinasse : Changes for 2.1 kernel map.
  26. * Michael Chastain : Change trampoline.S to gnu as.
  27. * Alan Cox : Dumb bug: 'B' step PPro's are fine
  28. * Ingo Molnar : Added APIC timers, based on code
  29. * from Jose Renau
  30. * Ingo Molnar : various cleanups and rewrites
  31. * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
  32. * Maciej W. Rozycki : Bits for genuine 82489DX APICs
  33. * Andi Kleen : Changed for SMP boot into long mode.
  34. * Martin J. Bligh : Added support for multi-quad systems
  35. * Dave Jones : Report invalid combinations of Athlon CPUs.
  36. * Rusty Russell : Hacked into shape for new "hotplug" boot process.
  37. * Andi Kleen : Converted to new state machine.
  38. * Ashok Raj : CPU hotplug support
  39. * Glauber Costa : i386 and x86_64 integration
  40. */
  41. #include <linux/init.h>
  42. #include <linux/smp.h>
  43. #include <linux/module.h>
  44. #include <linux/sched.h>
  45. #include <linux/percpu.h>
  46. #include <linux/bootmem.h>
  47. #include <linux/err.h>
  48. #include <linux/nmi.h>
  49. #include <asm/acpi.h>
  50. #include <asm/desc.h>
  51. #include <asm/nmi.h>
  52. #include <asm/irq.h>
  53. #include <asm/smp.h>
  54. #include <asm/trampoline.h>
  55. #include <asm/cpu.h>
  56. #include <asm/numa.h>
  57. #include <asm/pgtable.h>
  58. #include <asm/tlbflush.h>
  59. #include <asm/mtrr.h>
  60. #include <asm/vmi.h>
  61. #include <asm/genapic.h>
  62. #include <linux/mc146818rtc.h>
  63. #include <mach_apic.h>
  64. #include <mach_wakecpu.h>
  65. #include <smpboot_hooks.h>
  66. #ifdef CONFIG_X86_32
  67. u8 apicid_2_node[MAX_APICID];
  68. static int low_mappings;
  69. #endif
  70. /* State of each CPU */
  71. DEFINE_PER_CPU(int, cpu_state) = { 0 };
  72. /* Store all idle threads, this can be reused instead of creating
  73. * a new thread. Also avoids complicated thread destroy functionality
  74. * for idle threads.
  75. */
  76. #ifdef CONFIG_HOTPLUG_CPU
  77. /*
  78. * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
  79. * removed after init for !CONFIG_HOTPLUG_CPU.
  80. */
  81. static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
  82. #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
  83. #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
  84. #else
  85. struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
  86. #define get_idle_for_cpu(x) (idle_thread_array[(x)])
  87. #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
  88. #endif
  89. /* Number of siblings per CPU package */
  90. int smp_num_siblings = 1;
  91. EXPORT_SYMBOL(smp_num_siblings);
  92. /* Last level cache ID of each logical CPU */
  93. DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
  94. /* bitmap of online cpus */
  95. cpumask_t cpu_online_map __read_mostly;
  96. EXPORT_SYMBOL(cpu_online_map);
  97. cpumask_t cpu_callin_map;
  98. cpumask_t cpu_callout_map;
  99. cpumask_t cpu_possible_map;
  100. EXPORT_SYMBOL(cpu_possible_map);
  101. /* representing HT siblings of each logical CPU */
  102. DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
  103. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  104. /* representing HT and core siblings of each logical CPU */
  105. DEFINE_PER_CPU(cpumask_t, cpu_core_map);
  106. EXPORT_PER_CPU_SYMBOL(cpu_core_map);
  107. /* Per CPU bogomips and other parameters */
  108. DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
  109. EXPORT_PER_CPU_SYMBOL(cpu_info);
  110. static atomic_t init_deasserted;
  111. static int boot_cpu_logical_apicid;
  112. /* representing cpus for which sibling maps can be computed */
  113. static cpumask_t cpu_sibling_setup_map;
  114. /* Set if we find a B stepping CPU */
  115. int __cpuinitdata smp_b_stepping;
  116. #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
  117. /* which logical CPUs are on which nodes */
  118. cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
  119. { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
  120. EXPORT_SYMBOL(node_to_cpumask_map);
  121. /* which node each logical CPU is on */
  122. int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
  123. EXPORT_SYMBOL(cpu_to_node_map);
  124. /* set up a mapping between cpu and node. */
  125. static void map_cpu_to_node(int cpu, int node)
  126. {
  127. printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
  128. cpu_set(cpu, node_to_cpumask_map[node]);
  129. cpu_to_node_map[cpu] = node;
  130. }
  131. /* undo a mapping between cpu and node. */
  132. static void unmap_cpu_to_node(int cpu)
  133. {
  134. int node;
  135. printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
  136. for (node = 0; node < MAX_NUMNODES; node++)
  137. cpu_clear(cpu, node_to_cpumask_map[node]);
  138. cpu_to_node_map[cpu] = 0;
  139. }
  140. #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
  141. #define map_cpu_to_node(cpu, node) ({})
  142. #define unmap_cpu_to_node(cpu) ({})
  143. #endif
  144. #ifdef CONFIG_X86_32
  145. u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
  146. { [0 ... NR_CPUS-1] = BAD_APICID };
  147. static void map_cpu_to_logical_apicid(void)
  148. {
  149. int cpu = smp_processor_id();
  150. int apicid = logical_smp_processor_id();
  151. int node = apicid_to_node(apicid);
  152. if (!node_online(node))
  153. node = first_online_node;
  154. cpu_2_logical_apicid[cpu] = apicid;
  155. map_cpu_to_node(cpu, node);
  156. }
  157. void numa_remove_cpu(int cpu)
  158. {
  159. cpu_2_logical_apicid[cpu] = BAD_APICID;
  160. unmap_cpu_to_node(cpu);
  161. }
  162. #else
  163. #define map_cpu_to_logical_apicid() do {} while (0)
  164. #endif
  165. /*
  166. * Report back to the Boot Processor.
  167. * Running on AP.
  168. */
  169. static void __cpuinit smp_callin(void)
  170. {
  171. int cpuid, phys_id;
  172. unsigned long timeout;
  173. /*
  174. * If waken up by an INIT in an 82489DX configuration
  175. * we may get here before an INIT-deassert IPI reaches
  176. * our local APIC. We have to wait for the IPI or we'll
  177. * lock up on an APIC access.
  178. */
  179. wait_for_init_deassert(&init_deasserted);
  180. /*
  181. * (This works even if the APIC is not enabled.)
  182. */
  183. phys_id = GET_APIC_ID(read_apic_id());
  184. cpuid = smp_processor_id();
  185. if (cpu_isset(cpuid, cpu_callin_map)) {
  186. panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
  187. phys_id, cpuid);
  188. }
  189. pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
  190. /*
  191. * STARTUP IPIs are fragile beasts as they might sometimes
  192. * trigger some glue motherboard logic. Complete APIC bus
  193. * silence for 1 second, this overestimates the time the
  194. * boot CPU is spending to send the up to 2 STARTUP IPIs
  195. * by a factor of two. This should be enough.
  196. */
  197. /*
  198. * Waiting 2s total for startup (udelay is not yet working)
  199. */
  200. timeout = jiffies + 2*HZ;
  201. while (time_before(jiffies, timeout)) {
  202. /*
  203. * Has the boot CPU finished it's STARTUP sequence?
  204. */
  205. if (cpu_isset(cpuid, cpu_callout_map))
  206. break;
  207. cpu_relax();
  208. }
  209. if (!time_before(jiffies, timeout)) {
  210. panic("%s: CPU%d started up but did not get a callout!\n",
  211. __func__, cpuid);
  212. }
  213. /*
  214. * the boot CPU has finished the init stage and is spinning
  215. * on callin_map until we finish. We are free to set up this
  216. * CPU, first the APIC. (this is probably redundant on most
  217. * boards)
  218. */
  219. pr_debug("CALLIN, before setup_local_APIC().\n");
  220. smp_callin_clear_local_apic();
  221. setup_local_APIC();
  222. end_local_APIC_setup();
  223. map_cpu_to_logical_apicid();
  224. /*
  225. * Get our bogomips.
  226. *
  227. * Need to enable IRQs because it can take longer and then
  228. * the NMI watchdog might kill us.
  229. */
  230. local_irq_enable();
  231. calibrate_delay();
  232. local_irq_disable();
  233. pr_debug("Stack at about %p\n", &cpuid);
  234. /*
  235. * Save our processor parameters
  236. */
  237. smp_store_cpu_info(cpuid);
  238. /*
  239. * Allow the master to continue.
  240. */
  241. cpu_set(cpuid, cpu_callin_map);
  242. }
  243. /*
  244. * Activate a secondary processor.
  245. */
  246. static void __cpuinit start_secondary(void *unused)
  247. {
  248. /*
  249. * Don't put *anything* before cpu_init(), SMP booting is too
  250. * fragile that we want to limit the things done here to the
  251. * most necessary things.
  252. */
  253. #ifdef CONFIG_VMI
  254. vmi_bringup();
  255. #endif
  256. cpu_init();
  257. preempt_disable();
  258. smp_callin();
  259. /* otherwise gcc will move up smp_processor_id before the cpu_init */
  260. barrier();
  261. /*
  262. * Check TSC synchronization with the BP:
  263. */
  264. check_tsc_sync_target();
  265. if (nmi_watchdog == NMI_IO_APIC) {
  266. disable_8259A_irq(0);
  267. enable_NMI_through_LVT0();
  268. enable_8259A_irq(0);
  269. }
  270. #ifdef CONFIG_X86_32
  271. while (low_mappings)
  272. cpu_relax();
  273. __flush_tlb_all();
  274. #endif
  275. /* This must be done before setting cpu_online_map */
  276. set_cpu_sibling_map(raw_smp_processor_id());
  277. wmb();
  278. /*
  279. * We need to hold call_lock, so there is no inconsistency
  280. * between the time smp_call_function() determines number of
  281. * IPI recipients, and the time when the determination is made
  282. * for which cpus receive the IPI. Holding this
  283. * lock helps us to not include this cpu in a currently in progress
  284. * smp_call_function().
  285. */
  286. ipi_call_lock_irq();
  287. #ifdef CONFIG_X86_IO_APIC
  288. setup_vector_irq(smp_processor_id());
  289. #endif
  290. cpu_set(smp_processor_id(), cpu_online_map);
  291. ipi_call_unlock_irq();
  292. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  293. setup_secondary_clock();
  294. wmb();
  295. cpu_idle();
  296. }
  297. static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
  298. {
  299. /*
  300. * Mask B, Pentium, but not Pentium MMX
  301. */
  302. if (c->x86_vendor == X86_VENDOR_INTEL &&
  303. c->x86 == 5 &&
  304. c->x86_mask >= 1 && c->x86_mask <= 4 &&
  305. c->x86_model <= 3)
  306. /*
  307. * Remember we have B step Pentia with bugs
  308. */
  309. smp_b_stepping = 1;
  310. /*
  311. * Certain Athlons might work (for various values of 'work') in SMP
  312. * but they are not certified as MP capable.
  313. */
  314. if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
  315. if (num_possible_cpus() == 1)
  316. goto valid_k7;
  317. /* Athlon 660/661 is valid. */
  318. if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
  319. (c->x86_mask == 1)))
  320. goto valid_k7;
  321. /* Duron 670 is valid */
  322. if ((c->x86_model == 7) && (c->x86_mask == 0))
  323. goto valid_k7;
  324. /*
  325. * Athlon 662, Duron 671, and Athlon >model 7 have capability
  326. * bit. It's worth noting that the A5 stepping (662) of some
  327. * Athlon XP's have the MP bit set.
  328. * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
  329. * more.
  330. */
  331. if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
  332. ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
  333. (c->x86_model > 7))
  334. if (cpu_has_mp)
  335. goto valid_k7;
  336. /* If we get here, not a certified SMP capable AMD system. */
  337. add_taint(TAINT_UNSAFE_SMP);
  338. }
  339. valid_k7:
  340. ;
  341. }
  342. static void __cpuinit smp_checks(void)
  343. {
  344. if (smp_b_stepping)
  345. printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
  346. "with B stepping processors.\n");
  347. /*
  348. * Don't taint if we are running SMP kernel on a single non-MP
  349. * approved Athlon
  350. */
  351. if (tainted & TAINT_UNSAFE_SMP) {
  352. if (num_online_cpus())
  353. printk(KERN_INFO "WARNING: This combination of AMD"
  354. "processors is not suitable for SMP.\n");
  355. else
  356. tainted &= ~TAINT_UNSAFE_SMP;
  357. }
  358. }
  359. /*
  360. * The bootstrap kernel entry code has set these up. Save them for
  361. * a given CPU
  362. */
  363. void __cpuinit smp_store_cpu_info(int id)
  364. {
  365. struct cpuinfo_x86 *c = &cpu_data(id);
  366. *c = boot_cpu_data;
  367. c->cpu_index = id;
  368. if (id != 0)
  369. identify_secondary_cpu(c);
  370. smp_apply_quirks(c);
  371. }
  372. void __cpuinit set_cpu_sibling_map(int cpu)
  373. {
  374. int i;
  375. struct cpuinfo_x86 *c = &cpu_data(cpu);
  376. cpu_set(cpu, cpu_sibling_setup_map);
  377. if (smp_num_siblings > 1) {
  378. for_each_cpu_mask_nr(i, cpu_sibling_setup_map) {
  379. if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
  380. c->cpu_core_id == cpu_data(i).cpu_core_id) {
  381. cpu_set(i, per_cpu(cpu_sibling_map, cpu));
  382. cpu_set(cpu, per_cpu(cpu_sibling_map, i));
  383. cpu_set(i, per_cpu(cpu_core_map, cpu));
  384. cpu_set(cpu, per_cpu(cpu_core_map, i));
  385. cpu_set(i, c->llc_shared_map);
  386. cpu_set(cpu, cpu_data(i).llc_shared_map);
  387. }
  388. }
  389. } else {
  390. cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
  391. }
  392. cpu_set(cpu, c->llc_shared_map);
  393. if (current_cpu_data.x86_max_cores == 1) {
  394. per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
  395. c->booted_cores = 1;
  396. return;
  397. }
  398. for_each_cpu_mask_nr(i, cpu_sibling_setup_map) {
  399. if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
  400. per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
  401. cpu_set(i, c->llc_shared_map);
  402. cpu_set(cpu, cpu_data(i).llc_shared_map);
  403. }
  404. if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
  405. cpu_set(i, per_cpu(cpu_core_map, cpu));
  406. cpu_set(cpu, per_cpu(cpu_core_map, i));
  407. /*
  408. * Does this new cpu bringup a new core?
  409. */
  410. if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
  411. /*
  412. * for each core in package, increment
  413. * the booted_cores for this new cpu
  414. */
  415. if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
  416. c->booted_cores++;
  417. /*
  418. * increment the core count for all
  419. * the other cpus in this package
  420. */
  421. if (i != cpu)
  422. cpu_data(i).booted_cores++;
  423. } else if (i != cpu && !c->booted_cores)
  424. c->booted_cores = cpu_data(i).booted_cores;
  425. }
  426. }
  427. }
  428. /* maps the cpu to the sched domain representing multi-core */
  429. cpumask_t cpu_coregroup_map(int cpu)
  430. {
  431. struct cpuinfo_x86 *c = &cpu_data(cpu);
  432. /*
  433. * For perf, we return last level cache shared map.
  434. * And for power savings, we return cpu_core_map
  435. */
  436. if (sched_mc_power_savings || sched_smt_power_savings)
  437. return per_cpu(cpu_core_map, cpu);
  438. else
  439. return c->llc_shared_map;
  440. }
  441. static void impress_friends(void)
  442. {
  443. int cpu;
  444. unsigned long bogosum = 0;
  445. /*
  446. * Allow the user to impress friends.
  447. */
  448. pr_debug("Before bogomips.\n");
  449. for_each_possible_cpu(cpu)
  450. if (cpu_isset(cpu, cpu_callout_map))
  451. bogosum += cpu_data(cpu).loops_per_jiffy;
  452. printk(KERN_INFO
  453. "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  454. num_online_cpus(),
  455. bogosum/(500000/HZ),
  456. (bogosum/(5000/HZ))%100);
  457. pr_debug("Before bogocount - setting activated=1.\n");
  458. }
  459. static inline void __inquire_remote_apic(int apicid)
  460. {
  461. unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
  462. char *names[] = { "ID", "VERSION", "SPIV" };
  463. int timeout;
  464. u32 status;
  465. printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
  466. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  467. printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
  468. /*
  469. * Wait for idle.
  470. */
  471. status = safe_apic_wait_icr_idle();
  472. if (status)
  473. printk(KERN_CONT
  474. "a previous APIC delivery may have failed\n");
  475. apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
  476. apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]);
  477. timeout = 0;
  478. do {
  479. udelay(100);
  480. status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
  481. } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
  482. switch (status) {
  483. case APIC_ICR_RR_VALID:
  484. status = apic_read(APIC_RRR);
  485. printk(KERN_CONT "%08x\n", status);
  486. break;
  487. default:
  488. printk(KERN_CONT "failed\n");
  489. }
  490. }
  491. }
  492. #ifdef WAKE_SECONDARY_VIA_NMI
  493. /*
  494. * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
  495. * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
  496. * won't ... remember to clear down the APIC, etc later.
  497. */
  498. static int __devinit
  499. wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
  500. {
  501. unsigned long send_status, accept_status = 0;
  502. int maxlvt;
  503. /* Target chip */
  504. apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
  505. /* Boot on the stack */
  506. /* Kick the second */
  507. apic_write(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
  508. pr_debug("Waiting for send to finish...\n");
  509. send_status = safe_apic_wait_icr_idle();
  510. /*
  511. * Give the other CPU some time to accept the IPI.
  512. */
  513. udelay(200);
  514. maxlvt = lapic_get_maxlvt();
  515. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  516. apic_write(APIC_ESR, 0);
  517. accept_status = (apic_read(APIC_ESR) & 0xEF);
  518. pr_debug("NMI sent.\n");
  519. if (send_status)
  520. printk(KERN_ERR "APIC never delivered???\n");
  521. if (accept_status)
  522. printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
  523. return (send_status | accept_status);
  524. }
  525. #endif /* WAKE_SECONDARY_VIA_NMI */
  526. #ifdef WAKE_SECONDARY_VIA_INIT
  527. static int __devinit
  528. wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
  529. {
  530. unsigned long send_status, accept_status = 0;
  531. int maxlvt, num_starts, j;
  532. if (get_uv_system_type() == UV_NON_UNIQUE_APIC) {
  533. send_status = uv_wakeup_secondary(phys_apicid, start_eip);
  534. atomic_set(&init_deasserted, 1);
  535. return send_status;
  536. }
  537. maxlvt = lapic_get_maxlvt();
  538. /*
  539. * Be paranoid about clearing APIC errors.
  540. */
  541. if (APIC_INTEGRATED(apic_version[phys_apicid])) {
  542. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  543. apic_write(APIC_ESR, 0);
  544. apic_read(APIC_ESR);
  545. }
  546. pr_debug("Asserting INIT.\n");
  547. /*
  548. * Turn INIT on target chip
  549. */
  550. apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
  551. /*
  552. * Send IPI
  553. */
  554. apic_write(APIC_ICR,
  555. APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
  556. pr_debug("Waiting for send to finish...\n");
  557. send_status = safe_apic_wait_icr_idle();
  558. mdelay(10);
  559. pr_debug("Deasserting INIT.\n");
  560. /* Target chip */
  561. apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
  562. /* Send IPI */
  563. apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
  564. pr_debug("Waiting for send to finish...\n");
  565. send_status = safe_apic_wait_icr_idle();
  566. mb();
  567. atomic_set(&init_deasserted, 1);
  568. /*
  569. * Should we send STARTUP IPIs ?
  570. *
  571. * Determine this based on the APIC version.
  572. * If we don't have an integrated APIC, don't send the STARTUP IPIs.
  573. */
  574. if (APIC_INTEGRATED(apic_version[phys_apicid]))
  575. num_starts = 2;
  576. else
  577. num_starts = 0;
  578. /*
  579. * Paravirt / VMI wants a startup IPI hook here to set up the
  580. * target processor state.
  581. */
  582. startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
  583. (unsigned long)stack_start.sp);
  584. /*
  585. * Run STARTUP IPI loop.
  586. */
  587. pr_debug("#startup loops: %d.\n", num_starts);
  588. for (j = 1; j <= num_starts; j++) {
  589. pr_debug("Sending STARTUP #%d.\n", j);
  590. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  591. apic_write(APIC_ESR, 0);
  592. apic_read(APIC_ESR);
  593. pr_debug("After apic_write.\n");
  594. /*
  595. * STARTUP IPI
  596. */
  597. /* Target chip */
  598. apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
  599. /* Boot on the stack */
  600. /* Kick the second */
  601. apic_write(APIC_ICR, APIC_DM_STARTUP | (start_eip >> 12));
  602. /*
  603. * Give the other CPU some time to accept the IPI.
  604. */
  605. udelay(300);
  606. pr_debug("Startup point 1.\n");
  607. pr_debug("Waiting for send to finish...\n");
  608. send_status = safe_apic_wait_icr_idle();
  609. /*
  610. * Give the other CPU some time to accept the IPI.
  611. */
  612. udelay(200);
  613. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  614. apic_write(APIC_ESR, 0);
  615. accept_status = (apic_read(APIC_ESR) & 0xEF);
  616. if (send_status || accept_status)
  617. break;
  618. }
  619. pr_debug("After Startup.\n");
  620. if (send_status)
  621. printk(KERN_ERR "APIC never delivered???\n");
  622. if (accept_status)
  623. printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
  624. return (send_status | accept_status);
  625. }
  626. #endif /* WAKE_SECONDARY_VIA_INIT */
  627. struct create_idle {
  628. struct work_struct work;
  629. struct task_struct *idle;
  630. struct completion done;
  631. int cpu;
  632. };
  633. static void __cpuinit do_fork_idle(struct work_struct *work)
  634. {
  635. struct create_idle *c_idle =
  636. container_of(work, struct create_idle, work);
  637. c_idle->idle = fork_idle(c_idle->cpu);
  638. complete(&c_idle->done);
  639. }
  640. #ifdef CONFIG_X86_64
  641. /*
  642. * Allocate node local memory for the AP pda.
  643. *
  644. * Must be called after the _cpu_pda pointer table is initialized.
  645. */
  646. int __cpuinit get_local_pda(int cpu)
  647. {
  648. struct x8664_pda *oldpda, *newpda;
  649. unsigned long size = sizeof(struct x8664_pda);
  650. int node = cpu_to_node(cpu);
  651. if (cpu_pda(cpu) && !cpu_pda(cpu)->in_bootmem)
  652. return 0;
  653. oldpda = cpu_pda(cpu);
  654. newpda = kmalloc_node(size, GFP_ATOMIC, node);
  655. if (!newpda) {
  656. printk(KERN_ERR "Could not allocate node local PDA "
  657. "for CPU %d on node %d\n", cpu, node);
  658. if (oldpda)
  659. return 0; /* have a usable pda */
  660. else
  661. return -1;
  662. }
  663. if (oldpda) {
  664. memcpy(newpda, oldpda, size);
  665. if (!after_bootmem)
  666. free_bootmem((unsigned long)oldpda, size);
  667. }
  668. newpda->in_bootmem = 0;
  669. cpu_pda(cpu) = newpda;
  670. return 0;
  671. }
  672. #endif /* CONFIG_X86_64 */
  673. static int __cpuinit do_boot_cpu(int apicid, int cpu)
  674. /*
  675. * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
  676. * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
  677. * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
  678. */
  679. {
  680. unsigned long boot_error = 0;
  681. int timeout;
  682. unsigned long start_ip;
  683. unsigned short nmi_high = 0, nmi_low = 0;
  684. struct create_idle c_idle = {
  685. .cpu = cpu,
  686. .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
  687. };
  688. INIT_WORK(&c_idle.work, do_fork_idle);
  689. #ifdef CONFIG_X86_64
  690. /* Allocate node local memory for AP pdas */
  691. if (cpu > 0) {
  692. boot_error = get_local_pda(cpu);
  693. if (boot_error)
  694. goto restore_state;
  695. /* if can't get pda memory, can't start cpu */
  696. }
  697. #endif
  698. alternatives_smp_switch(1);
  699. c_idle.idle = get_idle_for_cpu(cpu);
  700. /*
  701. * We can't use kernel_thread since we must avoid to
  702. * reschedule the child.
  703. */
  704. if (c_idle.idle) {
  705. c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
  706. (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
  707. init_idle(c_idle.idle, cpu);
  708. goto do_rest;
  709. }
  710. if (!keventd_up() || current_is_keventd())
  711. c_idle.work.func(&c_idle.work);
  712. else {
  713. schedule_work(&c_idle.work);
  714. wait_for_completion(&c_idle.done);
  715. }
  716. if (IS_ERR(c_idle.idle)) {
  717. printk("failed fork for CPU %d\n", cpu);
  718. return PTR_ERR(c_idle.idle);
  719. }
  720. set_idle_for_cpu(cpu, c_idle.idle);
  721. do_rest:
  722. #ifdef CONFIG_X86_32
  723. per_cpu(current_task, cpu) = c_idle.idle;
  724. init_gdt(cpu);
  725. /* Stack for startup_32 can be just as for start_secondary onwards */
  726. irq_ctx_init(cpu);
  727. #else
  728. cpu_pda(cpu)->pcurrent = c_idle.idle;
  729. clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
  730. #endif
  731. early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
  732. initial_code = (unsigned long)start_secondary;
  733. stack_start.sp = (void *) c_idle.idle->thread.sp;
  734. /* start_ip had better be page-aligned! */
  735. start_ip = setup_trampoline();
  736. /* So we see what's up */
  737. printk(KERN_INFO "Booting processor %d/%d ip %lx\n",
  738. cpu, apicid, start_ip);
  739. /*
  740. * This grunge runs the startup process for
  741. * the targeted processor.
  742. */
  743. atomic_set(&init_deasserted, 0);
  744. if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
  745. pr_debug("Setting warm reset code and vector.\n");
  746. store_NMI_vector(&nmi_high, &nmi_low);
  747. smpboot_setup_warm_reset_vector(start_ip);
  748. /*
  749. * Be paranoid about clearing APIC errors.
  750. */
  751. apic_write(APIC_ESR, 0);
  752. apic_read(APIC_ESR);
  753. }
  754. /*
  755. * Starting actual IPI sequence...
  756. */
  757. boot_error = wakeup_secondary_cpu(apicid, start_ip);
  758. if (!boot_error) {
  759. /*
  760. * allow APs to start initializing.
  761. */
  762. pr_debug("Before Callout %d.\n", cpu);
  763. cpu_set(cpu, cpu_callout_map);
  764. pr_debug("After Callout %d.\n", cpu);
  765. /*
  766. * Wait 5s total for a response
  767. */
  768. for (timeout = 0; timeout < 50000; timeout++) {
  769. if (cpu_isset(cpu, cpu_callin_map))
  770. break; /* It has booted */
  771. udelay(100);
  772. }
  773. if (cpu_isset(cpu, cpu_callin_map)) {
  774. /* number CPUs logically, starting from 1 (BSP is 0) */
  775. pr_debug("OK.\n");
  776. printk(KERN_INFO "CPU%d: ", cpu);
  777. print_cpu_info(&cpu_data(cpu));
  778. pr_debug("CPU has booted.\n");
  779. } else {
  780. boot_error = 1;
  781. if (*((volatile unsigned char *)trampoline_base)
  782. == 0xA5)
  783. /* trampoline started but...? */
  784. printk(KERN_ERR "Stuck ??\n");
  785. else
  786. /* trampoline code not run */
  787. printk(KERN_ERR "Not responding.\n");
  788. if (get_uv_system_type() != UV_NON_UNIQUE_APIC)
  789. inquire_remote_apic(apicid);
  790. }
  791. }
  792. #ifdef CONFIG_X86_64
  793. restore_state:
  794. #endif
  795. if (boot_error) {
  796. /* Try to put things back the way they were before ... */
  797. numa_remove_cpu(cpu); /* was set by numa_add_cpu */
  798. cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */
  799. cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
  800. cpu_clear(cpu, cpu_present_map);
  801. per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
  802. }
  803. /* mark "stuck" area as not stuck */
  804. *((volatile unsigned long *)trampoline_base) = 0;
  805. /*
  806. * Cleanup possible dangling ends...
  807. */
  808. smpboot_restore_warm_reset_vector();
  809. return boot_error;
  810. }
  811. int __cpuinit native_cpu_up(unsigned int cpu)
  812. {
  813. int apicid = cpu_present_to_apicid(cpu);
  814. unsigned long flags;
  815. int err;
  816. WARN_ON(irqs_disabled());
  817. pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
  818. if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
  819. !physid_isset(apicid, phys_cpu_present_map)) {
  820. printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
  821. return -EINVAL;
  822. }
  823. /*
  824. * Already booted CPU?
  825. */
  826. if (cpu_isset(cpu, cpu_callin_map)) {
  827. pr_debug("do_boot_cpu %d Already started\n", cpu);
  828. return -ENOSYS;
  829. }
  830. /*
  831. * Save current MTRR state in case it was changed since early boot
  832. * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
  833. */
  834. mtrr_save_state();
  835. per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
  836. #ifdef CONFIG_X86_32
  837. /* init low mem mapping */
  838. clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY,
  839. min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
  840. flush_tlb_all();
  841. low_mappings = 1;
  842. err = do_boot_cpu(apicid, cpu);
  843. zap_low_mappings();
  844. low_mappings = 0;
  845. #else
  846. err = do_boot_cpu(apicid, cpu);
  847. #endif
  848. if (err) {
  849. pr_debug("do_boot_cpu failed %d\n", err);
  850. return -EIO;
  851. }
  852. /*
  853. * Check TSC synchronization with the AP (keep irqs disabled
  854. * while doing so):
  855. */
  856. local_irq_save(flags);
  857. check_tsc_sync_source(cpu);
  858. local_irq_restore(flags);
  859. while (!cpu_online(cpu)) {
  860. cpu_relax();
  861. touch_nmi_watchdog();
  862. }
  863. return 0;
  864. }
  865. /*
  866. * Fall back to non SMP mode after errors.
  867. *
  868. * RED-PEN audit/test this more. I bet there is more state messed up here.
  869. */
  870. static __init void disable_smp(void)
  871. {
  872. cpu_present_map = cpumask_of_cpu(0);
  873. cpu_possible_map = cpumask_of_cpu(0);
  874. smpboot_clear_io_apic_irqs();
  875. if (smp_found_config)
  876. physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
  877. else
  878. physid_set_mask_of_physid(0, &phys_cpu_present_map);
  879. map_cpu_to_logical_apicid();
  880. cpu_set(0, per_cpu(cpu_sibling_map, 0));
  881. cpu_set(0, per_cpu(cpu_core_map, 0));
  882. }
  883. /*
  884. * Various sanity checks.
  885. */
  886. static int __init smp_sanity_check(unsigned max_cpus)
  887. {
  888. preempt_disable();
  889. if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
  890. printk(KERN_WARNING "weird, boot CPU (#%d) not listed"
  891. "by the BIOS.\n", hard_smp_processor_id());
  892. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  893. }
  894. /*
  895. * If we couldn't find an SMP configuration at boot time,
  896. * get out of here now!
  897. */
  898. if (!smp_found_config && !acpi_lapic) {
  899. preempt_enable();
  900. printk(KERN_NOTICE "SMP motherboard not detected.\n");
  901. disable_smp();
  902. if (APIC_init_uniprocessor())
  903. printk(KERN_NOTICE "Local APIC not detected."
  904. " Using dummy APIC emulation.\n");
  905. return -1;
  906. }
  907. /*
  908. * Should not be necessary because the MP table should list the boot
  909. * CPU too, but we do it for the sake of robustness anyway.
  910. */
  911. if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
  912. printk(KERN_NOTICE
  913. "weird, boot CPU (#%d) not listed by the BIOS.\n",
  914. boot_cpu_physical_apicid);
  915. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  916. }
  917. preempt_enable();
  918. /*
  919. * If we couldn't find a local APIC, then get out of here now!
  920. */
  921. if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
  922. !cpu_has_apic) {
  923. printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
  924. boot_cpu_physical_apicid);
  925. printk(KERN_ERR "... forcing use of dummy APIC emulation."
  926. "(tell your hw vendor)\n");
  927. smpboot_clear_io_apic();
  928. return -1;
  929. }
  930. verify_local_APIC();
  931. /*
  932. * If SMP should be disabled, then really disable it!
  933. */
  934. if (!max_cpus) {
  935. printk(KERN_INFO "SMP mode deactivated.\n");
  936. smpboot_clear_io_apic();
  937. localise_nmi_watchdog();
  938. connect_bsp_APIC();
  939. setup_local_APIC();
  940. end_local_APIC_setup();
  941. return -1;
  942. }
  943. return 0;
  944. }
  945. static void __init smp_cpu_index_default(void)
  946. {
  947. int i;
  948. struct cpuinfo_x86 *c;
  949. for_each_possible_cpu(i) {
  950. c = &cpu_data(i);
  951. /* mark all to hotplug */
  952. c->cpu_index = NR_CPUS;
  953. }
  954. }
  955. /*
  956. * Prepare for SMP bootup. The MP table or ACPI has been read
  957. * earlier. Just do some sanity checking here and enable APIC mode.
  958. */
  959. void __init native_smp_prepare_cpus(unsigned int max_cpus)
  960. {
  961. preempt_disable();
  962. smp_cpu_index_default();
  963. current_cpu_data = boot_cpu_data;
  964. cpu_callin_map = cpumask_of_cpu(0);
  965. mb();
  966. /*
  967. * Setup boot CPU information
  968. */
  969. smp_store_cpu_info(0); /* Final full version of the data */
  970. boot_cpu_logical_apicid = logical_smp_processor_id();
  971. current_thread_info()->cpu = 0; /* needed? */
  972. set_cpu_sibling_map(0);
  973. if (smp_sanity_check(max_cpus) < 0) {
  974. printk(KERN_INFO "SMP disabled\n");
  975. disable_smp();
  976. goto out;
  977. }
  978. preempt_disable();
  979. if (GET_APIC_ID(read_apic_id()) != boot_cpu_physical_apicid) {
  980. panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
  981. GET_APIC_ID(read_apic_id()), boot_cpu_physical_apicid);
  982. /* Or can we switch back to PIC here? */
  983. }
  984. preempt_enable();
  985. connect_bsp_APIC();
  986. /*
  987. * Switch from PIC to APIC mode.
  988. */
  989. setup_local_APIC();
  990. #ifdef CONFIG_X86_64
  991. /*
  992. * Enable IO APIC before setting up error vector
  993. */
  994. if (!skip_ioapic_setup && nr_ioapics)
  995. enable_IO_APIC();
  996. #endif
  997. end_local_APIC_setup();
  998. map_cpu_to_logical_apicid();
  999. setup_portio_remap();
  1000. smpboot_setup_io_apic();
  1001. /*
  1002. * Set up local APIC timer on boot CPU.
  1003. */
  1004. printk(KERN_INFO "CPU%d: ", 0);
  1005. print_cpu_info(&cpu_data(0));
  1006. setup_boot_clock();
  1007. out:
  1008. preempt_enable();
  1009. }
  1010. /*
  1011. * Early setup to make printk work.
  1012. */
  1013. void __init native_smp_prepare_boot_cpu(void)
  1014. {
  1015. int me = smp_processor_id();
  1016. #ifdef CONFIG_X86_32
  1017. init_gdt(me);
  1018. #endif
  1019. switch_to_new_gdt();
  1020. /* already set me in cpu_online_map in boot_cpu_init() */
  1021. cpu_set(me, cpu_callout_map);
  1022. per_cpu(cpu_state, me) = CPU_ONLINE;
  1023. }
  1024. void __init native_smp_cpus_done(unsigned int max_cpus)
  1025. {
  1026. pr_debug("Boot done.\n");
  1027. impress_friends();
  1028. smp_checks();
  1029. #ifdef CONFIG_X86_IO_APIC
  1030. setup_ioapic_dest();
  1031. #endif
  1032. check_nmi_watchdog();
  1033. }
  1034. #ifdef CONFIG_HOTPLUG_CPU
  1035. static void remove_siblinginfo(int cpu)
  1036. {
  1037. int sibling;
  1038. struct cpuinfo_x86 *c = &cpu_data(cpu);
  1039. for_each_cpu_mask_nr(sibling, per_cpu(cpu_core_map, cpu)) {
  1040. cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
  1041. /*/
  1042. * last thread sibling in this cpu core going down
  1043. */
  1044. if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
  1045. cpu_data(sibling).booted_cores--;
  1046. }
  1047. for_each_cpu_mask_nr(sibling, per_cpu(cpu_sibling_map, cpu))
  1048. cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
  1049. cpus_clear(per_cpu(cpu_sibling_map, cpu));
  1050. cpus_clear(per_cpu(cpu_core_map, cpu));
  1051. c->phys_proc_id = 0;
  1052. c->cpu_core_id = 0;
  1053. cpu_clear(cpu, cpu_sibling_setup_map);
  1054. }
  1055. static int additional_cpus __initdata = -1;
  1056. static __init int setup_additional_cpus(char *s)
  1057. {
  1058. return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
  1059. }
  1060. early_param("additional_cpus", setup_additional_cpus);
  1061. /*
  1062. * cpu_possible_map should be static, it cannot change as cpu's
  1063. * are onlined, or offlined. The reason is per-cpu data-structures
  1064. * are allocated by some modules at init time, and dont expect to
  1065. * do this dynamically on cpu arrival/departure.
  1066. * cpu_present_map on the other hand can change dynamically.
  1067. * In case when cpu_hotplug is not compiled, then we resort to current
  1068. * behaviour, which is cpu_possible == cpu_present.
  1069. * - Ashok Raj
  1070. *
  1071. * Three ways to find out the number of additional hotplug CPUs:
  1072. * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
  1073. * - The user can overwrite it with additional_cpus=NUM
  1074. * - Otherwise don't reserve additional CPUs.
  1075. * We do this because additional CPUs waste a lot of memory.
  1076. * -AK
  1077. */
  1078. __init void prefill_possible_map(void)
  1079. {
  1080. int i;
  1081. int possible;
  1082. /* no processor from mptable or madt */
  1083. if (!num_processors)
  1084. num_processors = 1;
  1085. #ifdef CONFIG_HOTPLUG_CPU
  1086. if (additional_cpus == -1) {
  1087. if (disabled_cpus > 0)
  1088. additional_cpus = disabled_cpus;
  1089. else
  1090. additional_cpus = 0;
  1091. }
  1092. #else
  1093. additional_cpus = 0;
  1094. #endif
  1095. possible = num_processors + additional_cpus;
  1096. if (possible > NR_CPUS)
  1097. possible = NR_CPUS;
  1098. printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
  1099. possible, max_t(int, possible - num_processors, 0));
  1100. for (i = 0; i < possible; i++)
  1101. cpu_set(i, cpu_possible_map);
  1102. nr_cpu_ids = possible;
  1103. }
  1104. static void __ref remove_cpu_from_maps(int cpu)
  1105. {
  1106. cpu_clear(cpu, cpu_online_map);
  1107. cpu_clear(cpu, cpu_callout_map);
  1108. cpu_clear(cpu, cpu_callin_map);
  1109. /* was set by cpu_init() */
  1110. cpu_clear(cpu, cpu_initialized);
  1111. numa_remove_cpu(cpu);
  1112. }
  1113. int __cpu_disable(void)
  1114. {
  1115. int cpu = smp_processor_id();
  1116. /*
  1117. * Perhaps use cpufreq to drop frequency, but that could go
  1118. * into generic code.
  1119. *
  1120. * We won't take down the boot processor on i386 due to some
  1121. * interrupts only being able to be serviced by the BSP.
  1122. * Especially so if we're not using an IOAPIC -zwane
  1123. */
  1124. if (cpu == 0)
  1125. return -EBUSY;
  1126. if (nmi_watchdog == NMI_LOCAL_APIC)
  1127. stop_apic_nmi_watchdog(NULL);
  1128. clear_local_APIC();
  1129. /*
  1130. * HACK:
  1131. * Allow any queued timer interrupts to get serviced
  1132. * This is only a temporary solution until we cleanup
  1133. * fixup_irqs as we do for IA64.
  1134. */
  1135. local_irq_enable();
  1136. mdelay(1);
  1137. local_irq_disable();
  1138. remove_siblinginfo(cpu);
  1139. /* It's now safe to remove this processor from the online map */
  1140. remove_cpu_from_maps(cpu);
  1141. fixup_irqs(cpu_online_map);
  1142. return 0;
  1143. }
  1144. void __cpu_die(unsigned int cpu)
  1145. {
  1146. /* We don't do anything here: idle task is faking death itself. */
  1147. unsigned int i;
  1148. for (i = 0; i < 10; i++) {
  1149. /* They ack this in play_dead by setting CPU_DEAD */
  1150. if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
  1151. printk(KERN_INFO "CPU %d is now offline\n", cpu);
  1152. if (1 == num_online_cpus())
  1153. alternatives_smp_switch(0);
  1154. return;
  1155. }
  1156. msleep(100);
  1157. }
  1158. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  1159. }
  1160. #else /* ... !CONFIG_HOTPLUG_CPU */
  1161. int __cpu_disable(void)
  1162. {
  1163. return -ENOSYS;
  1164. }
  1165. void __cpu_die(unsigned int cpu)
  1166. {
  1167. /* We said "no" in __cpu_disable */
  1168. BUG();
  1169. }
  1170. #endif
  1171. /*
  1172. * If the BIOS enumerates physical processors before logical,
  1173. * maxcpus=N at enumeration-time can be used to disable HT.
  1174. */
  1175. static int __init parse_maxcpus(char *arg)
  1176. {
  1177. extern unsigned int maxcpus;
  1178. if (arg)
  1179. maxcpus = simple_strtoul(arg, NULL, 0);
  1180. return 0;
  1181. }
  1182. early_param("maxcpus", parse_maxcpus);