spi-rspi.c 19 KB

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  1. /*
  2. * SH RSPI driver
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * Based on spi-sh.c:
  7. * Copyright (C) 2011 Renesas Solutions Corp.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/sched.h>
  26. #include <linux/errno.h>
  27. #include <linux/list.h>
  28. #include <linux/workqueue.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/io.h>
  32. #include <linux/clk.h>
  33. #include <linux/dmaengine.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/sh_dma.h>
  36. #include <linux/spi/spi.h>
  37. #include <linux/spi/rspi.h>
  38. #define RSPI_SPCR 0x00
  39. #define RSPI_SSLP 0x01
  40. #define RSPI_SPPCR 0x02
  41. #define RSPI_SPSR 0x03
  42. #define RSPI_SPDR 0x04
  43. #define RSPI_SPSCR 0x08
  44. #define RSPI_SPSSR 0x09
  45. #define RSPI_SPBR 0x0a
  46. #define RSPI_SPDCR 0x0b
  47. #define RSPI_SPCKD 0x0c
  48. #define RSPI_SSLND 0x0d
  49. #define RSPI_SPND 0x0e
  50. #define RSPI_SPCR2 0x0f
  51. #define RSPI_SPCMD0 0x10
  52. #define RSPI_SPCMD1 0x12
  53. #define RSPI_SPCMD2 0x14
  54. #define RSPI_SPCMD3 0x16
  55. #define RSPI_SPCMD4 0x18
  56. #define RSPI_SPCMD5 0x1a
  57. #define RSPI_SPCMD6 0x1c
  58. #define RSPI_SPCMD7 0x1e
  59. /* SPCR */
  60. #define SPCR_SPRIE 0x80
  61. #define SPCR_SPE 0x40
  62. #define SPCR_SPTIE 0x20
  63. #define SPCR_SPEIE 0x10
  64. #define SPCR_MSTR 0x08
  65. #define SPCR_MODFEN 0x04
  66. #define SPCR_TXMD 0x02
  67. #define SPCR_SPMS 0x01
  68. /* SSLP */
  69. #define SSLP_SSL1P 0x02
  70. #define SSLP_SSL0P 0x01
  71. /* SPPCR */
  72. #define SPPCR_MOIFE 0x20
  73. #define SPPCR_MOIFV 0x10
  74. #define SPPCR_SPOM 0x04
  75. #define SPPCR_SPLP2 0x02
  76. #define SPPCR_SPLP 0x01
  77. /* SPSR */
  78. #define SPSR_SPRF 0x80
  79. #define SPSR_SPTEF 0x20
  80. #define SPSR_PERF 0x08
  81. #define SPSR_MODF 0x04
  82. #define SPSR_IDLNF 0x02
  83. #define SPSR_OVRF 0x01
  84. /* SPSCR */
  85. #define SPSCR_SPSLN_MASK 0x07
  86. /* SPSSR */
  87. #define SPSSR_SPECM_MASK 0x70
  88. #define SPSSR_SPCP_MASK 0x07
  89. /* SPDCR */
  90. #define SPDCR_SPLW 0x20
  91. #define SPDCR_SPRDTD 0x10
  92. #define SPDCR_SLSEL1 0x08
  93. #define SPDCR_SLSEL0 0x04
  94. #define SPDCR_SLSEL_MASK 0x0c
  95. #define SPDCR_SPFC1 0x02
  96. #define SPDCR_SPFC0 0x01
  97. /* SPCKD */
  98. #define SPCKD_SCKDL_MASK 0x07
  99. /* SSLND */
  100. #define SSLND_SLNDL_MASK 0x07
  101. /* SPND */
  102. #define SPND_SPNDL_MASK 0x07
  103. /* SPCR2 */
  104. #define SPCR2_PTE 0x08
  105. #define SPCR2_SPIE 0x04
  106. #define SPCR2_SPOE 0x02
  107. #define SPCR2_SPPE 0x01
  108. /* SPCMDn */
  109. #define SPCMD_SCKDEN 0x8000
  110. #define SPCMD_SLNDEN 0x4000
  111. #define SPCMD_SPNDEN 0x2000
  112. #define SPCMD_LSBF 0x1000
  113. #define SPCMD_SPB_MASK 0x0f00
  114. #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
  115. #define SPCMD_SPB_20BIT 0x0000
  116. #define SPCMD_SPB_24BIT 0x0100
  117. #define SPCMD_SPB_32BIT 0x0200
  118. #define SPCMD_SSLKP 0x0080
  119. #define SPCMD_SSLA_MASK 0x0030
  120. #define SPCMD_BRDV_MASK 0x000c
  121. #define SPCMD_CPOL 0x0002
  122. #define SPCMD_CPHA 0x0001
  123. struct rspi_data {
  124. void __iomem *addr;
  125. u32 max_speed_hz;
  126. struct spi_master *master;
  127. struct list_head queue;
  128. struct work_struct ws;
  129. wait_queue_head_t wait;
  130. spinlock_t lock;
  131. struct clk *clk;
  132. unsigned char spsr;
  133. /* for dmaengine */
  134. struct dma_chan *chan_tx;
  135. struct dma_chan *chan_rx;
  136. int irq;
  137. unsigned dma_width_16bit:1;
  138. unsigned dma_callbacked:1;
  139. };
  140. static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
  141. {
  142. iowrite8(data, rspi->addr + offset);
  143. }
  144. static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
  145. {
  146. iowrite16(data, rspi->addr + offset);
  147. }
  148. static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
  149. {
  150. return ioread8(rspi->addr + offset);
  151. }
  152. static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
  153. {
  154. return ioread16(rspi->addr + offset);
  155. }
  156. static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
  157. {
  158. int tmp;
  159. unsigned char spbr;
  160. tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
  161. spbr = clamp(tmp, 0, 255);
  162. return spbr;
  163. }
  164. static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
  165. {
  166. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
  167. }
  168. static void rspi_disable_irq(struct rspi_data *rspi, u8 disable)
  169. {
  170. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
  171. }
  172. static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
  173. u8 enable_bit)
  174. {
  175. int ret;
  176. rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
  177. rspi_enable_irq(rspi, enable_bit);
  178. ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
  179. if (ret == 0 && !(rspi->spsr & wait_mask))
  180. return -ETIMEDOUT;
  181. return 0;
  182. }
  183. static void rspi_assert_ssl(struct rspi_data *rspi)
  184. {
  185. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
  186. }
  187. static void rspi_negate_ssl(struct rspi_data *rspi)
  188. {
  189. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
  190. }
  191. static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
  192. {
  193. /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
  194. rspi_write8(rspi, 0x00, RSPI_SPPCR);
  195. /* Sets transfer bit rate */
  196. rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
  197. /* Sets number of frames to be used: 1 frame */
  198. rspi_write8(rspi, 0x00, RSPI_SPDCR);
  199. /* Sets RSPCK, SSL, next-access delay value */
  200. rspi_write8(rspi, 0x00, RSPI_SPCKD);
  201. rspi_write8(rspi, 0x00, RSPI_SSLND);
  202. rspi_write8(rspi, 0x00, RSPI_SPND);
  203. /* Sets parity, interrupt mask */
  204. rspi_write8(rspi, 0x00, RSPI_SPCR2);
  205. /* Sets SPCMD */
  206. rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
  207. RSPI_SPCMD0);
  208. /* Sets RSPI mode */
  209. rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
  210. return 0;
  211. }
  212. static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
  213. struct spi_transfer *t)
  214. {
  215. int remain = t->len;
  216. u8 *data;
  217. data = (u8 *)t->tx_buf;
  218. while (remain > 0) {
  219. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
  220. RSPI_SPCR);
  221. if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
  222. dev_err(&rspi->master->dev,
  223. "%s: tx empty timeout\n", __func__);
  224. return -ETIMEDOUT;
  225. }
  226. rspi_write16(rspi, *data, RSPI_SPDR);
  227. data++;
  228. remain--;
  229. }
  230. /* Waiting for the last transmition */
  231. rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
  232. return 0;
  233. }
  234. static void rspi_dma_complete(void *arg)
  235. {
  236. struct rspi_data *rspi = arg;
  237. rspi->dma_callbacked = 1;
  238. wake_up_interruptible(&rspi->wait);
  239. }
  240. static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len,
  241. struct dma_chan *chan,
  242. enum dma_transfer_direction dir)
  243. {
  244. sg_init_table(sg, 1);
  245. sg_set_buf(sg, buf, len);
  246. sg_dma_len(sg) = len;
  247. return dma_map_sg(chan->device->dev, sg, 1, dir);
  248. }
  249. static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan,
  250. enum dma_transfer_direction dir)
  251. {
  252. dma_unmap_sg(chan->device->dev, sg, 1, dir);
  253. }
  254. static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len)
  255. {
  256. u16 *dst = buf;
  257. const u8 *src = data;
  258. while (len) {
  259. *dst++ = (u16)(*src++);
  260. len--;
  261. }
  262. }
  263. static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
  264. {
  265. u8 *dst = buf;
  266. const u16 *src = data;
  267. while (len) {
  268. *dst++ = (u8)*src++;
  269. len--;
  270. }
  271. }
  272. static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
  273. {
  274. struct scatterlist sg;
  275. void *buf = NULL;
  276. struct dma_async_tx_descriptor *desc;
  277. unsigned len;
  278. int ret = 0;
  279. if (rspi->dma_width_16bit) {
  280. /*
  281. * If DMAC bus width is 16-bit, the driver allocates a dummy
  282. * buffer. And, the driver converts original data into the
  283. * DMAC data as the following format:
  284. * original data: 1st byte, 2nd byte ...
  285. * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
  286. */
  287. len = t->len * 2;
  288. buf = kmalloc(len, GFP_KERNEL);
  289. if (!buf)
  290. return -ENOMEM;
  291. rspi_memory_to_8bit(buf, t->tx_buf, t->len);
  292. } else {
  293. len = t->len;
  294. buf = (void *)t->tx_buf;
  295. }
  296. if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
  297. ret = -EFAULT;
  298. goto end_nomap;
  299. }
  300. desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
  301. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  302. if (!desc) {
  303. ret = -EIO;
  304. goto end;
  305. }
  306. /*
  307. * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
  308. * called. So, this driver disables the IRQ while DMA transfer.
  309. */
  310. disable_irq(rspi->irq);
  311. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
  312. rspi_enable_irq(rspi, SPCR_SPTIE);
  313. rspi->dma_callbacked = 0;
  314. desc->callback = rspi_dma_complete;
  315. desc->callback_param = rspi;
  316. dmaengine_submit(desc);
  317. dma_async_issue_pending(rspi->chan_tx);
  318. ret = wait_event_interruptible_timeout(rspi->wait,
  319. rspi->dma_callbacked, HZ);
  320. if (ret > 0 && rspi->dma_callbacked)
  321. ret = 0;
  322. else if (!ret)
  323. ret = -ETIMEDOUT;
  324. rspi_disable_irq(rspi, SPCR_SPTIE);
  325. enable_irq(rspi->irq);
  326. end:
  327. rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
  328. end_nomap:
  329. if (rspi->dma_width_16bit)
  330. kfree(buf);
  331. return ret;
  332. }
  333. static void rspi_receive_init(struct rspi_data *rspi)
  334. {
  335. unsigned char spsr;
  336. spsr = rspi_read8(rspi, RSPI_SPSR);
  337. if (spsr & SPSR_SPRF)
  338. rspi_read16(rspi, RSPI_SPDR); /* dummy read */
  339. if (spsr & SPSR_OVRF)
  340. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
  341. RSPI_SPCR);
  342. }
  343. static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
  344. struct spi_transfer *t)
  345. {
  346. int remain = t->len;
  347. u8 *data;
  348. rspi_receive_init(rspi);
  349. data = (u8 *)t->rx_buf;
  350. while (remain > 0) {
  351. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
  352. RSPI_SPCR);
  353. if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
  354. dev_err(&rspi->master->dev,
  355. "%s: tx empty timeout\n", __func__);
  356. return -ETIMEDOUT;
  357. }
  358. /* dummy write for generate clock */
  359. rspi_write16(rspi, 0x00, RSPI_SPDR);
  360. if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
  361. dev_err(&rspi->master->dev,
  362. "%s: receive timeout\n", __func__);
  363. return -ETIMEDOUT;
  364. }
  365. /* SPDR allows 16 or 32-bit access only */
  366. *data = (u8)rspi_read16(rspi, RSPI_SPDR);
  367. data++;
  368. remain--;
  369. }
  370. return 0;
  371. }
  372. static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
  373. {
  374. struct scatterlist sg, sg_dummy;
  375. void *dummy = NULL, *rx_buf = NULL;
  376. struct dma_async_tx_descriptor *desc, *desc_dummy;
  377. unsigned len;
  378. int ret = 0;
  379. if (rspi->dma_width_16bit) {
  380. /*
  381. * If DMAC bus width is 16-bit, the driver allocates a dummy
  382. * buffer. And, finally the driver converts the DMAC data into
  383. * actual data as the following format:
  384. * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
  385. * actual data: 1st byte, 2nd byte ...
  386. */
  387. len = t->len * 2;
  388. rx_buf = kmalloc(len, GFP_KERNEL);
  389. if (!rx_buf)
  390. return -ENOMEM;
  391. } else {
  392. len = t->len;
  393. rx_buf = t->rx_buf;
  394. }
  395. /* prepare dummy transfer to generate SPI clocks */
  396. dummy = kzalloc(len, GFP_KERNEL);
  397. if (!dummy) {
  398. ret = -ENOMEM;
  399. goto end_nomap;
  400. }
  401. if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx,
  402. DMA_TO_DEVICE)) {
  403. ret = -EFAULT;
  404. goto end_nomap;
  405. }
  406. desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1,
  407. DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  408. if (!desc_dummy) {
  409. ret = -EIO;
  410. goto end_dummy_mapped;
  411. }
  412. /* prepare receive transfer */
  413. if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx,
  414. DMA_FROM_DEVICE)) {
  415. ret = -EFAULT;
  416. goto end_dummy_mapped;
  417. }
  418. desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE,
  419. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  420. if (!desc) {
  421. ret = -EIO;
  422. goto end;
  423. }
  424. rspi_receive_init(rspi);
  425. /*
  426. * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
  427. * called. So, this driver disables the IRQ while DMA transfer.
  428. */
  429. disable_irq(rspi->irq);
  430. rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
  431. rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
  432. rspi->dma_callbacked = 0;
  433. desc->callback = rspi_dma_complete;
  434. desc->callback_param = rspi;
  435. dmaengine_submit(desc);
  436. dma_async_issue_pending(rspi->chan_rx);
  437. desc_dummy->callback = NULL; /* No callback */
  438. dmaengine_submit(desc_dummy);
  439. dma_async_issue_pending(rspi->chan_tx);
  440. ret = wait_event_interruptible_timeout(rspi->wait,
  441. rspi->dma_callbacked, HZ);
  442. if (ret > 0 && rspi->dma_callbacked)
  443. ret = 0;
  444. else if (!ret)
  445. ret = -ETIMEDOUT;
  446. rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
  447. enable_irq(rspi->irq);
  448. end:
  449. rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
  450. end_dummy_mapped:
  451. rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE);
  452. end_nomap:
  453. if (rspi->dma_width_16bit) {
  454. if (!ret)
  455. rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len);
  456. kfree(rx_buf);
  457. }
  458. kfree(dummy);
  459. return ret;
  460. }
  461. static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t)
  462. {
  463. if (t->tx_buf && rspi->chan_tx)
  464. return 1;
  465. /* If the module receives data by DMAC, it also needs TX DMAC */
  466. if (t->rx_buf && rspi->chan_tx && rspi->chan_rx)
  467. return 1;
  468. return 0;
  469. }
  470. static void rspi_work(struct work_struct *work)
  471. {
  472. struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
  473. struct spi_message *mesg;
  474. struct spi_transfer *t;
  475. unsigned long flags;
  476. int ret;
  477. while (1) {
  478. spin_lock_irqsave(&rspi->lock, flags);
  479. if (list_empty(&rspi->queue)) {
  480. spin_unlock_irqrestore(&rspi->lock, flags);
  481. break;
  482. }
  483. mesg = list_entry(rspi->queue.next, struct spi_message, queue);
  484. list_del_init(&mesg->queue);
  485. spin_unlock_irqrestore(&rspi->lock, flags);
  486. rspi_assert_ssl(rspi);
  487. list_for_each_entry(t, &mesg->transfers, transfer_list) {
  488. if (t->tx_buf) {
  489. if (rspi_is_dma(rspi, t))
  490. ret = rspi_send_dma(rspi, t);
  491. else
  492. ret = rspi_send_pio(rspi, mesg, t);
  493. if (ret < 0)
  494. goto error;
  495. }
  496. if (t->rx_buf) {
  497. if (rspi_is_dma(rspi, t))
  498. ret = rspi_receive_dma(rspi, t);
  499. else
  500. ret = rspi_receive_pio(rspi, mesg, t);
  501. if (ret < 0)
  502. goto error;
  503. }
  504. mesg->actual_length += t->len;
  505. }
  506. rspi_negate_ssl(rspi);
  507. mesg->status = 0;
  508. mesg->complete(mesg->context);
  509. }
  510. return;
  511. error:
  512. mesg->status = ret;
  513. mesg->complete(mesg->context);
  514. }
  515. static int rspi_setup(struct spi_device *spi)
  516. {
  517. struct rspi_data *rspi = spi_master_get_devdata(spi->master);
  518. if (!spi->bits_per_word)
  519. spi->bits_per_word = 8;
  520. rspi->max_speed_hz = spi->max_speed_hz;
  521. rspi_set_config_register(rspi, 8);
  522. return 0;
  523. }
  524. static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
  525. {
  526. struct rspi_data *rspi = spi_master_get_devdata(spi->master);
  527. unsigned long flags;
  528. mesg->actual_length = 0;
  529. mesg->status = -EINPROGRESS;
  530. spin_lock_irqsave(&rspi->lock, flags);
  531. list_add_tail(&mesg->queue, &rspi->queue);
  532. schedule_work(&rspi->ws);
  533. spin_unlock_irqrestore(&rspi->lock, flags);
  534. return 0;
  535. }
  536. static void rspi_cleanup(struct spi_device *spi)
  537. {
  538. }
  539. static irqreturn_t rspi_irq(int irq, void *_sr)
  540. {
  541. struct rspi_data *rspi = (struct rspi_data *)_sr;
  542. unsigned long spsr;
  543. irqreturn_t ret = IRQ_NONE;
  544. unsigned char disable_irq = 0;
  545. rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
  546. if (spsr & SPSR_SPRF)
  547. disable_irq |= SPCR_SPRIE;
  548. if (spsr & SPSR_SPTEF)
  549. disable_irq |= SPCR_SPTIE;
  550. if (disable_irq) {
  551. ret = IRQ_HANDLED;
  552. rspi_disable_irq(rspi, disable_irq);
  553. wake_up(&rspi->wait);
  554. }
  555. return ret;
  556. }
  557. static int rspi_request_dma(struct rspi_data *rspi,
  558. struct platform_device *pdev)
  559. {
  560. struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
  561. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  562. dma_cap_mask_t mask;
  563. struct dma_slave_config cfg;
  564. int ret;
  565. if (!res || !rspi_pd)
  566. return 0; /* The driver assumes no error. */
  567. rspi->dma_width_16bit = rspi_pd->dma_width_16bit;
  568. /* If the module receives data by DMAC, it also needs TX DMAC */
  569. if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) {
  570. dma_cap_zero(mask);
  571. dma_cap_set(DMA_SLAVE, mask);
  572. rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter,
  573. (void *)rspi_pd->dma_rx_id);
  574. if (rspi->chan_rx) {
  575. cfg.slave_id = rspi_pd->dma_rx_id;
  576. cfg.direction = DMA_DEV_TO_MEM;
  577. cfg.dst_addr = 0;
  578. cfg.src_addr = res->start + RSPI_SPDR;
  579. ret = dmaengine_slave_config(rspi->chan_rx, &cfg);
  580. if (!ret)
  581. dev_info(&pdev->dev, "Use DMA when rx.\n");
  582. else
  583. return ret;
  584. }
  585. }
  586. if (rspi_pd->dma_tx_id) {
  587. dma_cap_zero(mask);
  588. dma_cap_set(DMA_SLAVE, mask);
  589. rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter,
  590. (void *)rspi_pd->dma_tx_id);
  591. if (rspi->chan_tx) {
  592. cfg.slave_id = rspi_pd->dma_tx_id;
  593. cfg.direction = DMA_MEM_TO_DEV;
  594. cfg.dst_addr = res->start + RSPI_SPDR;
  595. cfg.src_addr = 0;
  596. ret = dmaengine_slave_config(rspi->chan_tx, &cfg);
  597. if (!ret)
  598. dev_info(&pdev->dev, "Use DMA when tx\n");
  599. else
  600. return ret;
  601. }
  602. }
  603. return 0;
  604. }
  605. static void rspi_release_dma(struct rspi_data *rspi)
  606. {
  607. if (rspi->chan_tx)
  608. dma_release_channel(rspi->chan_tx);
  609. if (rspi->chan_rx)
  610. dma_release_channel(rspi->chan_rx);
  611. }
  612. static int rspi_remove(struct platform_device *pdev)
  613. {
  614. struct rspi_data *rspi = spi_master_get(platform_get_drvdata(pdev));
  615. spi_unregister_master(rspi->master);
  616. rspi_release_dma(rspi);
  617. free_irq(platform_get_irq(pdev, 0), rspi);
  618. clk_put(rspi->clk);
  619. iounmap(rspi->addr);
  620. spi_master_put(rspi->master);
  621. return 0;
  622. }
  623. static int rspi_probe(struct platform_device *pdev)
  624. {
  625. struct resource *res;
  626. struct spi_master *master;
  627. struct rspi_data *rspi;
  628. int ret, irq;
  629. char clk_name[16];
  630. /* get base addr */
  631. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  632. if (unlikely(res == NULL)) {
  633. dev_err(&pdev->dev, "invalid resource\n");
  634. return -EINVAL;
  635. }
  636. irq = platform_get_irq(pdev, 0);
  637. if (irq < 0) {
  638. dev_err(&pdev->dev, "platform_get_irq error\n");
  639. return -ENODEV;
  640. }
  641. master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
  642. if (master == NULL) {
  643. dev_err(&pdev->dev, "spi_alloc_master error.\n");
  644. return -ENOMEM;
  645. }
  646. rspi = spi_master_get_devdata(master);
  647. platform_set_drvdata(pdev, rspi);
  648. rspi->master = master;
  649. rspi->addr = ioremap(res->start, resource_size(res));
  650. if (rspi->addr == NULL) {
  651. dev_err(&pdev->dev, "ioremap error.\n");
  652. ret = -ENOMEM;
  653. goto error1;
  654. }
  655. snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
  656. rspi->clk = clk_get(&pdev->dev, clk_name);
  657. if (IS_ERR(rspi->clk)) {
  658. dev_err(&pdev->dev, "cannot get clock\n");
  659. ret = PTR_ERR(rspi->clk);
  660. goto error2;
  661. }
  662. clk_enable(rspi->clk);
  663. INIT_LIST_HEAD(&rspi->queue);
  664. spin_lock_init(&rspi->lock);
  665. INIT_WORK(&rspi->ws, rspi_work);
  666. init_waitqueue_head(&rspi->wait);
  667. master->num_chipselect = 2;
  668. master->bus_num = pdev->id;
  669. master->setup = rspi_setup;
  670. master->transfer = rspi_transfer;
  671. master->cleanup = rspi_cleanup;
  672. ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
  673. if (ret < 0) {
  674. dev_err(&pdev->dev, "request_irq error\n");
  675. goto error3;
  676. }
  677. rspi->irq = irq;
  678. ret = rspi_request_dma(rspi, pdev);
  679. if (ret < 0) {
  680. dev_err(&pdev->dev, "rspi_request_dma failed.\n");
  681. goto error4;
  682. }
  683. ret = spi_register_master(master);
  684. if (ret < 0) {
  685. dev_err(&pdev->dev, "spi_register_master error.\n");
  686. goto error4;
  687. }
  688. dev_info(&pdev->dev, "probed\n");
  689. return 0;
  690. error4:
  691. rspi_release_dma(rspi);
  692. free_irq(irq, rspi);
  693. error3:
  694. clk_put(rspi->clk);
  695. error2:
  696. iounmap(rspi->addr);
  697. error1:
  698. spi_master_put(master);
  699. return ret;
  700. }
  701. static struct platform_driver rspi_driver = {
  702. .probe = rspi_probe,
  703. .remove = rspi_remove,
  704. .driver = {
  705. .name = "rspi",
  706. .owner = THIS_MODULE,
  707. },
  708. };
  709. module_platform_driver(rspi_driver);
  710. MODULE_DESCRIPTION("Renesas RSPI bus driver");
  711. MODULE_LICENSE("GPL v2");
  712. MODULE_AUTHOR("Yoshihiro Shimoda");
  713. MODULE_ALIAS("platform:rspi");