spi-nuc900.c 9.6 KB

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  1. /*
  2. * Copyright (c) 2009 Nuvoton technology.
  3. * Wan ZongShun <mcuos.com@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/gpio.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/spi/spi_bitbang.h>
  26. #include <linux/platform_data/spi-nuc900.h>
  27. /* usi registers offset */
  28. #define USI_CNT 0x00
  29. #define USI_DIV 0x04
  30. #define USI_SSR 0x08
  31. #define USI_RX0 0x10
  32. #define USI_TX0 0x10
  33. /* usi register bit */
  34. #define ENINT (0x01 << 17)
  35. #define ENFLG (0x01 << 16)
  36. #define TXNUM (0x03 << 8)
  37. #define TXNEG (0x01 << 2)
  38. #define RXNEG (0x01 << 1)
  39. #define LSB (0x01 << 10)
  40. #define SELECTLEV (0x01 << 2)
  41. #define SELECTPOL (0x01 << 31)
  42. #define SELECTSLAVE 0x01
  43. #define GOBUSY 0x01
  44. struct nuc900_spi {
  45. struct spi_bitbang bitbang;
  46. struct completion done;
  47. void __iomem *regs;
  48. int irq;
  49. int len;
  50. int count;
  51. const unsigned char *tx;
  52. unsigned char *rx;
  53. struct clk *clk;
  54. struct resource *ioarea;
  55. struct spi_master *master;
  56. struct spi_device *curdev;
  57. struct device *dev;
  58. struct nuc900_spi_info *pdata;
  59. spinlock_t lock;
  60. struct resource *res;
  61. };
  62. static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
  63. {
  64. return spi_master_get_devdata(sdev->master);
  65. }
  66. static void nuc900_slave_select(struct spi_device *spi, unsigned int ssr)
  67. {
  68. struct nuc900_spi *hw = to_hw(spi);
  69. unsigned int val;
  70. unsigned int cs = spi->mode & SPI_CS_HIGH ? 1 : 0;
  71. unsigned int cpol = spi->mode & SPI_CPOL ? 1 : 0;
  72. unsigned long flags;
  73. spin_lock_irqsave(&hw->lock, flags);
  74. val = __raw_readl(hw->regs + USI_SSR);
  75. if (!cs)
  76. val &= ~SELECTLEV;
  77. else
  78. val |= SELECTLEV;
  79. if (!ssr)
  80. val &= ~SELECTSLAVE;
  81. else
  82. val |= SELECTSLAVE;
  83. __raw_writel(val, hw->regs + USI_SSR);
  84. val = __raw_readl(hw->regs + USI_CNT);
  85. if (!cpol)
  86. val &= ~SELECTPOL;
  87. else
  88. val |= SELECTPOL;
  89. __raw_writel(val, hw->regs + USI_CNT);
  90. spin_unlock_irqrestore(&hw->lock, flags);
  91. }
  92. static void nuc900_spi_chipsel(struct spi_device *spi, int value)
  93. {
  94. switch (value) {
  95. case BITBANG_CS_INACTIVE:
  96. nuc900_slave_select(spi, 0);
  97. break;
  98. case BITBANG_CS_ACTIVE:
  99. nuc900_slave_select(spi, 1);
  100. break;
  101. }
  102. }
  103. static void nuc900_spi_setup_txnum(struct nuc900_spi *hw,
  104. unsigned int txnum)
  105. {
  106. unsigned int val;
  107. unsigned long flags;
  108. spin_lock_irqsave(&hw->lock, flags);
  109. val = __raw_readl(hw->regs + USI_CNT);
  110. if (!txnum)
  111. val &= ~TXNUM;
  112. else
  113. val |= txnum << 0x08;
  114. __raw_writel(val, hw->regs + USI_CNT);
  115. spin_unlock_irqrestore(&hw->lock, flags);
  116. }
  117. static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
  118. unsigned int txbitlen)
  119. {
  120. unsigned int val;
  121. unsigned long flags;
  122. spin_lock_irqsave(&hw->lock, flags);
  123. val = __raw_readl(hw->regs + USI_CNT);
  124. val |= (txbitlen << 0x03);
  125. __raw_writel(val, hw->regs + USI_CNT);
  126. spin_unlock_irqrestore(&hw->lock, flags);
  127. }
  128. static void nuc900_spi_gobusy(struct nuc900_spi *hw)
  129. {
  130. unsigned int val;
  131. unsigned long flags;
  132. spin_lock_irqsave(&hw->lock, flags);
  133. val = __raw_readl(hw->regs + USI_CNT);
  134. val |= GOBUSY;
  135. __raw_writel(val, hw->regs + USI_CNT);
  136. spin_unlock_irqrestore(&hw->lock, flags);
  137. }
  138. static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
  139. {
  140. return hw->tx ? hw->tx[count] : 0;
  141. }
  142. static int nuc900_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  143. {
  144. struct nuc900_spi *hw = to_hw(spi);
  145. hw->tx = t->tx_buf;
  146. hw->rx = t->rx_buf;
  147. hw->len = t->len;
  148. hw->count = 0;
  149. __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0);
  150. nuc900_spi_gobusy(hw);
  151. wait_for_completion(&hw->done);
  152. return hw->count;
  153. }
  154. static irqreturn_t nuc900_spi_irq(int irq, void *dev)
  155. {
  156. struct nuc900_spi *hw = dev;
  157. unsigned int status;
  158. unsigned int count = hw->count;
  159. status = __raw_readl(hw->regs + USI_CNT);
  160. __raw_writel(status, hw->regs + USI_CNT);
  161. if (status & ENFLG) {
  162. hw->count++;
  163. if (hw->rx)
  164. hw->rx[count] = __raw_readl(hw->regs + USI_RX0);
  165. count++;
  166. if (count < hw->len) {
  167. __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0);
  168. nuc900_spi_gobusy(hw);
  169. } else {
  170. complete(&hw->done);
  171. }
  172. return IRQ_HANDLED;
  173. }
  174. complete(&hw->done);
  175. return IRQ_HANDLED;
  176. }
  177. static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge)
  178. {
  179. unsigned int val;
  180. unsigned long flags;
  181. spin_lock_irqsave(&hw->lock, flags);
  182. val = __raw_readl(hw->regs + USI_CNT);
  183. if (edge)
  184. val |= TXNEG;
  185. else
  186. val &= ~TXNEG;
  187. __raw_writel(val, hw->regs + USI_CNT);
  188. spin_unlock_irqrestore(&hw->lock, flags);
  189. }
  190. static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge)
  191. {
  192. unsigned int val;
  193. unsigned long flags;
  194. spin_lock_irqsave(&hw->lock, flags);
  195. val = __raw_readl(hw->regs + USI_CNT);
  196. if (edge)
  197. val |= RXNEG;
  198. else
  199. val &= ~RXNEG;
  200. __raw_writel(val, hw->regs + USI_CNT);
  201. spin_unlock_irqrestore(&hw->lock, flags);
  202. }
  203. static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb)
  204. {
  205. unsigned int val;
  206. unsigned long flags;
  207. spin_lock_irqsave(&hw->lock, flags);
  208. val = __raw_readl(hw->regs + USI_CNT);
  209. if (lsb)
  210. val |= LSB;
  211. else
  212. val &= ~LSB;
  213. __raw_writel(val, hw->regs + USI_CNT);
  214. spin_unlock_irqrestore(&hw->lock, flags);
  215. }
  216. static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
  217. {
  218. unsigned int val;
  219. unsigned long flags;
  220. spin_lock_irqsave(&hw->lock, flags);
  221. val = __raw_readl(hw->regs + USI_CNT);
  222. if (sleep)
  223. val |= (sleep << 12);
  224. else
  225. val &= ~(0x0f << 12);
  226. __raw_writel(val, hw->regs + USI_CNT);
  227. spin_unlock_irqrestore(&hw->lock, flags);
  228. }
  229. static void nuc900_enable_int(struct nuc900_spi *hw)
  230. {
  231. unsigned int val;
  232. unsigned long flags;
  233. spin_lock_irqsave(&hw->lock, flags);
  234. val = __raw_readl(hw->regs + USI_CNT);
  235. val |= ENINT;
  236. __raw_writel(val, hw->regs + USI_CNT);
  237. spin_unlock_irqrestore(&hw->lock, flags);
  238. }
  239. static void nuc900_set_divider(struct nuc900_spi *hw)
  240. {
  241. __raw_writel(hw->pdata->divider, hw->regs + USI_DIV);
  242. }
  243. static void nuc900_init_spi(struct nuc900_spi *hw)
  244. {
  245. clk_enable(hw->clk);
  246. spin_lock_init(&hw->lock);
  247. nuc900_tx_edge(hw, hw->pdata->txneg);
  248. nuc900_rx_edge(hw, hw->pdata->rxneg);
  249. nuc900_send_first(hw, hw->pdata->lsb);
  250. nuc900_set_sleep(hw, hw->pdata->sleep);
  251. nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen);
  252. nuc900_spi_setup_txnum(hw, hw->pdata->txnum);
  253. nuc900_set_divider(hw);
  254. nuc900_enable_int(hw);
  255. }
  256. static int nuc900_spi_probe(struct platform_device *pdev)
  257. {
  258. struct nuc900_spi *hw;
  259. struct spi_master *master;
  260. int err = 0;
  261. master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
  262. if (master == NULL) {
  263. dev_err(&pdev->dev, "No memory for spi_master\n");
  264. err = -ENOMEM;
  265. goto err_nomem;
  266. }
  267. hw = spi_master_get_devdata(master);
  268. hw->master = spi_master_get(master);
  269. hw->pdata = dev_get_platdata(&pdev->dev);
  270. hw->dev = &pdev->dev;
  271. if (hw->pdata == NULL) {
  272. dev_err(&pdev->dev, "No platform data supplied\n");
  273. err = -ENOENT;
  274. goto err_pdata;
  275. }
  276. platform_set_drvdata(pdev, hw);
  277. init_completion(&hw->done);
  278. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  279. master->num_chipselect = hw->pdata->num_cs;
  280. master->bus_num = hw->pdata->bus_num;
  281. hw->bitbang.master = hw->master;
  282. hw->bitbang.chipselect = nuc900_spi_chipsel;
  283. hw->bitbang.txrx_bufs = nuc900_spi_txrx;
  284. hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  285. if (hw->res == NULL) {
  286. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  287. err = -ENOENT;
  288. goto err_pdata;
  289. }
  290. hw->ioarea = request_mem_region(hw->res->start,
  291. resource_size(hw->res), pdev->name);
  292. if (hw->ioarea == NULL) {
  293. dev_err(&pdev->dev, "Cannot reserve region\n");
  294. err = -ENXIO;
  295. goto err_pdata;
  296. }
  297. hw->regs = ioremap(hw->res->start, resource_size(hw->res));
  298. if (hw->regs == NULL) {
  299. dev_err(&pdev->dev, "Cannot map IO\n");
  300. err = -ENXIO;
  301. goto err_iomap;
  302. }
  303. hw->irq = platform_get_irq(pdev, 0);
  304. if (hw->irq < 0) {
  305. dev_err(&pdev->dev, "No IRQ specified\n");
  306. err = -ENOENT;
  307. goto err_irq;
  308. }
  309. err = request_irq(hw->irq, nuc900_spi_irq, 0, pdev->name, hw);
  310. if (err) {
  311. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  312. goto err_irq;
  313. }
  314. hw->clk = clk_get(&pdev->dev, "spi");
  315. if (IS_ERR(hw->clk)) {
  316. dev_err(&pdev->dev, "No clock for device\n");
  317. err = PTR_ERR(hw->clk);
  318. goto err_clk;
  319. }
  320. mfp_set_groupg(&pdev->dev, NULL);
  321. nuc900_init_spi(hw);
  322. err = spi_bitbang_start(&hw->bitbang);
  323. if (err) {
  324. dev_err(&pdev->dev, "Failed to register SPI master\n");
  325. goto err_register;
  326. }
  327. return 0;
  328. err_register:
  329. clk_disable(hw->clk);
  330. clk_put(hw->clk);
  331. err_clk:
  332. free_irq(hw->irq, hw);
  333. err_irq:
  334. iounmap(hw->regs);
  335. err_iomap:
  336. release_mem_region(hw->res->start, resource_size(hw->res));
  337. kfree(hw->ioarea);
  338. err_pdata:
  339. spi_master_put(hw->master);
  340. err_nomem:
  341. return err;
  342. }
  343. static int nuc900_spi_remove(struct platform_device *dev)
  344. {
  345. struct nuc900_spi *hw = platform_get_drvdata(dev);
  346. free_irq(hw->irq, hw);
  347. spi_bitbang_stop(&hw->bitbang);
  348. clk_disable(hw->clk);
  349. clk_put(hw->clk);
  350. iounmap(hw->regs);
  351. release_mem_region(hw->res->start, resource_size(hw->res));
  352. kfree(hw->ioarea);
  353. spi_master_put(hw->master);
  354. return 0;
  355. }
  356. static struct platform_driver nuc900_spi_driver = {
  357. .probe = nuc900_spi_probe,
  358. .remove = nuc900_spi_remove,
  359. .driver = {
  360. .name = "nuc900-spi",
  361. .owner = THIS_MODULE,
  362. },
  363. };
  364. module_platform_driver(nuc900_spi_driver);
  365. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  366. MODULE_DESCRIPTION("nuc900 spi driver!");
  367. MODULE_LICENSE("GPL");
  368. MODULE_ALIAS("platform:nuc900-spi");