spi-mxs.c 15 KB

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  1. /*
  2. * Freescale MXS SPI master driver
  3. *
  4. * Copyright 2012 DENX Software Engineering, GmbH.
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  7. *
  8. * Rework and transition to new API by:
  9. * Marek Vasut <marex@denx.de>
  10. *
  11. * Based on previous attempt by:
  12. * Fabio Estevam <fabio.estevam@freescale.com>
  13. *
  14. * Based on code from U-Boot bootloader by:
  15. * Marek Vasut <marex@denx.de>
  16. *
  17. * Based on spi-stmp.c, which is:
  18. * Author: Dmitry Pervushin <dimka@embeddedalley.com>
  19. *
  20. * This program is free software; you can redistribute it and/or modify
  21. * it under the terms of the GNU General Public License as published by
  22. * the Free Software Foundation; either version 2 of the License, or
  23. * (at your option) any later version.
  24. *
  25. * This program is distributed in the hope that it will be useful,
  26. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28. * GNU General Public License for more details.
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/init.h>
  32. #include <linux/ioport.h>
  33. #include <linux/of.h>
  34. #include <linux/of_device.h>
  35. #include <linux/of_gpio.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/delay.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/dmaengine.h>
  41. #include <linux/highmem.h>
  42. #include <linux/clk.h>
  43. #include <linux/err.h>
  44. #include <linux/completion.h>
  45. #include <linux/gpio.h>
  46. #include <linux/regulator/consumer.h>
  47. #include <linux/module.h>
  48. #include <linux/stmp_device.h>
  49. #include <linux/spi/spi.h>
  50. #include <linux/spi/mxs-spi.h>
  51. #define DRIVER_NAME "mxs-spi"
  52. /* Use 10S timeout for very long transfers, it should suffice. */
  53. #define SSP_TIMEOUT 10000
  54. #define SG_MAXLEN 0xff00
  55. /*
  56. * Flags for txrx functions. More efficient that using an argument register for
  57. * each one.
  58. */
  59. #define TXRX_WRITE (1<<0) /* This is a write */
  60. #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
  61. struct mxs_spi {
  62. struct mxs_ssp ssp;
  63. struct completion c;
  64. };
  65. static int mxs_spi_setup_transfer(struct spi_device *dev,
  66. struct spi_transfer *t)
  67. {
  68. struct mxs_spi *spi = spi_master_get_devdata(dev->master);
  69. struct mxs_ssp *ssp = &spi->ssp;
  70. uint32_t hz = 0;
  71. hz = dev->max_speed_hz;
  72. if (t && t->speed_hz)
  73. hz = min(hz, t->speed_hz);
  74. if (hz == 0) {
  75. dev_err(&dev->dev, "Cannot continue with zero clock\n");
  76. return -EINVAL;
  77. }
  78. mxs_ssp_set_clk_rate(ssp, hz);
  79. writel(BM_SSP_CTRL0_LOCK_CS,
  80. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  81. writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
  82. BF_SSP_CTRL1_WORD_LENGTH
  83. (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
  84. ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
  85. ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
  86. ssp->base + HW_SSP_CTRL1(ssp));
  87. writel(0x0, ssp->base + HW_SSP_CMD0);
  88. writel(0x0, ssp->base + HW_SSP_CMD1);
  89. return 0;
  90. }
  91. static int mxs_spi_setup(struct spi_device *dev)
  92. {
  93. int err = 0;
  94. if (!dev->bits_per_word)
  95. dev->bits_per_word = 8;
  96. if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
  97. return -EINVAL;
  98. err = mxs_spi_setup_transfer(dev, NULL);
  99. if (err) {
  100. dev_err(&dev->dev,
  101. "Failed to setup transfer, error = %d\n", err);
  102. }
  103. return err;
  104. }
  105. static uint32_t mxs_spi_cs_to_reg(unsigned cs)
  106. {
  107. uint32_t select = 0;
  108. /*
  109. * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
  110. *
  111. * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
  112. * in HW_SSP_CTRL0 register do have multiple usage, please refer to
  113. * the datasheet for further details. In SPI mode, they are used to
  114. * toggle the chip-select lines (nCS pins).
  115. */
  116. if (cs & 1)
  117. select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
  118. if (cs & 2)
  119. select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
  120. return select;
  121. }
  122. static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
  123. {
  124. const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
  125. struct mxs_ssp *ssp = &spi->ssp;
  126. uint32_t reg;
  127. do {
  128. reg = readl_relaxed(ssp->base + offset);
  129. if (!set)
  130. reg = ~reg;
  131. reg &= mask;
  132. if (reg == mask)
  133. return 0;
  134. } while (time_before(jiffies, timeout));
  135. return -ETIMEDOUT;
  136. }
  137. static void mxs_ssp_dma_irq_callback(void *param)
  138. {
  139. struct mxs_spi *spi = param;
  140. complete(&spi->c);
  141. }
  142. static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
  143. {
  144. struct mxs_ssp *ssp = dev_id;
  145. dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
  146. __func__, __LINE__,
  147. readl(ssp->base + HW_SSP_CTRL1(ssp)),
  148. readl(ssp->base + HW_SSP_STATUS(ssp)));
  149. return IRQ_HANDLED;
  150. }
  151. static int mxs_spi_txrx_dma(struct mxs_spi *spi,
  152. unsigned char *buf, int len,
  153. unsigned int flags)
  154. {
  155. struct mxs_ssp *ssp = &spi->ssp;
  156. struct dma_async_tx_descriptor *desc = NULL;
  157. const bool vmalloced_buf = is_vmalloc_addr(buf);
  158. const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
  159. const int sgs = DIV_ROUND_UP(len, desc_len);
  160. int sg_count;
  161. int min, ret;
  162. uint32_t ctrl0;
  163. struct page *vm_page;
  164. void *sg_buf;
  165. struct {
  166. uint32_t pio[4];
  167. struct scatterlist sg;
  168. } *dma_xfer;
  169. if (!len)
  170. return -EINVAL;
  171. dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
  172. if (!dma_xfer)
  173. return -ENOMEM;
  174. INIT_COMPLETION(spi->c);
  175. /* Chip select was already programmed into CTRL0 */
  176. ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
  177. ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
  178. BM_SSP_CTRL0_READ);
  179. ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
  180. if (!(flags & TXRX_WRITE))
  181. ctrl0 |= BM_SSP_CTRL0_READ;
  182. /* Queue the DMA data transfer. */
  183. for (sg_count = 0; sg_count < sgs; sg_count++) {
  184. /* Prepare the transfer descriptor. */
  185. min = min(len, desc_len);
  186. /*
  187. * De-assert CS on last segment if flag is set (i.e., no more
  188. * transfers will follow)
  189. */
  190. if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
  191. ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
  192. if (ssp->devid == IMX23_SSP) {
  193. ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
  194. ctrl0 |= min;
  195. }
  196. dma_xfer[sg_count].pio[0] = ctrl0;
  197. dma_xfer[sg_count].pio[3] = min;
  198. if (vmalloced_buf) {
  199. vm_page = vmalloc_to_page(buf);
  200. if (!vm_page) {
  201. ret = -ENOMEM;
  202. goto err_vmalloc;
  203. }
  204. sg_buf = page_address(vm_page) +
  205. ((size_t)buf & ~PAGE_MASK);
  206. } else {
  207. sg_buf = buf;
  208. }
  209. sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
  210. ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
  211. (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  212. len -= min;
  213. buf += min;
  214. /* Queue the PIO register write transfer. */
  215. desc = dmaengine_prep_slave_sg(ssp->dmach,
  216. (struct scatterlist *)dma_xfer[sg_count].pio,
  217. (ssp->devid == IMX23_SSP) ? 1 : 4,
  218. DMA_TRANS_NONE,
  219. sg_count ? DMA_PREP_INTERRUPT : 0);
  220. if (!desc) {
  221. dev_err(ssp->dev,
  222. "Failed to get PIO reg. write descriptor.\n");
  223. ret = -EINVAL;
  224. goto err_mapped;
  225. }
  226. desc = dmaengine_prep_slave_sg(ssp->dmach,
  227. &dma_xfer[sg_count].sg, 1,
  228. (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  229. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  230. if (!desc) {
  231. dev_err(ssp->dev,
  232. "Failed to get DMA data write descriptor.\n");
  233. ret = -EINVAL;
  234. goto err_mapped;
  235. }
  236. }
  237. /*
  238. * The last descriptor must have this callback,
  239. * to finish the DMA transaction.
  240. */
  241. desc->callback = mxs_ssp_dma_irq_callback;
  242. desc->callback_param = spi;
  243. /* Start the transfer. */
  244. dmaengine_submit(desc);
  245. dma_async_issue_pending(ssp->dmach);
  246. ret = wait_for_completion_timeout(&spi->c,
  247. msecs_to_jiffies(SSP_TIMEOUT));
  248. if (!ret) {
  249. dev_err(ssp->dev, "DMA transfer timeout\n");
  250. ret = -ETIMEDOUT;
  251. dmaengine_terminate_all(ssp->dmach);
  252. goto err_vmalloc;
  253. }
  254. ret = 0;
  255. err_vmalloc:
  256. while (--sg_count >= 0) {
  257. err_mapped:
  258. dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
  259. (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  260. }
  261. kfree(dma_xfer);
  262. return ret;
  263. }
  264. static int mxs_spi_txrx_pio(struct mxs_spi *spi,
  265. unsigned char *buf, int len,
  266. unsigned int flags)
  267. {
  268. struct mxs_ssp *ssp = &spi->ssp;
  269. writel(BM_SSP_CTRL0_IGNORE_CRC,
  270. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  271. while (len--) {
  272. if (len == 0 && (flags & TXRX_DEASSERT_CS))
  273. writel(BM_SSP_CTRL0_IGNORE_CRC,
  274. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  275. if (ssp->devid == IMX23_SSP) {
  276. writel(BM_SSP_CTRL0_XFER_COUNT,
  277. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  278. writel(1,
  279. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  280. } else {
  281. writel(1, ssp->base + HW_SSP_XFER_SIZE);
  282. }
  283. if (flags & TXRX_WRITE)
  284. writel(BM_SSP_CTRL0_READ,
  285. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  286. else
  287. writel(BM_SSP_CTRL0_READ,
  288. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  289. writel(BM_SSP_CTRL0_RUN,
  290. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  291. if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
  292. return -ETIMEDOUT;
  293. if (flags & TXRX_WRITE)
  294. writel(*buf, ssp->base + HW_SSP_DATA(ssp));
  295. writel(BM_SSP_CTRL0_DATA_XFER,
  296. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  297. if (!(flags & TXRX_WRITE)) {
  298. if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
  299. BM_SSP_STATUS_FIFO_EMPTY, 0))
  300. return -ETIMEDOUT;
  301. *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
  302. }
  303. if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
  304. return -ETIMEDOUT;
  305. buf++;
  306. }
  307. if (len <= 0)
  308. return 0;
  309. return -ETIMEDOUT;
  310. }
  311. static int mxs_spi_transfer_one(struct spi_master *master,
  312. struct spi_message *m)
  313. {
  314. struct mxs_spi *spi = spi_master_get_devdata(master);
  315. struct mxs_ssp *ssp = &spi->ssp;
  316. struct spi_transfer *t, *tmp_t;
  317. unsigned int flag;
  318. int status = 0;
  319. /* Program CS register bits here, it will be used for all transfers. */
  320. writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
  321. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  322. writel(mxs_spi_cs_to_reg(m->spi->chip_select),
  323. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  324. list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
  325. status = mxs_spi_setup_transfer(m->spi, t);
  326. if (status)
  327. break;
  328. /* De-assert on last transfer, inverted by cs_change flag */
  329. flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
  330. TXRX_DEASSERT_CS : 0;
  331. if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
  332. dev_err(ssp->dev,
  333. "Cannot send and receive simultaneously\n");
  334. status = -EINVAL;
  335. break;
  336. }
  337. /*
  338. * Small blocks can be transfered via PIO.
  339. * Measured by empiric means:
  340. *
  341. * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
  342. *
  343. * DMA only: 2.164808 seconds, 473.0KB/s
  344. * Combined: 1.676276 seconds, 610.9KB/s
  345. */
  346. if (t->len < 32) {
  347. writel(BM_SSP_CTRL1_DMA_ENABLE,
  348. ssp->base + HW_SSP_CTRL1(ssp) +
  349. STMP_OFFSET_REG_CLR);
  350. if (t->tx_buf)
  351. status = mxs_spi_txrx_pio(spi,
  352. (void *)t->tx_buf,
  353. t->len, flag | TXRX_WRITE);
  354. if (t->rx_buf)
  355. status = mxs_spi_txrx_pio(spi,
  356. t->rx_buf, t->len,
  357. flag);
  358. } else {
  359. writel(BM_SSP_CTRL1_DMA_ENABLE,
  360. ssp->base + HW_SSP_CTRL1(ssp) +
  361. STMP_OFFSET_REG_SET);
  362. if (t->tx_buf)
  363. status = mxs_spi_txrx_dma(spi,
  364. (void *)t->tx_buf, t->len,
  365. flag | TXRX_WRITE);
  366. if (t->rx_buf)
  367. status = mxs_spi_txrx_dma(spi,
  368. t->rx_buf, t->len,
  369. flag);
  370. }
  371. if (status) {
  372. stmp_reset_block(ssp->base);
  373. break;
  374. }
  375. m->actual_length += t->len;
  376. }
  377. m->status = status;
  378. spi_finalize_current_message(master);
  379. return status;
  380. }
  381. static const struct of_device_id mxs_spi_dt_ids[] = {
  382. { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
  383. { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
  384. { /* sentinel */ }
  385. };
  386. MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
  387. static int mxs_spi_probe(struct platform_device *pdev)
  388. {
  389. const struct of_device_id *of_id =
  390. of_match_device(mxs_spi_dt_ids, &pdev->dev);
  391. struct device_node *np = pdev->dev.of_node;
  392. struct spi_master *master;
  393. struct mxs_spi *spi;
  394. struct mxs_ssp *ssp;
  395. struct resource *iores;
  396. struct clk *clk;
  397. void __iomem *base;
  398. int devid, clk_freq;
  399. int ret = 0, irq_err;
  400. /*
  401. * Default clock speed for the SPI core. 160MHz seems to
  402. * work reasonably well with most SPI flashes, so use this
  403. * as a default. Override with "clock-frequency" DT prop.
  404. */
  405. const int clk_freq_default = 160000000;
  406. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  407. irq_err = platform_get_irq(pdev, 0);
  408. if (irq_err < 0)
  409. return -EINVAL;
  410. base = devm_ioremap_resource(&pdev->dev, iores);
  411. if (IS_ERR(base))
  412. return PTR_ERR(base);
  413. clk = devm_clk_get(&pdev->dev, NULL);
  414. if (IS_ERR(clk))
  415. return PTR_ERR(clk);
  416. devid = (enum mxs_ssp_id) of_id->data;
  417. ret = of_property_read_u32(np, "clock-frequency",
  418. &clk_freq);
  419. if (ret)
  420. clk_freq = clk_freq_default;
  421. master = spi_alloc_master(&pdev->dev, sizeof(*spi));
  422. if (!master)
  423. return -ENOMEM;
  424. master->transfer_one_message = mxs_spi_transfer_one;
  425. master->setup = mxs_spi_setup;
  426. master->bits_per_word_mask = SPI_BPW_MASK(8);
  427. master->mode_bits = SPI_CPOL | SPI_CPHA;
  428. master->num_chipselect = 3;
  429. master->dev.of_node = np;
  430. master->flags = SPI_MASTER_HALF_DUPLEX;
  431. spi = spi_master_get_devdata(master);
  432. ssp = &spi->ssp;
  433. ssp->dev = &pdev->dev;
  434. ssp->clk = clk;
  435. ssp->base = base;
  436. ssp->devid = devid;
  437. init_completion(&spi->c);
  438. ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
  439. DRIVER_NAME, ssp);
  440. if (ret)
  441. goto out_master_free;
  442. ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
  443. if (!ssp->dmach) {
  444. dev_err(ssp->dev, "Failed to request DMA\n");
  445. ret = -ENODEV;
  446. goto out_master_free;
  447. }
  448. ret = clk_prepare_enable(ssp->clk);
  449. if (ret)
  450. goto out_dma_release;
  451. clk_set_rate(ssp->clk, clk_freq);
  452. ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
  453. ret = stmp_reset_block(ssp->base);
  454. if (ret)
  455. goto out_disable_clk;
  456. platform_set_drvdata(pdev, master);
  457. ret = spi_register_master(master);
  458. if (ret) {
  459. dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
  460. goto out_disable_clk;
  461. }
  462. return 0;
  463. out_disable_clk:
  464. clk_disable_unprepare(ssp->clk);
  465. out_dma_release:
  466. dma_release_channel(ssp->dmach);
  467. out_master_free:
  468. spi_master_put(master);
  469. return ret;
  470. }
  471. static int mxs_spi_remove(struct platform_device *pdev)
  472. {
  473. struct spi_master *master;
  474. struct mxs_spi *spi;
  475. struct mxs_ssp *ssp;
  476. master = spi_master_get(platform_get_drvdata(pdev));
  477. spi = spi_master_get_devdata(master);
  478. ssp = &spi->ssp;
  479. spi_unregister_master(master);
  480. clk_disable_unprepare(ssp->clk);
  481. dma_release_channel(ssp->dmach);
  482. spi_master_put(master);
  483. return 0;
  484. }
  485. static struct platform_driver mxs_spi_driver = {
  486. .probe = mxs_spi_probe,
  487. .remove = mxs_spi_remove,
  488. .driver = {
  489. .name = DRIVER_NAME,
  490. .owner = THIS_MODULE,
  491. .of_match_table = mxs_spi_dt_ids,
  492. },
  493. };
  494. module_platform_driver(mxs_spi_driver);
  495. MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
  496. MODULE_DESCRIPTION("MXS SPI master driver");
  497. MODULE_LICENSE("GPL");
  498. MODULE_ALIAS("platform:mxs-spi");