spi-au1550.c 26 KB

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  1. /*
  2. * au1550 psc spi controller driver
  3. * may work also with au1200, au1210, au1250
  4. * will not work on au1000, au1100 and au1500 (no full spi controller there)
  5. *
  6. * Copyright (c) 2006 ATRON electronic GmbH
  7. * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/slab.h>
  26. #include <linux/errno.h>
  27. #include <linux/module.h>
  28. #include <linux/device.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/resource.h>
  31. #include <linux/spi/spi.h>
  32. #include <linux/spi/spi_bitbang.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/completion.h>
  35. #include <asm/mach-au1x00/au1000.h>
  36. #include <asm/mach-au1x00/au1xxx_psc.h>
  37. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  38. #include <asm/mach-au1x00/au1550_spi.h>
  39. static unsigned usedma = 1;
  40. module_param(usedma, uint, 0644);
  41. /*
  42. #define AU1550_SPI_DEBUG_LOOPBACK
  43. */
  44. #define AU1550_SPI_DBDMA_DESCRIPTORS 1
  45. #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
  46. struct au1550_spi {
  47. struct spi_bitbang bitbang;
  48. volatile psc_spi_t __iomem *regs;
  49. int irq;
  50. unsigned freq_max;
  51. unsigned freq_min;
  52. unsigned len;
  53. unsigned tx_count;
  54. unsigned rx_count;
  55. const u8 *tx;
  56. u8 *rx;
  57. void (*rx_word)(struct au1550_spi *hw);
  58. void (*tx_word)(struct au1550_spi *hw);
  59. int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
  60. irqreturn_t (*irq_callback)(struct au1550_spi *hw);
  61. struct completion master_done;
  62. unsigned usedma;
  63. u32 dma_tx_id;
  64. u32 dma_rx_id;
  65. u32 dma_tx_ch;
  66. u32 dma_rx_ch;
  67. u8 *dma_rx_tmpbuf;
  68. unsigned dma_rx_tmpbuf_size;
  69. u32 dma_rx_tmpbuf_addr;
  70. struct spi_master *master;
  71. struct device *dev;
  72. struct au1550_spi_info *pdata;
  73. struct resource *ioarea;
  74. };
  75. /* we use an 8-bit memory device for dma transfers to/from spi fifo */
  76. static dbdev_tab_t au1550_spi_mem_dbdev =
  77. {
  78. .dev_id = DBDMA_MEM_CHAN,
  79. .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
  80. .dev_tsize = 0,
  81. .dev_devwidth = 8,
  82. .dev_physaddr = 0x00000000,
  83. .dev_intlevel = 0,
  84. .dev_intpolarity = 0
  85. };
  86. static int ddma_memid; /* id to above mem dma device */
  87. static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
  88. /*
  89. * compute BRG and DIV bits to setup spi clock based on main input clock rate
  90. * that was specified in platform data structure
  91. * according to au1550 datasheet:
  92. * psc_tempclk = psc_mainclk / (2 << DIV)
  93. * spiclk = psc_tempclk / (2 * (BRG + 1))
  94. * BRG valid range is 4..63
  95. * DIV valid range is 0..3
  96. */
  97. static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
  98. {
  99. u32 mainclk_hz = hw->pdata->mainclk_hz;
  100. u32 div, brg;
  101. for (div = 0; div < 4; div++) {
  102. brg = mainclk_hz / speed_hz / (4 << div);
  103. /* now we have BRG+1 in brg, so count with that */
  104. if (brg < (4 + 1)) {
  105. brg = (4 + 1); /* speed_hz too big */
  106. break; /* set lowest brg (div is == 0) */
  107. }
  108. if (brg <= (63 + 1))
  109. break; /* we have valid brg and div */
  110. }
  111. if (div == 4) {
  112. div = 3; /* speed_hz too small */
  113. brg = (63 + 1); /* set highest brg and div */
  114. }
  115. brg--;
  116. return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
  117. }
  118. static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
  119. {
  120. hw->regs->psc_spimsk =
  121. PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
  122. | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
  123. | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
  124. au_sync();
  125. hw->regs->psc_spievent =
  126. PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
  127. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
  128. | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
  129. au_sync();
  130. }
  131. static void au1550_spi_reset_fifos(struct au1550_spi *hw)
  132. {
  133. u32 pcr;
  134. hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
  135. au_sync();
  136. do {
  137. pcr = hw->regs->psc_spipcr;
  138. au_sync();
  139. } while (pcr != 0);
  140. }
  141. /*
  142. * dma transfers are used for the most common spi word size of 8-bits
  143. * we cannot easily change already set up dma channels' width, so if we wanted
  144. * dma support for more than 8-bit words (up to 24 bits), we would need to
  145. * setup dma channels from scratch on each spi transfer, based on bits_per_word
  146. * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
  147. * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
  148. * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
  149. */
  150. static void au1550_spi_chipsel(struct spi_device *spi, int value)
  151. {
  152. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  153. unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  154. u32 cfg, stat;
  155. switch (value) {
  156. case BITBANG_CS_INACTIVE:
  157. if (hw->pdata->deactivate_cs)
  158. hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
  159. cspol);
  160. break;
  161. case BITBANG_CS_ACTIVE:
  162. au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
  163. cfg = hw->regs->psc_spicfg;
  164. au_sync();
  165. hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
  166. au_sync();
  167. if (spi->mode & SPI_CPOL)
  168. cfg |= PSC_SPICFG_BI;
  169. else
  170. cfg &= ~PSC_SPICFG_BI;
  171. if (spi->mode & SPI_CPHA)
  172. cfg &= ~PSC_SPICFG_CDE;
  173. else
  174. cfg |= PSC_SPICFG_CDE;
  175. if (spi->mode & SPI_LSB_FIRST)
  176. cfg |= PSC_SPICFG_MLF;
  177. else
  178. cfg &= ~PSC_SPICFG_MLF;
  179. if (hw->usedma && spi->bits_per_word <= 8)
  180. cfg &= ~PSC_SPICFG_DD_DISABLE;
  181. else
  182. cfg |= PSC_SPICFG_DD_DISABLE;
  183. cfg = PSC_SPICFG_CLR_LEN(cfg);
  184. cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
  185. cfg = PSC_SPICFG_CLR_BAUD(cfg);
  186. cfg &= ~PSC_SPICFG_SET_DIV(3);
  187. cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
  188. hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
  189. au_sync();
  190. do {
  191. stat = hw->regs->psc_spistat;
  192. au_sync();
  193. } while ((stat & PSC_SPISTAT_DR) == 0);
  194. if (hw->pdata->activate_cs)
  195. hw->pdata->activate_cs(hw->pdata, spi->chip_select,
  196. cspol);
  197. break;
  198. }
  199. }
  200. static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
  201. {
  202. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  203. unsigned bpw, hz;
  204. u32 cfg, stat;
  205. bpw = spi->bits_per_word;
  206. hz = spi->max_speed_hz;
  207. if (t) {
  208. if (t->bits_per_word)
  209. bpw = t->bits_per_word;
  210. if (t->speed_hz)
  211. hz = t->speed_hz;
  212. }
  213. if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
  214. dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
  215. hz);
  216. return -EINVAL;
  217. }
  218. au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
  219. cfg = hw->regs->psc_spicfg;
  220. au_sync();
  221. hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
  222. au_sync();
  223. if (hw->usedma && bpw <= 8)
  224. cfg &= ~PSC_SPICFG_DD_DISABLE;
  225. else
  226. cfg |= PSC_SPICFG_DD_DISABLE;
  227. cfg = PSC_SPICFG_CLR_LEN(cfg);
  228. cfg |= PSC_SPICFG_SET_LEN(bpw);
  229. cfg = PSC_SPICFG_CLR_BAUD(cfg);
  230. cfg &= ~PSC_SPICFG_SET_DIV(3);
  231. cfg |= au1550_spi_baudcfg(hw, hz);
  232. hw->regs->psc_spicfg = cfg;
  233. au_sync();
  234. if (cfg & PSC_SPICFG_DE_ENABLE) {
  235. do {
  236. stat = hw->regs->psc_spistat;
  237. au_sync();
  238. } while ((stat & PSC_SPISTAT_DR) == 0);
  239. }
  240. au1550_spi_reset_fifos(hw);
  241. au1550_spi_mask_ack_all(hw);
  242. return 0;
  243. }
  244. static int au1550_spi_setup(struct spi_device *spi)
  245. {
  246. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  247. if (spi->max_speed_hz == 0)
  248. spi->max_speed_hz = hw->freq_max;
  249. if (spi->max_speed_hz > hw->freq_max
  250. || spi->max_speed_hz < hw->freq_min)
  251. return -EINVAL;
  252. /*
  253. * NOTE: cannot change speed and other hw settings immediately,
  254. * otherwise sharing of spi bus is not possible,
  255. * so do not call setupxfer(spi, NULL) here
  256. */
  257. return 0;
  258. }
  259. /*
  260. * for dma spi transfers, we have to setup rx channel, otherwise there is
  261. * no reliable way how to recognize that spi transfer is done
  262. * dma complete callbacks are called before real spi transfer is finished
  263. * and if only tx dma channel is set up (and rx fifo overflow event masked)
  264. * spi master done event irq is not generated unless rx fifo is empty (emptied)
  265. * so we need rx tmp buffer to use for rx dma if user does not provide one
  266. */
  267. static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
  268. {
  269. hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
  270. if (!hw->dma_rx_tmpbuf)
  271. return -ENOMEM;
  272. hw->dma_rx_tmpbuf_size = size;
  273. hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
  274. size, DMA_FROM_DEVICE);
  275. if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
  276. kfree(hw->dma_rx_tmpbuf);
  277. hw->dma_rx_tmpbuf = 0;
  278. hw->dma_rx_tmpbuf_size = 0;
  279. return -EFAULT;
  280. }
  281. return 0;
  282. }
  283. static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
  284. {
  285. dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
  286. hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
  287. kfree(hw->dma_rx_tmpbuf);
  288. hw->dma_rx_tmpbuf = 0;
  289. hw->dma_rx_tmpbuf_size = 0;
  290. }
  291. static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
  292. {
  293. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  294. dma_addr_t dma_tx_addr;
  295. dma_addr_t dma_rx_addr;
  296. u32 res;
  297. hw->len = t->len;
  298. hw->tx_count = 0;
  299. hw->rx_count = 0;
  300. hw->tx = t->tx_buf;
  301. hw->rx = t->rx_buf;
  302. dma_tx_addr = t->tx_dma;
  303. dma_rx_addr = t->rx_dma;
  304. /*
  305. * check if buffers are already dma mapped, map them otherwise:
  306. * - first map the TX buffer, so cache data gets written to memory
  307. * - then map the RX buffer, so that cache entries (with
  308. * soon-to-be-stale data) get removed
  309. * use rx buffer in place of tx if tx buffer was not provided
  310. * use temp rx buffer (preallocated or realloc to fit) for rx dma
  311. */
  312. if (t->tx_buf) {
  313. if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
  314. dma_tx_addr = dma_map_single(hw->dev,
  315. (void *)t->tx_buf,
  316. t->len, DMA_TO_DEVICE);
  317. if (dma_mapping_error(hw->dev, dma_tx_addr))
  318. dev_err(hw->dev, "tx dma map error\n");
  319. }
  320. }
  321. if (t->rx_buf) {
  322. if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
  323. dma_rx_addr = dma_map_single(hw->dev,
  324. (void *)t->rx_buf,
  325. t->len, DMA_FROM_DEVICE);
  326. if (dma_mapping_error(hw->dev, dma_rx_addr))
  327. dev_err(hw->dev, "rx dma map error\n");
  328. }
  329. } else {
  330. if (t->len > hw->dma_rx_tmpbuf_size) {
  331. int ret;
  332. au1550_spi_dma_rxtmp_free(hw);
  333. ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
  334. AU1550_SPI_DMA_RXTMP_MINSIZE));
  335. if (ret < 0)
  336. return ret;
  337. }
  338. hw->rx = hw->dma_rx_tmpbuf;
  339. dma_rx_addr = hw->dma_rx_tmpbuf_addr;
  340. dma_sync_single_for_device(hw->dev, dma_rx_addr,
  341. t->len, DMA_FROM_DEVICE);
  342. }
  343. if (!t->tx_buf) {
  344. dma_sync_single_for_device(hw->dev, dma_rx_addr,
  345. t->len, DMA_BIDIRECTIONAL);
  346. hw->tx = hw->rx;
  347. }
  348. /* put buffers on the ring */
  349. res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
  350. t->len, DDMA_FLAGS_IE);
  351. if (!res)
  352. dev_err(hw->dev, "rx dma put dest error\n");
  353. res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
  354. t->len, DDMA_FLAGS_IE);
  355. if (!res)
  356. dev_err(hw->dev, "tx dma put source error\n");
  357. au1xxx_dbdma_start(hw->dma_rx_ch);
  358. au1xxx_dbdma_start(hw->dma_tx_ch);
  359. /* by default enable nearly all events interrupt */
  360. hw->regs->psc_spimsk = PSC_SPIMSK_SD;
  361. au_sync();
  362. /* start the transfer */
  363. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  364. au_sync();
  365. wait_for_completion(&hw->master_done);
  366. au1xxx_dbdma_stop(hw->dma_tx_ch);
  367. au1xxx_dbdma_stop(hw->dma_rx_ch);
  368. if (!t->rx_buf) {
  369. /* using the temporal preallocated and premapped buffer */
  370. dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
  371. DMA_FROM_DEVICE);
  372. }
  373. /* unmap buffers if mapped above */
  374. if (t->rx_buf && t->rx_dma == 0 )
  375. dma_unmap_single(hw->dev, dma_rx_addr, t->len,
  376. DMA_FROM_DEVICE);
  377. if (t->tx_buf && t->tx_dma == 0 )
  378. dma_unmap_single(hw->dev, dma_tx_addr, t->len,
  379. DMA_TO_DEVICE);
  380. return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
  381. }
  382. static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
  383. {
  384. u32 stat, evnt;
  385. stat = hw->regs->psc_spistat;
  386. evnt = hw->regs->psc_spievent;
  387. au_sync();
  388. if ((stat & PSC_SPISTAT_DI) == 0) {
  389. dev_err(hw->dev, "Unexpected IRQ!\n");
  390. return IRQ_NONE;
  391. }
  392. if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
  393. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
  394. | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
  395. != 0) {
  396. /*
  397. * due to an spi error we consider transfer as done,
  398. * so mask all events until before next transfer start
  399. * and stop the possibly running dma immediately
  400. */
  401. au1550_spi_mask_ack_all(hw);
  402. au1xxx_dbdma_stop(hw->dma_rx_ch);
  403. au1xxx_dbdma_stop(hw->dma_tx_ch);
  404. /* get number of transferred bytes */
  405. hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
  406. hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
  407. au1xxx_dbdma_reset(hw->dma_rx_ch);
  408. au1xxx_dbdma_reset(hw->dma_tx_ch);
  409. au1550_spi_reset_fifos(hw);
  410. if (evnt == PSC_SPIEVNT_RO)
  411. dev_err(hw->dev,
  412. "dma transfer: receive FIFO overflow!\n");
  413. else
  414. dev_err(hw->dev,
  415. "dma transfer: unexpected SPI error "
  416. "(event=0x%x stat=0x%x)!\n", evnt, stat);
  417. complete(&hw->master_done);
  418. return IRQ_HANDLED;
  419. }
  420. if ((evnt & PSC_SPIEVNT_MD) != 0) {
  421. /* transfer completed successfully */
  422. au1550_spi_mask_ack_all(hw);
  423. hw->rx_count = hw->len;
  424. hw->tx_count = hw->len;
  425. complete(&hw->master_done);
  426. }
  427. return IRQ_HANDLED;
  428. }
  429. /* routines to handle different word sizes in pio mode */
  430. #define AU1550_SPI_RX_WORD(size, mask) \
  431. static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
  432. { \
  433. u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
  434. au_sync(); \
  435. if (hw->rx) { \
  436. *(u##size *)hw->rx = (u##size)fifoword; \
  437. hw->rx += (size) / 8; \
  438. } \
  439. hw->rx_count += (size) / 8; \
  440. }
  441. #define AU1550_SPI_TX_WORD(size, mask) \
  442. static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
  443. { \
  444. u32 fifoword = 0; \
  445. if (hw->tx) { \
  446. fifoword = *(u##size *)hw->tx & (u32)(mask); \
  447. hw->tx += (size) / 8; \
  448. } \
  449. hw->tx_count += (size) / 8; \
  450. if (hw->tx_count >= hw->len) \
  451. fifoword |= PSC_SPITXRX_LC; \
  452. hw->regs->psc_spitxrx = fifoword; \
  453. au_sync(); \
  454. }
  455. AU1550_SPI_RX_WORD(8,0xff)
  456. AU1550_SPI_RX_WORD(16,0xffff)
  457. AU1550_SPI_RX_WORD(32,0xffffff)
  458. AU1550_SPI_TX_WORD(8,0xff)
  459. AU1550_SPI_TX_WORD(16,0xffff)
  460. AU1550_SPI_TX_WORD(32,0xffffff)
  461. static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
  462. {
  463. u32 stat, mask;
  464. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  465. hw->tx = t->tx_buf;
  466. hw->rx = t->rx_buf;
  467. hw->len = t->len;
  468. hw->tx_count = 0;
  469. hw->rx_count = 0;
  470. /* by default enable nearly all events after filling tx fifo */
  471. mask = PSC_SPIMSK_SD;
  472. /* fill the transmit FIFO */
  473. while (hw->tx_count < hw->len) {
  474. hw->tx_word(hw);
  475. if (hw->tx_count >= hw->len) {
  476. /* mask tx fifo request interrupt as we are done */
  477. mask |= PSC_SPIMSK_TR;
  478. }
  479. stat = hw->regs->psc_spistat;
  480. au_sync();
  481. if (stat & PSC_SPISTAT_TF)
  482. break;
  483. }
  484. /* enable event interrupts */
  485. hw->regs->psc_spimsk = mask;
  486. au_sync();
  487. /* start the transfer */
  488. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  489. au_sync();
  490. wait_for_completion(&hw->master_done);
  491. return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
  492. }
  493. static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
  494. {
  495. int busy;
  496. u32 stat, evnt;
  497. stat = hw->regs->psc_spistat;
  498. evnt = hw->regs->psc_spievent;
  499. au_sync();
  500. if ((stat & PSC_SPISTAT_DI) == 0) {
  501. dev_err(hw->dev, "Unexpected IRQ!\n");
  502. return IRQ_NONE;
  503. }
  504. if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
  505. | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
  506. | PSC_SPIEVNT_SD))
  507. != 0) {
  508. /*
  509. * due to an error we consider transfer as done,
  510. * so mask all events until before next transfer start
  511. */
  512. au1550_spi_mask_ack_all(hw);
  513. au1550_spi_reset_fifos(hw);
  514. dev_err(hw->dev,
  515. "pio transfer: unexpected SPI error "
  516. "(event=0x%x stat=0x%x)!\n", evnt, stat);
  517. complete(&hw->master_done);
  518. return IRQ_HANDLED;
  519. }
  520. /*
  521. * while there is something to read from rx fifo
  522. * or there is a space to write to tx fifo:
  523. */
  524. do {
  525. busy = 0;
  526. stat = hw->regs->psc_spistat;
  527. au_sync();
  528. /*
  529. * Take care to not let the Rx FIFO overflow.
  530. *
  531. * We only write a byte if we have read one at least. Initially,
  532. * the write fifo is full, so we should read from the read fifo
  533. * first.
  534. * In case we miss a word from the read fifo, we should get a
  535. * RO event and should back out.
  536. */
  537. if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
  538. hw->rx_word(hw);
  539. busy = 1;
  540. if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
  541. hw->tx_word(hw);
  542. }
  543. } while (busy);
  544. hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
  545. au_sync();
  546. /*
  547. * Restart the SPI transmission in case of a transmit underflow.
  548. * This seems to work despite the notes in the Au1550 data book
  549. * of Figure 8-4 with flowchart for SPI master operation:
  550. *
  551. * """Note 1: An XFR Error Interrupt occurs, unless masked,
  552. * for any of the following events: Tx FIFO Underflow,
  553. * Rx FIFO Overflow, or Multiple-master Error
  554. * Note 2: In case of a Tx Underflow Error, all zeroes are
  555. * transmitted."""
  556. *
  557. * By simply restarting the spi transfer on Tx Underflow Error,
  558. * we assume that spi transfer was paused instead of zeroes
  559. * transmittion mentioned in the Note 2 of Au1550 data book.
  560. */
  561. if (evnt & PSC_SPIEVNT_TU) {
  562. hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
  563. au_sync();
  564. hw->regs->psc_spipcr = PSC_SPIPCR_MS;
  565. au_sync();
  566. }
  567. if (hw->rx_count >= hw->len) {
  568. /* transfer completed successfully */
  569. au1550_spi_mask_ack_all(hw);
  570. complete(&hw->master_done);
  571. }
  572. return IRQ_HANDLED;
  573. }
  574. static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
  575. {
  576. struct au1550_spi *hw = spi_master_get_devdata(spi->master);
  577. return hw->txrx_bufs(spi, t);
  578. }
  579. static irqreturn_t au1550_spi_irq(int irq, void *dev)
  580. {
  581. struct au1550_spi *hw = dev;
  582. return hw->irq_callback(hw);
  583. }
  584. static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
  585. {
  586. if (bpw <= 8) {
  587. if (hw->usedma) {
  588. hw->txrx_bufs = &au1550_spi_dma_txrxb;
  589. hw->irq_callback = &au1550_spi_dma_irq_callback;
  590. } else {
  591. hw->rx_word = &au1550_spi_rx_word_8;
  592. hw->tx_word = &au1550_spi_tx_word_8;
  593. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  594. hw->irq_callback = &au1550_spi_pio_irq_callback;
  595. }
  596. } else if (bpw <= 16) {
  597. hw->rx_word = &au1550_spi_rx_word_16;
  598. hw->tx_word = &au1550_spi_tx_word_16;
  599. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  600. hw->irq_callback = &au1550_spi_pio_irq_callback;
  601. } else {
  602. hw->rx_word = &au1550_spi_rx_word_32;
  603. hw->tx_word = &au1550_spi_tx_word_32;
  604. hw->txrx_bufs = &au1550_spi_pio_txrxb;
  605. hw->irq_callback = &au1550_spi_pio_irq_callback;
  606. }
  607. }
  608. static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
  609. {
  610. u32 stat, cfg;
  611. /* set up the PSC for SPI mode */
  612. hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
  613. au_sync();
  614. hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
  615. au_sync();
  616. hw->regs->psc_spicfg = 0;
  617. au_sync();
  618. hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
  619. au_sync();
  620. do {
  621. stat = hw->regs->psc_spistat;
  622. au_sync();
  623. } while ((stat & PSC_SPISTAT_SR) == 0);
  624. cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
  625. cfg |= PSC_SPICFG_SET_LEN(8);
  626. cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
  627. /* use minimal allowed brg and div values as initial setting: */
  628. cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
  629. #ifdef AU1550_SPI_DEBUG_LOOPBACK
  630. cfg |= PSC_SPICFG_LB;
  631. #endif
  632. hw->regs->psc_spicfg = cfg;
  633. au_sync();
  634. au1550_spi_mask_ack_all(hw);
  635. hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
  636. au_sync();
  637. do {
  638. stat = hw->regs->psc_spistat;
  639. au_sync();
  640. } while ((stat & PSC_SPISTAT_DR) == 0);
  641. au1550_spi_reset_fifos(hw);
  642. }
  643. static int au1550_spi_probe(struct platform_device *pdev)
  644. {
  645. struct au1550_spi *hw;
  646. struct spi_master *master;
  647. struct resource *r;
  648. int err = 0;
  649. master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
  650. if (master == NULL) {
  651. dev_err(&pdev->dev, "No memory for spi_master\n");
  652. err = -ENOMEM;
  653. goto err_nomem;
  654. }
  655. /* the spi->mode bits understood by this driver: */
  656. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  657. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
  658. hw = spi_master_get_devdata(master);
  659. hw->master = spi_master_get(master);
  660. hw->pdata = dev_get_platdata(&pdev->dev);
  661. hw->dev = &pdev->dev;
  662. if (hw->pdata == NULL) {
  663. dev_err(&pdev->dev, "No platform data supplied\n");
  664. err = -ENOENT;
  665. goto err_no_pdata;
  666. }
  667. r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  668. if (!r) {
  669. dev_err(&pdev->dev, "no IRQ\n");
  670. err = -ENODEV;
  671. goto err_no_iores;
  672. }
  673. hw->irq = r->start;
  674. hw->usedma = 0;
  675. r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  676. if (r) {
  677. hw->dma_tx_id = r->start;
  678. r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  679. if (r) {
  680. hw->dma_rx_id = r->start;
  681. if (usedma && ddma_memid) {
  682. if (pdev->dev.dma_mask == NULL)
  683. dev_warn(&pdev->dev, "no dma mask\n");
  684. else
  685. hw->usedma = 1;
  686. }
  687. }
  688. }
  689. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  690. if (!r) {
  691. dev_err(&pdev->dev, "no mmio resource\n");
  692. err = -ENODEV;
  693. goto err_no_iores;
  694. }
  695. hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
  696. pdev->name);
  697. if (!hw->ioarea) {
  698. dev_err(&pdev->dev, "Cannot reserve iomem region\n");
  699. err = -ENXIO;
  700. goto err_no_iores;
  701. }
  702. hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
  703. if (!hw->regs) {
  704. dev_err(&pdev->dev, "cannot ioremap\n");
  705. err = -ENXIO;
  706. goto err_ioremap;
  707. }
  708. platform_set_drvdata(pdev, hw);
  709. init_completion(&hw->master_done);
  710. hw->bitbang.master = hw->master;
  711. hw->bitbang.setup_transfer = au1550_spi_setupxfer;
  712. hw->bitbang.chipselect = au1550_spi_chipsel;
  713. hw->bitbang.master->setup = au1550_spi_setup;
  714. hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
  715. if (hw->usedma) {
  716. hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
  717. hw->dma_tx_id, NULL, (void *)hw);
  718. if (hw->dma_tx_ch == 0) {
  719. dev_err(&pdev->dev,
  720. "Cannot allocate tx dma channel\n");
  721. err = -ENXIO;
  722. goto err_no_txdma;
  723. }
  724. au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
  725. if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
  726. AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
  727. dev_err(&pdev->dev,
  728. "Cannot allocate tx dma descriptors\n");
  729. err = -ENXIO;
  730. goto err_no_txdma_descr;
  731. }
  732. hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
  733. ddma_memid, NULL, (void *)hw);
  734. if (hw->dma_rx_ch == 0) {
  735. dev_err(&pdev->dev,
  736. "Cannot allocate rx dma channel\n");
  737. err = -ENXIO;
  738. goto err_no_rxdma;
  739. }
  740. au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
  741. if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
  742. AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
  743. dev_err(&pdev->dev,
  744. "Cannot allocate rx dma descriptors\n");
  745. err = -ENXIO;
  746. goto err_no_rxdma_descr;
  747. }
  748. err = au1550_spi_dma_rxtmp_alloc(hw,
  749. AU1550_SPI_DMA_RXTMP_MINSIZE);
  750. if (err < 0) {
  751. dev_err(&pdev->dev,
  752. "Cannot allocate initial rx dma tmp buffer\n");
  753. goto err_dma_rxtmp_alloc;
  754. }
  755. }
  756. au1550_spi_bits_handlers_set(hw, 8);
  757. err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
  758. if (err) {
  759. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  760. goto err_no_irq;
  761. }
  762. master->bus_num = pdev->id;
  763. master->num_chipselect = hw->pdata->num_chipselect;
  764. /*
  765. * precompute valid range for spi freq - from au1550 datasheet:
  766. * psc_tempclk = psc_mainclk / (2 << DIV)
  767. * spiclk = psc_tempclk / (2 * (BRG + 1))
  768. * BRG valid range is 4..63
  769. * DIV valid range is 0..3
  770. * round the min and max frequencies to values that would still
  771. * produce valid brg and div
  772. */
  773. {
  774. int min_div = (2 << 0) * (2 * (4 + 1));
  775. int max_div = (2 << 3) * (2 * (63 + 1));
  776. hw->freq_max = hw->pdata->mainclk_hz / min_div;
  777. hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
  778. }
  779. au1550_spi_setup_psc_as_spi(hw);
  780. err = spi_bitbang_start(&hw->bitbang);
  781. if (err) {
  782. dev_err(&pdev->dev, "Failed to register SPI master\n");
  783. goto err_register;
  784. }
  785. dev_info(&pdev->dev,
  786. "spi master registered: bus_num=%d num_chipselect=%d\n",
  787. master->bus_num, master->num_chipselect);
  788. return 0;
  789. err_register:
  790. free_irq(hw->irq, hw);
  791. err_no_irq:
  792. au1550_spi_dma_rxtmp_free(hw);
  793. err_dma_rxtmp_alloc:
  794. err_no_rxdma_descr:
  795. if (hw->usedma)
  796. au1xxx_dbdma_chan_free(hw->dma_rx_ch);
  797. err_no_rxdma:
  798. err_no_txdma_descr:
  799. if (hw->usedma)
  800. au1xxx_dbdma_chan_free(hw->dma_tx_ch);
  801. err_no_txdma:
  802. iounmap((void __iomem *)hw->regs);
  803. err_ioremap:
  804. release_resource(hw->ioarea);
  805. kfree(hw->ioarea);
  806. err_no_iores:
  807. err_no_pdata:
  808. spi_master_put(hw->master);
  809. err_nomem:
  810. return err;
  811. }
  812. static int au1550_spi_remove(struct platform_device *pdev)
  813. {
  814. struct au1550_spi *hw = platform_get_drvdata(pdev);
  815. dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
  816. hw->master->bus_num);
  817. spi_bitbang_stop(&hw->bitbang);
  818. free_irq(hw->irq, hw);
  819. iounmap((void __iomem *)hw->regs);
  820. release_resource(hw->ioarea);
  821. kfree(hw->ioarea);
  822. if (hw->usedma) {
  823. au1550_spi_dma_rxtmp_free(hw);
  824. au1xxx_dbdma_chan_free(hw->dma_rx_ch);
  825. au1xxx_dbdma_chan_free(hw->dma_tx_ch);
  826. }
  827. spi_master_put(hw->master);
  828. return 0;
  829. }
  830. /* work with hotplug and coldplug */
  831. MODULE_ALIAS("platform:au1550-spi");
  832. static struct platform_driver au1550_spi_drv = {
  833. .remove = au1550_spi_remove,
  834. .driver = {
  835. .name = "au1550-spi",
  836. .owner = THIS_MODULE,
  837. },
  838. };
  839. static int __init au1550_spi_init(void)
  840. {
  841. /*
  842. * create memory device with 8 bits dev_devwidth
  843. * needed for proper byte ordering to spi fifo
  844. */
  845. if (usedma) {
  846. ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
  847. if (!ddma_memid)
  848. printk(KERN_ERR "au1550-spi: cannot add memory"
  849. "dbdma device\n");
  850. }
  851. return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
  852. }
  853. module_init(au1550_spi_init);
  854. static void __exit au1550_spi_exit(void)
  855. {
  856. if (usedma && ddma_memid)
  857. au1xxx_ddma_del_device(ddma_memid);
  858. platform_driver_unregister(&au1550_spi_drv);
  859. }
  860. module_exit(au1550_spi_exit);
  861. MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
  862. MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
  863. MODULE_LICENSE("GPL");