coh901318_lli.c 6.2 KB

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  1. /*
  2. * driver/dma/coh901318_lli.c
  3. *
  4. * Copyright (C) 2007-2009 ST-Ericsson
  5. * License terms: GNU General Public License (GPL) version 2
  6. * Support functions for handling lli for dma
  7. * Author: Per Friden <per.friden@stericsson.com>
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/dmapool.h>
  12. #include <linux/memory.h>
  13. #include <mach/coh901318.h>
  14. #include "coh901318_lli.h"
  15. #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
  16. #define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
  17. #define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
  18. #else
  19. #define DEBUGFS_POOL_COUNTER_RESET(pool)
  20. #define DEBUGFS_POOL_COUNTER_ADD(pool, add)
  21. #endif
  22. static struct coh901318_lli *
  23. coh901318_lli_next(struct coh901318_lli *data)
  24. {
  25. if (data == NULL || data->link_addr == 0)
  26. return NULL;
  27. return (struct coh901318_lli *) data->virt_link_addr;
  28. }
  29. int coh901318_pool_create(struct coh901318_pool *pool,
  30. struct device *dev,
  31. size_t size, size_t align)
  32. {
  33. spin_lock_init(&pool->lock);
  34. pool->dev = dev;
  35. pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
  36. DEBUGFS_POOL_COUNTER_RESET(pool);
  37. return 0;
  38. }
  39. int coh901318_pool_destroy(struct coh901318_pool *pool)
  40. {
  41. dma_pool_destroy(pool->dmapool);
  42. return 0;
  43. }
  44. struct coh901318_lli *
  45. coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
  46. {
  47. int i;
  48. struct coh901318_lli *head;
  49. struct coh901318_lli *lli;
  50. struct coh901318_lli *lli_prev;
  51. dma_addr_t phy;
  52. if (len == 0)
  53. goto err;
  54. spin_lock(&pool->lock);
  55. head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
  56. if (head == NULL)
  57. goto err;
  58. DEBUGFS_POOL_COUNTER_ADD(pool, 1);
  59. lli = head;
  60. lli->phy_this = phy;
  61. for (i = 1; i < len; i++) {
  62. lli_prev = lli;
  63. lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
  64. if (lli == NULL)
  65. goto err_clean_up;
  66. DEBUGFS_POOL_COUNTER_ADD(pool, 1);
  67. lli->phy_this = phy;
  68. lli_prev->link_addr = phy;
  69. lli_prev->virt_link_addr = lli;
  70. }
  71. lli->link_addr = 0x00000000U;
  72. spin_unlock(&pool->lock);
  73. return head;
  74. err:
  75. spin_unlock(&pool->lock);
  76. return NULL;
  77. err_clean_up:
  78. lli_prev->link_addr = 0x00000000U;
  79. spin_unlock(&pool->lock);
  80. coh901318_lli_free(pool, &head);
  81. return NULL;
  82. }
  83. void coh901318_lli_free(struct coh901318_pool *pool,
  84. struct coh901318_lli **lli)
  85. {
  86. struct coh901318_lli *l;
  87. struct coh901318_lli *next;
  88. if (lli == NULL)
  89. return;
  90. l = *lli;
  91. if (l == NULL)
  92. return;
  93. spin_lock(&pool->lock);
  94. while (l->link_addr) {
  95. next = l->virt_link_addr;
  96. dma_pool_free(pool->dmapool, l, l->phy_this);
  97. DEBUGFS_POOL_COUNTER_ADD(pool, -1);
  98. l = next;
  99. }
  100. dma_pool_free(pool->dmapool, l, l->phy_this);
  101. DEBUGFS_POOL_COUNTER_ADD(pool, -1);
  102. spin_unlock(&pool->lock);
  103. *lli = NULL;
  104. }
  105. int
  106. coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
  107. struct coh901318_lli *lli,
  108. dma_addr_t source, unsigned int size,
  109. dma_addr_t destination, u32 ctrl_chained,
  110. u32 ctrl_eom)
  111. {
  112. int s = size;
  113. dma_addr_t src = source;
  114. dma_addr_t dst = destination;
  115. lli->src_addr = src;
  116. lli->dst_addr = dst;
  117. while (lli->link_addr) {
  118. lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
  119. lli->src_addr = src;
  120. lli->dst_addr = dst;
  121. s -= MAX_DMA_PACKET_SIZE;
  122. lli = coh901318_lli_next(lli);
  123. src += MAX_DMA_PACKET_SIZE;
  124. dst += MAX_DMA_PACKET_SIZE;
  125. }
  126. lli->control = ctrl_eom | s;
  127. lli->src_addr = src;
  128. lli->dst_addr = dst;
  129. return 0;
  130. }
  131. int
  132. coh901318_lli_fill_single(struct coh901318_pool *pool,
  133. struct coh901318_lli *lli,
  134. dma_addr_t buf, unsigned int size,
  135. dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
  136. enum dma_data_direction dir)
  137. {
  138. int s = size;
  139. dma_addr_t src;
  140. dma_addr_t dst;
  141. if (dir == DMA_TO_DEVICE) {
  142. src = buf;
  143. dst = dev_addr;
  144. } else if (dir == DMA_FROM_DEVICE) {
  145. src = dev_addr;
  146. dst = buf;
  147. } else {
  148. return -EINVAL;
  149. }
  150. while (lli->link_addr) {
  151. size_t block_size = MAX_DMA_PACKET_SIZE;
  152. lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
  153. /* If we are on the next-to-final block and there will
  154. * be less than half a DMA packet left for the last
  155. * block, then we want to make this block a little
  156. * smaller to balance the sizes. This is meant to
  157. * avoid too small transfers if the buffer size is
  158. * (MAX_DMA_PACKET_SIZE*N + 1) */
  159. if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
  160. block_size = MAX_DMA_PACKET_SIZE/2;
  161. s -= block_size;
  162. lli->src_addr = src;
  163. lli->dst_addr = dst;
  164. lli = coh901318_lli_next(lli);
  165. if (dir == DMA_TO_DEVICE)
  166. src += block_size;
  167. else if (dir == DMA_FROM_DEVICE)
  168. dst += block_size;
  169. }
  170. lli->control = ctrl_eom | s;
  171. lli->src_addr = src;
  172. lli->dst_addr = dst;
  173. return 0;
  174. }
  175. int
  176. coh901318_lli_fill_sg(struct coh901318_pool *pool,
  177. struct coh901318_lli *lli,
  178. struct scatterlist *sgl, unsigned int nents,
  179. dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
  180. u32 ctrl_last,
  181. enum dma_data_direction dir, u32 ctrl_irq_mask)
  182. {
  183. int i;
  184. struct scatterlist *sg;
  185. u32 ctrl_sg;
  186. dma_addr_t src = 0;
  187. dma_addr_t dst = 0;
  188. u32 bytes_to_transfer;
  189. u32 elem_size;
  190. if (lli == NULL)
  191. goto err;
  192. spin_lock(&pool->lock);
  193. if (dir == DMA_TO_DEVICE)
  194. dst = dev_addr;
  195. else if (dir == DMA_FROM_DEVICE)
  196. src = dev_addr;
  197. else
  198. goto err;
  199. for_each_sg(sgl, sg, nents, i) {
  200. if (sg_is_chain(sg)) {
  201. /* sg continues to the next sg-element don't
  202. * send ctrl_finish until the last
  203. * sg-element in the chain
  204. */
  205. ctrl_sg = ctrl_chained;
  206. } else if (i == nents - 1)
  207. ctrl_sg = ctrl_last;
  208. else
  209. ctrl_sg = ctrl ? ctrl : ctrl_last;
  210. if (dir == DMA_TO_DEVICE)
  211. /* increment source address */
  212. src = sg_dma_address(sg);
  213. else
  214. /* increment destination address */
  215. dst = sg_dma_address(sg);
  216. bytes_to_transfer = sg_dma_len(sg);
  217. while (bytes_to_transfer) {
  218. u32 val;
  219. if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
  220. elem_size = MAX_DMA_PACKET_SIZE;
  221. val = ctrl_chained;
  222. } else {
  223. elem_size = bytes_to_transfer;
  224. val = ctrl_sg;
  225. }
  226. lli->control = val | elem_size;
  227. lli->src_addr = src;
  228. lli->dst_addr = dst;
  229. if (dir == DMA_FROM_DEVICE)
  230. dst += elem_size;
  231. else
  232. src += elem_size;
  233. BUG_ON(lli->link_addr & 3);
  234. bytes_to_transfer -= elem_size;
  235. lli = coh901318_lli_next(lli);
  236. }
  237. }
  238. spin_unlock(&pool->lock);
  239. return 0;
  240. err:
  241. spin_unlock(&pool->lock);
  242. return -EINVAL;
  243. }