cx23885-cards.c 32 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include "cx23885.h"
  27. #include "tuner-xc2028.h"
  28. #include "netup-init.h"
  29. #include "cx23888-ir.h"
  30. /* ------------------------------------------------------------------ */
  31. /* board config info */
  32. struct cx23885_board cx23885_boards[] = {
  33. [CX23885_BOARD_UNKNOWN] = {
  34. .name = "UNKNOWN/GENERIC",
  35. /* Ensure safe default for unknown boards */
  36. .clk_freq = 0,
  37. .input = {{
  38. .type = CX23885_VMUX_COMPOSITE1,
  39. .vmux = 0,
  40. }, {
  41. .type = CX23885_VMUX_COMPOSITE2,
  42. .vmux = 1,
  43. }, {
  44. .type = CX23885_VMUX_COMPOSITE3,
  45. .vmux = 2,
  46. }, {
  47. .type = CX23885_VMUX_COMPOSITE4,
  48. .vmux = 3,
  49. } },
  50. },
  51. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  52. .name = "Hauppauge WinTV-HVR1800lp",
  53. .portc = CX23885_MPEG_DVB,
  54. .input = {{
  55. .type = CX23885_VMUX_TELEVISION,
  56. .vmux = 0,
  57. .gpio0 = 0xff00,
  58. }, {
  59. .type = CX23885_VMUX_DEBUG,
  60. .vmux = 0,
  61. .gpio0 = 0xff01,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE1,
  64. .vmux = 1,
  65. .gpio0 = 0xff02,
  66. }, {
  67. .type = CX23885_VMUX_SVIDEO,
  68. .vmux = 2,
  69. .gpio0 = 0xff02,
  70. } },
  71. },
  72. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  73. .name = "Hauppauge WinTV-HVR1800",
  74. .porta = CX23885_ANALOG_VIDEO,
  75. .portb = CX23885_MPEG_ENCODER,
  76. .portc = CX23885_MPEG_DVB,
  77. .tuner_type = TUNER_PHILIPS_TDA8290,
  78. .tuner_addr = 0x42, /* 0x84 >> 1 */
  79. .input = {{
  80. .type = CX23885_VMUX_TELEVISION,
  81. .vmux = CX25840_VIN7_CH3 |
  82. CX25840_VIN5_CH2 |
  83. CX25840_VIN2_CH1,
  84. .gpio0 = 0,
  85. }, {
  86. .type = CX23885_VMUX_COMPOSITE1,
  87. .vmux = CX25840_VIN7_CH3 |
  88. CX25840_VIN4_CH2 |
  89. CX25840_VIN6_CH1,
  90. .gpio0 = 0,
  91. }, {
  92. .type = CX23885_VMUX_SVIDEO,
  93. .vmux = CX25840_VIN7_CH3 |
  94. CX25840_VIN4_CH2 |
  95. CX25840_VIN8_CH1 |
  96. CX25840_SVIDEO_ON,
  97. .gpio0 = 0,
  98. } },
  99. },
  100. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  101. .name = "Hauppauge WinTV-HVR1250",
  102. .portc = CX23885_MPEG_DVB,
  103. .input = {{
  104. .type = CX23885_VMUX_TELEVISION,
  105. .vmux = 0,
  106. .gpio0 = 0xff00,
  107. }, {
  108. .type = CX23885_VMUX_DEBUG,
  109. .vmux = 0,
  110. .gpio0 = 0xff01,
  111. }, {
  112. .type = CX23885_VMUX_COMPOSITE1,
  113. .vmux = 1,
  114. .gpio0 = 0xff02,
  115. }, {
  116. .type = CX23885_VMUX_SVIDEO,
  117. .vmux = 2,
  118. .gpio0 = 0xff02,
  119. } },
  120. },
  121. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  122. .name = "DViCO FusionHDTV5 Express",
  123. .portb = CX23885_MPEG_DVB,
  124. },
  125. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  126. .name = "Hauppauge WinTV-HVR1500Q",
  127. .portc = CX23885_MPEG_DVB,
  128. },
  129. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  130. .name = "Hauppauge WinTV-HVR1500",
  131. .portc = CX23885_MPEG_DVB,
  132. },
  133. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  134. .name = "Hauppauge WinTV-HVR1200",
  135. .portc = CX23885_MPEG_DVB,
  136. },
  137. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  138. .name = "Hauppauge WinTV-HVR1700",
  139. .portc = CX23885_MPEG_DVB,
  140. },
  141. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  142. .name = "Hauppauge WinTV-HVR1400",
  143. .portc = CX23885_MPEG_DVB,
  144. },
  145. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  146. .name = "DViCO FusionHDTV7 Dual Express",
  147. .portb = CX23885_MPEG_DVB,
  148. .portc = CX23885_MPEG_DVB,
  149. },
  150. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  151. .name = "DViCO FusionHDTV DVB-T Dual Express",
  152. .portb = CX23885_MPEG_DVB,
  153. .portc = CX23885_MPEG_DVB,
  154. },
  155. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  156. .name = "Leadtek Winfast PxDVR3200 H",
  157. .portc = CX23885_MPEG_DVB,
  158. },
  159. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  160. .name = "Compro VideoMate E650F",
  161. .portc = CX23885_MPEG_DVB,
  162. },
  163. [CX23885_BOARD_TBS_6920] = {
  164. .name = "TurboSight TBS 6920",
  165. .portb = CX23885_MPEG_DVB,
  166. },
  167. [CX23885_BOARD_TEVII_S470] = {
  168. .name = "TeVii S470",
  169. .portb = CX23885_MPEG_DVB,
  170. },
  171. [CX23885_BOARD_DVBWORLD_2005] = {
  172. .name = "DVBWorld DVB-S2 2005",
  173. .portb = CX23885_MPEG_DVB,
  174. },
  175. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  176. .cimax = 1,
  177. .name = "NetUP Dual DVB-S2 CI",
  178. .portb = CX23885_MPEG_DVB,
  179. .portc = CX23885_MPEG_DVB,
  180. },
  181. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  182. .name = "Hauppauge WinTV-HVR1270",
  183. .portc = CX23885_MPEG_DVB,
  184. },
  185. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  186. .name = "Hauppauge WinTV-HVR1275",
  187. .portc = CX23885_MPEG_DVB,
  188. },
  189. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  190. .name = "Hauppauge WinTV-HVR1255",
  191. .portc = CX23885_MPEG_DVB,
  192. },
  193. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  194. .name = "Hauppauge WinTV-HVR1210",
  195. .portc = CX23885_MPEG_DVB,
  196. },
  197. [CX23885_BOARD_MYGICA_X8506] = {
  198. .name = "Mygica X8506 DMB-TH",
  199. .tuner_type = TUNER_XC5000,
  200. .tuner_addr = 0x61,
  201. .porta = CX23885_ANALOG_VIDEO,
  202. .portb = CX23885_MPEG_DVB,
  203. .input = {
  204. {
  205. .type = CX23885_VMUX_TELEVISION,
  206. .vmux = CX25840_COMPOSITE2,
  207. },
  208. {
  209. .type = CX23885_VMUX_COMPOSITE1,
  210. .vmux = CX25840_COMPOSITE8,
  211. },
  212. {
  213. .type = CX23885_VMUX_SVIDEO,
  214. .vmux = CX25840_SVIDEO_LUMA3 |
  215. CX25840_SVIDEO_CHROMA4,
  216. },
  217. {
  218. .type = CX23885_VMUX_COMPONENT,
  219. .vmux = CX25840_COMPONENT_ON |
  220. CX25840_VIN1_CH1 |
  221. CX25840_VIN6_CH2 |
  222. CX25840_VIN7_CH3,
  223. },
  224. },
  225. },
  226. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  227. .name = "Magic-Pro ProHDTV Extreme 2",
  228. .tuner_type = TUNER_XC5000,
  229. .tuner_addr = 0x61,
  230. .porta = CX23885_ANALOG_VIDEO,
  231. .portb = CX23885_MPEG_DVB,
  232. .input = {
  233. {
  234. .type = CX23885_VMUX_TELEVISION,
  235. .vmux = CX25840_COMPOSITE2,
  236. },
  237. {
  238. .type = CX23885_VMUX_COMPOSITE1,
  239. .vmux = CX25840_COMPOSITE8,
  240. },
  241. {
  242. .type = CX23885_VMUX_SVIDEO,
  243. .vmux = CX25840_SVIDEO_LUMA3 |
  244. CX25840_SVIDEO_CHROMA4,
  245. },
  246. {
  247. .type = CX23885_VMUX_COMPONENT,
  248. .vmux = CX25840_COMPONENT_ON |
  249. CX25840_VIN1_CH1 |
  250. CX25840_VIN6_CH2 |
  251. CX25840_VIN7_CH3,
  252. },
  253. },
  254. },
  255. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  256. .name = "Hauppauge WinTV-HVR1850",
  257. .portb = CX23885_MPEG_ENCODER,
  258. .portc = CX23885_MPEG_DVB,
  259. },
  260. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  261. .name = "Compro VideoMate E800",
  262. .portc = CX23885_MPEG_DVB,
  263. },
  264. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  265. .name = "Hauppauge WinTV-HVR1290",
  266. .portc = CX23885_MPEG_DVB,
  267. },
  268. [CX23885_BOARD_MYGICA_X8558PRO] = {
  269. .name = "Mygica X8558 PRO DMB-TH",
  270. .portb = CX23885_MPEG_DVB,
  271. .portc = CX23885_MPEG_DVB,
  272. },
  273. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  274. .name = "LEADTEK WinFast PxTV1200",
  275. .porta = CX23885_ANALOG_VIDEO,
  276. .tuner_type = TUNER_XC2028,
  277. .tuner_addr = 0x61,
  278. .input = {{
  279. .type = CX23885_VMUX_TELEVISION,
  280. .vmux = CX25840_VIN2_CH1 |
  281. CX25840_VIN5_CH2 |
  282. CX25840_NONE0_CH3,
  283. }, {
  284. .type = CX23885_VMUX_COMPOSITE1,
  285. .vmux = CX25840_COMPOSITE1,
  286. }, {
  287. .type = CX23885_VMUX_SVIDEO,
  288. .vmux = CX25840_SVIDEO_LUMA3 |
  289. CX25840_SVIDEO_CHROMA4,
  290. }, {
  291. .type = CX23885_VMUX_COMPONENT,
  292. .vmux = CX25840_VIN7_CH1 |
  293. CX25840_VIN6_CH2 |
  294. CX25840_VIN8_CH3 |
  295. CX25840_COMPONENT_ON,
  296. } },
  297. },
  298. };
  299. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  300. /* ------------------------------------------------------------------ */
  301. /* PCI subsystem IDs */
  302. struct cx23885_subid cx23885_subids[] = {
  303. {
  304. .subvendor = 0x0070,
  305. .subdevice = 0x3400,
  306. .card = CX23885_BOARD_UNKNOWN,
  307. }, {
  308. .subvendor = 0x0070,
  309. .subdevice = 0x7600,
  310. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  311. }, {
  312. .subvendor = 0x0070,
  313. .subdevice = 0x7800,
  314. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  315. }, {
  316. .subvendor = 0x0070,
  317. .subdevice = 0x7801,
  318. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  319. }, {
  320. .subvendor = 0x0070,
  321. .subdevice = 0x7809,
  322. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  323. }, {
  324. .subvendor = 0x0070,
  325. .subdevice = 0x7911,
  326. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  327. }, {
  328. .subvendor = 0x18ac,
  329. .subdevice = 0xd500,
  330. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  331. }, {
  332. .subvendor = 0x0070,
  333. .subdevice = 0x7790,
  334. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  335. }, {
  336. .subvendor = 0x0070,
  337. .subdevice = 0x7797,
  338. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  339. }, {
  340. .subvendor = 0x0070,
  341. .subdevice = 0x7710,
  342. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  343. }, {
  344. .subvendor = 0x0070,
  345. .subdevice = 0x7717,
  346. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  347. }, {
  348. .subvendor = 0x0070,
  349. .subdevice = 0x71d1,
  350. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  351. }, {
  352. .subvendor = 0x0070,
  353. .subdevice = 0x71d3,
  354. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  355. }, {
  356. .subvendor = 0x0070,
  357. .subdevice = 0x8101,
  358. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  359. }, {
  360. .subvendor = 0x0070,
  361. .subdevice = 0x8010,
  362. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  363. }, {
  364. .subvendor = 0x18ac,
  365. .subdevice = 0xd618,
  366. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  367. }, {
  368. .subvendor = 0x18ac,
  369. .subdevice = 0xdb78,
  370. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  371. }, {
  372. .subvendor = 0x107d,
  373. .subdevice = 0x6681,
  374. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  375. }, {
  376. .subvendor = 0x185b,
  377. .subdevice = 0xe800,
  378. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  379. }, {
  380. .subvendor = 0x6920,
  381. .subdevice = 0x8888,
  382. .card = CX23885_BOARD_TBS_6920,
  383. }, {
  384. .subvendor = 0xd470,
  385. .subdevice = 0x9022,
  386. .card = CX23885_BOARD_TEVII_S470,
  387. }, {
  388. .subvendor = 0x0001,
  389. .subdevice = 0x2005,
  390. .card = CX23885_BOARD_DVBWORLD_2005,
  391. }, {
  392. .subvendor = 0x1b55,
  393. .subdevice = 0x2a2c,
  394. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  395. }, {
  396. .subvendor = 0x0070,
  397. .subdevice = 0x2211,
  398. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  399. }, {
  400. .subvendor = 0x0070,
  401. .subdevice = 0x2215,
  402. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  403. }, {
  404. .subvendor = 0x0070,
  405. .subdevice = 0x2251,
  406. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  407. }, {
  408. .subvendor = 0x0070,
  409. .subdevice = 0x2291,
  410. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  411. }, {
  412. .subvendor = 0x0070,
  413. .subdevice = 0x2295,
  414. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  415. }, {
  416. .subvendor = 0x14f1,
  417. .subdevice = 0x8651,
  418. .card = CX23885_BOARD_MYGICA_X8506,
  419. }, {
  420. .subvendor = 0x14f1,
  421. .subdevice = 0x8657,
  422. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  423. }, {
  424. .subvendor = 0x0070,
  425. .subdevice = 0x8541,
  426. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  427. }, {
  428. .subvendor = 0x1858,
  429. .subdevice = 0xe800,
  430. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  431. }, {
  432. .subvendor = 0x0070,
  433. .subdevice = 0x8551,
  434. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  435. }, {
  436. .subvendor = 0x14f1,
  437. .subdevice = 0x8578,
  438. .card = CX23885_BOARD_MYGICA_X8558PRO,
  439. }, {
  440. .subvendor = 0x107d,
  441. .subdevice = 0x6f22,
  442. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  443. },
  444. };
  445. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  446. void cx23885_card_list(struct cx23885_dev *dev)
  447. {
  448. int i;
  449. if (0 == dev->pci->subsystem_vendor &&
  450. 0 == dev->pci->subsystem_device) {
  451. printk(KERN_INFO
  452. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  453. "%s: be autodetected. Pass card=<n> insmod option\n"
  454. "%s: to workaround that. Redirect complaints to the\n"
  455. "%s: vendor of the TV card. Best regards,\n"
  456. "%s: -- tux\n",
  457. dev->name, dev->name, dev->name, dev->name, dev->name);
  458. } else {
  459. printk(KERN_INFO
  460. "%s: Your board isn't known (yet) to the driver.\n"
  461. "%s: Try to pick one of the existing card configs via\n"
  462. "%s: card=<n> insmod option. Updating to the latest\n"
  463. "%s: version might help as well.\n",
  464. dev->name, dev->name, dev->name, dev->name);
  465. }
  466. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  467. dev->name);
  468. for (i = 0; i < cx23885_bcount; i++)
  469. printk(KERN_INFO "%s: card=%d -> %s\n",
  470. dev->name, i, cx23885_boards[i].name);
  471. }
  472. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  473. {
  474. struct tveeprom tv;
  475. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  476. eeprom_data);
  477. /* Make sure we support the board model */
  478. switch (tv.model) {
  479. case 22001:
  480. /* WinTV-HVR1270 (PCIe, Retail, half height)
  481. * ATSC/QAM and basic analog, IR Blast */
  482. case 22009:
  483. /* WinTV-HVR1210 (PCIe, Retail, half height)
  484. * DVB-T and basic analog, IR Blast */
  485. case 22011:
  486. /* WinTV-HVR1270 (PCIe, Retail, half height)
  487. * ATSC/QAM and basic analog, IR Recv */
  488. case 22019:
  489. /* WinTV-HVR1210 (PCIe, Retail, half height)
  490. * DVB-T and basic analog, IR Recv */
  491. case 22021:
  492. /* WinTV-HVR1275 (PCIe, Retail, half height)
  493. * ATSC/QAM and basic analog, IR Recv */
  494. case 22029:
  495. /* WinTV-HVR1210 (PCIe, Retail, half height)
  496. * DVB-T and basic analog, IR Recv */
  497. case 22101:
  498. /* WinTV-HVR1270 (PCIe, Retail, full height)
  499. * ATSC/QAM and basic analog, IR Blast */
  500. case 22109:
  501. /* WinTV-HVR1210 (PCIe, Retail, full height)
  502. * DVB-T and basic analog, IR Blast */
  503. case 22111:
  504. /* WinTV-HVR1270 (PCIe, Retail, full height)
  505. * ATSC/QAM and basic analog, IR Recv */
  506. case 22119:
  507. /* WinTV-HVR1210 (PCIe, Retail, full height)
  508. * DVB-T and basic analog, IR Recv */
  509. case 22121:
  510. /* WinTV-HVR1275 (PCIe, Retail, full height)
  511. * ATSC/QAM and basic analog, IR Recv */
  512. case 22129:
  513. /* WinTV-HVR1210 (PCIe, Retail, full height)
  514. * DVB-T and basic analog, IR Recv */
  515. case 71009:
  516. /* WinTV-HVR1200 (PCIe, Retail, full height)
  517. * DVB-T and basic analog */
  518. case 71359:
  519. /* WinTV-HVR1200 (PCIe, OEM, half height)
  520. * DVB-T and basic analog */
  521. case 71439:
  522. /* WinTV-HVR1200 (PCIe, OEM, half height)
  523. * DVB-T and basic analog */
  524. case 71449:
  525. /* WinTV-HVR1200 (PCIe, OEM, full height)
  526. * DVB-T and basic analog */
  527. case 71939:
  528. /* WinTV-HVR1200 (PCIe, OEM, half height)
  529. * DVB-T and basic analog */
  530. case 71949:
  531. /* WinTV-HVR1200 (PCIe, OEM, full height)
  532. * DVB-T and basic analog */
  533. case 71959:
  534. /* WinTV-HVR1200 (PCIe, OEM, full height)
  535. * DVB-T and basic analog */
  536. case 71979:
  537. /* WinTV-HVR1200 (PCIe, OEM, half height)
  538. * DVB-T and basic analog */
  539. case 71999:
  540. /* WinTV-HVR1200 (PCIe, OEM, full height)
  541. * DVB-T and basic analog */
  542. case 76601:
  543. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  544. channel ATSC and MPEG2 HW Encoder */
  545. case 77001:
  546. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  547. and Basic analog */
  548. case 77011:
  549. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  550. and Basic analog */
  551. case 77041:
  552. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  553. and Basic analog */
  554. case 77051:
  555. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  556. and Basic analog */
  557. case 78011:
  558. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  559. Dual channel ATSC and MPEG2 HW Encoder */
  560. case 78501:
  561. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  562. Dual channel ATSC and MPEG2 HW Encoder */
  563. case 78521:
  564. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  565. Dual channel ATSC and MPEG2 HW Encoder */
  566. case 78531:
  567. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  568. Dual channel ATSC and MPEG2 HW Encoder */
  569. case 78631:
  570. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  571. Dual channel ATSC and MPEG2 HW Encoder */
  572. case 79001:
  573. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  574. ATSC and Basic analog */
  575. case 79101:
  576. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  577. ATSC and Basic analog */
  578. case 79561:
  579. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  580. ATSC and Basic analog */
  581. case 79571:
  582. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  583. ATSC and Basic analog */
  584. case 79671:
  585. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  586. ATSC and Basic analog */
  587. case 80019:
  588. /* WinTV-HVR1400 (Express Card, Retail, IR,
  589. * DVB-T and Basic analog */
  590. case 81509:
  591. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  592. * DVB-T and MPEG2 HW Encoder */
  593. case 81519:
  594. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  595. * DVB-T and MPEG2 HW Encoder */
  596. break;
  597. case 85021:
  598. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  599. Dual channel ATSC and MPEG2 HW Encoder */
  600. break;
  601. case 85721:
  602. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  603. Dual channel ATSC and Basic analog */
  604. break;
  605. default:
  606. printk(KERN_WARNING "%s: warning: "
  607. "unknown hauppauge model #%d\n",
  608. dev->name, tv.model);
  609. break;
  610. }
  611. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  612. dev->name, tv.model);
  613. }
  614. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  615. {
  616. struct cx23885_tsport *port = priv;
  617. struct cx23885_dev *dev = port->dev;
  618. u32 bitmask = 0;
  619. if (command == XC2028_RESET_CLK)
  620. return 0;
  621. if (command != 0) {
  622. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  623. __func__, command);
  624. return -EINVAL;
  625. }
  626. switch (dev->board) {
  627. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  628. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  629. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  630. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  631. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  632. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  633. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  634. /* Tuner Reset Command */
  635. bitmask = 0x04;
  636. break;
  637. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  638. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  639. /* Two identical tuners on two different i2c buses,
  640. * we need to reset the correct gpio. */
  641. if (port->nr == 1)
  642. bitmask = 0x01;
  643. else if (port->nr == 2)
  644. bitmask = 0x04;
  645. break;
  646. }
  647. if (bitmask) {
  648. /* Drive the tuner into reset and back out */
  649. cx_clear(GP0_IO, bitmask);
  650. mdelay(200);
  651. cx_set(GP0_IO, bitmask);
  652. }
  653. return 0;
  654. }
  655. void cx23885_gpio_setup(struct cx23885_dev *dev)
  656. {
  657. switch (dev->board) {
  658. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  659. /* GPIO-0 cx24227 demodulator reset */
  660. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  661. break;
  662. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  663. /* GPIO-0 cx24227 demodulator */
  664. /* GPIO-2 xc3028 tuner */
  665. /* Put the parts into reset */
  666. cx_set(GP0_IO, 0x00050000);
  667. cx_clear(GP0_IO, 0x00000005);
  668. msleep(5);
  669. /* Bring the parts out of reset */
  670. cx_set(GP0_IO, 0x00050005);
  671. break;
  672. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  673. /* GPIO-0 cx24227 demodulator reset */
  674. /* GPIO-2 xc5000 tuner reset */
  675. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  676. break;
  677. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  678. /* GPIO-0 656_CLK */
  679. /* GPIO-1 656_D0 */
  680. /* GPIO-2 8295A Reset */
  681. /* GPIO-3-10 cx23417 data0-7 */
  682. /* GPIO-11-14 cx23417 addr0-3 */
  683. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  684. /* GPIO-19 IR_RX */
  685. /* CX23417 GPIO's */
  686. /* EIO15 Zilog Reset */
  687. /* EIO14 S5H1409/CX24227 Reset */
  688. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  689. /* Put the demod into reset and protect the eeprom */
  690. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  691. mdelay(100);
  692. /* Bring the demod and blaster out of reset */
  693. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  694. mdelay(100);
  695. /* Force the TDA8295A into reset and back */
  696. cx23885_gpio_enable(dev, GPIO_2, 1);
  697. cx23885_gpio_set(dev, GPIO_2);
  698. mdelay(20);
  699. cx23885_gpio_clear(dev, GPIO_2);
  700. mdelay(20);
  701. cx23885_gpio_set(dev, GPIO_2);
  702. mdelay(20);
  703. break;
  704. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  705. /* GPIO-0 tda10048 demodulator reset */
  706. /* GPIO-2 tda18271 tuner reset */
  707. /* Put the parts into reset and back */
  708. cx_set(GP0_IO, 0x00050000);
  709. mdelay(20);
  710. cx_clear(GP0_IO, 0x00000005);
  711. mdelay(20);
  712. cx_set(GP0_IO, 0x00050005);
  713. break;
  714. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  715. /* GPIO-0 TDA10048 demodulator reset */
  716. /* GPIO-2 TDA8295A Reset */
  717. /* GPIO-3-10 cx23417 data0-7 */
  718. /* GPIO-11-14 cx23417 addr0-3 */
  719. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  720. /* The following GPIO's are on the interna AVCore (cx25840) */
  721. /* GPIO-19 IR_RX */
  722. /* GPIO-20 IR_TX 416/DVBT Select */
  723. /* GPIO-21 IIS DAT */
  724. /* GPIO-22 IIS WCLK */
  725. /* GPIO-23 IIS BCLK */
  726. /* Put the parts into reset and back */
  727. cx_set(GP0_IO, 0x00050000);
  728. mdelay(20);
  729. cx_clear(GP0_IO, 0x00000005);
  730. mdelay(20);
  731. cx_set(GP0_IO, 0x00050005);
  732. break;
  733. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  734. /* GPIO-0 Dibcom7000p demodulator reset */
  735. /* GPIO-2 xc3028L tuner reset */
  736. /* GPIO-13 LED */
  737. /* Put the parts into reset and back */
  738. cx_set(GP0_IO, 0x00050000);
  739. mdelay(20);
  740. cx_clear(GP0_IO, 0x00000005);
  741. mdelay(20);
  742. cx_set(GP0_IO, 0x00050005);
  743. break;
  744. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  745. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  746. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  747. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  748. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  749. /* Put the parts into reset and back */
  750. cx_set(GP0_IO, 0x000f0000);
  751. mdelay(20);
  752. cx_clear(GP0_IO, 0x0000000f);
  753. mdelay(20);
  754. cx_set(GP0_IO, 0x000f000f);
  755. break;
  756. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  757. /* GPIO-0 portb xc3028 reset */
  758. /* GPIO-1 portb zl10353 reset */
  759. /* GPIO-2 portc xc3028 reset */
  760. /* GPIO-3 portc zl10353 reset */
  761. /* Put the parts into reset and back */
  762. cx_set(GP0_IO, 0x000f0000);
  763. mdelay(20);
  764. cx_clear(GP0_IO, 0x0000000f);
  765. mdelay(20);
  766. cx_set(GP0_IO, 0x000f000f);
  767. break;
  768. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  769. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  770. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  771. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  772. /* GPIO-2 xc3028 tuner reset */
  773. /* The following GPIO's are on the internal AVCore (cx25840) */
  774. /* GPIO-? zl10353 demod reset */
  775. /* Put the parts into reset and back */
  776. cx_set(GP0_IO, 0x00040000);
  777. mdelay(20);
  778. cx_clear(GP0_IO, 0x00000004);
  779. mdelay(20);
  780. cx_set(GP0_IO, 0x00040004);
  781. break;
  782. case CX23885_BOARD_TBS_6920:
  783. cx_write(MC417_CTL, 0x00000036);
  784. cx_write(MC417_OEN, 0x00001000);
  785. cx_set(MC417_RWD, 0x00000002);
  786. mdelay(200);
  787. cx_clear(MC417_RWD, 0x00000800);
  788. mdelay(200);
  789. cx_set(MC417_RWD, 0x00000800);
  790. mdelay(200);
  791. break;
  792. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  793. /* GPIO-0 INTA from CiMax1
  794. GPIO-1 INTB from CiMax2
  795. GPIO-2 reset chips
  796. GPIO-3 to GPIO-10 data/addr for CA
  797. GPIO-11 ~CS0 to CiMax1
  798. GPIO-12 ~CS1 to CiMax2
  799. GPIO-13 ADL0 load LSB addr
  800. GPIO-14 ADL1 load MSB addr
  801. GPIO-15 ~RDY from CiMax
  802. GPIO-17 ~RD to CiMax
  803. GPIO-18 ~WR to CiMax
  804. */
  805. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  806. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  807. cx_clear(GP0_IO, 0x00030004);
  808. mdelay(100);/* reset delay */
  809. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  810. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  811. /* GPIO-15 IN as ~ACK, rest as OUT */
  812. cx_write(MC417_OEN, 0x00001000);
  813. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  814. cx_write(MC417_RWD, 0x0000c300);
  815. /* enable irq */
  816. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  817. break;
  818. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  819. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  820. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  821. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  822. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  823. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  824. /* GPIO-9 Demod reset */
  825. /* Put the parts into reset and back */
  826. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  827. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  828. cx23885_gpio_clear(dev, GPIO_9);
  829. mdelay(20);
  830. cx23885_gpio_set(dev, GPIO_9);
  831. break;
  832. case CX23885_BOARD_MYGICA_X8506:
  833. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  834. /* GPIO-0 (0)Analog / (1)Digital TV */
  835. /* GPIO-1 reset XC5000 */
  836. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  837. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  838. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  839. mdelay(100);
  840. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  841. mdelay(100);
  842. break;
  843. case CX23885_BOARD_MYGICA_X8558PRO:
  844. /* GPIO-0 reset first ATBM8830 */
  845. /* GPIO-1 reset second ATBM8830 */
  846. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  847. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  848. mdelay(100);
  849. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  850. mdelay(100);
  851. break;
  852. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  853. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  854. /* GPIO-0 656_CLK */
  855. /* GPIO-1 656_D0 */
  856. /* GPIO-2 Wake# */
  857. /* GPIO-3-10 cx23417 data0-7 */
  858. /* GPIO-11-14 cx23417 addr0-3 */
  859. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  860. /* GPIO-19 IR_RX */
  861. /* GPIO-20 C_IR_TX */
  862. /* GPIO-21 I2S DAT */
  863. /* GPIO-22 I2S WCLK */
  864. /* GPIO-23 I2S BCLK */
  865. /* ALT GPIO: EXP GPIO LATCH */
  866. /* CX23417 GPIO's */
  867. /* GPIO-14 S5H1411/CX24228 Reset */
  868. /* GPIO-13 EEPROM write protect */
  869. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  870. /* Put the demod into reset and protect the eeprom */
  871. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  872. mdelay(100);
  873. /* Bring the demod out of reset */
  874. mc417_gpio_set(dev, GPIO_14);
  875. mdelay(100);
  876. /* CX24228 GPIO */
  877. /* Connected to IF / Mux */
  878. break;
  879. }
  880. }
  881. int cx23885_ir_init(struct cx23885_dev *dev)
  882. {
  883. int ret = 0;
  884. switch (dev->board) {
  885. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  886. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  887. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  888. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  889. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  890. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  891. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  892. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  893. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  894. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  895. /* FIXME: Implement me */
  896. break;
  897. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  898. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  899. ret = cx23888_ir_probe(dev);
  900. if (ret)
  901. break;
  902. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  903. dev->pci_irqmask |= PCI_MSK_IR;
  904. break;
  905. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  906. request_module("ir-kbd-i2c");
  907. break;
  908. }
  909. return ret;
  910. }
  911. void cx23885_ir_fini(struct cx23885_dev *dev)
  912. {
  913. switch (dev->board) {
  914. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  915. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  916. dev->pci_irqmask &= ~PCI_MSK_IR;
  917. cx_clear(PCI_INT_MSK, PCI_MSK_IR);
  918. cx23888_ir_remove(dev);
  919. dev->sd_ir = NULL;
  920. break;
  921. }
  922. }
  923. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  924. {
  925. switch (dev->board) {
  926. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  927. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  928. if (dev->sd_ir && (dev->pci_irqmask & PCI_MSK_IR))
  929. cx_set(PCI_INT_MSK, PCI_MSK_IR);
  930. break;
  931. }
  932. }
  933. void cx23885_card_setup(struct cx23885_dev *dev)
  934. {
  935. struct cx23885_tsport *ts1 = &dev->ts1;
  936. struct cx23885_tsport *ts2 = &dev->ts2;
  937. static u8 eeprom[256];
  938. if (dev->i2c_bus[0].i2c_rc == 0) {
  939. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  940. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  941. eeprom, sizeof(eeprom));
  942. }
  943. switch (dev->board) {
  944. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  945. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  946. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  947. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  948. if (dev->i2c_bus[0].i2c_rc == 0)
  949. hauppauge_eeprom(dev, eeprom+0x80);
  950. break;
  951. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  952. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  953. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  954. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  955. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  956. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  957. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  958. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  959. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  960. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  961. if (dev->i2c_bus[0].i2c_rc == 0)
  962. hauppauge_eeprom(dev, eeprom+0xc0);
  963. break;
  964. }
  965. switch (dev->board) {
  966. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  967. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  968. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  969. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  970. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  971. /* break omitted intentionally */
  972. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  973. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  974. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  975. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  976. break;
  977. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  978. /* Defaults for VID B - Analog encoder */
  979. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  980. ts1->gen_ctrl_val = 0x10e;
  981. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  982. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  983. /* APB_TSVALERR_POL (active low)*/
  984. ts1->vld_misc_val = 0x2000;
  985. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  986. /* Defaults for VID C */
  987. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  988. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  989. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  990. break;
  991. case CX23885_BOARD_TBS_6920:
  992. ts1->gen_ctrl_val = 0x4; /* Parallel */
  993. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  994. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  995. break;
  996. case CX23885_BOARD_TEVII_S470:
  997. case CX23885_BOARD_DVBWORLD_2005:
  998. ts1->gen_ctrl_val = 0x5; /* Parallel */
  999. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1000. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1001. break;
  1002. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1003. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1004. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1005. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1006. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1007. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1008. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1009. break;
  1010. case CX23885_BOARD_MYGICA_X8506:
  1011. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1012. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1013. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1014. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1015. break;
  1016. case CX23885_BOARD_MYGICA_X8558PRO:
  1017. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1018. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1019. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1020. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1021. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1022. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1023. break;
  1024. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1025. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1026. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1027. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1028. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1029. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1030. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1031. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1032. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1033. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1034. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1035. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1036. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1037. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1038. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1039. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1040. default:
  1041. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1042. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1043. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1044. }
  1045. /* Certain boards support analog, or require the avcore to be
  1046. * loaded, ensure this happens.
  1047. */
  1048. switch (dev->board) {
  1049. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1050. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1051. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1052. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1053. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1054. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1055. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1056. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1057. case CX23885_BOARD_MYGICA_X8506:
  1058. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1059. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1060. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1061. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1062. &dev->i2c_bus[2].i2c_adap,
  1063. "cx25840", "cx25840", 0x88 >> 1, NULL);
  1064. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1065. break;
  1066. }
  1067. /* AUX-PLL 27MHz CLK */
  1068. switch (dev->board) {
  1069. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1070. netup_initialize(dev);
  1071. break;
  1072. }
  1073. }
  1074. /* ------------------------------------------------------------------ */