ad5421.c 13 KB

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  1. /*
  2. * AD5421 Digital to analog converters driver
  3. *
  4. * Copyright 2011 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/slab.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/sysfs.h>
  19. #include <linux/iio/events.h>
  20. #include <linux/iio/dac/ad5421.h>
  21. #define AD5421_REG_DAC_DATA 0x1
  22. #define AD5421_REG_CTRL 0x2
  23. #define AD5421_REG_OFFSET 0x3
  24. #define AD5421_REG_GAIN 0x4
  25. /* load dac and fault shared the same register number. Writing to it will cause
  26. * a dac load command, reading from it will return the fault status register */
  27. #define AD5421_REG_LOAD_DAC 0x5
  28. #define AD5421_REG_FAULT 0x5
  29. #define AD5421_REG_FORCE_ALARM_CURRENT 0x6
  30. #define AD5421_REG_RESET 0x7
  31. #define AD5421_REG_START_CONVERSION 0x8
  32. #define AD5421_REG_NOOP 0x9
  33. #define AD5421_CTRL_WATCHDOG_DISABLE BIT(12)
  34. #define AD5421_CTRL_AUTO_FAULT_READBACK BIT(11)
  35. #define AD5421_CTRL_MIN_CURRENT BIT(9)
  36. #define AD5421_CTRL_ADC_SOURCE_TEMP BIT(8)
  37. #define AD5421_CTRL_ADC_ENABLE BIT(7)
  38. #define AD5421_CTRL_PWR_DOWN_INT_VREF BIT(6)
  39. #define AD5421_FAULT_SPI BIT(15)
  40. #define AD5421_FAULT_PEC BIT(14)
  41. #define AD5421_FAULT_OVER_CURRENT BIT(13)
  42. #define AD5421_FAULT_UNDER_CURRENT BIT(12)
  43. #define AD5421_FAULT_TEMP_OVER_140 BIT(11)
  44. #define AD5421_FAULT_TEMP_OVER_100 BIT(10)
  45. #define AD5421_FAULT_UNDER_VOLTAGE_6V BIT(9)
  46. #define AD5421_FAULT_UNDER_VOLTAGE_12V BIT(8)
  47. /* These bits will cause the fault pin to go high */
  48. #define AD5421_FAULT_TRIGGER_IRQ \
  49. (AD5421_FAULT_SPI | AD5421_FAULT_PEC | AD5421_FAULT_OVER_CURRENT | \
  50. AD5421_FAULT_UNDER_CURRENT | AD5421_FAULT_TEMP_OVER_140)
  51. /**
  52. * struct ad5421_state - driver instance specific data
  53. * @spi: spi_device
  54. * @ctrl: control register cache
  55. * @current_range: current range which the device is configured for
  56. * @data: spi transfer buffers
  57. * @fault_mask: software masking of events
  58. */
  59. struct ad5421_state {
  60. struct spi_device *spi;
  61. unsigned int ctrl;
  62. enum ad5421_current_range current_range;
  63. unsigned int fault_mask;
  64. /*
  65. * DMA (thus cache coherency maintenance) requires the
  66. * transfer buffers to live in their own cache lines.
  67. */
  68. union {
  69. u32 d32;
  70. u8 d8[4];
  71. } data[2] ____cacheline_aligned;
  72. };
  73. static const struct iio_event_spec ad5421_current_event[] = {
  74. {
  75. .type = IIO_EV_TYPE_THRESH,
  76. .dir = IIO_EV_DIR_RISING,
  77. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  78. BIT(IIO_EV_INFO_ENABLE),
  79. }, {
  80. .type = IIO_EV_TYPE_THRESH,
  81. .dir = IIO_EV_DIR_FALLING,
  82. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  83. BIT(IIO_EV_INFO_ENABLE),
  84. },
  85. };
  86. static const struct iio_event_spec ad5421_temp_event[] = {
  87. {
  88. .type = IIO_EV_TYPE_THRESH,
  89. .dir = IIO_EV_DIR_RISING,
  90. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  91. BIT(IIO_EV_INFO_ENABLE),
  92. },
  93. };
  94. static const struct iio_chan_spec ad5421_channels[] = {
  95. {
  96. .type = IIO_CURRENT,
  97. .indexed = 1,
  98. .output = 1,
  99. .channel = 0,
  100. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  101. BIT(IIO_CHAN_INFO_CALIBSCALE) |
  102. BIT(IIO_CHAN_INFO_CALIBBIAS),
  103. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
  104. BIT(IIO_CHAN_INFO_OFFSET),
  105. .scan_type = IIO_ST('u', 16, 16, 0),
  106. .event_spec = ad5421_current_event,
  107. .num_event_specs = ARRAY_SIZE(ad5421_current_event),
  108. },
  109. {
  110. .type = IIO_TEMP,
  111. .channel = -1,
  112. .event_spec = ad5421_temp_event,
  113. .num_event_specs = ARRAY_SIZE(ad5421_temp_event),
  114. },
  115. };
  116. static int ad5421_write_unlocked(struct iio_dev *indio_dev,
  117. unsigned int reg, unsigned int val)
  118. {
  119. struct ad5421_state *st = iio_priv(indio_dev);
  120. st->data[0].d32 = cpu_to_be32((reg << 16) | val);
  121. return spi_write(st->spi, &st->data[0].d8[1], 3);
  122. }
  123. static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg,
  124. unsigned int val)
  125. {
  126. int ret;
  127. mutex_lock(&indio_dev->mlock);
  128. ret = ad5421_write_unlocked(indio_dev, reg, val);
  129. mutex_unlock(&indio_dev->mlock);
  130. return ret;
  131. }
  132. static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg)
  133. {
  134. struct ad5421_state *st = iio_priv(indio_dev);
  135. int ret;
  136. struct spi_transfer t[] = {
  137. {
  138. .tx_buf = &st->data[0].d8[1],
  139. .len = 3,
  140. .cs_change = 1,
  141. }, {
  142. .rx_buf = &st->data[1].d8[1],
  143. .len = 3,
  144. },
  145. };
  146. mutex_lock(&indio_dev->mlock);
  147. st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
  148. ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
  149. if (ret >= 0)
  150. ret = be32_to_cpu(st->data[1].d32) & 0xffff;
  151. mutex_unlock(&indio_dev->mlock);
  152. return ret;
  153. }
  154. static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
  155. unsigned int clr)
  156. {
  157. struct ad5421_state *st = iio_priv(indio_dev);
  158. unsigned int ret;
  159. mutex_lock(&indio_dev->mlock);
  160. st->ctrl &= ~clr;
  161. st->ctrl |= set;
  162. ret = ad5421_write_unlocked(indio_dev, AD5421_REG_CTRL, st->ctrl);
  163. mutex_unlock(&indio_dev->mlock);
  164. return ret;
  165. }
  166. static irqreturn_t ad5421_fault_handler(int irq, void *data)
  167. {
  168. struct iio_dev *indio_dev = data;
  169. struct ad5421_state *st = iio_priv(indio_dev);
  170. unsigned int fault;
  171. unsigned int old_fault = 0;
  172. unsigned int events;
  173. fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
  174. if (!fault)
  175. return IRQ_NONE;
  176. /* If we had a fault, this might mean that the DAC has lost its state
  177. * and has been reset. Make sure that the control register actually
  178. * contains what we expect it to contain. Otherwise the watchdog might
  179. * be enabled and we get watchdog timeout faults, which will render the
  180. * DAC unusable. */
  181. ad5421_update_ctrl(indio_dev, 0, 0);
  182. /* The fault pin stays high as long as a fault condition is present and
  183. * it is not possible to mask fault conditions. For certain fault
  184. * conditions for example like over-temperature it takes some time
  185. * until the fault condition disappears. If we would exit the interrupt
  186. * handler immediately after handling the event it would be entered
  187. * again instantly. Thus we fall back to polling in case we detect that
  188. * a interrupt condition is still present.
  189. */
  190. do {
  191. /* 0xffff is a invalid value for the register and will only be
  192. * read if there has been a communication error */
  193. if (fault == 0xffff)
  194. fault = 0;
  195. /* we are only interested in new events */
  196. events = (old_fault ^ fault) & fault;
  197. events &= st->fault_mask;
  198. if (events & AD5421_FAULT_OVER_CURRENT) {
  199. iio_push_event(indio_dev,
  200. IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
  201. 0,
  202. IIO_EV_TYPE_THRESH,
  203. IIO_EV_DIR_RISING),
  204. iio_get_time_ns());
  205. }
  206. if (events & AD5421_FAULT_UNDER_CURRENT) {
  207. iio_push_event(indio_dev,
  208. IIO_UNMOD_EVENT_CODE(IIO_CURRENT,
  209. 0,
  210. IIO_EV_TYPE_THRESH,
  211. IIO_EV_DIR_FALLING),
  212. iio_get_time_ns());
  213. }
  214. if (events & AD5421_FAULT_TEMP_OVER_140) {
  215. iio_push_event(indio_dev,
  216. IIO_UNMOD_EVENT_CODE(IIO_TEMP,
  217. 0,
  218. IIO_EV_TYPE_MAG,
  219. IIO_EV_DIR_RISING),
  220. iio_get_time_ns());
  221. }
  222. old_fault = fault;
  223. fault = ad5421_read(indio_dev, AD5421_REG_FAULT);
  224. /* still active? go to sleep for some time */
  225. if (fault & AD5421_FAULT_TRIGGER_IRQ)
  226. msleep(1000);
  227. } while (fault & AD5421_FAULT_TRIGGER_IRQ);
  228. return IRQ_HANDLED;
  229. }
  230. static void ad5421_get_current_min_max(struct ad5421_state *st,
  231. unsigned int *min, unsigned int *max)
  232. {
  233. /* The current range is configured using external pins, which are
  234. * usually hard-wired and not run-time switchable. */
  235. switch (st->current_range) {
  236. case AD5421_CURRENT_RANGE_4mA_20mA:
  237. *min = 4000;
  238. *max = 20000;
  239. break;
  240. case AD5421_CURRENT_RANGE_3mA8_21mA:
  241. *min = 3800;
  242. *max = 21000;
  243. break;
  244. case AD5421_CURRENT_RANGE_3mA2_24mA:
  245. *min = 3200;
  246. *max = 24000;
  247. break;
  248. default:
  249. *min = 0;
  250. *max = 1;
  251. break;
  252. }
  253. }
  254. static inline unsigned int ad5421_get_offset(struct ad5421_state *st)
  255. {
  256. unsigned int min, max;
  257. ad5421_get_current_min_max(st, &min, &max);
  258. return (min * (1 << 16)) / (max - min);
  259. }
  260. static int ad5421_read_raw(struct iio_dev *indio_dev,
  261. struct iio_chan_spec const *chan, int *val, int *val2, long m)
  262. {
  263. struct ad5421_state *st = iio_priv(indio_dev);
  264. unsigned int min, max;
  265. int ret;
  266. if (chan->type != IIO_CURRENT)
  267. return -EINVAL;
  268. switch (m) {
  269. case IIO_CHAN_INFO_RAW:
  270. ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
  271. if (ret < 0)
  272. return ret;
  273. *val = ret;
  274. return IIO_VAL_INT;
  275. case IIO_CHAN_INFO_SCALE:
  276. ad5421_get_current_min_max(st, &min, &max);
  277. *val = max - min;
  278. *val2 = (1 << 16) * 1000;
  279. return IIO_VAL_FRACTIONAL;
  280. case IIO_CHAN_INFO_OFFSET:
  281. *val = ad5421_get_offset(st);
  282. return IIO_VAL_INT;
  283. case IIO_CHAN_INFO_CALIBBIAS:
  284. ret = ad5421_read(indio_dev, AD5421_REG_OFFSET);
  285. if (ret < 0)
  286. return ret;
  287. *val = ret - 32768;
  288. return IIO_VAL_INT;
  289. case IIO_CHAN_INFO_CALIBSCALE:
  290. ret = ad5421_read(indio_dev, AD5421_REG_GAIN);
  291. if (ret < 0)
  292. return ret;
  293. *val = ret;
  294. return IIO_VAL_INT;
  295. }
  296. return -EINVAL;
  297. }
  298. static int ad5421_write_raw(struct iio_dev *indio_dev,
  299. struct iio_chan_spec const *chan, int val, int val2, long mask)
  300. {
  301. const unsigned int max_val = 1 << 16;
  302. switch (mask) {
  303. case IIO_CHAN_INFO_RAW:
  304. if (val >= max_val || val < 0)
  305. return -EINVAL;
  306. return ad5421_write(indio_dev, AD5421_REG_DAC_DATA, val);
  307. case IIO_CHAN_INFO_CALIBBIAS:
  308. val += 32768;
  309. if (val >= max_val || val < 0)
  310. return -EINVAL;
  311. return ad5421_write(indio_dev, AD5421_REG_OFFSET, val);
  312. case IIO_CHAN_INFO_CALIBSCALE:
  313. if (val >= max_val || val < 0)
  314. return -EINVAL;
  315. return ad5421_write(indio_dev, AD5421_REG_GAIN, val);
  316. default:
  317. break;
  318. }
  319. return -EINVAL;
  320. }
  321. static int ad5421_write_event_config(struct iio_dev *indio_dev,
  322. const struct iio_chan_spec *chan, enum iio_event_type type,
  323. enum iio_event_direction dir, int state)
  324. {
  325. struct ad5421_state *st = iio_priv(indio_dev);
  326. unsigned int mask;
  327. switch (chan->type) {
  328. case IIO_CURRENT:
  329. if (dir == IIO_EV_DIR_RISING)
  330. mask = AD5421_FAULT_OVER_CURRENT;
  331. else
  332. mask = AD5421_FAULT_UNDER_CURRENT;
  333. break;
  334. case IIO_TEMP:
  335. mask = AD5421_FAULT_TEMP_OVER_140;
  336. break;
  337. default:
  338. return -EINVAL;
  339. }
  340. mutex_lock(&indio_dev->mlock);
  341. if (state)
  342. st->fault_mask |= mask;
  343. else
  344. st->fault_mask &= ~mask;
  345. mutex_unlock(&indio_dev->mlock);
  346. return 0;
  347. }
  348. static int ad5421_read_event_config(struct iio_dev *indio_dev,
  349. const struct iio_chan_spec *chan, enum iio_event_type type,
  350. enum iio_event_direction dir)
  351. {
  352. struct ad5421_state *st = iio_priv(indio_dev);
  353. unsigned int mask;
  354. switch (chan->type) {
  355. case IIO_CURRENT:
  356. if (dir == IIO_EV_DIR_RISING)
  357. mask = AD5421_FAULT_OVER_CURRENT;
  358. else
  359. mask = AD5421_FAULT_UNDER_CURRENT;
  360. break;
  361. case IIO_TEMP:
  362. mask = AD5421_FAULT_TEMP_OVER_140;
  363. break;
  364. default:
  365. return -EINVAL;
  366. }
  367. return (bool)(st->fault_mask & mask);
  368. }
  369. static int ad5421_read_event_value(struct iio_dev *indio_dev,
  370. const struct iio_chan_spec *chan, enum iio_event_type type,
  371. enum iio_event_direction dir, enum iio_event_info info, int *val,
  372. int *val2)
  373. {
  374. int ret;
  375. switch (chan->type) {
  376. case IIO_CURRENT:
  377. ret = ad5421_read(indio_dev, AD5421_REG_DAC_DATA);
  378. if (ret < 0)
  379. return ret;
  380. *val = ret;
  381. break;
  382. case IIO_TEMP:
  383. *val = 140000;
  384. break;
  385. default:
  386. return -EINVAL;
  387. }
  388. return IIO_VAL_INT;
  389. }
  390. static const struct iio_info ad5421_info = {
  391. .read_raw = ad5421_read_raw,
  392. .write_raw = ad5421_write_raw,
  393. .read_event_config_new = ad5421_read_event_config,
  394. .write_event_config_new = ad5421_write_event_config,
  395. .read_event_value_new = ad5421_read_event_value,
  396. .driver_module = THIS_MODULE,
  397. };
  398. static int ad5421_probe(struct spi_device *spi)
  399. {
  400. struct ad5421_platform_data *pdata = dev_get_platdata(&spi->dev);
  401. struct iio_dev *indio_dev;
  402. struct ad5421_state *st;
  403. int ret;
  404. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  405. if (indio_dev == NULL) {
  406. dev_err(&spi->dev, "Failed to allocate iio device\n");
  407. return -ENOMEM;
  408. }
  409. st = iio_priv(indio_dev);
  410. spi_set_drvdata(spi, indio_dev);
  411. st->spi = spi;
  412. indio_dev->dev.parent = &spi->dev;
  413. indio_dev->name = "ad5421";
  414. indio_dev->info = &ad5421_info;
  415. indio_dev->modes = INDIO_DIRECT_MODE;
  416. indio_dev->channels = ad5421_channels;
  417. indio_dev->num_channels = ARRAY_SIZE(ad5421_channels);
  418. st->ctrl = AD5421_CTRL_WATCHDOG_DISABLE |
  419. AD5421_CTRL_AUTO_FAULT_READBACK;
  420. if (pdata) {
  421. st->current_range = pdata->current_range;
  422. if (pdata->external_vref)
  423. st->ctrl |= AD5421_CTRL_PWR_DOWN_INT_VREF;
  424. } else {
  425. st->current_range = AD5421_CURRENT_RANGE_4mA_20mA;
  426. }
  427. /* write initial ctrl register value */
  428. ad5421_update_ctrl(indio_dev, 0, 0);
  429. if (spi->irq) {
  430. ret = devm_request_threaded_irq(&spi->dev, spi->irq,
  431. NULL,
  432. ad5421_fault_handler,
  433. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  434. "ad5421 fault",
  435. indio_dev);
  436. if (ret)
  437. return ret;
  438. }
  439. return iio_device_register(indio_dev);
  440. }
  441. static int ad5421_remove(struct spi_device *spi)
  442. {
  443. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  444. iio_device_unregister(indio_dev);
  445. return 0;
  446. }
  447. static struct spi_driver ad5421_driver = {
  448. .driver = {
  449. .name = "ad5421",
  450. .owner = THIS_MODULE,
  451. },
  452. .probe = ad5421_probe,
  453. .remove = ad5421_remove,
  454. };
  455. module_spi_driver(ad5421_driver);
  456. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  457. MODULE_DESCRIPTION("Analog Devices AD5421 DAC");
  458. MODULE_LICENSE("GPL v2");
  459. MODULE_ALIAS("spi:ad5421");