spu_base.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893
  1. /*
  2. * Low-level SPU handling
  3. *
  4. * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
  5. *
  6. * Author: Arnd Bergmann <arndb@de.ibm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #undef DEBUG
  23. #include <linux/interrupt.h>
  24. #include <linux/list.h>
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/poll.h>
  28. #include <linux/ptrace.h>
  29. #include <linux/slab.h>
  30. #include <linux/wait.h>
  31. #include <asm/firmware.h>
  32. #include <asm/io.h>
  33. #include <asm/prom.h>
  34. #include <linux/mutex.h>
  35. #include <asm/spu.h>
  36. #include <asm/spu_priv1.h>
  37. #include <asm/mmu_context.h>
  38. #include "interrupt.h"
  39. const struct spu_priv1_ops *spu_priv1_ops;
  40. EXPORT_SYMBOL_GPL(spu_priv1_ops);
  41. static int __spu_trap_invalid_dma(struct spu *spu)
  42. {
  43. pr_debug("%s\n", __FUNCTION__);
  44. spu->dma_callback(spu, SPE_EVENT_INVALID_DMA);
  45. return 0;
  46. }
  47. static int __spu_trap_dma_align(struct spu *spu)
  48. {
  49. pr_debug("%s\n", __FUNCTION__);
  50. spu->dma_callback(spu, SPE_EVENT_DMA_ALIGNMENT);
  51. return 0;
  52. }
  53. static int __spu_trap_error(struct spu *spu)
  54. {
  55. pr_debug("%s\n", __FUNCTION__);
  56. spu->dma_callback(spu, SPE_EVENT_SPE_ERROR);
  57. return 0;
  58. }
  59. static void spu_restart_dma(struct spu *spu)
  60. {
  61. struct spu_priv2 __iomem *priv2 = spu->priv2;
  62. if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
  63. out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
  64. }
  65. static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
  66. {
  67. struct spu_priv2 __iomem *priv2 = spu->priv2;
  68. struct mm_struct *mm = spu->mm;
  69. u64 esid, vsid, llp;
  70. pr_debug("%s\n", __FUNCTION__);
  71. if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
  72. /* SLBs are pre-loaded for context switch, so
  73. * we should never get here!
  74. */
  75. printk("%s: invalid access during switch!\n", __func__);
  76. return 1;
  77. }
  78. esid = (ea & ESID_MASK) | SLB_ESID_V;
  79. switch(REGION_ID(ea)) {
  80. case USER_REGION_ID:
  81. #ifdef CONFIG_HUGETLB_PAGE
  82. if (in_hugepage_area(mm->context, ea))
  83. llp = mmu_psize_defs[mmu_huge_psize].sllp;
  84. else
  85. #endif
  86. llp = mmu_psize_defs[mmu_virtual_psize].sllp;
  87. vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) |
  88. SLB_VSID_USER | llp;
  89. break;
  90. case VMALLOC_REGION_ID:
  91. llp = mmu_psize_defs[mmu_virtual_psize].sllp;
  92. vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
  93. SLB_VSID_KERNEL | llp;
  94. break;
  95. case KERNEL_REGION_ID:
  96. llp = mmu_psize_defs[mmu_linear_psize].sllp;
  97. vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
  98. SLB_VSID_KERNEL | llp;
  99. break;
  100. default:
  101. /* Future: support kernel segments so that drivers
  102. * can use SPUs.
  103. */
  104. pr_debug("invalid region access at %016lx\n", ea);
  105. return 1;
  106. }
  107. out_be64(&priv2->slb_index_W, spu->slb_replace);
  108. out_be64(&priv2->slb_vsid_RW, vsid);
  109. out_be64(&priv2->slb_esid_RW, esid);
  110. spu->slb_replace++;
  111. if (spu->slb_replace >= 8)
  112. spu->slb_replace = 0;
  113. spu_restart_dma(spu);
  114. return 0;
  115. }
  116. extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
  117. static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
  118. {
  119. pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
  120. /* Handle kernel space hash faults immediately.
  121. User hash faults need to be deferred to process context. */
  122. if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
  123. && REGION_ID(ea) != USER_REGION_ID
  124. && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
  125. spu_restart_dma(spu);
  126. return 0;
  127. }
  128. if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
  129. printk("%s: invalid access during switch!\n", __func__);
  130. return 1;
  131. }
  132. spu->dar = ea;
  133. spu->dsisr = dsisr;
  134. mb();
  135. spu->stop_callback(spu);
  136. return 0;
  137. }
  138. static irqreturn_t
  139. spu_irq_class_0(int irq, void *data)
  140. {
  141. struct spu *spu;
  142. spu = data;
  143. spu->class_0_pending = 1;
  144. spu->stop_callback(spu);
  145. return IRQ_HANDLED;
  146. }
  147. int
  148. spu_irq_class_0_bottom(struct spu *spu)
  149. {
  150. unsigned long stat, mask;
  151. spu->class_0_pending = 0;
  152. mask = spu_int_mask_get(spu, 0);
  153. stat = spu_int_stat_get(spu, 0);
  154. stat &= mask;
  155. if (stat & 1) /* invalid DMA alignment */
  156. __spu_trap_dma_align(spu);
  157. if (stat & 2) /* invalid MFC DMA */
  158. __spu_trap_invalid_dma(spu);
  159. if (stat & 4) /* error on SPU */
  160. __spu_trap_error(spu);
  161. spu_int_stat_clear(spu, 0, stat);
  162. return (stat & 0x7) ? -EIO : 0;
  163. }
  164. EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
  165. static irqreturn_t
  166. spu_irq_class_1(int irq, void *data)
  167. {
  168. struct spu *spu;
  169. unsigned long stat, mask, dar, dsisr;
  170. spu = data;
  171. /* atomically read & clear class1 status. */
  172. spin_lock(&spu->register_lock);
  173. mask = spu_int_mask_get(spu, 1);
  174. stat = spu_int_stat_get(spu, 1) & mask;
  175. dar = spu_mfc_dar_get(spu);
  176. dsisr = spu_mfc_dsisr_get(spu);
  177. if (stat & 2) /* mapping fault */
  178. spu_mfc_dsisr_set(spu, 0ul);
  179. spu_int_stat_clear(spu, 1, stat);
  180. spin_unlock(&spu->register_lock);
  181. pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
  182. dar, dsisr);
  183. if (stat & 1) /* segment fault */
  184. __spu_trap_data_seg(spu, dar);
  185. if (stat & 2) { /* mapping fault */
  186. __spu_trap_data_map(spu, dar, dsisr);
  187. }
  188. if (stat & 4) /* ls compare & suspend on get */
  189. ;
  190. if (stat & 8) /* ls compare & suspend on put */
  191. ;
  192. return stat ? IRQ_HANDLED : IRQ_NONE;
  193. }
  194. EXPORT_SYMBOL_GPL(spu_irq_class_1_bottom);
  195. static irqreturn_t
  196. spu_irq_class_2(int irq, void *data)
  197. {
  198. struct spu *spu;
  199. unsigned long stat;
  200. unsigned long mask;
  201. spu = data;
  202. spin_lock(&spu->register_lock);
  203. stat = spu_int_stat_get(spu, 2);
  204. mask = spu_int_mask_get(spu, 2);
  205. /* ignore interrupts we're not waiting for */
  206. stat &= mask;
  207. /*
  208. * mailbox interrupts (0x1 and 0x10) are level triggered.
  209. * mask them now before acknowledging.
  210. */
  211. if (stat & 0x11)
  212. spu_int_mask_and(spu, 2, ~(stat & 0x11));
  213. /* acknowledge all interrupts before the callbacks */
  214. spu_int_stat_clear(spu, 2, stat);
  215. spin_unlock(&spu->register_lock);
  216. pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
  217. if (stat & 1) /* PPC core mailbox */
  218. spu->ibox_callback(spu);
  219. if (stat & 2) /* SPU stop-and-signal */
  220. spu->stop_callback(spu);
  221. if (stat & 4) /* SPU halted */
  222. spu->stop_callback(spu);
  223. if (stat & 8) /* DMA tag group complete */
  224. spu->mfc_callback(spu);
  225. if (stat & 0x10) /* SPU mailbox threshold */
  226. spu->wbox_callback(spu);
  227. return stat ? IRQ_HANDLED : IRQ_NONE;
  228. }
  229. static int spu_request_irqs(struct spu *spu)
  230. {
  231. int ret = 0;
  232. if (spu->irqs[0] != NO_IRQ) {
  233. snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
  234. spu->number);
  235. ret = request_irq(spu->irqs[0], spu_irq_class_0,
  236. IRQF_DISABLED,
  237. spu->irq_c0, spu);
  238. if (ret)
  239. goto bail0;
  240. }
  241. if (spu->irqs[1] != NO_IRQ) {
  242. snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
  243. spu->number);
  244. ret = request_irq(spu->irqs[1], spu_irq_class_1,
  245. IRQF_DISABLED,
  246. spu->irq_c1, spu);
  247. if (ret)
  248. goto bail1;
  249. }
  250. if (spu->irqs[2] != NO_IRQ) {
  251. snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
  252. spu->number);
  253. ret = request_irq(spu->irqs[2], spu_irq_class_2,
  254. IRQF_DISABLED,
  255. spu->irq_c2, spu);
  256. if (ret)
  257. goto bail2;
  258. }
  259. return 0;
  260. bail2:
  261. if (spu->irqs[1] != NO_IRQ)
  262. free_irq(spu->irqs[1], spu);
  263. bail1:
  264. if (spu->irqs[0] != NO_IRQ)
  265. free_irq(spu->irqs[0], spu);
  266. bail0:
  267. return ret;
  268. }
  269. static void spu_free_irqs(struct spu *spu)
  270. {
  271. if (spu->irqs[0] != NO_IRQ)
  272. free_irq(spu->irqs[0], spu);
  273. if (spu->irqs[1] != NO_IRQ)
  274. free_irq(spu->irqs[1], spu);
  275. if (spu->irqs[2] != NO_IRQ)
  276. free_irq(spu->irqs[2], spu);
  277. }
  278. static struct list_head spu_list[MAX_NUMNODES];
  279. static DEFINE_MUTEX(spu_mutex);
  280. static void spu_init_channels(struct spu *spu)
  281. {
  282. static const struct {
  283. unsigned channel;
  284. unsigned count;
  285. } zero_list[] = {
  286. { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
  287. { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
  288. }, count_list[] = {
  289. { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
  290. { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
  291. { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
  292. };
  293. struct spu_priv2 __iomem *priv2;
  294. int i;
  295. priv2 = spu->priv2;
  296. /* initialize all channel data to zero */
  297. for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
  298. int count;
  299. out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
  300. for (count = 0; count < zero_list[i].count; count++)
  301. out_be64(&priv2->spu_chnldata_RW, 0);
  302. }
  303. /* initialize channel counts to meaningful values */
  304. for (i = 0; i < ARRAY_SIZE(count_list); i++) {
  305. out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
  306. out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
  307. }
  308. }
  309. struct spu *spu_alloc_node(int node)
  310. {
  311. struct spu *spu = NULL;
  312. mutex_lock(&spu_mutex);
  313. if (!list_empty(&spu_list[node])) {
  314. spu = list_entry(spu_list[node].next, struct spu, list);
  315. list_del_init(&spu->list);
  316. pr_debug("Got SPU %d %d\n", spu->number, spu->node);
  317. spu_init_channels(spu);
  318. }
  319. mutex_unlock(&spu_mutex);
  320. return spu;
  321. }
  322. EXPORT_SYMBOL_GPL(spu_alloc_node);
  323. struct spu *spu_alloc(void)
  324. {
  325. struct spu *spu = NULL;
  326. int node;
  327. for (node = 0; node < MAX_NUMNODES; node++) {
  328. spu = spu_alloc_node(node);
  329. if (spu)
  330. break;
  331. }
  332. return spu;
  333. }
  334. void spu_free(struct spu *spu)
  335. {
  336. mutex_lock(&spu_mutex);
  337. list_add_tail(&spu->list, &spu_list[spu->node]);
  338. mutex_unlock(&spu_mutex);
  339. }
  340. EXPORT_SYMBOL_GPL(spu_free);
  341. static int spu_handle_mm_fault(struct spu *spu)
  342. {
  343. struct mm_struct *mm = spu->mm;
  344. struct vm_area_struct *vma;
  345. u64 ea, dsisr, is_write;
  346. int ret;
  347. ea = spu->dar;
  348. dsisr = spu->dsisr;
  349. #if 0
  350. if (!IS_VALID_EA(ea)) {
  351. return -EFAULT;
  352. }
  353. #endif /* XXX */
  354. if (mm == NULL) {
  355. return -EFAULT;
  356. }
  357. if (mm->pgd == NULL) {
  358. return -EFAULT;
  359. }
  360. down_read(&mm->mmap_sem);
  361. vma = find_vma(mm, ea);
  362. if (!vma)
  363. goto bad_area;
  364. if (vma->vm_start <= ea)
  365. goto good_area;
  366. if (!(vma->vm_flags & VM_GROWSDOWN))
  367. goto bad_area;
  368. #if 0
  369. if (expand_stack(vma, ea))
  370. goto bad_area;
  371. #endif /* XXX */
  372. good_area:
  373. is_write = dsisr & MFC_DSISR_ACCESS_PUT;
  374. if (is_write) {
  375. if (!(vma->vm_flags & VM_WRITE))
  376. goto bad_area;
  377. } else {
  378. if (dsisr & MFC_DSISR_ACCESS_DENIED)
  379. goto bad_area;
  380. if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
  381. goto bad_area;
  382. }
  383. ret = 0;
  384. switch (handle_mm_fault(mm, vma, ea, is_write)) {
  385. case VM_FAULT_MINOR:
  386. current->min_flt++;
  387. break;
  388. case VM_FAULT_MAJOR:
  389. current->maj_flt++;
  390. break;
  391. case VM_FAULT_SIGBUS:
  392. ret = -EFAULT;
  393. goto bad_area;
  394. case VM_FAULT_OOM:
  395. ret = -ENOMEM;
  396. goto bad_area;
  397. default:
  398. BUG();
  399. }
  400. up_read(&mm->mmap_sem);
  401. return ret;
  402. bad_area:
  403. up_read(&mm->mmap_sem);
  404. return -EFAULT;
  405. }
  406. int spu_irq_class_1_bottom(struct spu *spu)
  407. {
  408. u64 ea, dsisr, access, error = 0UL;
  409. int ret = 0;
  410. ea = spu->dar;
  411. dsisr = spu->dsisr;
  412. if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)) {
  413. u64 flags;
  414. access = (_PAGE_PRESENT | _PAGE_USER);
  415. access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
  416. local_irq_save(flags);
  417. if (hash_page(ea, access, 0x300) != 0)
  418. error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
  419. local_irq_restore(flags);
  420. }
  421. if (error & CLASS1_ENABLE_STORAGE_FAULT_INTR) {
  422. if ((ret = spu_handle_mm_fault(spu)) != 0)
  423. error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
  424. else
  425. error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
  426. }
  427. spu->dar = 0UL;
  428. spu->dsisr = 0UL;
  429. if (!error) {
  430. spu_restart_dma(spu);
  431. } else {
  432. __spu_trap_invalid_dma(spu);
  433. }
  434. return ret;
  435. }
  436. static int __init find_spu_node_id(struct device_node *spe)
  437. {
  438. const unsigned int *id;
  439. struct device_node *cpu;
  440. cpu = spe->parent->parent;
  441. id = get_property(cpu, "node-id", NULL);
  442. return id ? *id : 0;
  443. }
  444. static int __init cell_spuprop_present(struct spu *spu, struct device_node *spe,
  445. const char *prop)
  446. {
  447. static DEFINE_MUTEX(add_spumem_mutex);
  448. const struct address_prop {
  449. unsigned long address;
  450. unsigned int len;
  451. } __attribute__((packed)) *p;
  452. int proplen;
  453. unsigned long start_pfn, nr_pages;
  454. struct pglist_data *pgdata;
  455. struct zone *zone;
  456. int ret;
  457. p = get_property(spe, prop, &proplen);
  458. WARN_ON(proplen != sizeof (*p));
  459. start_pfn = p->address >> PAGE_SHIFT;
  460. nr_pages = ((unsigned long)p->len + PAGE_SIZE - 1) >> PAGE_SHIFT;
  461. pgdata = NODE_DATA(spu->nid);
  462. zone = pgdata->node_zones;
  463. /* XXX rethink locking here */
  464. mutex_lock(&add_spumem_mutex);
  465. ret = __add_pages(zone, start_pfn, nr_pages);
  466. mutex_unlock(&add_spumem_mutex);
  467. return ret;
  468. }
  469. static void __iomem * __init map_spe_prop(struct spu *spu,
  470. struct device_node *n, const char *name)
  471. {
  472. const struct address_prop {
  473. unsigned long address;
  474. unsigned int len;
  475. } __attribute__((packed)) *prop;
  476. const void *p;
  477. int proplen;
  478. void __iomem *ret = NULL;
  479. int err = 0;
  480. p = get_property(n, name, &proplen);
  481. if (proplen != sizeof (struct address_prop))
  482. return NULL;
  483. prop = p;
  484. err = cell_spuprop_present(spu, n, name);
  485. if (err && (err != -EEXIST))
  486. goto out;
  487. ret = ioremap(prop->address, prop->len);
  488. out:
  489. return ret;
  490. }
  491. static void spu_unmap(struct spu *spu)
  492. {
  493. iounmap(spu->priv2);
  494. iounmap(spu->priv1);
  495. iounmap(spu->problem);
  496. iounmap((__force u8 __iomem *)spu->local_store);
  497. }
  498. /* This function shall be abstracted for HV platforms */
  499. static int __init spu_map_interrupts_old(struct spu *spu, struct device_node *np)
  500. {
  501. unsigned int isrc;
  502. const u32 *tmp;
  503. /* Get the interrupt source unit from the device-tree */
  504. tmp = get_property(np, "isrc", NULL);
  505. if (!tmp)
  506. return -ENODEV;
  507. isrc = tmp[0];
  508. /* Add the node number */
  509. isrc |= spu->node << IIC_IRQ_NODE_SHIFT;
  510. /* Now map interrupts of all 3 classes */
  511. spu->irqs[0] = irq_create_mapping(NULL, IIC_IRQ_CLASS_0 | isrc);
  512. spu->irqs[1] = irq_create_mapping(NULL, IIC_IRQ_CLASS_1 | isrc);
  513. spu->irqs[2] = irq_create_mapping(NULL, IIC_IRQ_CLASS_2 | isrc);
  514. /* Right now, we only fail if class 2 failed */
  515. return spu->irqs[2] == NO_IRQ ? -EINVAL : 0;
  516. }
  517. static int __init spu_map_device_old(struct spu *spu, struct device_node *node)
  518. {
  519. const char *prop;
  520. int ret;
  521. ret = -ENODEV;
  522. spu->name = get_property(node, "name", NULL);
  523. if (!spu->name)
  524. goto out;
  525. prop = get_property(node, "local-store", NULL);
  526. if (!prop)
  527. goto out;
  528. spu->local_store_phys = *(unsigned long *)prop;
  529. /* we use local store as ram, not io memory */
  530. spu->local_store = (void __force *)
  531. map_spe_prop(spu, node, "local-store");
  532. if (!spu->local_store)
  533. goto out;
  534. prop = get_property(node, "problem", NULL);
  535. if (!prop)
  536. goto out_unmap;
  537. spu->problem_phys = *(unsigned long *)prop;
  538. spu->problem= map_spe_prop(spu, node, "problem");
  539. if (!spu->problem)
  540. goto out_unmap;
  541. spu->priv1= map_spe_prop(spu, node, "priv1");
  542. /* priv1 is not available on a hypervisor */
  543. spu->priv2= map_spe_prop(spu, node, "priv2");
  544. if (!spu->priv2)
  545. goto out_unmap;
  546. ret = 0;
  547. goto out;
  548. out_unmap:
  549. spu_unmap(spu);
  550. out:
  551. return ret;
  552. }
  553. static int __init spu_map_interrupts(struct spu *spu, struct device_node *np)
  554. {
  555. struct of_irq oirq;
  556. int ret;
  557. int i;
  558. for (i=0; i < 3; i++) {
  559. ret = of_irq_map_one(np, i, &oirq);
  560. if (ret)
  561. goto err;
  562. ret = -EINVAL;
  563. spu->irqs[i] = irq_create_of_mapping(oirq.controller,
  564. oirq.specifier, oirq.size);
  565. if (spu->irqs[i] == NO_IRQ)
  566. goto err;
  567. }
  568. return 0;
  569. err:
  570. pr_debug("failed to map irq %x for spu %s\n", *oirq.specifier, spu->name);
  571. for (; i >= 0; i--) {
  572. if (spu->irqs[i] != NO_IRQ)
  573. irq_dispose_mapping(spu->irqs[i]);
  574. }
  575. return ret;
  576. }
  577. static int spu_map_resource(struct device_node *node, int nr,
  578. void __iomem** virt, unsigned long *phys)
  579. {
  580. struct resource resource = { };
  581. int ret;
  582. ret = of_address_to_resource(node, 0, &resource);
  583. if (ret)
  584. goto out;
  585. if (phys)
  586. *phys = resource.start;
  587. *virt = ioremap(resource.start, resource.end - resource.start);
  588. if (!*virt)
  589. ret = -EINVAL;
  590. out:
  591. return ret;
  592. }
  593. static int __init spu_map_device(struct spu *spu, struct device_node *node)
  594. {
  595. int ret = -ENODEV;
  596. spu->name = get_property(node, "name", NULL);
  597. if (!spu->name)
  598. goto out;
  599. ret = spu_map_resource(node, 0, (void __iomem**)&spu->local_store,
  600. &spu->local_store_phys);
  601. if (ret)
  602. goto out;
  603. ret = spu_map_resource(node, 1, (void __iomem**)&spu->problem,
  604. &spu->problem_phys);
  605. if (ret)
  606. goto out_unmap;
  607. ret = spu_map_resource(node, 2, (void __iomem**)&spu->priv2,
  608. NULL);
  609. if (ret)
  610. goto out_unmap;
  611. if (!firmware_has_feature(FW_FEATURE_LPAR))
  612. ret = spu_map_resource(node, 3, (void __iomem**)&spu->priv1,
  613. NULL);
  614. if (ret)
  615. goto out_unmap;
  616. return 0;
  617. out_unmap:
  618. spu_unmap(spu);
  619. out:
  620. pr_debug("failed to map spe %s: %d\n", spu->name, ret);
  621. return ret;
  622. }
  623. struct sysdev_class spu_sysdev_class = {
  624. set_kset_name("spu")
  625. };
  626. static int spu_create_sysdev(struct spu *spu)
  627. {
  628. int ret;
  629. spu->sysdev.id = spu->number;
  630. spu->sysdev.cls = &spu_sysdev_class;
  631. ret = sysdev_register(&spu->sysdev);
  632. if (ret) {
  633. printk(KERN_ERR "Can't register SPU %d with sysfs\n",
  634. spu->number);
  635. return ret;
  636. }
  637. sysfs_add_device_to_node(&spu->sysdev, spu->nid);
  638. return 0;
  639. }
  640. static void spu_destroy_sysdev(struct spu *spu)
  641. {
  642. sysfs_remove_device_from_node(&spu->sysdev, spu->nid);
  643. sysdev_unregister(&spu->sysdev);
  644. }
  645. static int __init create_spu(struct device_node *spe)
  646. {
  647. struct spu *spu;
  648. int ret;
  649. static int number;
  650. ret = -ENOMEM;
  651. spu = kzalloc(sizeof (*spu), GFP_KERNEL);
  652. if (!spu)
  653. goto out;
  654. spu->node = find_spu_node_id(spe);
  655. if (spu->node >= MAX_NUMNODES) {
  656. printk(KERN_WARNING "SPE %s on node %d ignored,"
  657. " node number too big\n", spe->full_name, spu->node);
  658. printk(KERN_WARNING "Check if CONFIG_NUMA is enabled.\n");
  659. return -ENODEV;
  660. }
  661. spu->nid = of_node_to_nid(spe);
  662. if (spu->nid == -1)
  663. spu->nid = 0;
  664. ret = spu_map_device(spu, spe);
  665. /* try old method */
  666. if (ret)
  667. ret = spu_map_device_old(spu, spe);
  668. if (ret)
  669. goto out_free;
  670. ret = spu_map_interrupts(spu, spe);
  671. if (ret)
  672. ret = spu_map_interrupts_old(spu, spe);
  673. if (ret)
  674. goto out_unmap;
  675. spin_lock_init(&spu->register_lock);
  676. spu_mfc_sdr_setup(spu);
  677. spu_mfc_sr1_set(spu, 0x33);
  678. mutex_lock(&spu_mutex);
  679. spu->number = number++;
  680. ret = spu_request_irqs(spu);
  681. if (ret)
  682. goto out_unlock;
  683. ret = spu_create_sysdev(spu);
  684. if (ret)
  685. goto out_free_irqs;
  686. list_add(&spu->list, &spu_list[spu->node]);
  687. mutex_unlock(&spu_mutex);
  688. pr_debug(KERN_DEBUG "Using SPE %s %p %p %p %p %d\n",
  689. spu->name, spu->local_store,
  690. spu->problem, spu->priv1, spu->priv2, spu->number);
  691. goto out;
  692. out_free_irqs:
  693. spu_free_irqs(spu);
  694. out_unlock:
  695. mutex_unlock(&spu_mutex);
  696. out_unmap:
  697. spu_unmap(spu);
  698. out_free:
  699. kfree(spu);
  700. out:
  701. return ret;
  702. }
  703. static void destroy_spu(struct spu *spu)
  704. {
  705. list_del_init(&spu->list);
  706. spu_destroy_sysdev(spu);
  707. spu_free_irqs(spu);
  708. spu_unmap(spu);
  709. kfree(spu);
  710. }
  711. static void cleanup_spu_base(void)
  712. {
  713. struct spu *spu, *tmp;
  714. int node;
  715. mutex_lock(&spu_mutex);
  716. for (node = 0; node < MAX_NUMNODES; node++) {
  717. list_for_each_entry_safe(spu, tmp, &spu_list[node], list)
  718. destroy_spu(spu);
  719. }
  720. mutex_unlock(&spu_mutex);
  721. sysdev_class_unregister(&spu_sysdev_class);
  722. }
  723. module_exit(cleanup_spu_base);
  724. static int __init init_spu_base(void)
  725. {
  726. struct device_node *node;
  727. int i, ret;
  728. /* create sysdev class for spus */
  729. ret = sysdev_class_register(&spu_sysdev_class);
  730. if (ret)
  731. return ret;
  732. for (i = 0; i < MAX_NUMNODES; i++)
  733. INIT_LIST_HEAD(&spu_list[i]);
  734. ret = -ENODEV;
  735. for (node = of_find_node_by_type(NULL, "spe");
  736. node; node = of_find_node_by_type(node, "spe")) {
  737. ret = create_spu(node);
  738. if (ret) {
  739. printk(KERN_WARNING "%s: Error initializing %s\n",
  740. __FUNCTION__, node->name);
  741. cleanup_spu_base();
  742. break;
  743. }
  744. }
  745. return ret;
  746. }
  747. module_init(init_spu_base);
  748. MODULE_LICENSE("GPL");
  749. MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");