dove.dtsi 11 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,dove";
  5. model = "Marvell Armada 88AP510 SoC";
  6. interrupt-parent = <&intc>;
  7. aliases {
  8. gpio0 = &gpio0;
  9. gpio1 = &gpio1;
  10. gpio2 = &gpio2;
  11. };
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu0: cpu@0 {
  16. compatible = "marvell,pj4a", "marvell,sheeva-v7";
  17. device_type = "cpu";
  18. next-level-cache = <&l2>;
  19. reg = <0>;
  20. };
  21. };
  22. l2: l2-cache {
  23. compatible = "marvell,tauros2-cache";
  24. marvell,tauros2-cache-features = <0>;
  25. };
  26. mbus {
  27. compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
  28. #address-cells = <2>;
  29. #size-cells = <1>;
  30. controller = <&mbusc>;
  31. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
  32. pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
  33. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
  34. MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
  35. MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
  36. MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
  37. MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
  38. internal-regs {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
  43. 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
  44. 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
  45. 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
  46. mbusc: mbus-ctrl@20000 {
  47. compatible = "marvell,mbus-controller";
  48. reg = <0x20000 0x80>, <0x800100 0x8>;
  49. };
  50. timer: timer@20300 {
  51. compatible = "marvell,orion-timer";
  52. reg = <0x20300 0x20>;
  53. interrupt-parent = <&bridge_intc>;
  54. interrupts = <1>, <2>;
  55. clocks = <&core_clk 0>;
  56. };
  57. intc: main-interrupt-ctrl@20200 {
  58. compatible = "marvell,orion-intc";
  59. interrupt-controller;
  60. #interrupt-cells = <1>;
  61. reg = <0x20200 0x10>, <0x20210 0x10>;
  62. };
  63. bridge_intc: bridge-interrupt-ctrl@20110 {
  64. compatible = "marvell,orion-bridge-intc";
  65. interrupt-controller;
  66. #interrupt-cells = <1>;
  67. reg = <0x20110 0x8>;
  68. interrupts = <0>;
  69. marvell,#interrupts = <5>;
  70. };
  71. core_clk: core-clocks@d0214 {
  72. compatible = "marvell,dove-core-clock";
  73. reg = <0xd0214 0x4>;
  74. #clock-cells = <1>;
  75. };
  76. gate_clk: clock-gating-ctrl@d0038 {
  77. compatible = "marvell,dove-gating-clock";
  78. reg = <0xd0038 0x4>;
  79. clocks = <&core_clk 0>;
  80. #clock-cells = <1>;
  81. };
  82. thermal: thermal-diode@d001c {
  83. compatible = "marvell,dove-thermal";
  84. reg = <0xd001c 0x0c>, <0xd005c 0x08>;
  85. };
  86. uart0: serial@12000 {
  87. compatible = "ns16550a";
  88. reg = <0x12000 0x100>;
  89. reg-shift = <2>;
  90. interrupts = <7>;
  91. clocks = <&core_clk 0>;
  92. status = "disabled";
  93. };
  94. uart1: serial@12100 {
  95. compatible = "ns16550a";
  96. reg = <0x12100 0x100>;
  97. reg-shift = <2>;
  98. interrupts = <8>;
  99. clocks = <&core_clk 0>;
  100. pinctrl-0 = <&pmx_uart1>;
  101. pinctrl-names = "default";
  102. status = "disabled";
  103. };
  104. uart2: serial@12200 {
  105. compatible = "ns16550a";
  106. reg = <0x12000 0x100>;
  107. reg-shift = <2>;
  108. interrupts = <9>;
  109. clocks = <&core_clk 0>;
  110. status = "disabled";
  111. };
  112. uart3: serial@12300 {
  113. compatible = "ns16550a";
  114. reg = <0x12100 0x100>;
  115. reg-shift = <2>;
  116. interrupts = <10>;
  117. clocks = <&core_clk 0>;
  118. status = "disabled";
  119. };
  120. gpio0: gpio-ctrl@d0400 {
  121. compatible = "marvell,orion-gpio";
  122. #gpio-cells = <2>;
  123. gpio-controller;
  124. reg = <0xd0400 0x20>;
  125. ngpios = <32>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. interrupts = <12>, <13>, <14>, <60>;
  129. };
  130. gpio1: gpio-ctrl@d0420 {
  131. compatible = "marvell,orion-gpio";
  132. #gpio-cells = <2>;
  133. gpio-controller;
  134. reg = <0xd0420 0x20>;
  135. ngpios = <32>;
  136. interrupt-controller;
  137. #interrupt-cells = <2>;
  138. interrupts = <61>;
  139. };
  140. gpio2: gpio-ctrl@e8400 {
  141. compatible = "marvell,orion-gpio";
  142. #gpio-cells = <2>;
  143. gpio-controller;
  144. reg = <0xe8400 0x0c>;
  145. ngpios = <8>;
  146. };
  147. pinctrl: pin-ctrl@d0200 {
  148. compatible = "marvell,dove-pinctrl";
  149. reg = <0xd0200 0x10>;
  150. clocks = <&gate_clk 22>;
  151. pmx_gpio_0: pmx-gpio-0 {
  152. marvell,pins = "mpp0";
  153. marvell,function = "gpio";
  154. };
  155. pmx_gpio_1: pmx-gpio-1 {
  156. marvell,pins = "mpp1";
  157. marvell,function = "gpio";
  158. };
  159. pmx_gpio_2: pmx-gpio-2 {
  160. marvell,pins = "mpp2";
  161. marvell,function = "gpio";
  162. };
  163. pmx_gpio_3: pmx-gpio-3 {
  164. marvell,pins = "mpp3";
  165. marvell,function = "gpio";
  166. };
  167. pmx_gpio_4: pmx-gpio-4 {
  168. marvell,pins = "mpp4";
  169. marvell,function = "gpio";
  170. };
  171. pmx_gpio_5: pmx-gpio-5 {
  172. marvell,pins = "mpp5";
  173. marvell,function = "gpio";
  174. };
  175. pmx_gpio_6: pmx-gpio-6 {
  176. marvell,pins = "mpp6";
  177. marvell,function = "gpio";
  178. };
  179. pmx_gpio_7: pmx-gpio-7 {
  180. marvell,pins = "mpp7";
  181. marvell,function = "gpio";
  182. };
  183. pmx_gpio_8: pmx-gpio-8 {
  184. marvell,pins = "mpp8";
  185. marvell,function = "gpio";
  186. };
  187. pmx_gpio_9: pmx-gpio-9 {
  188. marvell,pins = "mpp9";
  189. marvell,function = "gpio";
  190. };
  191. pmx_gpio_10: pmx-gpio-10 {
  192. marvell,pins = "mpp10";
  193. marvell,function = "gpio";
  194. };
  195. pmx_gpio_11: pmx-gpio-11 {
  196. marvell,pins = "mpp11";
  197. marvell,function = "gpio";
  198. };
  199. pmx_gpio_12: pmx-gpio-12 {
  200. marvell,pins = "mpp12";
  201. marvell,function = "gpio";
  202. };
  203. pmx_gpio_13: pmx-gpio-13 {
  204. marvell,pins = "mpp13";
  205. marvell,function = "gpio";
  206. };
  207. pmx_gpio_14: pmx-gpio-14 {
  208. marvell,pins = "mpp14";
  209. marvell,function = "gpio";
  210. };
  211. pmx_gpio_15: pmx-gpio-15 {
  212. marvell,pins = "mpp15";
  213. marvell,function = "gpio";
  214. };
  215. pmx_gpio_16: pmx-gpio-16 {
  216. marvell,pins = "mpp16";
  217. marvell,function = "gpio";
  218. };
  219. pmx_gpio_17: pmx-gpio-17 {
  220. marvell,pins = "mpp17";
  221. marvell,function = "gpio";
  222. };
  223. pmx_gpio_18: pmx-gpio-18 {
  224. marvell,pins = "mpp18";
  225. marvell,function = "gpio";
  226. };
  227. pmx_gpio_19: pmx-gpio-19 {
  228. marvell,pins = "mpp19";
  229. marvell,function = "gpio";
  230. };
  231. pmx_gpio_20: pmx-gpio-20 {
  232. marvell,pins = "mpp20";
  233. marvell,function = "gpio";
  234. };
  235. pmx_gpio_21: pmx-gpio-21 {
  236. marvell,pins = "mpp21";
  237. marvell,function = "gpio";
  238. };
  239. pmx_camera: pmx-camera {
  240. marvell,pins = "mpp_camera";
  241. marvell,function = "camera";
  242. };
  243. pmx_camera_gpio: pmx-camera-gpio {
  244. marvell,pins = "mpp_camera";
  245. marvell,function = "gpio";
  246. };
  247. pmx_sdio0: pmx-sdio0 {
  248. marvell,pins = "mpp_sdio0";
  249. marvell,function = "sdio0";
  250. };
  251. pmx_sdio0_gpio: pmx-sdio0-gpio {
  252. marvell,pins = "mpp_sdio0";
  253. marvell,function = "gpio";
  254. };
  255. pmx_sdio1: pmx-sdio1 {
  256. marvell,pins = "mpp_sdio1";
  257. marvell,function = "sdio1";
  258. };
  259. pmx_sdio1_gpio: pmx-sdio1-gpio {
  260. marvell,pins = "mpp_sdio1";
  261. marvell,function = "gpio";
  262. };
  263. pmx_audio1_gpio: pmx-audio1-gpio {
  264. marvell,pins = "mpp_audio1";
  265. marvell,function = "gpio";
  266. };
  267. pmx_spi0: pmx-spi0 {
  268. marvell,pins = "mpp_spi0";
  269. marvell,function = "spi0";
  270. };
  271. pmx_spi0_gpio: pmx-spi0-gpio {
  272. marvell,pins = "mpp_spi0";
  273. marvell,function = "gpio";
  274. };
  275. pmx_uart1: pmx-uart1 {
  276. marvell,pins = "mpp_uart1";
  277. marvell,function = "uart1";
  278. };
  279. pmx_uart1_gpio: pmx-uart1-gpio {
  280. marvell,pins = "mpp_uart1";
  281. marvell,function = "gpio";
  282. };
  283. pmx_nand: pmx-nand {
  284. marvell,pins = "mpp_nand";
  285. marvell,function = "nand";
  286. };
  287. pmx_nand_gpo: pmx-nand-gpo {
  288. marvell,pins = "mpp_nand";
  289. marvell,function = "gpo";
  290. };
  291. };
  292. spi0: spi-ctrl@10600 {
  293. compatible = "marvell,orion-spi";
  294. #address-cells = <1>;
  295. #size-cells = <0>;
  296. cell-index = <0>;
  297. interrupts = <6>;
  298. reg = <0x10600 0x28>;
  299. clocks = <&core_clk 0>;
  300. pinctrl-0 = <&pmx_spi0>;
  301. pinctrl-names = "default";
  302. status = "disabled";
  303. };
  304. spi1: spi-ctrl@14600 {
  305. compatible = "marvell,orion-spi";
  306. #address-cells = <1>;
  307. #size-cells = <0>;
  308. cell-index = <1>;
  309. interrupts = <5>;
  310. reg = <0x14600 0x28>;
  311. clocks = <&core_clk 0>;
  312. status = "disabled";
  313. };
  314. i2c0: i2c-ctrl@11000 {
  315. compatible = "marvell,mv64xxx-i2c";
  316. reg = <0x11000 0x20>;
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. interrupts = <11>;
  320. clock-frequency = <400000>;
  321. timeout-ms = <1000>;
  322. clocks = <&core_clk 0>;
  323. status = "disabled";
  324. };
  325. ehci0: usb-host@50000 {
  326. compatible = "marvell,orion-ehci";
  327. reg = <0x50000 0x1000>;
  328. interrupts = <24>;
  329. clocks = <&gate_clk 0>;
  330. status = "okay";
  331. };
  332. ehci1: usb-host@51000 {
  333. compatible = "marvell,orion-ehci";
  334. reg = <0x51000 0x1000>;
  335. interrupts = <25>;
  336. clocks = <&gate_clk 1>;
  337. status = "okay";
  338. };
  339. sdio0: sdio-host@92000 {
  340. compatible = "marvell,dove-sdhci";
  341. reg = <0x92000 0x100>;
  342. interrupts = <35>, <37>;
  343. clocks = <&gate_clk 8>;
  344. pinctrl-0 = <&pmx_sdio0>;
  345. pinctrl-names = "default";
  346. status = "disabled";
  347. };
  348. sdio1: sdio-host@90000 {
  349. compatible = "marvell,dove-sdhci";
  350. reg = <0x90000 0x100>;
  351. interrupts = <36>, <38>;
  352. clocks = <&gate_clk 9>;
  353. pinctrl-0 = <&pmx_sdio1>;
  354. pinctrl-names = "default";
  355. status = "disabled";
  356. };
  357. sata0: sata-host@a0000 {
  358. compatible = "marvell,orion-sata";
  359. reg = <0xa0000 0x2400>;
  360. interrupts = <62>;
  361. clocks = <&gate_clk 3>;
  362. nr-ports = <1>;
  363. status = "disabled";
  364. };
  365. rtc: real-time-clock@d8500 {
  366. compatible = "marvell,orion-rtc";
  367. reg = <0xd8500 0x20>;
  368. };
  369. crypto: crypto-engine@30000 {
  370. compatible = "marvell,orion-crypto";
  371. reg = <0x30000 0x10000>,
  372. <0xffffe000 0x800>;
  373. reg-names = "regs", "sram";
  374. interrupts = <31>;
  375. clocks = <&gate_clk 15>;
  376. status = "okay";
  377. };
  378. xor0: dma-engine@60800 {
  379. compatible = "marvell,orion-xor";
  380. reg = <0x60800 0x100
  381. 0x60a00 0x100>;
  382. clocks = <&gate_clk 23>;
  383. status = "okay";
  384. channel0 {
  385. interrupts = <39>;
  386. dmacap,memcpy;
  387. dmacap,xor;
  388. };
  389. channel1 {
  390. interrupts = <40>;
  391. dmacap,memcpy;
  392. dmacap,xor;
  393. };
  394. };
  395. xor1: dma-engine@60900 {
  396. compatible = "marvell,orion-xor";
  397. reg = <0x60900 0x100
  398. 0x60b00 0x100>;
  399. clocks = <&gate_clk 24>;
  400. status = "okay";
  401. channel0 {
  402. interrupts = <42>;
  403. dmacap,memcpy;
  404. dmacap,xor;
  405. };
  406. channel1 {
  407. interrupts = <43>;
  408. dmacap,memcpy;
  409. dmacap,xor;
  410. };
  411. };
  412. mdio: mdio-bus@72004 {
  413. compatible = "marvell,orion-mdio";
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. reg = <0x72004 0x84>;
  417. interrupts = <30>;
  418. clocks = <&gate_clk 2>;
  419. status = "disabled";
  420. ethphy: ethernet-phy {
  421. device-type = "ethernet-phy";
  422. /* set phy address in board file */
  423. };
  424. };
  425. eth: ethernet-ctrl@72000 {
  426. compatible = "marvell,orion-eth";
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. reg = <0x72000 0x4000>;
  430. clocks = <&gate_clk 2>;
  431. marvell,tx-checksum-limit = <1600>;
  432. status = "disabled";
  433. ethernet-port@0 {
  434. device_type = "network";
  435. compatible = "marvell,orion-eth-port";
  436. reg = <0>;
  437. interrupts = <29>;
  438. /* overwrite MAC address in bootloader */
  439. local-mac-address = [00 00 00 00 00 00];
  440. phy-handle = <&ethphy>;
  441. };
  442. };
  443. };
  444. };
  445. };