twl6030-irq.c 12 KB

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  1. /*
  2. * twl6030-irq.c - TWL6030 irq support
  3. *
  4. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  5. *
  6. * Modifications to defer interrupt handling to a kernel thread:
  7. * Copyright (C) 2006 MontaVista Software, Inc.
  8. *
  9. * Based on tlv320aic23.c:
  10. * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  11. *
  12. * Code cleanup and modifications to IRQ handler.
  13. * by syed khasim <x0khasim@ti.com>
  14. *
  15. * TWL6030 specific code and IRQ handling changes by
  16. * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
  17. * Balaji T K <balajitk@ti.com>
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License as published by
  21. * the Free Software Foundation; either version 2 of the License, or
  22. * (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  32. */
  33. #include <linux/init.h>
  34. #include <linux/export.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/irq.h>
  37. #include <linux/kthread.h>
  38. #include <linux/i2c/twl.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/suspend.h>
  41. #include <linux/of.h>
  42. #include <linux/irqdomain.h>
  43. #include "twl-core.h"
  44. /*
  45. * TWL6030 (unlike its predecessors, which had two level interrupt handling)
  46. * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
  47. * It exposes status bits saying who has raised an interrupt. There are
  48. * three mask registers that corresponds to these status registers, that
  49. * enables/disables these interrupts.
  50. *
  51. * We set up IRQs starting at a platform-specified base. An interrupt map table,
  52. * specifies mapping between interrupt number and the associated module.
  53. */
  54. #define TWL6030_NR_IRQS 20
  55. static int twl6030_interrupt_mapping[24] = {
  56. PWR_INTR_OFFSET, /* Bit 0 PWRON */
  57. PWR_INTR_OFFSET, /* Bit 1 RPWRON */
  58. PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
  59. RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
  60. RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
  61. HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
  62. SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
  63. SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
  64. SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
  65. BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
  66. SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
  67. MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
  68. RSV_INTR_OFFSET, /* Bit 12 Reserved */
  69. MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
  70. MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
  71. GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
  72. USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
  73. USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
  74. USBOTG_INTR_OFFSET, /* Bit 18 ID */
  75. USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
  76. CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
  77. CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
  78. CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
  79. RSV_INTR_OFFSET, /* Bit 23 Reserved */
  80. };
  81. /*----------------------------------------------------------------------*/
  82. struct twl6030_irq {
  83. unsigned int irq_base;
  84. int twl_irq;
  85. bool irq_wake_enabled;
  86. atomic_t wakeirqs;
  87. struct notifier_block pm_nb;
  88. struct irq_chip irq_chip;
  89. struct irq_domain *irq_domain;
  90. };
  91. static struct twl6030_irq *twl6030_irq;
  92. static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
  93. unsigned long pm_event, void *unused)
  94. {
  95. int chained_wakeups;
  96. struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
  97. pm_nb);
  98. switch (pm_event) {
  99. case PM_SUSPEND_PREPARE:
  100. chained_wakeups = atomic_read(&pdata->wakeirqs);
  101. if (chained_wakeups && !pdata->irq_wake_enabled) {
  102. if (enable_irq_wake(pdata->twl_irq))
  103. pr_err("twl6030 IRQ wake enable failed\n");
  104. else
  105. pdata->irq_wake_enabled = true;
  106. } else if (!chained_wakeups && pdata->irq_wake_enabled) {
  107. disable_irq_wake(pdata->twl_irq);
  108. pdata->irq_wake_enabled = false;
  109. }
  110. disable_irq(pdata->twl_irq);
  111. break;
  112. case PM_POST_SUSPEND:
  113. enable_irq(pdata->twl_irq);
  114. break;
  115. default:
  116. break;
  117. }
  118. return NOTIFY_DONE;
  119. }
  120. /*
  121. * Threaded irq handler for the twl6030 interrupt.
  122. * We query the interrupt controller in the twl6030 to determine
  123. * which module is generating the interrupt request and call
  124. * handle_nested_irq for that module.
  125. */
  126. static irqreturn_t twl6030_irq_thread(int irq, void *data)
  127. {
  128. int i, ret;
  129. union {
  130. u8 bytes[4];
  131. u32 int_sts;
  132. } sts;
  133. struct twl6030_irq *pdata = data;
  134. /* read INT_STS_A, B and C in one shot using a burst read */
  135. ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
  136. if (ret) {
  137. pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
  138. return IRQ_HANDLED;
  139. }
  140. sts.bytes[3] = 0; /* Only 24 bits are valid*/
  141. /*
  142. * Since VBUS status bit is not reliable for VBUS disconnect
  143. * use CHARGER VBUS detection status bit instead.
  144. */
  145. if (sts.bytes[2] & 0x10)
  146. sts.bytes[2] |= 0x08;
  147. for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++)
  148. if (sts.int_sts & 0x1) {
  149. int module_irq =
  150. irq_find_mapping(pdata->irq_domain,
  151. twl6030_interrupt_mapping[i]);
  152. if (module_irq)
  153. handle_nested_irq(module_irq);
  154. else
  155. pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
  156. i);
  157. pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
  158. i, module_irq);
  159. }
  160. /*
  161. * NOTE:
  162. * Simulation confirms that documentation is wrong w.r.t the
  163. * interrupt status clear operation. A single *byte* write to
  164. * any one of STS_A to STS_C register results in all three
  165. * STS registers being reset. Since it does not matter which
  166. * value is written, all three registers are cleared on a
  167. * single byte write, so we just use 0x0 to clear.
  168. */
  169. ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
  170. if (ret)
  171. pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
  172. return IRQ_HANDLED;
  173. }
  174. /*----------------------------------------------------------------------*/
  175. static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
  176. {
  177. struct twl6030_irq *pdata = irq_get_chip_data(d->irq);
  178. if (on)
  179. atomic_inc(&pdata->wakeirqs);
  180. else
  181. atomic_dec(&pdata->wakeirqs);
  182. return 0;
  183. }
  184. int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
  185. {
  186. int ret;
  187. u8 unmask_value;
  188. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
  189. REG_INT_STS_A + offset);
  190. unmask_value &= (~(bit_mask));
  191. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
  192. REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
  193. return ret;
  194. }
  195. EXPORT_SYMBOL(twl6030_interrupt_unmask);
  196. int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
  197. {
  198. int ret;
  199. u8 mask_value;
  200. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
  201. REG_INT_STS_A + offset);
  202. mask_value |= (bit_mask);
  203. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
  204. REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
  205. return ret;
  206. }
  207. EXPORT_SYMBOL(twl6030_interrupt_mask);
  208. int twl6030_mmc_card_detect_config(void)
  209. {
  210. int ret;
  211. u8 reg_val = 0;
  212. /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
  213. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  214. REG_INT_MSK_LINE_B);
  215. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  216. REG_INT_MSK_STS_B);
  217. /*
  218. * Initially Configuring MMC_CTRL for receiving interrupts &
  219. * Card status on TWL6030 for MMC1
  220. */
  221. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
  222. if (ret < 0) {
  223. pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
  224. return ret;
  225. }
  226. reg_val &= ~VMMC_AUTO_OFF;
  227. reg_val |= SW_FC;
  228. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
  229. if (ret < 0) {
  230. pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
  231. return ret;
  232. }
  233. /* Configuring PullUp-PullDown register */
  234. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
  235. TWL6030_CFG_INPUT_PUPD3);
  236. if (ret < 0) {
  237. pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
  238. ret);
  239. return ret;
  240. }
  241. reg_val &= ~(MMC_PU | MMC_PD);
  242. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
  243. TWL6030_CFG_INPUT_PUPD3);
  244. if (ret < 0) {
  245. pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
  246. ret);
  247. return ret;
  248. }
  249. return irq_find_mapping(twl6030_irq->irq_domain,
  250. MMCDETECT_INTR_OFFSET);
  251. }
  252. EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
  253. int twl6030_mmc_card_detect(struct device *dev, int slot)
  254. {
  255. int ret = -EIO;
  256. u8 read_reg = 0;
  257. struct platform_device *pdev = to_platform_device(dev);
  258. if (pdev->id) {
  259. /* TWL6030 provide's Card detect support for
  260. * only MMC1 controller.
  261. */
  262. pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
  263. return ret;
  264. }
  265. /*
  266. * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
  267. * 0 - Card not present ,1 - Card present
  268. */
  269. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
  270. TWL6030_MMCCTRL);
  271. if (ret >= 0)
  272. ret = read_reg & STS_MMC;
  273. return ret;
  274. }
  275. EXPORT_SYMBOL(twl6030_mmc_card_detect);
  276. static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
  277. irq_hw_number_t hwirq)
  278. {
  279. struct twl6030_irq *pdata = d->host_data;
  280. irq_set_chip_data(virq, pdata);
  281. irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
  282. irq_set_nested_thread(virq, true);
  283. irq_set_parent(virq, pdata->twl_irq);
  284. #ifdef CONFIG_ARM
  285. /*
  286. * ARM requires an extra step to clear IRQ_NOREQUEST, which it
  287. * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
  288. */
  289. set_irq_flags(virq, IRQF_VALID);
  290. #else
  291. /* same effect on other architectures */
  292. irq_set_noprobe(virq);
  293. #endif
  294. return 0;
  295. }
  296. static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
  297. {
  298. #ifdef CONFIG_ARM
  299. set_irq_flags(virq, 0);
  300. #endif
  301. irq_set_chip_and_handler(virq, NULL, NULL);
  302. irq_set_chip_data(virq, NULL);
  303. }
  304. static struct irq_domain_ops twl6030_irq_domain_ops = {
  305. .map = twl6030_irq_map,
  306. .unmap = twl6030_irq_unmap,
  307. .xlate = irq_domain_xlate_onetwocell,
  308. };
  309. int twl6030_init_irq(struct device *dev, int irq_num)
  310. {
  311. struct device_node *node = dev->of_node;
  312. int nr_irqs;
  313. int status;
  314. u8 mask[3];
  315. nr_irqs = TWL6030_NR_IRQS;
  316. twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
  317. if (!twl6030_irq) {
  318. dev_err(dev, "twl6030_irq: Memory allocation failed\n");
  319. return -ENOMEM;
  320. }
  321. mask[0] = 0xFF;
  322. mask[1] = 0xFF;
  323. mask[2] = 0xFF;
  324. /* mask all int lines */
  325. status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
  326. /* mask all int sts */
  327. status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
  328. /* clear INT_STS_A,B,C */
  329. status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
  330. if (status < 0) {
  331. dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
  332. return status;
  333. }
  334. /*
  335. * install an irq handler for each of the modules;
  336. * clone dummy irq_chip since PIH can't *do* anything
  337. */
  338. twl6030_irq->irq_chip = dummy_irq_chip;
  339. twl6030_irq->irq_chip.name = "twl6030";
  340. twl6030_irq->irq_chip.irq_set_type = NULL;
  341. twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
  342. twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
  343. atomic_set(&twl6030_irq->wakeirqs, 0);
  344. twl6030_irq->irq_domain =
  345. irq_domain_add_linear(node, nr_irqs,
  346. &twl6030_irq_domain_ops, twl6030_irq);
  347. if (!twl6030_irq->irq_domain) {
  348. dev_err(dev, "Can't add irq_domain\n");
  349. return -ENOMEM;
  350. }
  351. dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
  352. /* install an irq handler to demultiplex the TWL6030 interrupt */
  353. status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
  354. IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
  355. if (status < 0) {
  356. dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
  357. goto fail_irq;
  358. }
  359. twl6030_irq->twl_irq = irq_num;
  360. register_pm_notifier(&twl6030_irq->pm_nb);
  361. return 0;
  362. fail_irq:
  363. irq_domain_remove(twl6030_irq->irq_domain);
  364. return status;
  365. }
  366. int twl6030_exit_irq(void)
  367. {
  368. if (twl6030_irq && twl6030_irq->twl_irq) {
  369. unregister_pm_notifier(&twl6030_irq->pm_nb);
  370. free_irq(twl6030_irq->twl_irq, NULL);
  371. /*
  372. * TODO: IRQ domain and allocated nested IRQ descriptors
  373. * should be freed somehow here. Now It can't be done, because
  374. * child devices will not be deleted during removing of
  375. * TWL Core driver and they will still contain allocated
  376. * virt IRQs in their Resources tables.
  377. * The same prevents us from using devm_request_threaded_irq()
  378. * in this module.
  379. */
  380. }
  381. return 0;
  382. }