am33xx.dtsi 11 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/pinctrl/am33xx.h>
  12. #include "skeleton.dtsi"
  13. / {
  14. compatible = "ti,am33xx";
  15. interrupt-parent = <&intc>;
  16. aliases {
  17. serial0 = &uart0;
  18. serial1 = &uart1;
  19. serial2 = &uart2;
  20. serial3 = &uart3;
  21. serial4 = &uart4;
  22. serial5 = &uart5;
  23. d_can0 = &dcan0;
  24. d_can1 = &dcan1;
  25. };
  26. cpus {
  27. cpu@0 {
  28. compatible = "arm,cortex-a8";
  29. /*
  30. * To consider voltage drop between PMIC and SoC,
  31. * tolerance value is reduced to 2% from 4% and
  32. * voltage value is increased as a precaution.
  33. */
  34. operating-points = <
  35. /* kHz uV */
  36. 720000 1285000
  37. 600000 1225000
  38. 500000 1125000
  39. 275000 1125000
  40. >;
  41. voltage-tolerance = <2>; /* 2 percentage */
  42. clock-latency = <300000>; /* From omap-cpufreq driver */
  43. };
  44. };
  45. /*
  46. * The soc node represents the soc top level view. It is uses for IPs
  47. * that are not memory mapped in the MPU view or for the MPU itself.
  48. */
  49. soc {
  50. compatible = "ti,omap-infra";
  51. mpu {
  52. compatible = "ti,omap3-mpu";
  53. ti,hwmods = "mpu";
  54. };
  55. };
  56. am33xx_pinmux: pinmux@44e10800 {
  57. compatible = "pinctrl-single";
  58. reg = <0x44e10800 0x0238>;
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. pinctrl-single,register-width = <32>;
  62. pinctrl-single,function-mask = <0x7f>;
  63. };
  64. /*
  65. * XXX: Use a flat representation of the AM33XX interconnect.
  66. * The real AM33XX interconnect network is quite complex.Since
  67. * that will not bring real advantage to represent that in DT
  68. * for the moment, just use a fake OCP bus entry to represent
  69. * the whole bus hierarchy.
  70. */
  71. ocp {
  72. compatible = "simple-bus";
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. ranges;
  76. ti,hwmods = "l3_main";
  77. intc: interrupt-controller@48200000 {
  78. compatible = "ti,omap2-intc";
  79. interrupt-controller;
  80. #interrupt-cells = <1>;
  81. ti,intc-size = <128>;
  82. reg = <0x48200000 0x1000>;
  83. };
  84. gpio0: gpio@44e07000 {
  85. compatible = "ti,omap4-gpio";
  86. ti,hwmods = "gpio1";
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. interrupt-controller;
  90. #interrupt-cells = <1>;
  91. reg = <0x44e07000 0x1000>;
  92. interrupts = <96>;
  93. };
  94. gpio1: gpio@4804c000 {
  95. compatible = "ti,omap4-gpio";
  96. ti,hwmods = "gpio2";
  97. gpio-controller;
  98. #gpio-cells = <2>;
  99. interrupt-controller;
  100. #interrupt-cells = <1>;
  101. reg = <0x4804c000 0x1000>;
  102. interrupts = <98>;
  103. };
  104. gpio2: gpio@481ac000 {
  105. compatible = "ti,omap4-gpio";
  106. ti,hwmods = "gpio3";
  107. gpio-controller;
  108. #gpio-cells = <2>;
  109. interrupt-controller;
  110. #interrupt-cells = <1>;
  111. reg = <0x481ac000 0x1000>;
  112. interrupts = <32>;
  113. };
  114. gpio3: gpio@481ae000 {
  115. compatible = "ti,omap4-gpio";
  116. ti,hwmods = "gpio4";
  117. gpio-controller;
  118. #gpio-cells = <2>;
  119. interrupt-controller;
  120. #interrupt-cells = <1>;
  121. reg = <0x481ae000 0x1000>;
  122. interrupts = <62>;
  123. };
  124. uart0: serial@44e09000 {
  125. compatible = "ti,omap3-uart";
  126. ti,hwmods = "uart1";
  127. clock-frequency = <48000000>;
  128. reg = <0x44e09000 0x2000>;
  129. interrupts = <72>;
  130. status = "disabled";
  131. };
  132. uart1: serial@48022000 {
  133. compatible = "ti,omap3-uart";
  134. ti,hwmods = "uart2";
  135. clock-frequency = <48000000>;
  136. reg = <0x48022000 0x2000>;
  137. interrupts = <73>;
  138. status = "disabled";
  139. };
  140. uart2: serial@48024000 {
  141. compatible = "ti,omap3-uart";
  142. ti,hwmods = "uart3";
  143. clock-frequency = <48000000>;
  144. reg = <0x48024000 0x2000>;
  145. interrupts = <74>;
  146. status = "disabled";
  147. };
  148. uart3: serial@481a6000 {
  149. compatible = "ti,omap3-uart";
  150. ti,hwmods = "uart4";
  151. clock-frequency = <48000000>;
  152. reg = <0x481a6000 0x2000>;
  153. interrupts = <44>;
  154. status = "disabled";
  155. };
  156. uart4: serial@481a8000 {
  157. compatible = "ti,omap3-uart";
  158. ti,hwmods = "uart5";
  159. clock-frequency = <48000000>;
  160. reg = <0x481a8000 0x2000>;
  161. interrupts = <45>;
  162. status = "disabled";
  163. };
  164. uart5: serial@481aa000 {
  165. compatible = "ti,omap3-uart";
  166. ti,hwmods = "uart6";
  167. clock-frequency = <48000000>;
  168. reg = <0x481aa000 0x2000>;
  169. interrupts = <46>;
  170. status = "disabled";
  171. };
  172. i2c0: i2c@44e0b000 {
  173. compatible = "ti,omap4-i2c";
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. ti,hwmods = "i2c1";
  177. reg = <0x44e0b000 0x1000>;
  178. interrupts = <70>;
  179. status = "disabled";
  180. };
  181. i2c1: i2c@4802a000 {
  182. compatible = "ti,omap4-i2c";
  183. #address-cells = <1>;
  184. #size-cells = <0>;
  185. ti,hwmods = "i2c2";
  186. reg = <0x4802a000 0x1000>;
  187. interrupts = <71>;
  188. status = "disabled";
  189. };
  190. i2c2: i2c@4819c000 {
  191. compatible = "ti,omap4-i2c";
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. ti,hwmods = "i2c3";
  195. reg = <0x4819c000 0x1000>;
  196. interrupts = <30>;
  197. status = "disabled";
  198. };
  199. wdt2: wdt@44e35000 {
  200. compatible = "ti,omap3-wdt";
  201. ti,hwmods = "wd_timer2";
  202. reg = <0x44e35000 0x1000>;
  203. interrupts = <91>;
  204. };
  205. dcan0: d_can@481cc000 {
  206. compatible = "bosch,d_can";
  207. ti,hwmods = "d_can0";
  208. reg = <0x481cc000 0x2000
  209. 0x44e10644 0x4>;
  210. interrupts = <52>;
  211. status = "disabled";
  212. };
  213. dcan1: d_can@481d0000 {
  214. compatible = "bosch,d_can";
  215. ti,hwmods = "d_can1";
  216. reg = <0x481d0000 0x2000
  217. 0x44e10644 0x4>;
  218. interrupts = <55>;
  219. status = "disabled";
  220. };
  221. timer1: timer@44e31000 {
  222. compatible = "ti,am335x-timer-1ms";
  223. reg = <0x44e31000 0x400>;
  224. interrupts = <67>;
  225. ti,hwmods = "timer1";
  226. ti,timer-alwon;
  227. };
  228. timer2: timer@48040000 {
  229. compatible = "ti,am335x-timer";
  230. reg = <0x48040000 0x400>;
  231. interrupts = <68>;
  232. ti,hwmods = "timer2";
  233. };
  234. timer3: timer@48042000 {
  235. compatible = "ti,am335x-timer";
  236. reg = <0x48042000 0x400>;
  237. interrupts = <69>;
  238. ti,hwmods = "timer3";
  239. };
  240. timer4: timer@48044000 {
  241. compatible = "ti,am335x-timer";
  242. reg = <0x48044000 0x400>;
  243. interrupts = <92>;
  244. ti,hwmods = "timer4";
  245. ti,timer-pwm;
  246. };
  247. timer5: timer@48046000 {
  248. compatible = "ti,am335x-timer";
  249. reg = <0x48046000 0x400>;
  250. interrupts = <93>;
  251. ti,hwmods = "timer5";
  252. ti,timer-pwm;
  253. };
  254. timer6: timer@48048000 {
  255. compatible = "ti,am335x-timer";
  256. reg = <0x48048000 0x400>;
  257. interrupts = <94>;
  258. ti,hwmods = "timer6";
  259. ti,timer-pwm;
  260. };
  261. timer7: timer@4804a000 {
  262. compatible = "ti,am335x-timer";
  263. reg = <0x4804a000 0x400>;
  264. interrupts = <95>;
  265. ti,hwmods = "timer7";
  266. ti,timer-pwm;
  267. };
  268. rtc@44e3e000 {
  269. compatible = "ti,da830-rtc";
  270. reg = <0x44e3e000 0x1000>;
  271. interrupts = <75
  272. 76>;
  273. ti,hwmods = "rtc";
  274. };
  275. spi0: spi@48030000 {
  276. compatible = "ti,omap4-mcspi";
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. reg = <0x48030000 0x400>;
  280. interrupts = <65>;
  281. ti,spi-num-cs = <2>;
  282. ti,hwmods = "spi0";
  283. status = "disabled";
  284. };
  285. spi1: spi@481a0000 {
  286. compatible = "ti,omap4-mcspi";
  287. #address-cells = <1>;
  288. #size-cells = <0>;
  289. reg = <0x481a0000 0x400>;
  290. interrupts = <125>;
  291. ti,spi-num-cs = <2>;
  292. ti,hwmods = "spi1";
  293. status = "disabled";
  294. };
  295. usb@47400000 {
  296. compatible = "ti,musb-am33xx";
  297. reg = <0x47400000 0x1000 /* usbss */
  298. 0x47401000 0x800 /* musb instance 0 */
  299. 0x47401800 0x800>; /* musb instance 1 */
  300. interrupts = <17 /* usbss */
  301. 18 /* musb instance 0 */
  302. 19>; /* musb instance 1 */
  303. multipoint = <1>;
  304. num-eps = <16>;
  305. ram-bits = <12>;
  306. port0-mode = <3>;
  307. port1-mode = <3>;
  308. power = <250>;
  309. ti,hwmods = "usb_otg_hs";
  310. };
  311. epwmss0: epwmss@48300000 {
  312. compatible = "ti,am33xx-pwmss";
  313. reg = <0x48300000 0x10>;
  314. ti,hwmods = "epwmss0";
  315. #address-cells = <1>;
  316. #size-cells = <1>;
  317. status = "disabled";
  318. ranges = <0x48300100 0x48300100 0x80 /* ECAP */
  319. 0x48300180 0x48300180 0x80 /* EQEP */
  320. 0x48300200 0x48300200 0x80>; /* EHRPWM */
  321. ecap0: ecap@48300100 {
  322. compatible = "ti,am33xx-ecap";
  323. #pwm-cells = <3>;
  324. reg = <0x48300100 0x80>;
  325. ti,hwmods = "ecap0";
  326. status = "disabled";
  327. };
  328. ehrpwm0: ehrpwm@48300200 {
  329. compatible = "ti,am33xx-ehrpwm";
  330. #pwm-cells = <3>;
  331. reg = <0x48300200 0x80>;
  332. ti,hwmods = "ehrpwm0";
  333. status = "disabled";
  334. };
  335. };
  336. epwmss1: epwmss@48302000 {
  337. compatible = "ti,am33xx-pwmss";
  338. reg = <0x48302000 0x10>;
  339. ti,hwmods = "epwmss1";
  340. #address-cells = <1>;
  341. #size-cells = <1>;
  342. status = "disabled";
  343. ranges = <0x48302100 0x48302100 0x80 /* ECAP */
  344. 0x48302180 0x48302180 0x80 /* EQEP */
  345. 0x48302200 0x48302200 0x80>; /* EHRPWM */
  346. ecap1: ecap@48302100 {
  347. compatible = "ti,am33xx-ecap";
  348. #pwm-cells = <3>;
  349. reg = <0x48302100 0x80>;
  350. ti,hwmods = "ecap1";
  351. status = "disabled";
  352. };
  353. ehrpwm1: ehrpwm@48302200 {
  354. compatible = "ti,am33xx-ehrpwm";
  355. #pwm-cells = <3>;
  356. reg = <0x48302200 0x80>;
  357. ti,hwmods = "ehrpwm1";
  358. status = "disabled";
  359. };
  360. };
  361. epwmss2: epwmss@48304000 {
  362. compatible = "ti,am33xx-pwmss";
  363. reg = <0x48304000 0x10>;
  364. ti,hwmods = "epwmss2";
  365. #address-cells = <1>;
  366. #size-cells = <1>;
  367. status = "disabled";
  368. ranges = <0x48304100 0x48304100 0x80 /* ECAP */
  369. 0x48304180 0x48304180 0x80 /* EQEP */
  370. 0x48304200 0x48304200 0x80>; /* EHRPWM */
  371. ecap2: ecap@48304100 {
  372. compatible = "ti,am33xx-ecap";
  373. #pwm-cells = <3>;
  374. reg = <0x48304100 0x80>;
  375. ti,hwmods = "ecap2";
  376. status = "disabled";
  377. };
  378. ehrpwm2: ehrpwm@48304200 {
  379. compatible = "ti,am33xx-ehrpwm";
  380. #pwm-cells = <3>;
  381. reg = <0x48304200 0x80>;
  382. ti,hwmods = "ehrpwm2";
  383. status = "disabled";
  384. };
  385. };
  386. mac: ethernet@4a100000 {
  387. compatible = "ti,cpsw";
  388. ti,hwmods = "cpgmac0";
  389. cpdma_channels = <8>;
  390. ale_entries = <1024>;
  391. bd_ram_size = <0x2000>;
  392. no_bd_ram = <0>;
  393. rx_descs = <64>;
  394. mac_control = <0x20>;
  395. slaves = <2>;
  396. active_slave = <0>;
  397. cpts_clock_mult = <0x80000000>;
  398. cpts_clock_shift = <29>;
  399. reg = <0x4a100000 0x800
  400. 0x4a101200 0x100>;
  401. #address-cells = <1>;
  402. #size-cells = <1>;
  403. interrupt-parent = <&intc>;
  404. /*
  405. * c0_rx_thresh_pend
  406. * c0_rx_pend
  407. * c0_tx_pend
  408. * c0_misc_pend
  409. */
  410. interrupts = <40 41 42 43>;
  411. ranges;
  412. davinci_mdio: mdio@4a101000 {
  413. compatible = "ti,davinci_mdio";
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. ti,hwmods = "davinci_mdio";
  417. bus_freq = <1000000>;
  418. reg = <0x4a101000 0x100>;
  419. };
  420. cpsw_emac0: slave@4a100200 {
  421. /* Filled in by U-Boot */
  422. mac-address = [ 00 00 00 00 00 00 ];
  423. };
  424. cpsw_emac1: slave@4a100300 {
  425. /* Filled in by U-Boot */
  426. mac-address = [ 00 00 00 00 00 00 ];
  427. };
  428. };
  429. ocmcram: ocmcram@40300000 {
  430. compatible = "ti,am3352-ocmcram";
  431. reg = <0x40300000 0x10000>;
  432. ti,hwmods = "ocmcram";
  433. ti,no_idle_on_suspend;
  434. };
  435. wkup_m3: wkup_m3@44d00000 {
  436. compatible = "ti,am3353-wkup-m3";
  437. reg = <0x44d00000 0x4000 /* M3 UMEM */
  438. 0x44d80000 0x2000>; /* M3 DMEM */
  439. ti,hwmods = "wkup_m3";
  440. };
  441. elm: elm@48080000 {
  442. compatible = "ti,am3352-elm";
  443. reg = <0x48080000 0x2000>;
  444. interrupts = <4>;
  445. ti,hwmods = "elm";
  446. status = "disabled";
  447. };
  448. gpmc: gpmc@50000000 {
  449. compatible = "ti,am3352-gpmc";
  450. ti,hwmods = "gpmc";
  451. reg = <0x50000000 0x2000>;
  452. interrupts = <100>;
  453. gpmc,num-cs = <7>;
  454. gpmc,num-waitpins = <2>;
  455. #address-cells = <2>;
  456. #size-cells = <1>;
  457. status = "disabled";
  458. };
  459. };
  460. };