Kconfig 65 KB

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  1. config ARM
  2. bool
  3. default y
  4. select ARCH_HAVE_CUSTOM_GPIO_H
  5. select HAVE_AOUT
  6. select HAVE_DMA_API_DEBUG
  7. select HAVE_IDE if PCI || ISA || PCMCIA
  8. select HAVE_DMA_ATTRS
  9. select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
  10. select HAVE_MEMBLOCK
  11. select RTC_LIB
  12. select SYS_SUPPORTS_APM_EMULATION
  13. select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  14. select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  15. select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  16. select HAVE_ARCH_KGDB
  17. select HAVE_ARCH_TRACEHOOK
  18. select HAVE_KPROBES if !XIP_KERNEL
  19. select HAVE_KRETPROBES if (HAVE_KPROBES)
  20. select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  21. select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  22. select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  23. select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  24. select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  25. select HAVE_GENERIC_DMA_COHERENT
  26. select HAVE_KERNEL_GZIP
  27. select HAVE_KERNEL_LZO
  28. select HAVE_KERNEL_LZMA
  29. select HAVE_KERNEL_XZ
  30. select HAVE_IRQ_WORK
  31. select HAVE_PERF_EVENTS
  32. select PERF_USE_VMALLOC
  33. select HAVE_REGS_AND_STACK_ACCESS_API
  34. select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  35. select HAVE_C_RECORDMCOUNT
  36. select HAVE_GENERIC_HARDIRQS
  37. select HARDIRQS_SW_RESEND
  38. select GENERIC_IRQ_PROBE
  39. select GENERIC_IRQ_SHOW
  40. select GENERIC_IRQ_PROBE
  41. select HARDIRQS_SW_RESEND
  42. select CPU_PM if (SUSPEND || CPU_IDLE)
  43. select GENERIC_PCI_IOMAP
  44. select HAVE_BPF_JIT
  45. select GENERIC_SMP_IDLE_THREAD
  46. select KTIME_SCALAR
  47. select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  48. help
  49. The ARM series is a line of low-power-consumption RISC chip designs
  50. licensed by ARM Ltd and targeted at embedded applications and
  51. handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
  52. manufactured, but legacy ARM-based PC hardware remains popular in
  53. Europe. There is an ARM Linux project with a web page at
  54. <http://www.arm.linux.org.uk/>.
  55. config ARM_HAS_SG_CHAIN
  56. bool
  57. config NEED_SG_DMA_LENGTH
  58. bool
  59. config ARM_DMA_USE_IOMMU
  60. select NEED_SG_DMA_LENGTH
  61. select ARM_HAS_SG_CHAIN
  62. bool
  63. config HAVE_PWM
  64. bool
  65. config MIGHT_HAVE_PCI
  66. bool
  67. config SYS_SUPPORTS_APM_EMULATION
  68. bool
  69. config GENERIC_GPIO
  70. bool
  71. config HAVE_TCM
  72. bool
  73. select GENERIC_ALLOCATOR
  74. config HAVE_PROC_CPU
  75. bool
  76. config NO_IOPORT
  77. bool
  78. config EISA
  79. bool
  80. ---help---
  81. The Extended Industry Standard Architecture (EISA) bus was
  82. developed as an open alternative to the IBM MicroChannel bus.
  83. The EISA bus provided some of the features of the IBM MicroChannel
  84. bus while maintaining backward compatibility with cards made for
  85. the older ISA bus. The EISA bus saw limited use between 1988 and
  86. 1995 when it was made obsolete by the PCI bus.
  87. Say Y here if you are building a kernel for an EISA-based machine.
  88. Otherwise, say N.
  89. config SBUS
  90. bool
  91. config STACKTRACE_SUPPORT
  92. bool
  93. default y
  94. config HAVE_LATENCYTOP_SUPPORT
  95. bool
  96. depends on !SMP
  97. default y
  98. config LOCKDEP_SUPPORT
  99. bool
  100. default y
  101. config TRACE_IRQFLAGS_SUPPORT
  102. bool
  103. default y
  104. config GENERIC_LOCKBREAK
  105. bool
  106. default y
  107. depends on SMP && PREEMPT
  108. config RWSEM_GENERIC_SPINLOCK
  109. bool
  110. default y
  111. config RWSEM_XCHGADD_ALGORITHM
  112. bool
  113. config ARCH_HAS_ILOG2_U32
  114. bool
  115. config ARCH_HAS_ILOG2_U64
  116. bool
  117. config ARCH_HAS_CPUFREQ
  118. bool
  119. help
  120. Internal node to signify that the ARCH has CPUFREQ support
  121. and that the relevant menu configurations are displayed for
  122. it.
  123. config GENERIC_HWEIGHT
  124. bool
  125. default y
  126. config GENERIC_CALIBRATE_DELAY
  127. bool
  128. default y
  129. config ARCH_MAY_HAVE_PC_FDC
  130. bool
  131. config ZONE_DMA
  132. bool
  133. config NEED_DMA_MAP_STATE
  134. def_bool y
  135. config ARCH_HAS_DMA_SET_COHERENT_MASK
  136. bool
  137. config GENERIC_ISA_DMA
  138. bool
  139. config FIQ
  140. bool
  141. config NEED_RET_TO_USER
  142. bool
  143. config ARCH_MTD_XIP
  144. bool
  145. config VECTORS_BASE
  146. hex
  147. default 0xffff0000 if MMU || CPU_HIGH_VECTOR
  148. default DRAM_BASE if REMAP_VECTORS_TO_RAM
  149. default 0x00000000
  150. help
  151. The base address of exception vectors.
  152. config ARM_PATCH_PHYS_VIRT
  153. bool "Patch physical to virtual translations at runtime" if EMBEDDED
  154. default y
  155. depends on !XIP_KERNEL && MMU
  156. depends on !ARCH_REALVIEW || !SPARSEMEM
  157. help
  158. Patch phys-to-virt and virt-to-phys translation functions at
  159. boot and module load time according to the position of the
  160. kernel in system memory.
  161. This can only be used with non-XIP MMU kernels where the base
  162. of physical memory is at a 16MB boundary.
  163. Only disable this option if you know that you do not require
  164. this feature (eg, building a kernel for a single machine) and
  165. you need to shrink the kernel to the minimal size.
  166. config NEED_MACH_IO_H
  167. bool
  168. help
  169. Select this when mach/io.h is required to provide special
  170. definitions for this platform. The need for mach/io.h should
  171. be avoided when possible.
  172. config NEED_MACH_MEMORY_H
  173. bool
  174. help
  175. Select this when mach/memory.h is required to provide special
  176. definitions for this platform. The need for mach/memory.h should
  177. be avoided when possible.
  178. config PHYS_OFFSET
  179. hex "Physical address of main memory" if MMU
  180. depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
  181. default DRAM_BASE if !MMU
  182. help
  183. Please provide the physical address corresponding to the
  184. location of main memory in your system.
  185. config GENERIC_BUG
  186. def_bool y
  187. depends on BUG
  188. source "init/Kconfig"
  189. source "kernel/Kconfig.freezer"
  190. menu "System Type"
  191. config MMU
  192. bool "MMU-based Paged Memory Management Support"
  193. default y
  194. help
  195. Select if you want MMU-based virtualised addressing space
  196. support by paged memory management. If unsure, say 'Y'.
  197. #
  198. # The "ARM system type" choice list is ordered alphabetically by option
  199. # text. Please add new entries in the option alphabetic order.
  200. #
  201. choice
  202. prompt "ARM system type"
  203. default ARCH_VERSATILE
  204. config ARCH_INTEGRATOR
  205. bool "ARM Ltd. Integrator family"
  206. select ARM_AMBA
  207. select ARCH_HAS_CPUFREQ
  208. select CLKDEV_LOOKUP
  209. select HAVE_MACH_CLKDEV
  210. select HAVE_TCM
  211. select ICST
  212. select GENERIC_CLOCKEVENTS
  213. select PLAT_VERSATILE
  214. select PLAT_VERSATILE_FPGA_IRQ
  215. select NEED_MACH_MEMORY_H
  216. select SPARSE_IRQ
  217. select MULTI_IRQ_HANDLER
  218. help
  219. Support for ARM's Integrator platform.
  220. config ARCH_REALVIEW
  221. bool "ARM Ltd. RealView family"
  222. select ARM_AMBA
  223. select CLKDEV_LOOKUP
  224. select HAVE_MACH_CLKDEV
  225. select ICST
  226. select GENERIC_CLOCKEVENTS
  227. select ARCH_WANT_OPTIONAL_GPIOLIB
  228. select PLAT_VERSATILE
  229. select PLAT_VERSATILE_CLCD
  230. select ARM_TIMER_SP804
  231. select GPIO_PL061 if GPIOLIB
  232. select NEED_MACH_MEMORY_H
  233. help
  234. This enables support for ARM Ltd RealView boards.
  235. config ARCH_VERSATILE
  236. bool "ARM Ltd. Versatile family"
  237. select ARM_AMBA
  238. select ARM_VIC
  239. select CLKDEV_LOOKUP
  240. select HAVE_MACH_CLKDEV
  241. select ICST
  242. select GENERIC_CLOCKEVENTS
  243. select ARCH_WANT_OPTIONAL_GPIOLIB
  244. select PLAT_VERSATILE
  245. select PLAT_VERSATILE_CLCD
  246. select PLAT_VERSATILE_FPGA_IRQ
  247. select ARM_TIMER_SP804
  248. help
  249. This enables support for ARM Ltd Versatile board.
  250. config ARCH_VEXPRESS
  251. bool "ARM Ltd. Versatile Express family"
  252. select ARCH_WANT_OPTIONAL_GPIOLIB
  253. select ARM_AMBA
  254. select ARM_TIMER_SP804
  255. select CLKDEV_LOOKUP
  256. select HAVE_MACH_CLKDEV
  257. select GENERIC_CLOCKEVENTS
  258. select HAVE_CLK
  259. select HAVE_PATA_PLATFORM
  260. select ICST
  261. select NO_IOPORT
  262. select PLAT_VERSATILE
  263. select PLAT_VERSATILE_CLCD
  264. help
  265. This enables support for the ARM Ltd Versatile Express boards.
  266. config ARCH_AT91
  267. bool "Atmel AT91"
  268. select ARCH_REQUIRE_GPIOLIB
  269. select HAVE_CLK
  270. select CLKDEV_LOOKUP
  271. select IRQ_DOMAIN
  272. select NEED_MACH_IO_H if PCCARD
  273. help
  274. This enables support for systems based on Atmel
  275. AT91RM9200 and AT91SAM9* processors.
  276. config ARCH_BCMRING
  277. bool "Broadcom BCMRING"
  278. depends on MMU
  279. select CPU_V6
  280. select ARM_AMBA
  281. select ARM_TIMER_SP804
  282. select CLKDEV_LOOKUP
  283. select GENERIC_CLOCKEVENTS
  284. select ARCH_WANT_OPTIONAL_GPIOLIB
  285. help
  286. Support for Broadcom's BCMRing platform.
  287. config ARCH_HIGHBANK
  288. bool "Calxeda Highbank-based"
  289. select ARCH_WANT_OPTIONAL_GPIOLIB
  290. select ARM_AMBA
  291. select ARM_GIC
  292. select ARM_TIMER_SP804
  293. select CACHE_L2X0
  294. select CLKDEV_LOOKUP
  295. select CPU_V7
  296. select GENERIC_CLOCKEVENTS
  297. select HAVE_ARM_SCU
  298. select HAVE_SMP
  299. select SPARSE_IRQ
  300. select USE_OF
  301. help
  302. Support for the Calxeda Highbank SoC based boards.
  303. config ARCH_CLPS711X
  304. bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
  305. select CPU_ARM720T
  306. select ARCH_USES_GETTIMEOFFSET
  307. select NEED_MACH_MEMORY_H
  308. help
  309. Support for Cirrus Logic 711x/721x/731x based boards.
  310. config ARCH_CNS3XXX
  311. bool "Cavium Networks CNS3XXX family"
  312. select CPU_V6K
  313. select GENERIC_CLOCKEVENTS
  314. select ARM_GIC
  315. select MIGHT_HAVE_CACHE_L2X0
  316. select MIGHT_HAVE_PCI
  317. select PCI_DOMAINS if PCI
  318. help
  319. Support for Cavium Networks CNS3XXX platform.
  320. config ARCH_GEMINI
  321. bool "Cortina Systems Gemini"
  322. select CPU_FA526
  323. select ARCH_REQUIRE_GPIOLIB
  324. select ARCH_USES_GETTIMEOFFSET
  325. help
  326. Support for the Cortina Systems Gemini family SoCs
  327. config ARCH_PRIMA2
  328. bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
  329. select CPU_V7
  330. select NO_IOPORT
  331. select GENERIC_CLOCKEVENTS
  332. select CLKDEV_LOOKUP
  333. select GENERIC_IRQ_CHIP
  334. select MIGHT_HAVE_CACHE_L2X0
  335. select PINCTRL
  336. select PINCTRL_SIRF
  337. select USE_OF
  338. select ZONE_DMA
  339. help
  340. Support for CSR SiRFSoC ARM Cortex A9 Platform
  341. config ARCH_EBSA110
  342. bool "EBSA-110"
  343. select CPU_SA110
  344. select ISA
  345. select NO_IOPORT
  346. select ARCH_USES_GETTIMEOFFSET
  347. select NEED_MACH_IO_H
  348. select NEED_MACH_MEMORY_H
  349. help
  350. This is an evaluation board for the StrongARM processor available
  351. from Digital. It has limited hardware on-board, including an
  352. Ethernet interface, two PCMCIA sockets, two serial ports and a
  353. parallel port.
  354. config ARCH_EP93XX
  355. bool "EP93xx-based"
  356. select CPU_ARM920T
  357. select ARM_AMBA
  358. select ARM_VIC
  359. select CLKDEV_LOOKUP
  360. select ARCH_REQUIRE_GPIOLIB
  361. select ARCH_HAS_HOLES_MEMORYMODEL
  362. select ARCH_USES_GETTIMEOFFSET
  363. select NEED_MACH_MEMORY_H
  364. help
  365. This enables support for the Cirrus EP93xx series of CPUs.
  366. config ARCH_FOOTBRIDGE
  367. bool "FootBridge"
  368. select CPU_SA110
  369. select FOOTBRIDGE
  370. select GENERIC_CLOCKEVENTS
  371. select HAVE_IDE
  372. select NEED_MACH_IO_H if !MMU
  373. select NEED_MACH_MEMORY_H
  374. help
  375. Support for systems based on the DC21285 companion chip
  376. ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
  377. config ARCH_MXC
  378. bool "Freescale MXC/iMX-based"
  379. select GENERIC_CLOCKEVENTS
  380. select ARCH_REQUIRE_GPIOLIB
  381. select CLKDEV_LOOKUP
  382. select CLKSRC_MMIO
  383. select GENERIC_IRQ_CHIP
  384. select MULTI_IRQ_HANDLER
  385. help
  386. Support for Freescale MXC/iMX-based family of processors
  387. config ARCH_MXS
  388. bool "Freescale MXS-based"
  389. select GENERIC_CLOCKEVENTS
  390. select ARCH_REQUIRE_GPIOLIB
  391. select CLKDEV_LOOKUP
  392. select CLKSRC_MMIO
  393. select COMMON_CLK
  394. select HAVE_CLK_PREPARE
  395. select PINCTRL
  396. select USE_OF
  397. help
  398. Support for Freescale MXS-based family of processors
  399. config ARCH_NETX
  400. bool "Hilscher NetX based"
  401. select CLKSRC_MMIO
  402. select CPU_ARM926T
  403. select ARM_VIC
  404. select GENERIC_CLOCKEVENTS
  405. help
  406. This enables support for systems based on the Hilscher NetX Soc
  407. config ARCH_H720X
  408. bool "Hynix HMS720x-based"
  409. select CPU_ARM720T
  410. select ISA_DMA_API
  411. select ARCH_USES_GETTIMEOFFSET
  412. help
  413. This enables support for systems based on the Hynix HMS720x
  414. config ARCH_IOP13XX
  415. bool "IOP13xx-based"
  416. depends on MMU
  417. select CPU_XSC3
  418. select PLAT_IOP
  419. select PCI
  420. select ARCH_SUPPORTS_MSI
  421. select VMSPLIT_1G
  422. select NEED_MACH_IO_H
  423. select NEED_MACH_MEMORY_H
  424. select NEED_RET_TO_USER
  425. help
  426. Support for Intel's IOP13XX (XScale) family of processors.
  427. config ARCH_IOP32X
  428. bool "IOP32x-based"
  429. depends on MMU
  430. select CPU_XSCALE
  431. select NEED_MACH_IO_H
  432. select NEED_RET_TO_USER
  433. select PLAT_IOP
  434. select PCI
  435. select ARCH_REQUIRE_GPIOLIB
  436. help
  437. Support for Intel's 80219 and IOP32X (XScale) family of
  438. processors.
  439. config ARCH_IOP33X
  440. bool "IOP33x-based"
  441. depends on MMU
  442. select CPU_XSCALE
  443. select NEED_MACH_IO_H
  444. select NEED_RET_TO_USER
  445. select PLAT_IOP
  446. select PCI
  447. select ARCH_REQUIRE_GPIOLIB
  448. help
  449. Support for Intel's IOP33X (XScale) family of processors.
  450. config ARCH_IXP4XX
  451. bool "IXP4xx-based"
  452. depends on MMU
  453. select ARCH_HAS_DMA_SET_COHERENT_MASK
  454. select CLKSRC_MMIO
  455. select CPU_XSCALE
  456. select ARCH_REQUIRE_GPIOLIB
  457. select GENERIC_CLOCKEVENTS
  458. select MIGHT_HAVE_PCI
  459. select NEED_MACH_IO_H
  460. select DMABOUNCE if PCI
  461. help
  462. Support for Intel's IXP4XX (XScale) family of processors.
  463. config ARCH_DOVE
  464. bool "Marvell Dove"
  465. select CPU_V7
  466. select PCI
  467. select ARCH_REQUIRE_GPIOLIB
  468. select GENERIC_CLOCKEVENTS
  469. select PLAT_ORION
  470. help
  471. Support for the Marvell Dove SoC 88AP510
  472. config ARCH_KIRKWOOD
  473. bool "Marvell Kirkwood"
  474. select CPU_FEROCEON
  475. select PCI
  476. select ARCH_REQUIRE_GPIOLIB
  477. select GENERIC_CLOCKEVENTS
  478. select PLAT_ORION
  479. help
  480. Support for the following Marvell Kirkwood series SoCs:
  481. 88F6180, 88F6192 and 88F6281.
  482. config ARCH_LPC32XX
  483. bool "NXP LPC32XX"
  484. select CLKSRC_MMIO
  485. select CPU_ARM926T
  486. select ARCH_REQUIRE_GPIOLIB
  487. select HAVE_IDE
  488. select ARM_AMBA
  489. select USB_ARCH_HAS_OHCI
  490. select CLKDEV_LOOKUP
  491. select GENERIC_CLOCKEVENTS
  492. select USE_OF
  493. help
  494. Support for the NXP LPC32XX family of processors
  495. config ARCH_MV78XX0
  496. bool "Marvell MV78xx0"
  497. select CPU_FEROCEON
  498. select PCI
  499. select ARCH_REQUIRE_GPIOLIB
  500. select GENERIC_CLOCKEVENTS
  501. select NEED_MACH_IO_H
  502. select PLAT_ORION
  503. help
  504. Support for the following Marvell MV78xx0 series SoCs:
  505. MV781x0, MV782x0.
  506. config ARCH_ORION5X
  507. bool "Marvell Orion"
  508. depends on MMU
  509. select CPU_FEROCEON
  510. select PCI
  511. select ARCH_REQUIRE_GPIOLIB
  512. select GENERIC_CLOCKEVENTS
  513. select PLAT_ORION
  514. help
  515. Support for the following Marvell Orion 5x series SoCs:
  516. Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
  517. Orion-2 (5281), Orion-1-90 (6183).
  518. config ARCH_MMP
  519. bool "Marvell PXA168/910/MMP2"
  520. depends on MMU
  521. select ARCH_REQUIRE_GPIOLIB
  522. select CLKDEV_LOOKUP
  523. select GENERIC_CLOCKEVENTS
  524. select GPIO_PXA
  525. select IRQ_DOMAIN
  526. select PLAT_PXA
  527. select SPARSE_IRQ
  528. select GENERIC_ALLOCATOR
  529. help
  530. Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
  531. config ARCH_KS8695
  532. bool "Micrel/Kendin KS8695"
  533. select CPU_ARM922T
  534. select ARCH_REQUIRE_GPIOLIB
  535. select ARCH_USES_GETTIMEOFFSET
  536. select NEED_MACH_MEMORY_H
  537. help
  538. Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
  539. System-on-Chip devices.
  540. config ARCH_W90X900
  541. bool "Nuvoton W90X900 CPU"
  542. select CPU_ARM926T
  543. select ARCH_REQUIRE_GPIOLIB
  544. select CLKDEV_LOOKUP
  545. select CLKSRC_MMIO
  546. select GENERIC_CLOCKEVENTS
  547. help
  548. Support for Nuvoton (Winbond logic dept.) ARM9 processor,
  549. At present, the w90x900 has been renamed nuc900, regarding
  550. the ARM series product line, you can login the following
  551. link address to know more.
  552. <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
  553. ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
  554. config ARCH_TEGRA
  555. bool "NVIDIA Tegra"
  556. select CLKDEV_LOOKUP
  557. select CLKSRC_MMIO
  558. select GENERIC_CLOCKEVENTS
  559. select GENERIC_GPIO
  560. select HAVE_CLK
  561. select HAVE_SMP
  562. select MIGHT_HAVE_CACHE_L2X0
  563. select ARCH_HAS_CPUFREQ
  564. help
  565. This enables support for NVIDIA Tegra based systems (Tegra APX,
  566. Tegra 6xx and Tegra 2 series).
  567. config ARCH_PICOXCELL
  568. bool "Picochip picoXcell"
  569. select ARCH_REQUIRE_GPIOLIB
  570. select ARM_PATCH_PHYS_VIRT
  571. select ARM_VIC
  572. select CPU_V6K
  573. select DW_APB_TIMER
  574. select GENERIC_CLOCKEVENTS
  575. select GENERIC_GPIO
  576. select HAVE_TCM
  577. select NO_IOPORT
  578. select SPARSE_IRQ
  579. select USE_OF
  580. help
  581. This enables support for systems based on the Picochip picoXcell
  582. family of Femtocell devices. The picoxcell support requires device tree
  583. for all boards.
  584. config ARCH_PNX4008
  585. bool "Philips Nexperia PNX4008 Mobile"
  586. select CPU_ARM926T
  587. select CLKDEV_LOOKUP
  588. select ARCH_USES_GETTIMEOFFSET
  589. help
  590. This enables support for Philips PNX4008 mobile platform.
  591. config ARCH_PXA
  592. bool "PXA2xx/PXA3xx-based"
  593. depends on MMU
  594. select ARCH_MTD_XIP
  595. select ARCH_HAS_CPUFREQ
  596. select CLKDEV_LOOKUP
  597. select CLKSRC_MMIO
  598. select ARCH_REQUIRE_GPIOLIB
  599. select GENERIC_CLOCKEVENTS
  600. select GPIO_PXA
  601. select PLAT_PXA
  602. select SPARSE_IRQ
  603. select AUTO_ZRELADDR
  604. select MULTI_IRQ_HANDLER
  605. select ARM_CPU_SUSPEND if PM
  606. select HAVE_IDE
  607. help
  608. Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
  609. config ARCH_MSM
  610. bool "Qualcomm MSM"
  611. select HAVE_CLK
  612. select GENERIC_CLOCKEVENTS
  613. select ARCH_REQUIRE_GPIOLIB
  614. select CLKDEV_LOOKUP
  615. help
  616. Support for Qualcomm MSM/QSD based systems. This runs on the
  617. apps processor of the MSM/QSD and depends on a shared memory
  618. interface to the modem processor which runs the baseband
  619. stack and controls some vital subsystems
  620. (clock and power control, etc).
  621. config ARCH_SHMOBILE
  622. bool "Renesas SH-Mobile / R-Mobile"
  623. select HAVE_CLK
  624. select CLKDEV_LOOKUP
  625. select HAVE_MACH_CLKDEV
  626. select HAVE_SMP
  627. select GENERIC_CLOCKEVENTS
  628. select MIGHT_HAVE_CACHE_L2X0
  629. select NO_IOPORT
  630. select SPARSE_IRQ
  631. select MULTI_IRQ_HANDLER
  632. select PM_GENERIC_DOMAINS if PM
  633. select NEED_MACH_MEMORY_H
  634. help
  635. Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
  636. config ARCH_RPC
  637. bool "RiscPC"
  638. select ARCH_ACORN
  639. select FIQ
  640. select ARCH_MAY_HAVE_PC_FDC
  641. select HAVE_PATA_PLATFORM
  642. select ISA_DMA_API
  643. select NO_IOPORT
  644. select ARCH_SPARSEMEM_ENABLE
  645. select ARCH_USES_GETTIMEOFFSET
  646. select HAVE_IDE
  647. select NEED_MACH_IO_H
  648. select NEED_MACH_MEMORY_H
  649. help
  650. On the Acorn Risc-PC, Linux can support the internal IDE disk and
  651. CD-ROM interface, serial and parallel port, and the floppy drive.
  652. config ARCH_SA1100
  653. bool "SA1100-based"
  654. select CLKSRC_MMIO
  655. select CPU_SA1100
  656. select ISA
  657. select ARCH_SPARSEMEM_ENABLE
  658. select ARCH_MTD_XIP
  659. select ARCH_HAS_CPUFREQ
  660. select CPU_FREQ
  661. select GENERIC_CLOCKEVENTS
  662. select CLKDEV_LOOKUP
  663. select ARCH_REQUIRE_GPIOLIB
  664. select HAVE_IDE
  665. select NEED_MACH_MEMORY_H
  666. select SPARSE_IRQ
  667. help
  668. Support for StrongARM 11x0 based boards.
  669. config ARCH_S3C24XX
  670. bool "Samsung S3C24XX SoCs"
  671. select GENERIC_GPIO
  672. select ARCH_HAS_CPUFREQ
  673. select HAVE_CLK
  674. select CLKDEV_LOOKUP
  675. select ARCH_USES_GETTIMEOFFSET
  676. select HAVE_S3C2410_I2C if I2C
  677. select HAVE_S3C_RTC if RTC_CLASS
  678. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  679. select NEED_MACH_IO_H
  680. help
  681. Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
  682. and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
  683. (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
  684. Samsung SMDK2410 development board (and derivatives).
  685. config ARCH_S3C64XX
  686. bool "Samsung S3C64XX"
  687. select PLAT_SAMSUNG
  688. select CPU_V6
  689. select ARM_VIC
  690. select HAVE_CLK
  691. select HAVE_TCM
  692. select CLKDEV_LOOKUP
  693. select NO_IOPORT
  694. select ARCH_USES_GETTIMEOFFSET
  695. select ARCH_HAS_CPUFREQ
  696. select ARCH_REQUIRE_GPIOLIB
  697. select SAMSUNG_CLKSRC
  698. select SAMSUNG_IRQ_VIC_TIMER
  699. select S3C_GPIO_TRACK
  700. select S3C_DEV_NAND
  701. select USB_ARCH_HAS_OHCI
  702. select SAMSUNG_GPIOLIB_4BIT
  703. select HAVE_S3C2410_I2C if I2C
  704. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  705. help
  706. Samsung S3C64XX series based systems
  707. config ARCH_S5P64X0
  708. bool "Samsung S5P6440 S5P6450"
  709. select CPU_V6
  710. select GENERIC_GPIO
  711. select HAVE_CLK
  712. select CLKDEV_LOOKUP
  713. select CLKSRC_MMIO
  714. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  715. select GENERIC_CLOCKEVENTS
  716. select HAVE_S3C2410_I2C if I2C
  717. select HAVE_S3C_RTC if RTC_CLASS
  718. help
  719. Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
  720. SMDK6450.
  721. config ARCH_S5PC100
  722. bool "Samsung S5PC100"
  723. select GENERIC_GPIO
  724. select HAVE_CLK
  725. select CLKDEV_LOOKUP
  726. select CPU_V7
  727. select ARCH_USES_GETTIMEOFFSET
  728. select HAVE_S3C2410_I2C if I2C
  729. select HAVE_S3C_RTC if RTC_CLASS
  730. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  731. help
  732. Samsung S5PC100 series based systems
  733. config ARCH_S5PV210
  734. bool "Samsung S5PV210/S5PC110"
  735. select CPU_V7
  736. select ARCH_SPARSEMEM_ENABLE
  737. select ARCH_HAS_HOLES_MEMORYMODEL
  738. select GENERIC_GPIO
  739. select HAVE_CLK
  740. select CLKDEV_LOOKUP
  741. select CLKSRC_MMIO
  742. select ARCH_HAS_CPUFREQ
  743. select GENERIC_CLOCKEVENTS
  744. select HAVE_S3C2410_I2C if I2C
  745. select HAVE_S3C_RTC if RTC_CLASS
  746. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  747. select NEED_MACH_MEMORY_H
  748. help
  749. Samsung S5PV210/S5PC110 series based systems
  750. config ARCH_EXYNOS
  751. bool "SAMSUNG EXYNOS"
  752. select CPU_V7
  753. select ARCH_SPARSEMEM_ENABLE
  754. select ARCH_HAS_HOLES_MEMORYMODEL
  755. select GENERIC_GPIO
  756. select HAVE_CLK
  757. select CLKDEV_LOOKUP
  758. select ARCH_HAS_CPUFREQ
  759. select GENERIC_CLOCKEVENTS
  760. select HAVE_S3C_RTC if RTC_CLASS
  761. select HAVE_S3C2410_I2C if I2C
  762. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  763. select NEED_MACH_MEMORY_H
  764. help
  765. Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
  766. config ARCH_SHARK
  767. bool "Shark"
  768. select CPU_SA110
  769. select ISA
  770. select ISA_DMA
  771. select ZONE_DMA
  772. select PCI
  773. select ARCH_USES_GETTIMEOFFSET
  774. select NEED_MACH_MEMORY_H
  775. help
  776. Support for the StrongARM based Digital DNARD machine, also known
  777. as "Shark" (<http://www.shark-linux.de/shark.html>).
  778. config ARCH_U300
  779. bool "ST-Ericsson U300 Series"
  780. depends on MMU
  781. select CLKSRC_MMIO
  782. select CPU_ARM926T
  783. select HAVE_TCM
  784. select ARM_AMBA
  785. select ARM_PATCH_PHYS_VIRT
  786. select ARM_VIC
  787. select GENERIC_CLOCKEVENTS
  788. select CLKDEV_LOOKUP
  789. select HAVE_MACH_CLKDEV
  790. select GENERIC_GPIO
  791. select ARCH_REQUIRE_GPIOLIB
  792. help
  793. Support for ST-Ericsson U300 series mobile platforms.
  794. config ARCH_U8500
  795. bool "ST-Ericsson U8500 Series"
  796. depends on MMU
  797. select CPU_V7
  798. select ARM_AMBA
  799. select GENERIC_CLOCKEVENTS
  800. select CLKDEV_LOOKUP
  801. select ARCH_REQUIRE_GPIOLIB
  802. select ARCH_HAS_CPUFREQ
  803. select HAVE_SMP
  804. select MIGHT_HAVE_CACHE_L2X0
  805. help
  806. Support for ST-Ericsson's Ux500 architecture
  807. config ARCH_NOMADIK
  808. bool "STMicroelectronics Nomadik"
  809. select ARM_AMBA
  810. select ARM_VIC
  811. select CPU_ARM926T
  812. select CLKDEV_LOOKUP
  813. select GENERIC_CLOCKEVENTS
  814. select PINCTRL
  815. select MIGHT_HAVE_CACHE_L2X0
  816. select ARCH_REQUIRE_GPIOLIB
  817. help
  818. Support for the Nomadik platform by ST-Ericsson
  819. config ARCH_DAVINCI
  820. bool "TI DaVinci"
  821. select GENERIC_CLOCKEVENTS
  822. select ARCH_REQUIRE_GPIOLIB
  823. select ZONE_DMA
  824. select HAVE_IDE
  825. select CLKDEV_LOOKUP
  826. select GENERIC_ALLOCATOR
  827. select GENERIC_IRQ_CHIP
  828. select ARCH_HAS_HOLES_MEMORYMODEL
  829. help
  830. Support for TI's DaVinci platform.
  831. config ARCH_OMAP
  832. bool "TI OMAP"
  833. select HAVE_CLK
  834. select ARCH_REQUIRE_GPIOLIB
  835. select ARCH_HAS_CPUFREQ
  836. select CLKSRC_MMIO
  837. select GENERIC_CLOCKEVENTS
  838. select ARCH_HAS_HOLES_MEMORYMODEL
  839. help
  840. Support for TI's OMAP platform (OMAP1/2/3/4).
  841. config PLAT_SPEAR
  842. bool "ST SPEAr"
  843. select ARM_AMBA
  844. select ARCH_REQUIRE_GPIOLIB
  845. select CLKDEV_LOOKUP
  846. select COMMON_CLK
  847. select CLKSRC_MMIO
  848. select GENERIC_CLOCKEVENTS
  849. select HAVE_CLK
  850. help
  851. Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
  852. config ARCH_VT8500
  853. bool "VIA/WonderMedia 85xx"
  854. select CPU_ARM926T
  855. select GENERIC_GPIO
  856. select ARCH_HAS_CPUFREQ
  857. select GENERIC_CLOCKEVENTS
  858. select ARCH_REQUIRE_GPIOLIB
  859. select HAVE_PWM
  860. help
  861. Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
  862. config ARCH_ZYNQ
  863. bool "Xilinx Zynq ARM Cortex A9 Platform"
  864. select CPU_V7
  865. select GENERIC_CLOCKEVENTS
  866. select CLKDEV_LOOKUP
  867. select ARM_GIC
  868. select ARM_AMBA
  869. select ICST
  870. select MIGHT_HAVE_CACHE_L2X0
  871. select USE_OF
  872. help
  873. Support for Xilinx Zynq ARM Cortex A9 Platform
  874. endchoice
  875. #
  876. # This is sorted alphabetically by mach-* pathname. However, plat-*
  877. # Kconfigs may be included either alphabetically (according to the
  878. # plat- suffix) or along side the corresponding mach-* source.
  879. #
  880. source "arch/arm/mach-at91/Kconfig"
  881. source "arch/arm/mach-bcmring/Kconfig"
  882. source "arch/arm/mach-clps711x/Kconfig"
  883. source "arch/arm/mach-cns3xxx/Kconfig"
  884. source "arch/arm/mach-davinci/Kconfig"
  885. source "arch/arm/mach-dove/Kconfig"
  886. source "arch/arm/mach-ep93xx/Kconfig"
  887. source "arch/arm/mach-footbridge/Kconfig"
  888. source "arch/arm/mach-gemini/Kconfig"
  889. source "arch/arm/mach-h720x/Kconfig"
  890. source "arch/arm/mach-integrator/Kconfig"
  891. source "arch/arm/mach-iop32x/Kconfig"
  892. source "arch/arm/mach-iop33x/Kconfig"
  893. source "arch/arm/mach-iop13xx/Kconfig"
  894. source "arch/arm/mach-ixp4xx/Kconfig"
  895. source "arch/arm/mach-kirkwood/Kconfig"
  896. source "arch/arm/mach-ks8695/Kconfig"
  897. source "arch/arm/mach-lpc32xx/Kconfig"
  898. source "arch/arm/mach-msm/Kconfig"
  899. source "arch/arm/mach-mv78xx0/Kconfig"
  900. source "arch/arm/plat-mxc/Kconfig"
  901. source "arch/arm/mach-mxs/Kconfig"
  902. source "arch/arm/mach-netx/Kconfig"
  903. source "arch/arm/mach-nomadik/Kconfig"
  904. source "arch/arm/plat-nomadik/Kconfig"
  905. source "arch/arm/plat-omap/Kconfig"
  906. source "arch/arm/mach-omap1/Kconfig"
  907. source "arch/arm/mach-omap2/Kconfig"
  908. source "arch/arm/mach-orion5x/Kconfig"
  909. source "arch/arm/mach-pxa/Kconfig"
  910. source "arch/arm/plat-pxa/Kconfig"
  911. source "arch/arm/mach-mmp/Kconfig"
  912. source "arch/arm/mach-realview/Kconfig"
  913. source "arch/arm/mach-sa1100/Kconfig"
  914. source "arch/arm/plat-samsung/Kconfig"
  915. source "arch/arm/plat-s3c24xx/Kconfig"
  916. source "arch/arm/plat-spear/Kconfig"
  917. source "arch/arm/mach-s3c24xx/Kconfig"
  918. if ARCH_S3C24XX
  919. source "arch/arm/mach-s3c2412/Kconfig"
  920. source "arch/arm/mach-s3c2440/Kconfig"
  921. endif
  922. if ARCH_S3C64XX
  923. source "arch/arm/mach-s3c64xx/Kconfig"
  924. endif
  925. source "arch/arm/mach-s5p64x0/Kconfig"
  926. source "arch/arm/mach-s5pc100/Kconfig"
  927. source "arch/arm/mach-s5pv210/Kconfig"
  928. source "arch/arm/mach-exynos/Kconfig"
  929. source "arch/arm/mach-shmobile/Kconfig"
  930. source "arch/arm/mach-tegra/Kconfig"
  931. source "arch/arm/mach-u300/Kconfig"
  932. source "arch/arm/mach-ux500/Kconfig"
  933. source "arch/arm/mach-versatile/Kconfig"
  934. source "arch/arm/mach-vexpress/Kconfig"
  935. source "arch/arm/plat-versatile/Kconfig"
  936. source "arch/arm/mach-vt8500/Kconfig"
  937. source "arch/arm/mach-w90x900/Kconfig"
  938. # Definitions to make life easier
  939. config ARCH_ACORN
  940. bool
  941. config PLAT_IOP
  942. bool
  943. select GENERIC_CLOCKEVENTS
  944. config PLAT_ORION
  945. bool
  946. select CLKSRC_MMIO
  947. select GENERIC_IRQ_CHIP
  948. select COMMON_CLK
  949. config PLAT_PXA
  950. bool
  951. config PLAT_VERSATILE
  952. bool
  953. config ARM_TIMER_SP804
  954. bool
  955. select CLKSRC_MMIO
  956. select HAVE_SCHED_CLOCK
  957. source arch/arm/mm/Kconfig
  958. config ARM_NR_BANKS
  959. int
  960. default 16 if ARCH_EP93XX
  961. default 8
  962. config IWMMXT
  963. bool "Enable iWMMXt support"
  964. depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
  965. default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
  966. help
  967. Enable support for iWMMXt context switching at run time if
  968. running on a CPU that supports it.
  969. config XSCALE_PMU
  970. bool
  971. depends on CPU_XSCALE
  972. default y
  973. config CPU_HAS_PMU
  974. depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
  975. (!ARCH_OMAP3 || OMAP3_EMU)
  976. default y
  977. bool
  978. config MULTI_IRQ_HANDLER
  979. bool
  980. help
  981. Allow each machine to specify it's own IRQ handler at run time.
  982. if !MMU
  983. source "arch/arm/Kconfig-nommu"
  984. endif
  985. config ARM_ERRATA_326103
  986. bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
  987. depends on CPU_V6
  988. help
  989. Executing a SWP instruction to read-only memory does not set bit 11
  990. of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
  991. treat the access as a read, preventing a COW from occurring and
  992. causing the faulting task to livelock.
  993. config ARM_ERRATA_411920
  994. bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
  995. depends on CPU_V6 || CPU_V6K
  996. help
  997. Invalidation of the Instruction Cache operation can
  998. fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
  999. It does not affect the MPCore. This option enables the ARM Ltd.
  1000. recommended workaround.
  1001. config ARM_ERRATA_430973
  1002. bool "ARM errata: Stale prediction on replaced interworking branch"
  1003. depends on CPU_V7
  1004. help
  1005. This option enables the workaround for the 430973 Cortex-A8
  1006. (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
  1007. interworking branch is replaced with another code sequence at the
  1008. same virtual address, whether due to self-modifying code or virtual
  1009. to physical address re-mapping, Cortex-A8 does not recover from the
  1010. stale interworking branch prediction. This results in Cortex-A8
  1011. executing the new code sequence in the incorrect ARM or Thumb state.
  1012. The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
  1013. and also flushes the branch target cache at every context switch.
  1014. Note that setting specific bits in the ACTLR register may not be
  1015. available in non-secure mode.
  1016. config ARM_ERRATA_458693
  1017. bool "ARM errata: Processor deadlock when a false hazard is created"
  1018. depends on CPU_V7
  1019. help
  1020. This option enables the workaround for the 458693 Cortex-A8 (r2p0)
  1021. erratum. For very specific sequences of memory operations, it is
  1022. possible for a hazard condition intended for a cache line to instead
  1023. be incorrectly associated with a different cache line. This false
  1024. hazard might then cause a processor deadlock. The workaround enables
  1025. the L1 caching of the NEON accesses and disables the PLD instruction
  1026. in the ACTLR register. Note that setting specific bits in the ACTLR
  1027. register may not be available in non-secure mode.
  1028. config ARM_ERRATA_460075
  1029. bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
  1030. depends on CPU_V7
  1031. help
  1032. This option enables the workaround for the 460075 Cortex-A8 (r2p0)
  1033. erratum. Any asynchronous access to the L2 cache may encounter a
  1034. situation in which recent store transactions to the L2 cache are lost
  1035. and overwritten with stale memory contents from external memory. The
  1036. workaround disables the write-allocate mode for the L2 cache via the
  1037. ACTLR register. Note that setting specific bits in the ACTLR register
  1038. may not be available in non-secure mode.
  1039. config ARM_ERRATA_742230
  1040. bool "ARM errata: DMB operation may be faulty"
  1041. depends on CPU_V7 && SMP
  1042. help
  1043. This option enables the workaround for the 742230 Cortex-A9
  1044. (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
  1045. between two write operations may not ensure the correct visibility
  1046. ordering of the two writes. This workaround sets a specific bit in
  1047. the diagnostic register of the Cortex-A9 which causes the DMB
  1048. instruction to behave as a DSB, ensuring the correct behaviour of
  1049. the two writes.
  1050. config ARM_ERRATA_742231
  1051. bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
  1052. depends on CPU_V7 && SMP
  1053. help
  1054. This option enables the workaround for the 742231 Cortex-A9
  1055. (r2p0..r2p2) erratum. Under certain conditions, specific to the
  1056. Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
  1057. accessing some data located in the same cache line, may get corrupted
  1058. data due to bad handling of the address hazard when the line gets
  1059. replaced from one of the CPUs at the same time as another CPU is
  1060. accessing it. This workaround sets specific bits in the diagnostic
  1061. register of the Cortex-A9 which reduces the linefill issuing
  1062. capabilities of the processor.
  1063. config PL310_ERRATA_588369
  1064. bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
  1065. depends on CACHE_L2X0
  1066. help
  1067. The PL310 L2 cache controller implements three types of Clean &
  1068. Invalidate maintenance operations: by Physical Address
  1069. (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
  1070. They are architecturally defined to behave as the execution of a
  1071. clean operation followed immediately by an invalidate operation,
  1072. both performing to the same memory location. This functionality
  1073. is not correctly implemented in PL310 as clean lines are not
  1074. invalidated as a result of these operations.
  1075. config ARM_ERRATA_720789
  1076. bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
  1077. depends on CPU_V7
  1078. help
  1079. This option enables the workaround for the 720789 Cortex-A9 (prior to
  1080. r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
  1081. broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
  1082. As a consequence of this erratum, some TLB entries which should be
  1083. invalidated are not, resulting in an incoherency in the system page
  1084. tables. The workaround changes the TLB flushing routines to invalidate
  1085. entries regardless of the ASID.
  1086. config PL310_ERRATA_727915
  1087. bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
  1088. depends on CACHE_L2X0
  1089. help
  1090. PL310 implements the Clean & Invalidate by Way L2 cache maintenance
  1091. operation (offset 0x7FC). This operation runs in background so that
  1092. PL310 can handle normal accesses while it is in progress. Under very
  1093. rare circumstances, due to this erratum, write data can be lost when
  1094. PL310 treats a cacheable write transaction during a Clean &
  1095. Invalidate by Way operation.
  1096. config ARM_ERRATA_743622
  1097. bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
  1098. depends on CPU_V7
  1099. help
  1100. This option enables the workaround for the 743622 Cortex-A9
  1101. (r2p*) erratum. Under very rare conditions, a faulty
  1102. optimisation in the Cortex-A9 Store Buffer may lead to data
  1103. corruption. This workaround sets a specific bit in the diagnostic
  1104. register of the Cortex-A9 which disables the Store Buffer
  1105. optimisation, preventing the defect from occurring. This has no
  1106. visible impact on the overall performance or power consumption of the
  1107. processor.
  1108. config ARM_ERRATA_751472
  1109. bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
  1110. depends on CPU_V7
  1111. help
  1112. This option enables the workaround for the 751472 Cortex-A9 (prior
  1113. to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
  1114. completion of a following broadcasted operation if the second
  1115. operation is received by a CPU before the ICIALLUIS has completed,
  1116. potentially leading to corrupted entries in the cache or TLB.
  1117. config PL310_ERRATA_753970
  1118. bool "PL310 errata: cache sync operation may be faulty"
  1119. depends on CACHE_PL310
  1120. help
  1121. This option enables the workaround for the 753970 PL310 (r3p0) erratum.
  1122. Under some condition the effect of cache sync operation on
  1123. the store buffer still remains when the operation completes.
  1124. This means that the store buffer is always asked to drain and
  1125. this prevents it from merging any further writes. The workaround
  1126. is to replace the normal offset of cache sync operation (0x730)
  1127. by another offset targeting an unmapped PL310 register 0x740.
  1128. This has the same effect as the cache sync operation: store buffer
  1129. drain and waiting for all buffers empty.
  1130. config ARM_ERRATA_754322
  1131. bool "ARM errata: possible faulty MMU translations following an ASID switch"
  1132. depends on CPU_V7
  1133. help
  1134. This option enables the workaround for the 754322 Cortex-A9 (r2p*,
  1135. r3p*) erratum. A speculative memory access may cause a page table walk
  1136. which starts prior to an ASID switch but completes afterwards. This
  1137. can populate the micro-TLB with a stale entry which may be hit with
  1138. the new ASID. This workaround places two dsb instructions in the mm
  1139. switching code so that no page table walks can cross the ASID switch.
  1140. config ARM_ERRATA_754327
  1141. bool "ARM errata: no automatic Store Buffer drain"
  1142. depends on CPU_V7 && SMP
  1143. help
  1144. This option enables the workaround for the 754327 Cortex-A9 (prior to
  1145. r2p0) erratum. The Store Buffer does not have any automatic draining
  1146. mechanism and therefore a livelock may occur if an external agent
  1147. continuously polls a memory location waiting to observe an update.
  1148. This workaround defines cpu_relax() as smp_mb(), preventing correctly
  1149. written polling loops from denying visibility of updates to memory.
  1150. config ARM_ERRATA_364296
  1151. bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
  1152. depends on CPU_V6 && !SMP
  1153. help
  1154. This options enables the workaround for the 364296 ARM1136
  1155. r0p2 erratum (possible cache data corruption with
  1156. hit-under-miss enabled). It sets the undocumented bit 31 in
  1157. the auxiliary control register and the FI bit in the control
  1158. register, thus disabling hit-under-miss without putting the
  1159. processor into full low interrupt latency mode. ARM11MPCore
  1160. is not affected.
  1161. config ARM_ERRATA_764369
  1162. bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
  1163. depends on CPU_V7 && SMP
  1164. help
  1165. This option enables the workaround for erratum 764369
  1166. affecting Cortex-A9 MPCore with two or more processors (all
  1167. current revisions). Under certain timing circumstances, a data
  1168. cache line maintenance operation by MVA targeting an Inner
  1169. Shareable memory region may fail to proceed up to either the
  1170. Point of Coherency or to the Point of Unification of the
  1171. system. This workaround adds a DSB instruction before the
  1172. relevant cache maintenance functions and sets a specific bit
  1173. in the diagnostic control register of the SCU.
  1174. config PL310_ERRATA_769419
  1175. bool "PL310 errata: no automatic Store Buffer drain"
  1176. depends on CACHE_L2X0
  1177. help
  1178. On revisions of the PL310 prior to r3p2, the Store Buffer does
  1179. not automatically drain. This can cause normal, non-cacheable
  1180. writes to be retained when the memory system is idle, leading
  1181. to suboptimal I/O performance for drivers using coherent DMA.
  1182. This option adds a write barrier to the cpu_idle loop so that,
  1183. on systems with an outer cache, the store buffer is drained
  1184. explicitly.
  1185. endmenu
  1186. source "arch/arm/common/Kconfig"
  1187. menu "Bus support"
  1188. config ARM_AMBA
  1189. bool
  1190. config ISA
  1191. bool
  1192. help
  1193. Find out whether you have ISA slots on your motherboard. ISA is the
  1194. name of a bus system, i.e. the way the CPU talks to the other stuff
  1195. inside your box. Other bus systems are PCI, EISA, MicroChannel
  1196. (MCA) or VESA. ISA is an older system, now being displaced by PCI;
  1197. newer boards don't support it. If you have ISA, say Y, otherwise N.
  1198. # Select ISA DMA controller support
  1199. config ISA_DMA
  1200. bool
  1201. select ISA_DMA_API
  1202. # Select ISA DMA interface
  1203. config ISA_DMA_API
  1204. bool
  1205. config PCI
  1206. bool "PCI support" if MIGHT_HAVE_PCI
  1207. help
  1208. Find out whether you have a PCI motherboard. PCI is the name of a
  1209. bus system, i.e. the way the CPU talks to the other stuff inside
  1210. your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
  1211. VESA. If you have PCI, say Y, otherwise N.
  1212. config PCI_DOMAINS
  1213. bool
  1214. depends on PCI
  1215. config PCI_NANOENGINE
  1216. bool "BSE nanoEngine PCI support"
  1217. depends on SA1100_NANOENGINE
  1218. help
  1219. Enable PCI on the BSE nanoEngine board.
  1220. config PCI_SYSCALL
  1221. def_bool PCI
  1222. # Select the host bridge type
  1223. config PCI_HOST_VIA82C505
  1224. bool
  1225. depends on PCI && ARCH_SHARK
  1226. default y
  1227. config PCI_HOST_ITE8152
  1228. bool
  1229. depends on PCI && MACH_ARMCORE
  1230. default y
  1231. select DMABOUNCE
  1232. source "drivers/pci/Kconfig"
  1233. source "drivers/pcmcia/Kconfig"
  1234. endmenu
  1235. menu "Kernel Features"
  1236. config HAVE_SMP
  1237. bool
  1238. help
  1239. This option should be selected by machines which have an SMP-
  1240. capable CPU.
  1241. The only effect of this option is to make the SMP-related
  1242. options available to the user for configuration.
  1243. config SMP
  1244. bool "Symmetric Multi-Processing"
  1245. depends on CPU_V6K || CPU_V7
  1246. depends on GENERIC_CLOCKEVENTS
  1247. depends on HAVE_SMP
  1248. depends on MMU
  1249. select USE_GENERIC_SMP_HELPERS
  1250. select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
  1251. help
  1252. This enables support for systems with more than one CPU. If you have
  1253. a system with only one CPU, like most personal computers, say N. If
  1254. you have a system with more than one CPU, say Y.
  1255. If you say N here, the kernel will run on single and multiprocessor
  1256. machines, but will use only one CPU of a multiprocessor machine. If
  1257. you say Y here, the kernel will run on many, but not all, single
  1258. processor machines. On a single processor machine, the kernel will
  1259. run faster if you say N here.
  1260. See also <file:Documentation/x86/i386/IO-APIC.txt>,
  1261. <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
  1262. <http://tldp.org/HOWTO/SMP-HOWTO.html>.
  1263. If you don't know what to do here, say N.
  1264. config SMP_ON_UP
  1265. bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
  1266. depends on EXPERIMENTAL
  1267. depends on SMP && !XIP_KERNEL
  1268. default y
  1269. help
  1270. SMP kernels contain instructions which fail on non-SMP processors.
  1271. Enabling this option allows the kernel to modify itself to make
  1272. these instructions safe. Disabling it allows about 1K of space
  1273. savings.
  1274. If you don't know what to do here, say Y.
  1275. config ARM_CPU_TOPOLOGY
  1276. bool "Support cpu topology definition"
  1277. depends on SMP && CPU_V7
  1278. default y
  1279. help
  1280. Support ARM cpu topology definition. The MPIDR register defines
  1281. affinity between processors which is then used to describe the cpu
  1282. topology of an ARM System.
  1283. config SCHED_MC
  1284. bool "Multi-core scheduler support"
  1285. depends on ARM_CPU_TOPOLOGY
  1286. help
  1287. Multi-core scheduler support improves the CPU scheduler's decision
  1288. making when dealing with multi-core CPU chips at a cost of slightly
  1289. increased overhead in some places. If unsure say N here.
  1290. config SCHED_SMT
  1291. bool "SMT scheduler support"
  1292. depends on ARM_CPU_TOPOLOGY
  1293. help
  1294. Improves the CPU scheduler's decision making when dealing with
  1295. MultiThreading at a cost of slightly increased overhead in some
  1296. places. If unsure say N here.
  1297. config HAVE_ARM_SCU
  1298. bool
  1299. help
  1300. This option enables support for the ARM system coherency unit
  1301. config ARM_ARCH_TIMER
  1302. bool "Architected timer support"
  1303. depends on CPU_V7
  1304. help
  1305. This option enables support for the ARM architected timer
  1306. config HAVE_ARM_TWD
  1307. bool
  1308. depends on SMP
  1309. help
  1310. This options enables support for the ARM timer and watchdog unit
  1311. choice
  1312. prompt "Memory split"
  1313. default VMSPLIT_3G
  1314. help
  1315. Select the desired split between kernel and user memory.
  1316. If you are not absolutely sure what you are doing, leave this
  1317. option alone!
  1318. config VMSPLIT_3G
  1319. bool "3G/1G user/kernel split"
  1320. config VMSPLIT_2G
  1321. bool "2G/2G user/kernel split"
  1322. config VMSPLIT_1G
  1323. bool "1G/3G user/kernel split"
  1324. endchoice
  1325. config PAGE_OFFSET
  1326. hex
  1327. default 0x40000000 if VMSPLIT_1G
  1328. default 0x80000000 if VMSPLIT_2G
  1329. default 0xC0000000
  1330. config NR_CPUS
  1331. int "Maximum number of CPUs (2-32)"
  1332. range 2 32
  1333. depends on SMP
  1334. default "4"
  1335. config HOTPLUG_CPU
  1336. bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
  1337. depends on SMP && HOTPLUG && EXPERIMENTAL
  1338. help
  1339. Say Y here to experiment with turning CPUs off and on. CPUs
  1340. can be controlled through /sys/devices/system/cpu.
  1341. config LOCAL_TIMERS
  1342. bool "Use local timer interrupts"
  1343. depends on SMP
  1344. default y
  1345. select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
  1346. help
  1347. Enable support for local timers on SMP platforms, rather then the
  1348. legacy IPI broadcast method. Local timers allows the system
  1349. accounting to be spread across the timer interval, preventing a
  1350. "thundering herd" at every timer tick.
  1351. config ARCH_NR_GPIO
  1352. int
  1353. default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
  1354. default 355 if ARCH_U8500
  1355. default 264 if MACH_H4700
  1356. default 0
  1357. help
  1358. Maximum number of GPIOs in the system.
  1359. If unsure, leave the default value.
  1360. source kernel/Kconfig.preempt
  1361. config HZ
  1362. int
  1363. default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
  1364. ARCH_S5PV210 || ARCH_EXYNOS4
  1365. default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
  1366. default AT91_TIMER_HZ if ARCH_AT91
  1367. default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
  1368. default 100
  1369. config THUMB2_KERNEL
  1370. bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
  1371. depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
  1372. select AEABI
  1373. select ARM_ASM_UNIFIED
  1374. select ARM_UNWIND
  1375. help
  1376. By enabling this option, the kernel will be compiled in
  1377. Thumb-2 mode. A compiler/assembler that understand the unified
  1378. ARM-Thumb syntax is needed.
  1379. If unsure, say N.
  1380. config THUMB2_AVOID_R_ARM_THM_JUMP11
  1381. bool "Work around buggy Thumb-2 short branch relocations in gas"
  1382. depends on THUMB2_KERNEL && MODULES
  1383. default y
  1384. help
  1385. Various binutils versions can resolve Thumb-2 branches to
  1386. locally-defined, preemptible global symbols as short-range "b.n"
  1387. branch instructions.
  1388. This is a problem, because there's no guarantee the final
  1389. destination of the symbol, or any candidate locations for a
  1390. trampoline, are within range of the branch. For this reason, the
  1391. kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
  1392. relocation in modules at all, and it makes little sense to add
  1393. support.
  1394. The symptom is that the kernel fails with an "unsupported
  1395. relocation" error when loading some modules.
  1396. Until fixed tools are available, passing
  1397. -fno-optimize-sibling-calls to gcc should prevent gcc generating
  1398. code which hits this problem, at the cost of a bit of extra runtime
  1399. stack usage in some cases.
  1400. The problem is described in more detail at:
  1401. https://bugs.launchpad.net/binutils-linaro/+bug/725126
  1402. Only Thumb-2 kernels are affected.
  1403. Unless you are sure your tools don't have this problem, say Y.
  1404. config ARM_ASM_UNIFIED
  1405. bool
  1406. config AEABI
  1407. bool "Use the ARM EABI to compile the kernel"
  1408. help
  1409. This option allows for the kernel to be compiled using the latest
  1410. ARM ABI (aka EABI). This is only useful if you are using a user
  1411. space environment that is also compiled with EABI.
  1412. Since there are major incompatibilities between the legacy ABI and
  1413. EABI, especially with regard to structure member alignment, this
  1414. option also changes the kernel syscall calling convention to
  1415. disambiguate both ABIs and allow for backward compatibility support
  1416. (selected with CONFIG_OABI_COMPAT).
  1417. To use this you need GCC version 4.0.0 or later.
  1418. config OABI_COMPAT
  1419. bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
  1420. depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
  1421. default y
  1422. help
  1423. This option preserves the old syscall interface along with the
  1424. new (ARM EABI) one. It also provides a compatibility layer to
  1425. intercept syscalls that have structure arguments which layout
  1426. in memory differs between the legacy ABI and the new ARM EABI
  1427. (only for non "thumb" binaries). This option adds a tiny
  1428. overhead to all syscalls and produces a slightly larger kernel.
  1429. If you know you'll be using only pure EABI user space then you
  1430. can say N here. If this option is not selected and you attempt
  1431. to execute a legacy ABI binary then the result will be
  1432. UNPREDICTABLE (in fact it can be predicted that it won't work
  1433. at all). If in doubt say Y.
  1434. config ARCH_HAS_HOLES_MEMORYMODEL
  1435. bool
  1436. config ARCH_SPARSEMEM_ENABLE
  1437. bool
  1438. config ARCH_SPARSEMEM_DEFAULT
  1439. def_bool ARCH_SPARSEMEM_ENABLE
  1440. config ARCH_SELECT_MEMORY_MODEL
  1441. def_bool ARCH_SPARSEMEM_ENABLE
  1442. config HAVE_ARCH_PFN_VALID
  1443. def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
  1444. config HIGHMEM
  1445. bool "High Memory Support"
  1446. depends on MMU
  1447. help
  1448. The address space of ARM processors is only 4 Gigabytes large
  1449. and it has to accommodate user address space, kernel address
  1450. space as well as some memory mapped IO. That means that, if you
  1451. have a large amount of physical memory and/or IO, not all of the
  1452. memory can be "permanently mapped" by the kernel. The physical
  1453. memory that is not permanently mapped is called "high memory".
  1454. Depending on the selected kernel/user memory split, minimum
  1455. vmalloc space and actual amount of RAM, you may not need this
  1456. option which should result in a slightly faster kernel.
  1457. If unsure, say n.
  1458. config HIGHPTE
  1459. bool "Allocate 2nd-level pagetables from highmem"
  1460. depends on HIGHMEM
  1461. config HW_PERF_EVENTS
  1462. bool "Enable hardware performance counter support for perf events"
  1463. depends on PERF_EVENTS && CPU_HAS_PMU
  1464. default y
  1465. help
  1466. Enable hardware performance counter support for perf events. If
  1467. disabled, perf events will use software events only.
  1468. source "mm/Kconfig"
  1469. config FORCE_MAX_ZONEORDER
  1470. int "Maximum zone order" if ARCH_SHMOBILE
  1471. range 11 64 if ARCH_SHMOBILE
  1472. default "9" if SA1111
  1473. default "11"
  1474. help
  1475. The kernel memory allocator divides physically contiguous memory
  1476. blocks into "zones", where each zone is a power of two number of
  1477. pages. This option selects the largest power of two that the kernel
  1478. keeps in the memory allocator. If you need to allocate very large
  1479. blocks of physically contiguous memory, then you may need to
  1480. increase this value.
  1481. This config option is actually maximum order plus one. For example,
  1482. a value of 11 means that the largest free memory block is 2^10 pages.
  1483. config LEDS
  1484. bool "Timer and CPU usage LEDs"
  1485. depends on ARCH_CDB89712 || ARCH_EBSA110 || \
  1486. ARCH_EBSA285 || ARCH_INTEGRATOR || \
  1487. ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
  1488. ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
  1489. ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
  1490. ARCH_AT91 || ARCH_DAVINCI || \
  1491. ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
  1492. help
  1493. If you say Y here, the LEDs on your machine will be used
  1494. to provide useful information about your current system status.
  1495. If you are compiling a kernel for a NetWinder or EBSA-285, you will
  1496. be able to select which LEDs are active using the options below. If
  1497. you are compiling a kernel for the EBSA-110 or the LART however, the
  1498. red LED will simply flash regularly to indicate that the system is
  1499. still functional. It is safe to say Y here if you have a CATS
  1500. system, but the driver will do nothing.
  1501. config LEDS_TIMER
  1502. bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
  1503. OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
  1504. || MACH_OMAP_PERSEUS2
  1505. depends on LEDS
  1506. depends on !GENERIC_CLOCKEVENTS
  1507. default y if ARCH_EBSA110
  1508. help
  1509. If you say Y here, one of the system LEDs (the green one on the
  1510. NetWinder, the amber one on the EBSA285, or the red one on the LART)
  1511. will flash regularly to indicate that the system is still
  1512. operational. This is mainly useful to kernel hackers who are
  1513. debugging unstable kernels.
  1514. The LART uses the same LED for both Timer LED and CPU usage LED
  1515. functions. You may choose to use both, but the Timer LED function
  1516. will overrule the CPU usage LED.
  1517. config LEDS_CPU
  1518. bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
  1519. !ARCH_OMAP) \
  1520. || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
  1521. || MACH_OMAP_PERSEUS2
  1522. depends on LEDS
  1523. help
  1524. If you say Y here, the red LED will be used to give a good real
  1525. time indication of CPU usage, by lighting whenever the idle task
  1526. is not currently executing.
  1527. The LART uses the same LED for both Timer LED and CPU usage LED
  1528. functions. You may choose to use both, but the Timer LED function
  1529. will overrule the CPU usage LED.
  1530. config ALIGNMENT_TRAP
  1531. bool
  1532. depends on CPU_CP15_MMU
  1533. default y if !ARCH_EBSA110
  1534. select HAVE_PROC_CPU if PROC_FS
  1535. help
  1536. ARM processors cannot fetch/store information which is not
  1537. naturally aligned on the bus, i.e., a 4 byte fetch must start at an
  1538. address divisible by 4. On 32-bit ARM processors, these non-aligned
  1539. fetch/store instructions will be emulated in software if you say
  1540. here, which has a severe performance impact. This is necessary for
  1541. correct operation of some network protocols. With an IP-only
  1542. configuration it is safe to say N, otherwise say Y.
  1543. config UACCESS_WITH_MEMCPY
  1544. bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
  1545. depends on MMU && EXPERIMENTAL
  1546. default y if CPU_FEROCEON
  1547. help
  1548. Implement faster copy_to_user and clear_user methods for CPU
  1549. cores where a 8-word STM instruction give significantly higher
  1550. memory write throughput than a sequence of individual 32bit stores.
  1551. A possible side effect is a slight increase in scheduling latency
  1552. between threads sharing the same address space if they invoke
  1553. such copy operations with large buffers.
  1554. However, if the CPU data cache is using a write-allocate mode,
  1555. this option is unlikely to provide any performance gain.
  1556. config SECCOMP
  1557. bool
  1558. prompt "Enable seccomp to safely compute untrusted bytecode"
  1559. ---help---
  1560. This kernel feature is useful for number crunching applications
  1561. that may need to compute untrusted bytecode during their
  1562. execution. By using pipes or other transports made available to
  1563. the process as file descriptors supporting the read/write
  1564. syscalls, it's possible to isolate those applications in
  1565. their own address space using seccomp. Once seccomp is
  1566. enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
  1567. and the task is only allowed to execute a few safe syscalls
  1568. defined by each seccomp mode.
  1569. config CC_STACKPROTECTOR
  1570. bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
  1571. depends on EXPERIMENTAL
  1572. help
  1573. This option turns on the -fstack-protector GCC feature. This
  1574. feature puts, at the beginning of functions, a canary value on
  1575. the stack just before the return address, and validates
  1576. the value just before actually returning. Stack based buffer
  1577. overflows (that need to overwrite this return address) now also
  1578. overwrite the canary, which gets detected and the attack is then
  1579. neutralized via a kernel panic.
  1580. This feature requires gcc version 4.2 or above.
  1581. config DEPRECATED_PARAM_STRUCT
  1582. bool "Provide old way to pass kernel parameters"
  1583. help
  1584. This was deprecated in 2001 and announced to live on for 5 years.
  1585. Some old boot loaders still use this way.
  1586. endmenu
  1587. menu "Boot options"
  1588. config USE_OF
  1589. bool "Flattened Device Tree support"
  1590. select OF
  1591. select OF_EARLY_FLATTREE
  1592. select IRQ_DOMAIN
  1593. help
  1594. Include support for flattened device tree machine descriptions.
  1595. # Compressed boot loader in ROM. Yes, we really want to ask about
  1596. # TEXT and BSS so we preserve their values in the config files.
  1597. config ZBOOT_ROM_TEXT
  1598. hex "Compressed ROM boot loader base address"
  1599. default "0"
  1600. help
  1601. The physical address at which the ROM-able zImage is to be
  1602. placed in the target. Platforms which normally make use of
  1603. ROM-able zImage formats normally set this to a suitable
  1604. value in their defconfig file.
  1605. If ZBOOT_ROM is not enabled, this has no effect.
  1606. config ZBOOT_ROM_BSS
  1607. hex "Compressed ROM boot loader BSS address"
  1608. default "0"
  1609. help
  1610. The base address of an area of read/write memory in the target
  1611. for the ROM-able zImage which must be available while the
  1612. decompressor is running. It must be large enough to hold the
  1613. entire decompressed kernel plus an additional 128 KiB.
  1614. Platforms which normally make use of ROM-able zImage formats
  1615. normally set this to a suitable value in their defconfig file.
  1616. If ZBOOT_ROM is not enabled, this has no effect.
  1617. config ZBOOT_ROM
  1618. bool "Compressed boot loader in ROM/flash"
  1619. depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
  1620. help
  1621. Say Y here if you intend to execute your compressed kernel image
  1622. (zImage) directly from ROM or flash. If unsure, say N.
  1623. choice
  1624. prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
  1625. depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
  1626. default ZBOOT_ROM_NONE
  1627. help
  1628. Include experimental SD/MMC loading code in the ROM-able zImage.
  1629. With this enabled it is possible to write the ROM-able zImage
  1630. kernel image to an MMC or SD card and boot the kernel straight
  1631. from the reset vector. At reset the processor Mask ROM will load
  1632. the first part of the ROM-able zImage which in turn loads the
  1633. rest the kernel image to RAM.
  1634. config ZBOOT_ROM_NONE
  1635. bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
  1636. help
  1637. Do not load image from SD or MMC
  1638. config ZBOOT_ROM_MMCIF
  1639. bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
  1640. help
  1641. Load image from MMCIF hardware block.
  1642. config ZBOOT_ROM_SH_MOBILE_SDHI
  1643. bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
  1644. help
  1645. Load image from SDHI hardware block
  1646. endchoice
  1647. config ARM_APPENDED_DTB
  1648. bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
  1649. depends on OF && !ZBOOT_ROM && EXPERIMENTAL
  1650. help
  1651. With this option, the boot code will look for a device tree binary
  1652. (DTB) appended to zImage
  1653. (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
  1654. This is meant as a backward compatibility convenience for those
  1655. systems with a bootloader that can't be upgraded to accommodate
  1656. the documented boot protocol using a device tree.
  1657. Beware that there is very little in terms of protection against
  1658. this option being confused by leftover garbage in memory that might
  1659. look like a DTB header after a reboot if no actual DTB is appended
  1660. to zImage. Do not leave this option active in a production kernel
  1661. if you don't intend to always append a DTB. Proper passing of the
  1662. location into r2 of a bootloader provided DTB is always preferable
  1663. to this option.
  1664. config ARM_ATAG_DTB_COMPAT
  1665. bool "Supplement the appended DTB with traditional ATAG information"
  1666. depends on ARM_APPENDED_DTB
  1667. help
  1668. Some old bootloaders can't be updated to a DTB capable one, yet
  1669. they provide ATAGs with memory configuration, the ramdisk address,
  1670. the kernel cmdline string, etc. Such information is dynamically
  1671. provided by the bootloader and can't always be stored in a static
  1672. DTB. To allow a device tree enabled kernel to be used with such
  1673. bootloaders, this option allows zImage to extract the information
  1674. from the ATAG list and store it at run time into the appended DTB.
  1675. config CMDLINE
  1676. string "Default kernel command string"
  1677. default ""
  1678. help
  1679. On some architectures (EBSA110 and CATS), there is currently no way
  1680. for the boot loader to pass arguments to the kernel. For these
  1681. architectures, you should supply some command-line options at build
  1682. time by entering them here. As a minimum, you should specify the
  1683. memory size and the root device (e.g., mem=64M root=/dev/nfs).
  1684. choice
  1685. prompt "Kernel command line type" if CMDLINE != ""
  1686. default CMDLINE_FROM_BOOTLOADER
  1687. config CMDLINE_FROM_BOOTLOADER
  1688. bool "Use bootloader kernel arguments if available"
  1689. help
  1690. Uses the command-line options passed by the boot loader. If
  1691. the boot loader doesn't provide any, the default kernel command
  1692. string provided in CMDLINE will be used.
  1693. config CMDLINE_EXTEND
  1694. bool "Extend bootloader kernel arguments"
  1695. help
  1696. The command-line arguments provided by the boot loader will be
  1697. appended to the default kernel command string.
  1698. config CMDLINE_FORCE
  1699. bool "Always use the default kernel command string"
  1700. help
  1701. Always use the default kernel command string, even if the boot
  1702. loader passes other arguments to the kernel.
  1703. This is useful if you cannot or don't want to change the
  1704. command-line options your boot loader passes to the kernel.
  1705. endchoice
  1706. config XIP_KERNEL
  1707. bool "Kernel Execute-In-Place from ROM"
  1708. depends on !ZBOOT_ROM && !ARM_LPAE
  1709. help
  1710. Execute-In-Place allows the kernel to run from non-volatile storage
  1711. directly addressable by the CPU, such as NOR flash. This saves RAM
  1712. space since the text section of the kernel is not loaded from flash
  1713. to RAM. Read-write sections, such as the data section and stack,
  1714. are still copied to RAM. The XIP kernel is not compressed since
  1715. it has to run directly from flash, so it will take more space to
  1716. store it. The flash address used to link the kernel object files,
  1717. and for storing it, is configuration dependent. Therefore, if you
  1718. say Y here, you must know the proper physical address where to
  1719. store the kernel image depending on your own flash memory usage.
  1720. Also note that the make target becomes "make xipImage" rather than
  1721. "make zImage" or "make Image". The final kernel binary to put in
  1722. ROM memory will be arch/arm/boot/xipImage.
  1723. If unsure, say N.
  1724. config XIP_PHYS_ADDR
  1725. hex "XIP Kernel Physical Location"
  1726. depends on XIP_KERNEL
  1727. default "0x00080000"
  1728. help
  1729. This is the physical address in your flash memory the kernel will
  1730. be linked for and stored to. This address is dependent on your
  1731. own flash usage.
  1732. config KEXEC
  1733. bool "Kexec system call (EXPERIMENTAL)"
  1734. depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
  1735. help
  1736. kexec is a system call that implements the ability to shutdown your
  1737. current kernel, and to start another kernel. It is like a reboot
  1738. but it is independent of the system firmware. And like a reboot
  1739. you can start any kernel with it, not just Linux.
  1740. It is an ongoing process to be certain the hardware in a machine
  1741. is properly shutdown, so do not be surprised if this code does not
  1742. initially work for you. It may help to enable device hotplugging
  1743. support.
  1744. config ATAGS_PROC
  1745. bool "Export atags in procfs"
  1746. depends on KEXEC
  1747. default y
  1748. help
  1749. Should the atags used to boot the kernel be exported in an "atags"
  1750. file in procfs. Useful with kexec.
  1751. config CRASH_DUMP
  1752. bool "Build kdump crash kernel (EXPERIMENTAL)"
  1753. depends on EXPERIMENTAL
  1754. help
  1755. Generate crash dump after being started by kexec. This should
  1756. be normally only set in special crash dump kernels which are
  1757. loaded in the main kernel with kexec-tools into a specially
  1758. reserved region and then later executed after a crash by
  1759. kdump/kexec. The crash dump kernel must be compiled to a
  1760. memory address not used by the main kernel
  1761. For more details see Documentation/kdump/kdump.txt
  1762. config AUTO_ZRELADDR
  1763. bool "Auto calculation of the decompressed kernel image address"
  1764. depends on !ZBOOT_ROM && !ARCH_U300
  1765. help
  1766. ZRELADDR is the physical address where the decompressed kernel
  1767. image will be placed. If AUTO_ZRELADDR is selected, the address
  1768. will be determined at run-time by masking the current IP with
  1769. 0xf8000000. This assumes the zImage being placed in the first 128MB
  1770. from start of memory.
  1771. endmenu
  1772. menu "CPU Power Management"
  1773. if ARCH_HAS_CPUFREQ
  1774. source "drivers/cpufreq/Kconfig"
  1775. config CPU_FREQ_IMX
  1776. tristate "CPUfreq driver for i.MX CPUs"
  1777. depends on ARCH_MXC && CPU_FREQ
  1778. help
  1779. This enables the CPUfreq driver for i.MX CPUs.
  1780. config CPU_FREQ_SA1100
  1781. bool
  1782. config CPU_FREQ_SA1110
  1783. bool
  1784. config CPU_FREQ_INTEGRATOR
  1785. tristate "CPUfreq driver for ARM Integrator CPUs"
  1786. depends on ARCH_INTEGRATOR && CPU_FREQ
  1787. default y
  1788. help
  1789. This enables the CPUfreq driver for ARM Integrator CPUs.
  1790. For details, take a look at <file:Documentation/cpu-freq>.
  1791. If in doubt, say Y.
  1792. config CPU_FREQ_PXA
  1793. bool
  1794. depends on CPU_FREQ && ARCH_PXA && PXA25x
  1795. default y
  1796. select CPU_FREQ_TABLE
  1797. select CPU_FREQ_DEFAULT_GOV_USERSPACE
  1798. config CPU_FREQ_S3C
  1799. bool
  1800. help
  1801. Internal configuration node for common cpufreq on Samsung SoC
  1802. config CPU_FREQ_S3C24XX
  1803. bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
  1804. depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
  1805. select CPU_FREQ_S3C
  1806. help
  1807. This enables the CPUfreq driver for the Samsung S3C24XX family
  1808. of CPUs.
  1809. For details, take a look at <file:Documentation/cpu-freq>.
  1810. If in doubt, say N.
  1811. config CPU_FREQ_S3C24XX_PLL
  1812. bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
  1813. depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
  1814. help
  1815. Compile in support for changing the PLL frequency from the
  1816. S3C24XX series CPUfreq driver. The PLL takes time to settle
  1817. after a frequency change, so by default it is not enabled.
  1818. This also means that the PLL tables for the selected CPU(s) will
  1819. be built which may increase the size of the kernel image.
  1820. config CPU_FREQ_S3C24XX_DEBUG
  1821. bool "Debug CPUfreq Samsung driver core"
  1822. depends on CPU_FREQ_S3C24XX
  1823. help
  1824. Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
  1825. config CPU_FREQ_S3C24XX_IODEBUG
  1826. bool "Debug CPUfreq Samsung driver IO timing"
  1827. depends on CPU_FREQ_S3C24XX
  1828. help
  1829. Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
  1830. config CPU_FREQ_S3C24XX_DEBUGFS
  1831. bool "Export debugfs for CPUFreq"
  1832. depends on CPU_FREQ_S3C24XX && DEBUG_FS
  1833. help
  1834. Export status information via debugfs.
  1835. endif
  1836. source "drivers/cpuidle/Kconfig"
  1837. endmenu
  1838. menu "Floating point emulation"
  1839. comment "At least one emulation must be selected"
  1840. config FPE_NWFPE
  1841. bool "NWFPE math emulation"
  1842. depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
  1843. ---help---
  1844. Say Y to include the NWFPE floating point emulator in the kernel.
  1845. This is necessary to run most binaries. Linux does not currently
  1846. support floating point hardware so you need to say Y here even if
  1847. your machine has an FPA or floating point co-processor podule.
  1848. You may say N here if you are going to load the Acorn FPEmulator
  1849. early in the bootup.
  1850. config FPE_NWFPE_XP
  1851. bool "Support extended precision"
  1852. depends on FPE_NWFPE
  1853. help
  1854. Say Y to include 80-bit support in the kernel floating-point
  1855. emulator. Otherwise, only 32 and 64-bit support is compiled in.
  1856. Note that gcc does not generate 80-bit operations by default,
  1857. so in most cases this option only enlarges the size of the
  1858. floating point emulator without any good reason.
  1859. You almost surely want to say N here.
  1860. config FPE_FASTFPE
  1861. bool "FastFPE math emulation (EXPERIMENTAL)"
  1862. depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
  1863. ---help---
  1864. Say Y here to include the FAST floating point emulator in the kernel.
  1865. This is an experimental much faster emulator which now also has full
  1866. precision for the mantissa. It does not support any exceptions.
  1867. It is very simple, and approximately 3-6 times faster than NWFPE.
  1868. It should be sufficient for most programs. It may be not suitable
  1869. for scientific calculations, but you have to check this for yourself.
  1870. If you do not feel you need a faster FP emulation you should better
  1871. choose NWFPE.
  1872. config VFP
  1873. bool "VFP-format floating point maths"
  1874. depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
  1875. help
  1876. Say Y to include VFP support code in the kernel. This is needed
  1877. if your hardware includes a VFP unit.
  1878. Please see <file:Documentation/arm/VFP/release-notes.txt> for
  1879. release notes and additional status information.
  1880. Say N if your target does not have VFP hardware.
  1881. config VFPv3
  1882. bool
  1883. depends on VFP
  1884. default y if CPU_V7
  1885. config NEON
  1886. bool "Advanced SIMD (NEON) Extension support"
  1887. depends on VFPv3 && CPU_V7
  1888. help
  1889. Say Y to include support code for NEON, the ARMv7 Advanced SIMD
  1890. Extension.
  1891. endmenu
  1892. menu "Userspace binary formats"
  1893. source "fs/Kconfig.binfmt"
  1894. config ARTHUR
  1895. tristate "RISC OS personality"
  1896. depends on !AEABI
  1897. help
  1898. Say Y here to include the kernel code necessary if you want to run
  1899. Acorn RISC OS/Arthur binaries under Linux. This code is still very
  1900. experimental; if this sounds frightening, say N and sleep in peace.
  1901. You can also say M here to compile this support as a module (which
  1902. will be called arthur).
  1903. endmenu
  1904. menu "Power management options"
  1905. source "kernel/power/Kconfig"
  1906. config ARCH_SUSPEND_POSSIBLE
  1907. depends on !ARCH_S5PC100 && !ARCH_TEGRA
  1908. depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
  1909. CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
  1910. def_bool y
  1911. config ARM_CPU_SUSPEND
  1912. def_bool PM_SLEEP
  1913. endmenu
  1914. source "net/Kconfig"
  1915. source "drivers/Kconfig"
  1916. source "fs/Kconfig"
  1917. source "arch/arm/Kconfig.debug"
  1918. source "security/Kconfig"
  1919. source "crypto/Kconfig"
  1920. source "lib/Kconfig"