pci.c 2.6 KB

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  1. /*
  2. * FSL SoC setup code
  3. *
  4. * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/stddef.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/errno.h>
  15. #include <linux/pci.h>
  16. #include <linux/delay.h>
  17. #include <linux/irq.h>
  18. #include <linux/module.h>
  19. #include <asm/system.h>
  20. #include <asm/atomic.h>
  21. #include <asm/io.h>
  22. #include <asm/pci-bridge.h>
  23. #include <asm/prom.h>
  24. #include <sysdev/fsl_soc.h>
  25. #undef DEBUG
  26. #ifdef DEBUG
  27. #define DBG(x...) printk(x)
  28. #else
  29. #define DBG(x...)
  30. #endif
  31. int mpc83xx_exclude_device(struct pci_controller *hose, u_char bus, u_char devfn)
  32. {
  33. if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
  34. return PCIBIOS_DEVICE_NOT_FOUND;
  35. return PCIBIOS_SUCCESSFUL;
  36. }
  37. int __init mpc83xx_add_bridge(struct device_node *dev)
  38. {
  39. int len;
  40. struct pci_controller *hose;
  41. struct resource rsrc;
  42. const int *bus_range;
  43. int primary = 1, has_address = 0;
  44. phys_addr_t immr = get_immrbase();
  45. DBG("Adding PCI host bridge %s\n", dev->full_name);
  46. /* Fetch host bridge registers address */
  47. has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
  48. /* Get bus range if any */
  49. bus_range = of_get_property(dev, "bus-range", &len);
  50. if (bus_range == NULL || len < 2 * sizeof(int)) {
  51. printk(KERN_WARNING "Can't get bus-range for %s, assume"
  52. " bus 0\n", dev->full_name);
  53. }
  54. pci_assign_all_buses = 1;
  55. hose = pcibios_alloc_controller();
  56. if (!hose)
  57. return -ENOMEM;
  58. hose->arch_data = dev;
  59. hose->first_busno = bus_range ? bus_range[0] : 0;
  60. hose->last_busno = bus_range ? bus_range[1] : 0xff;
  61. /* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
  62. * the other at 0x8600, we consider the 0x8500 the primary controller
  63. */
  64. /* PCI 1 */
  65. if ((rsrc.start & 0xfffff) == 0x8500) {
  66. setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
  67. }
  68. /* PCI 2 */
  69. if ((rsrc.start & 0xfffff) == 0x8600) {
  70. setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
  71. primary = 0;
  72. }
  73. printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
  74. "Firmware bus number: %d->%d\n",
  75. (unsigned long long)rsrc.start, hose->first_busno,
  76. hose->last_busno);
  77. DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
  78. hose, hose->cfg_addr, hose->cfg_data);
  79. /* Interpret the "ranges" property */
  80. /* This also maps the I/O region and sets isa_io/mem_base */
  81. pci_process_bridge_OF_ranges(hose, dev, primary);
  82. return 0;
  83. }