mach-qt2410.c 9.0 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
  2. *
  3. * Copyright (C) 2006 by OpenMoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/timer.h>
  28. #include <linux/init.h>
  29. #include <linux/sysdev.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/serial_core.h>
  32. #include <linux/spi/spi.h>
  33. #include <linux/spi/spi_bitbang.h>
  34. #include <linux/mtd/mtd.h>
  35. #include <linux/mtd/nand.h>
  36. #include <linux/mtd/nand_ecc.h>
  37. #include <linux/mtd/partitions.h>
  38. #include <asm/mach/arch.h>
  39. #include <asm/mach/map.h>
  40. #include <asm/mach/irq.h>
  41. #include <asm/hardware.h>
  42. #include <asm/io.h>
  43. #include <asm/irq.h>
  44. #include <asm/mach-types.h>
  45. #include <asm/arch/regs-gpio.h>
  46. #include <asm/arch/leds-gpio.h>
  47. #include <asm/plat-s3c/regs-serial.h>
  48. #include <asm/arch/fb.h>
  49. #include <asm/plat-s3c/nand.h>
  50. #include <asm/plat-s3c24xx/udc.h>
  51. #include <asm/arch/spi.h>
  52. #include <asm/arch/spi-gpio.h>
  53. #include <asm/plat-s3c24xx/common-smdk.h>
  54. #include <asm/plat-s3c24xx/devs.h>
  55. #include <asm/plat-s3c24xx/cpu.h>
  56. #include <asm/plat-s3c24xx/pm.h>
  57. static struct map_desc qt2410_iodesc[] __initdata = {
  58. { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  59. };
  60. #define UCON S3C2410_UCON_DEFAULT
  61. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  62. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  63. static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  64. [0] = {
  65. .hwport = 0,
  66. .flags = 0,
  67. .ucon = UCON,
  68. .ulcon = ULCON,
  69. .ufcon = UFCON,
  70. },
  71. [1] = {
  72. .hwport = 1,
  73. .flags = 0,
  74. .ucon = UCON,
  75. .ulcon = ULCON,
  76. .ufcon = UFCON,
  77. },
  78. [2] = {
  79. .hwport = 2,
  80. .flags = 0,
  81. .ucon = UCON,
  82. .ulcon = ULCON,
  83. .ufcon = UFCON,
  84. }
  85. };
  86. /* LCD driver info */
  87. static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  88. {
  89. /* Configuration for 640x480 SHARP LQ080V3DG01 */
  90. .regs = {
  91. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  92. S3C2410_LCDCON1_TFT |
  93. S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
  94. .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */
  95. S3C2410_LCDCON2_LINEVAL(479) |
  96. S3C2410_LCDCON2_VFPD(10) | /* 11 */
  97. S3C2410_LCDCON2_VSPW(14), /* 15 */
  98. .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */
  99. S3C2410_LCDCON3_HOZVAL(639) | /* 640 */
  100. S3C2410_LCDCON3_HFPD(115), /* 116 */
  101. .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
  102. S3C2410_LCDCON4_HSPW(95), /* 96 */
  103. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  104. S3C2410_LCDCON5_INVVLINE |
  105. S3C2410_LCDCON5_INVVFRAME |
  106. S3C2410_LCDCON5_PWREN |
  107. S3C2410_LCDCON5_HWSWP,
  108. },
  109. .width = 640,
  110. .height = 480,
  111. .xres = 640,
  112. .yres = 480,
  113. .bpp = 16,
  114. },
  115. {
  116. /* Configuration for 480x640 toppoly TD028TTEC1 */
  117. .regs = {
  118. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  119. S3C2410_LCDCON1_TFT |
  120. S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
  121. .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */
  122. S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
  123. S3C2410_LCDCON2_VFPD(3) | /* 4 */
  124. S3C2410_LCDCON2_VSPW(1), /* 2 */
  125. .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */
  126. S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
  127. S3C2410_LCDCON3_HFPD(23), /* 24 */
  128. .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
  129. S3C2410_LCDCON4_HSPW(7), /* 8 */
  130. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  131. S3C2410_LCDCON5_INVVLINE |
  132. S3C2410_LCDCON5_INVVFRAME |
  133. S3C2410_LCDCON5_PWREN |
  134. S3C2410_LCDCON5_HWSWP,
  135. },
  136. .width = 480,
  137. .height = 640,
  138. .xres = 480,
  139. .yres = 640,
  140. .bpp = 16,
  141. },
  142. {
  143. /* Config for 240x320 LCD */
  144. .regs = {
  145. .lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
  146. S3C2410_LCDCON1_TFT |
  147. S3C2410_LCDCON1_CLKVAL(0x04),
  148. .lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
  149. S3C2410_LCDCON2_LINEVAL(319) |
  150. S3C2410_LCDCON2_VFPD(6) |
  151. S3C2410_LCDCON2_VSPW(3),
  152. .lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
  153. S3C2410_LCDCON3_HOZVAL(239) |
  154. S3C2410_LCDCON3_HFPD(7),
  155. .lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
  156. S3C2410_LCDCON4_HSPW(3),
  157. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  158. S3C2410_LCDCON5_INVVLINE |
  159. S3C2410_LCDCON5_INVVFRAME |
  160. S3C2410_LCDCON5_PWREN |
  161. S3C2410_LCDCON5_HWSWP,
  162. },
  163. .width = 240,
  164. .height = 320,
  165. .xres = 240,
  166. .yres = 320,
  167. .bpp = 16,
  168. },
  169. };
  170. static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
  171. .displays = qt2410_lcd_cfg,
  172. .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
  173. .default_display = 0,
  174. .lpcsel = ((0xCE6) & ~7) | 1<<4,
  175. };
  176. /* CS8900 */
  177. static struct resource qt2410_cs89x0_resources[] = {
  178. [0] = {
  179. .start = 0x19000000,
  180. .end = 0x19000000 + 16,
  181. .flags = IORESOURCE_MEM,
  182. },
  183. [1] = {
  184. .start = IRQ_EINT9,
  185. .end = IRQ_EINT9,
  186. .flags = IORESOURCE_IRQ,
  187. },
  188. };
  189. static struct platform_device qt2410_cs89x0 = {
  190. .name = "cirrus-cs89x0",
  191. .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
  192. .resource = qt2410_cs89x0_resources,
  193. };
  194. /* LED */
  195. static struct s3c24xx_led_platdata qt2410_pdata_led = {
  196. .gpio = S3C2410_GPB0,
  197. .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
  198. .name = "led",
  199. .def_trigger = "timer",
  200. };
  201. static struct platform_device qt2410_led = {
  202. .name = "s3c24xx_led",
  203. .id = 0,
  204. .dev = {
  205. .platform_data = &qt2410_pdata_led,
  206. },
  207. };
  208. /* SPI */
  209. static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
  210. {
  211. switch (cs) {
  212. case BITBANG_CS_ACTIVE:
  213. s3c2410_gpio_setpin(S3C2410_GPB5, 0);
  214. break;
  215. case BITBANG_CS_INACTIVE:
  216. s3c2410_gpio_setpin(S3C2410_GPB5, 1);
  217. break;
  218. }
  219. }
  220. static struct s3c2410_spigpio_info spi_gpio_cfg = {
  221. .pin_clk = S3C2410_GPG7,
  222. .pin_mosi = S3C2410_GPG6,
  223. .pin_miso = S3C2410_GPG5,
  224. .chip_select = &spi_gpio_cs,
  225. };
  226. static struct platform_device qt2410_spi = {
  227. .name = "s3c24xx-spi-gpio",
  228. .id = 1,
  229. .dev = {
  230. .platform_data = &spi_gpio_cfg,
  231. },
  232. };
  233. /* Board devices */
  234. static struct platform_device *qt2410_devices[] __initdata = {
  235. &s3c_device_usb,
  236. &s3c_device_lcd,
  237. &s3c_device_wdt,
  238. &s3c_device_i2c,
  239. &s3c_device_iis,
  240. &s3c_device_sdi,
  241. &s3c_device_usbgadget,
  242. &qt2410_spi,
  243. &qt2410_cs89x0,
  244. &qt2410_led,
  245. };
  246. static struct mtd_partition qt2410_nand_part[] = {
  247. [0] = {
  248. .name = "U-Boot",
  249. .size = 0x30000,
  250. .offset = 0,
  251. },
  252. [1] = {
  253. .name = "U-Boot environment",
  254. .offset = 0x30000,
  255. .size = 0x4000,
  256. },
  257. [2] = {
  258. .name = "kernel",
  259. .offset = 0x34000,
  260. .size = SZ_2M,
  261. },
  262. [3] = {
  263. .name = "initrd",
  264. .offset = 0x234000,
  265. .size = SZ_4M,
  266. },
  267. [4] = {
  268. .name = "jffs2",
  269. .offset = 0x634000,
  270. .size = 0x39cc000,
  271. },
  272. };
  273. static struct s3c2410_nand_set qt2410_nand_sets[] = {
  274. [0] = {
  275. .name = "NAND",
  276. .nr_chips = 1,
  277. .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
  278. .partitions = qt2410_nand_part,
  279. },
  280. };
  281. /* choose a set of timings which should suit most 512Mbit
  282. * chips and beyond.
  283. */
  284. static struct s3c2410_platform_nand qt2410_nand_info = {
  285. .tacls = 20,
  286. .twrph0 = 60,
  287. .twrph1 = 20,
  288. .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
  289. .sets = qt2410_nand_sets,
  290. };
  291. /* UDC */
  292. static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
  293. };
  294. static char tft_type = 's';
  295. static int __init qt2410_tft_setup(char *str)
  296. {
  297. tft_type = str[0];
  298. return 1;
  299. }
  300. __setup("tft=", qt2410_tft_setup);
  301. static void __init qt2410_map_io(void)
  302. {
  303. s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
  304. s3c24xx_init_clocks(12*1000*1000);
  305. s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
  306. }
  307. static void __init qt2410_machine_init(void)
  308. {
  309. s3c_device_nand.dev.platform_data = &qt2410_nand_info;
  310. switch (tft_type) {
  311. case 'p': /* production */
  312. qt2410_fb_info.default_display = 1;
  313. break;
  314. case 'b': /* big */
  315. qt2410_fb_info.default_display = 0;
  316. break;
  317. case 's': /* small */
  318. default:
  319. qt2410_fb_info.default_display = 2;
  320. break;
  321. }
  322. s3c24xx_fb_set_platdata(&qt2410_fb_info);
  323. s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
  324. s3c2410_gpio_setpin(S3C2410_GPB0, 1);
  325. s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
  326. s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
  327. platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
  328. s3c2410_pm_init();
  329. }
  330. MACHINE_START(QT2410, "QT2410")
  331. .phys_io = S3C2410_PA_UART,
  332. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  333. .boot_params = S3C2410_SDRAM_PA + 0x100,
  334. .map_io = qt2410_map_io,
  335. .init_irq = s3c24xx_init_irq,
  336. .init_machine = qt2410_machine_init,
  337. .timer = &s3c24xx_timer,
  338. MACHINE_END