rv515.c 38 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include "rv515d.h"
  32. #include "radeon.h"
  33. #include "radeon_asic.h"
  34. #include "atom.h"
  35. #include "rv515_reg_safe.h"
  36. /* This files gather functions specifics to: rv515 */
  37. static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  38. static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  39. static void rv515_gpu_init(struct radeon_device *rdev);
  40. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  41. static const u32 crtc_offsets[2] =
  42. {
  43. 0,
  44. AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  45. };
  46. void rv515_debugfs(struct radeon_device *rdev)
  47. {
  48. if (r100_debugfs_rbbm_init(rdev)) {
  49. DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  50. }
  51. if (rv515_debugfs_pipes_info_init(rdev)) {
  52. DRM_ERROR("Failed to register debugfs file for pipes !\n");
  53. }
  54. if (rv515_debugfs_ga_info_init(rdev)) {
  55. DRM_ERROR("Failed to register debugfs file for pipes !\n");
  56. }
  57. }
  58. void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
  59. {
  60. int r;
  61. r = radeon_ring_lock(rdev, ring, 64);
  62. if (r) {
  63. return;
  64. }
  65. radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
  66. radeon_ring_write(ring,
  67. ISYNC_ANY2D_IDLE3D |
  68. ISYNC_ANY3D_IDLE2D |
  69. ISYNC_WAIT_IDLEGUI |
  70. ISYNC_CPSCRATCH_IDLEGUI);
  71. radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  72. radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  73. radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
  74. radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
  75. radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
  76. radeon_ring_write(ring, 0);
  77. radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
  78. radeon_ring_write(ring, 0);
  79. radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
  80. radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
  81. radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
  82. radeon_ring_write(ring, 0);
  83. radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  84. radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  85. radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  86. radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  87. radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  88. radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  89. radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
  90. radeon_ring_write(ring, 0);
  91. radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  92. radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  93. radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  94. radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  95. radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
  96. radeon_ring_write(ring,
  97. ((6 << MS_X0_SHIFT) |
  98. (6 << MS_Y0_SHIFT) |
  99. (6 << MS_X1_SHIFT) |
  100. (6 << MS_Y1_SHIFT) |
  101. (6 << MS_X2_SHIFT) |
  102. (6 << MS_Y2_SHIFT) |
  103. (6 << MSBD0_Y_SHIFT) |
  104. (6 << MSBD0_X_SHIFT)));
  105. radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
  106. radeon_ring_write(ring,
  107. ((6 << MS_X3_SHIFT) |
  108. (6 << MS_Y3_SHIFT) |
  109. (6 << MS_X4_SHIFT) |
  110. (6 << MS_Y4_SHIFT) |
  111. (6 << MS_X5_SHIFT) |
  112. (6 << MS_Y5_SHIFT) |
  113. (6 << MSBD1_SHIFT)));
  114. radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
  115. radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
  116. radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
  117. radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
  118. radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
  119. radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
  120. radeon_ring_write(ring, PACKET0(0x20C8, 0));
  121. radeon_ring_write(ring, 0);
  122. radeon_ring_unlock_commit(rdev, ring);
  123. }
  124. int rv515_mc_wait_for_idle(struct radeon_device *rdev)
  125. {
  126. unsigned i;
  127. uint32_t tmp;
  128. for (i = 0; i < rdev->usec_timeout; i++) {
  129. /* read MC_STATUS */
  130. tmp = RREG32_MC(MC_STATUS);
  131. if (tmp & MC_STATUS_IDLE) {
  132. return 0;
  133. }
  134. DRM_UDELAY(1);
  135. }
  136. return -1;
  137. }
  138. void rv515_vga_render_disable(struct radeon_device *rdev)
  139. {
  140. WREG32(R_000300_VGA_RENDER_CONTROL,
  141. RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
  142. }
  143. static void rv515_gpu_init(struct radeon_device *rdev)
  144. {
  145. unsigned pipe_select_current, gb_pipe_select, tmp;
  146. if (r100_gui_wait_for_idle(rdev)) {
  147. printk(KERN_WARNING "Failed to wait GUI idle while "
  148. "resetting GPU. Bad things might happen.\n");
  149. }
  150. rv515_vga_render_disable(rdev);
  151. r420_pipes_init(rdev);
  152. gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
  153. tmp = RREG32(R300_DST_PIPE_CONFIG);
  154. pipe_select_current = (tmp >> 2) & 3;
  155. tmp = (1 << pipe_select_current) |
  156. (((gb_pipe_select >> 8) & 0xF) << 4);
  157. WREG32_PLL(0x000D, tmp);
  158. if (r100_gui_wait_for_idle(rdev)) {
  159. printk(KERN_WARNING "Failed to wait GUI idle while "
  160. "resetting GPU. Bad things might happen.\n");
  161. }
  162. if (rv515_mc_wait_for_idle(rdev)) {
  163. printk(KERN_WARNING "Failed to wait MC idle while "
  164. "programming pipes. Bad things might happen.\n");
  165. }
  166. }
  167. static void rv515_vram_get_type(struct radeon_device *rdev)
  168. {
  169. uint32_t tmp;
  170. rdev->mc.vram_width = 128;
  171. rdev->mc.vram_is_ddr = true;
  172. tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
  173. switch (tmp) {
  174. case 0:
  175. rdev->mc.vram_width = 64;
  176. break;
  177. case 1:
  178. rdev->mc.vram_width = 128;
  179. break;
  180. default:
  181. rdev->mc.vram_width = 128;
  182. break;
  183. }
  184. }
  185. static void rv515_mc_init(struct radeon_device *rdev)
  186. {
  187. rv515_vram_get_type(rdev);
  188. r100_vram_init_sizes(rdev);
  189. radeon_vram_location(rdev, &rdev->mc, 0);
  190. rdev->mc.gtt_base_align = 0;
  191. if (!(rdev->flags & RADEON_IS_AGP))
  192. radeon_gtt_location(rdev, &rdev->mc);
  193. radeon_update_bandwidth_info(rdev);
  194. }
  195. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  196. {
  197. uint32_t r;
  198. WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
  199. r = RREG32(MC_IND_DATA);
  200. WREG32(MC_IND_INDEX, 0);
  201. return r;
  202. }
  203. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  204. {
  205. WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
  206. WREG32(MC_IND_DATA, (v));
  207. WREG32(MC_IND_INDEX, 0);
  208. }
  209. #if defined(CONFIG_DEBUG_FS)
  210. static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
  211. {
  212. struct drm_info_node *node = (struct drm_info_node *) m->private;
  213. struct drm_device *dev = node->minor->dev;
  214. struct radeon_device *rdev = dev->dev_private;
  215. uint32_t tmp;
  216. tmp = RREG32(GB_PIPE_SELECT);
  217. seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
  218. tmp = RREG32(SU_REG_DEST);
  219. seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
  220. tmp = RREG32(GB_TILE_CONFIG);
  221. seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
  222. tmp = RREG32(DST_PIPE_CONFIG);
  223. seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
  224. return 0;
  225. }
  226. static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
  227. {
  228. struct drm_info_node *node = (struct drm_info_node *) m->private;
  229. struct drm_device *dev = node->minor->dev;
  230. struct radeon_device *rdev = dev->dev_private;
  231. uint32_t tmp;
  232. tmp = RREG32(0x2140);
  233. seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
  234. radeon_asic_reset(rdev);
  235. tmp = RREG32(0x425C);
  236. seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
  237. return 0;
  238. }
  239. static struct drm_info_list rv515_pipes_info_list[] = {
  240. {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
  241. };
  242. static struct drm_info_list rv515_ga_info_list[] = {
  243. {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
  244. };
  245. #endif
  246. static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
  247. {
  248. #if defined(CONFIG_DEBUG_FS)
  249. return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
  250. #else
  251. return 0;
  252. #endif
  253. }
  254. static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
  255. {
  256. #if defined(CONFIG_DEBUG_FS)
  257. return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
  258. #else
  259. return 0;
  260. #endif
  261. }
  262. void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
  263. {
  264. u32 crtc_enabled, tmp, frame_count, blackout;
  265. int i, j;
  266. save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
  267. save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
  268. /* disable VGA render */
  269. WREG32(R_000300_VGA_RENDER_CONTROL, 0);
  270. /* blank the display controllers */
  271. for (i = 0; i < rdev->num_crtc; i++) {
  272. crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
  273. if (crtc_enabled) {
  274. save->crtc_enabled[i] = true;
  275. tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
  276. if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
  277. radeon_wait_for_vblank(rdev, i);
  278. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  279. tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
  280. WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
  281. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  282. }
  283. /* wait for the next frame */
  284. frame_count = radeon_get_vblank_counter(rdev, i);
  285. for (j = 0; j < rdev->usec_timeout; j++) {
  286. if (radeon_get_vblank_counter(rdev, i) != frame_count)
  287. break;
  288. udelay(1);
  289. }
  290. /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
  291. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  292. tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
  293. tmp &= ~AVIVO_CRTC_EN;
  294. WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
  295. WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  296. save->crtc_enabled[i] = false;
  297. /* ***** */
  298. } else {
  299. save->crtc_enabled[i] = false;
  300. }
  301. }
  302. radeon_mc_wait_for_idle(rdev);
  303. if (rdev->family >= CHIP_R600) {
  304. if (rdev->family >= CHIP_RV770)
  305. blackout = RREG32(R700_MC_CITF_CNTL);
  306. else
  307. blackout = RREG32(R600_CITF_CNTL);
  308. if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
  309. /* Block CPU access */
  310. WREG32(R600_BIF_FB_EN, 0);
  311. /* blackout the MC */
  312. blackout |= R600_BLACKOUT_MASK;
  313. if (rdev->family >= CHIP_RV770)
  314. WREG32(R700_MC_CITF_CNTL, blackout);
  315. else
  316. WREG32(R600_CITF_CNTL, blackout);
  317. }
  318. }
  319. /* wait for the MC to settle */
  320. udelay(100);
  321. /* lock double buffered regs */
  322. for (i = 0; i < rdev->num_crtc; i++) {
  323. if (save->crtc_enabled[i]) {
  324. tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
  325. if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
  326. tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  327. WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
  328. }
  329. tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
  330. if (!(tmp & 1)) {
  331. tmp |= 1;
  332. WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
  333. }
  334. }
  335. }
  336. }
  337. void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
  338. {
  339. u32 tmp, frame_count;
  340. int i, j;
  341. /* update crtc base addresses */
  342. for (i = 0; i < rdev->num_crtc; i++) {
  343. if (rdev->family >= CHIP_RV770) {
  344. if (i == 0) {
  345. WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
  346. upper_32_bits(rdev->mc.vram_start));
  347. WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
  348. upper_32_bits(rdev->mc.vram_start));
  349. } else {
  350. WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
  351. upper_32_bits(rdev->mc.vram_start));
  352. WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
  353. upper_32_bits(rdev->mc.vram_start));
  354. }
  355. }
  356. WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
  357. (u32)rdev->mc.vram_start);
  358. WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
  359. (u32)rdev->mc.vram_start);
  360. }
  361. WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
  362. /* unlock regs and wait for update */
  363. for (i = 0; i < rdev->num_crtc; i++) {
  364. if (save->crtc_enabled[i]) {
  365. tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
  366. if ((tmp & 0x3) != 0) {
  367. tmp &= ~0x3;
  368. WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
  369. }
  370. tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
  371. if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
  372. tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  373. WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
  374. }
  375. tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
  376. if (tmp & 1) {
  377. tmp &= ~1;
  378. WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
  379. }
  380. for (j = 0; j < rdev->usec_timeout; j++) {
  381. tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
  382. if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
  383. break;
  384. udelay(1);
  385. }
  386. }
  387. }
  388. if (rdev->family >= CHIP_R600) {
  389. /* unblackout the MC */
  390. if (rdev->family >= CHIP_RV770)
  391. tmp = RREG32(R700_MC_CITF_CNTL);
  392. else
  393. tmp = RREG32(R600_CITF_CNTL);
  394. tmp &= ~R600_BLACKOUT_MASK;
  395. if (rdev->family >= CHIP_RV770)
  396. WREG32(R700_MC_CITF_CNTL, tmp);
  397. else
  398. WREG32(R600_CITF_CNTL, tmp);
  399. /* allow CPU access */
  400. WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
  401. }
  402. for (i = 0; i < rdev->num_crtc; i++) {
  403. if (save->crtc_enabled[i]) {
  404. tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
  405. tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
  406. WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
  407. /* wait for the next frame */
  408. frame_count = radeon_get_vblank_counter(rdev, i);
  409. for (j = 0; j < rdev->usec_timeout; j++) {
  410. if (radeon_get_vblank_counter(rdev, i) != frame_count)
  411. break;
  412. udelay(1);
  413. }
  414. }
  415. }
  416. /* Unlock vga access */
  417. WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
  418. mdelay(1);
  419. WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
  420. }
  421. static void rv515_mc_program(struct radeon_device *rdev)
  422. {
  423. struct rv515_mc_save save;
  424. /* Stops all mc clients */
  425. rv515_mc_stop(rdev, &save);
  426. /* Wait for mc idle */
  427. if (rv515_mc_wait_for_idle(rdev))
  428. dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  429. /* Write VRAM size in case we are limiting it */
  430. WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  431. /* Program MC, should be a 32bits limited address space */
  432. WREG32_MC(R_000001_MC_FB_LOCATION,
  433. S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
  434. S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
  435. WREG32(R_000134_HDP_FB_LOCATION,
  436. S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  437. if (rdev->flags & RADEON_IS_AGP) {
  438. WREG32_MC(R_000002_MC_AGP_LOCATION,
  439. S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
  440. S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
  441. WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
  442. WREG32_MC(R_000004_MC_AGP_BASE_2,
  443. S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
  444. } else {
  445. WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
  446. WREG32_MC(R_000003_MC_AGP_BASE, 0);
  447. WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
  448. }
  449. rv515_mc_resume(rdev, &save);
  450. }
  451. void rv515_clock_startup(struct radeon_device *rdev)
  452. {
  453. if (radeon_dynclks != -1 && radeon_dynclks)
  454. radeon_atom_set_clock_gating(rdev, 1);
  455. /* We need to force on some of the block */
  456. WREG32_PLL(R_00000F_CP_DYN_CNTL,
  457. RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
  458. WREG32_PLL(R_000011_E2_DYN_CNTL,
  459. RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
  460. WREG32_PLL(R_000013_IDCT_DYN_CNTL,
  461. RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
  462. }
  463. static int rv515_startup(struct radeon_device *rdev)
  464. {
  465. int r;
  466. rv515_mc_program(rdev);
  467. /* Resume clock */
  468. rv515_clock_startup(rdev);
  469. /* Initialize GPU configuration (# pipes, ...) */
  470. rv515_gpu_init(rdev);
  471. /* Initialize GART (initialize after TTM so we can allocate
  472. * memory through TTM but finalize after TTM) */
  473. if (rdev->flags & RADEON_IS_PCIE) {
  474. r = rv370_pcie_gart_enable(rdev);
  475. if (r)
  476. return r;
  477. }
  478. /* allocate wb buffer */
  479. r = radeon_wb_init(rdev);
  480. if (r)
  481. return r;
  482. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  483. if (r) {
  484. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  485. return r;
  486. }
  487. /* Enable IRQ */
  488. rs600_irq_set(rdev);
  489. rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  490. /* 1M ring buffer */
  491. r = r100_cp_init(rdev, 1024 * 1024);
  492. if (r) {
  493. dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  494. return r;
  495. }
  496. r = radeon_ib_pool_init(rdev);
  497. if (r) {
  498. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  499. return r;
  500. }
  501. return 0;
  502. }
  503. int rv515_resume(struct radeon_device *rdev)
  504. {
  505. int r;
  506. /* Make sur GART are not working */
  507. if (rdev->flags & RADEON_IS_PCIE)
  508. rv370_pcie_gart_disable(rdev);
  509. /* Resume clock before doing reset */
  510. rv515_clock_startup(rdev);
  511. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  512. if (radeon_asic_reset(rdev)) {
  513. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  514. RREG32(R_000E40_RBBM_STATUS),
  515. RREG32(R_0007C0_CP_STAT));
  516. }
  517. /* post */
  518. atom_asic_init(rdev->mode_info.atom_context);
  519. /* Resume clock after posting */
  520. rv515_clock_startup(rdev);
  521. /* Initialize surface registers */
  522. radeon_surface_init(rdev);
  523. rdev->accel_working = true;
  524. r = rv515_startup(rdev);
  525. if (r) {
  526. rdev->accel_working = false;
  527. }
  528. return r;
  529. }
  530. int rv515_suspend(struct radeon_device *rdev)
  531. {
  532. r100_cp_disable(rdev);
  533. radeon_wb_disable(rdev);
  534. rs600_irq_disable(rdev);
  535. if (rdev->flags & RADEON_IS_PCIE)
  536. rv370_pcie_gart_disable(rdev);
  537. return 0;
  538. }
  539. void rv515_set_safe_registers(struct radeon_device *rdev)
  540. {
  541. rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
  542. rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
  543. }
  544. void rv515_fini(struct radeon_device *rdev)
  545. {
  546. r100_cp_fini(rdev);
  547. radeon_wb_fini(rdev);
  548. radeon_ib_pool_fini(rdev);
  549. radeon_gem_fini(rdev);
  550. rv370_pcie_gart_fini(rdev);
  551. radeon_agp_fini(rdev);
  552. radeon_irq_kms_fini(rdev);
  553. radeon_fence_driver_fini(rdev);
  554. radeon_bo_fini(rdev);
  555. radeon_atombios_fini(rdev);
  556. kfree(rdev->bios);
  557. rdev->bios = NULL;
  558. }
  559. int rv515_init(struct radeon_device *rdev)
  560. {
  561. int r;
  562. /* Initialize scratch registers */
  563. radeon_scratch_init(rdev);
  564. /* Initialize surface registers */
  565. radeon_surface_init(rdev);
  566. /* TODO: disable VGA need to use VGA request */
  567. /* restore some register to sane defaults */
  568. r100_restore_sanity(rdev);
  569. /* BIOS*/
  570. if (!radeon_get_bios(rdev)) {
  571. if (ASIC_IS_AVIVO(rdev))
  572. return -EINVAL;
  573. }
  574. if (rdev->is_atom_bios) {
  575. r = radeon_atombios_init(rdev);
  576. if (r)
  577. return r;
  578. } else {
  579. dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
  580. return -EINVAL;
  581. }
  582. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  583. if (radeon_asic_reset(rdev)) {
  584. dev_warn(rdev->dev,
  585. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  586. RREG32(R_000E40_RBBM_STATUS),
  587. RREG32(R_0007C0_CP_STAT));
  588. }
  589. /* check if cards are posted or not */
  590. if (radeon_boot_test_post_card(rdev) == false)
  591. return -EINVAL;
  592. /* Initialize clocks */
  593. radeon_get_clock_info(rdev->ddev);
  594. /* initialize AGP */
  595. if (rdev->flags & RADEON_IS_AGP) {
  596. r = radeon_agp_init(rdev);
  597. if (r) {
  598. radeon_agp_disable(rdev);
  599. }
  600. }
  601. /* initialize memory controller */
  602. rv515_mc_init(rdev);
  603. rv515_debugfs(rdev);
  604. /* Fence driver */
  605. r = radeon_fence_driver_init(rdev);
  606. if (r)
  607. return r;
  608. r = radeon_irq_kms_init(rdev);
  609. if (r)
  610. return r;
  611. /* Memory manager */
  612. r = radeon_bo_init(rdev);
  613. if (r)
  614. return r;
  615. r = rv370_pcie_gart_init(rdev);
  616. if (r)
  617. return r;
  618. rv515_set_safe_registers(rdev);
  619. rdev->accel_working = true;
  620. r = rv515_startup(rdev);
  621. if (r) {
  622. /* Somethings want wront with the accel init stop accel */
  623. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  624. r100_cp_fini(rdev);
  625. radeon_wb_fini(rdev);
  626. radeon_ib_pool_fini(rdev);
  627. radeon_irq_kms_fini(rdev);
  628. rv370_pcie_gart_fini(rdev);
  629. radeon_agp_fini(rdev);
  630. rdev->accel_working = false;
  631. }
  632. return 0;
  633. }
  634. void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
  635. {
  636. int index_reg = 0x6578 + crtc->crtc_offset;
  637. int data_reg = 0x657c + crtc->crtc_offset;
  638. WREG32(0x659C + crtc->crtc_offset, 0x0);
  639. WREG32(0x6594 + crtc->crtc_offset, 0x705);
  640. WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
  641. WREG32(0x65D8 + crtc->crtc_offset, 0x0);
  642. WREG32(0x65B0 + crtc->crtc_offset, 0x0);
  643. WREG32(0x65C0 + crtc->crtc_offset, 0x0);
  644. WREG32(0x65D4 + crtc->crtc_offset, 0x0);
  645. WREG32(index_reg, 0x0);
  646. WREG32(data_reg, 0x841880A8);
  647. WREG32(index_reg, 0x1);
  648. WREG32(data_reg, 0x84208680);
  649. WREG32(index_reg, 0x2);
  650. WREG32(data_reg, 0xBFF880B0);
  651. WREG32(index_reg, 0x100);
  652. WREG32(data_reg, 0x83D88088);
  653. WREG32(index_reg, 0x101);
  654. WREG32(data_reg, 0x84608680);
  655. WREG32(index_reg, 0x102);
  656. WREG32(data_reg, 0xBFF080D0);
  657. WREG32(index_reg, 0x200);
  658. WREG32(data_reg, 0x83988068);
  659. WREG32(index_reg, 0x201);
  660. WREG32(data_reg, 0x84A08680);
  661. WREG32(index_reg, 0x202);
  662. WREG32(data_reg, 0xBFF080F8);
  663. WREG32(index_reg, 0x300);
  664. WREG32(data_reg, 0x83588058);
  665. WREG32(index_reg, 0x301);
  666. WREG32(data_reg, 0x84E08660);
  667. WREG32(index_reg, 0x302);
  668. WREG32(data_reg, 0xBFF88120);
  669. WREG32(index_reg, 0x400);
  670. WREG32(data_reg, 0x83188040);
  671. WREG32(index_reg, 0x401);
  672. WREG32(data_reg, 0x85008660);
  673. WREG32(index_reg, 0x402);
  674. WREG32(data_reg, 0xBFF88150);
  675. WREG32(index_reg, 0x500);
  676. WREG32(data_reg, 0x82D88030);
  677. WREG32(index_reg, 0x501);
  678. WREG32(data_reg, 0x85408640);
  679. WREG32(index_reg, 0x502);
  680. WREG32(data_reg, 0xBFF88180);
  681. WREG32(index_reg, 0x600);
  682. WREG32(data_reg, 0x82A08018);
  683. WREG32(index_reg, 0x601);
  684. WREG32(data_reg, 0x85808620);
  685. WREG32(index_reg, 0x602);
  686. WREG32(data_reg, 0xBFF081B8);
  687. WREG32(index_reg, 0x700);
  688. WREG32(data_reg, 0x82608010);
  689. WREG32(index_reg, 0x701);
  690. WREG32(data_reg, 0x85A08600);
  691. WREG32(index_reg, 0x702);
  692. WREG32(data_reg, 0x800081F0);
  693. WREG32(index_reg, 0x800);
  694. WREG32(data_reg, 0x8228BFF8);
  695. WREG32(index_reg, 0x801);
  696. WREG32(data_reg, 0x85E085E0);
  697. WREG32(index_reg, 0x802);
  698. WREG32(data_reg, 0xBFF88228);
  699. WREG32(index_reg, 0x10000);
  700. WREG32(data_reg, 0x82A8BF00);
  701. WREG32(index_reg, 0x10001);
  702. WREG32(data_reg, 0x82A08CC0);
  703. WREG32(index_reg, 0x10002);
  704. WREG32(data_reg, 0x8008BEF8);
  705. WREG32(index_reg, 0x10100);
  706. WREG32(data_reg, 0x81F0BF28);
  707. WREG32(index_reg, 0x10101);
  708. WREG32(data_reg, 0x83608CA0);
  709. WREG32(index_reg, 0x10102);
  710. WREG32(data_reg, 0x8018BED0);
  711. WREG32(index_reg, 0x10200);
  712. WREG32(data_reg, 0x8148BF38);
  713. WREG32(index_reg, 0x10201);
  714. WREG32(data_reg, 0x84408C80);
  715. WREG32(index_reg, 0x10202);
  716. WREG32(data_reg, 0x8008BEB8);
  717. WREG32(index_reg, 0x10300);
  718. WREG32(data_reg, 0x80B0BF78);
  719. WREG32(index_reg, 0x10301);
  720. WREG32(data_reg, 0x85008C20);
  721. WREG32(index_reg, 0x10302);
  722. WREG32(data_reg, 0x8020BEA0);
  723. WREG32(index_reg, 0x10400);
  724. WREG32(data_reg, 0x8028BF90);
  725. WREG32(index_reg, 0x10401);
  726. WREG32(data_reg, 0x85E08BC0);
  727. WREG32(index_reg, 0x10402);
  728. WREG32(data_reg, 0x8018BE90);
  729. WREG32(index_reg, 0x10500);
  730. WREG32(data_reg, 0xBFB8BFB0);
  731. WREG32(index_reg, 0x10501);
  732. WREG32(data_reg, 0x86C08B40);
  733. WREG32(index_reg, 0x10502);
  734. WREG32(data_reg, 0x8010BE90);
  735. WREG32(index_reg, 0x10600);
  736. WREG32(data_reg, 0xBF58BFC8);
  737. WREG32(index_reg, 0x10601);
  738. WREG32(data_reg, 0x87A08AA0);
  739. WREG32(index_reg, 0x10602);
  740. WREG32(data_reg, 0x8010BE98);
  741. WREG32(index_reg, 0x10700);
  742. WREG32(data_reg, 0xBF10BFF0);
  743. WREG32(index_reg, 0x10701);
  744. WREG32(data_reg, 0x886089E0);
  745. WREG32(index_reg, 0x10702);
  746. WREG32(data_reg, 0x8018BEB0);
  747. WREG32(index_reg, 0x10800);
  748. WREG32(data_reg, 0xBED8BFE8);
  749. WREG32(index_reg, 0x10801);
  750. WREG32(data_reg, 0x89408940);
  751. WREG32(index_reg, 0x10802);
  752. WREG32(data_reg, 0xBFE8BED8);
  753. WREG32(index_reg, 0x20000);
  754. WREG32(data_reg, 0x80008000);
  755. WREG32(index_reg, 0x20001);
  756. WREG32(data_reg, 0x90008000);
  757. WREG32(index_reg, 0x20002);
  758. WREG32(data_reg, 0x80008000);
  759. WREG32(index_reg, 0x20003);
  760. WREG32(data_reg, 0x80008000);
  761. WREG32(index_reg, 0x20100);
  762. WREG32(data_reg, 0x80108000);
  763. WREG32(index_reg, 0x20101);
  764. WREG32(data_reg, 0x8FE0BF70);
  765. WREG32(index_reg, 0x20102);
  766. WREG32(data_reg, 0xBFE880C0);
  767. WREG32(index_reg, 0x20103);
  768. WREG32(data_reg, 0x80008000);
  769. WREG32(index_reg, 0x20200);
  770. WREG32(data_reg, 0x8018BFF8);
  771. WREG32(index_reg, 0x20201);
  772. WREG32(data_reg, 0x8F80BF08);
  773. WREG32(index_reg, 0x20202);
  774. WREG32(data_reg, 0xBFD081A0);
  775. WREG32(index_reg, 0x20203);
  776. WREG32(data_reg, 0xBFF88000);
  777. WREG32(index_reg, 0x20300);
  778. WREG32(data_reg, 0x80188000);
  779. WREG32(index_reg, 0x20301);
  780. WREG32(data_reg, 0x8EE0BEC0);
  781. WREG32(index_reg, 0x20302);
  782. WREG32(data_reg, 0xBFB082A0);
  783. WREG32(index_reg, 0x20303);
  784. WREG32(data_reg, 0x80008000);
  785. WREG32(index_reg, 0x20400);
  786. WREG32(data_reg, 0x80188000);
  787. WREG32(index_reg, 0x20401);
  788. WREG32(data_reg, 0x8E00BEA0);
  789. WREG32(index_reg, 0x20402);
  790. WREG32(data_reg, 0xBF8883C0);
  791. WREG32(index_reg, 0x20403);
  792. WREG32(data_reg, 0x80008000);
  793. WREG32(index_reg, 0x20500);
  794. WREG32(data_reg, 0x80188000);
  795. WREG32(index_reg, 0x20501);
  796. WREG32(data_reg, 0x8D00BE90);
  797. WREG32(index_reg, 0x20502);
  798. WREG32(data_reg, 0xBF588500);
  799. WREG32(index_reg, 0x20503);
  800. WREG32(data_reg, 0x80008008);
  801. WREG32(index_reg, 0x20600);
  802. WREG32(data_reg, 0x80188000);
  803. WREG32(index_reg, 0x20601);
  804. WREG32(data_reg, 0x8BC0BE98);
  805. WREG32(index_reg, 0x20602);
  806. WREG32(data_reg, 0xBF308660);
  807. WREG32(index_reg, 0x20603);
  808. WREG32(data_reg, 0x80008008);
  809. WREG32(index_reg, 0x20700);
  810. WREG32(data_reg, 0x80108000);
  811. WREG32(index_reg, 0x20701);
  812. WREG32(data_reg, 0x8A80BEB0);
  813. WREG32(index_reg, 0x20702);
  814. WREG32(data_reg, 0xBF0087C0);
  815. WREG32(index_reg, 0x20703);
  816. WREG32(data_reg, 0x80008008);
  817. WREG32(index_reg, 0x20800);
  818. WREG32(data_reg, 0x80108000);
  819. WREG32(index_reg, 0x20801);
  820. WREG32(data_reg, 0x8920BED0);
  821. WREG32(index_reg, 0x20802);
  822. WREG32(data_reg, 0xBED08920);
  823. WREG32(index_reg, 0x20803);
  824. WREG32(data_reg, 0x80008010);
  825. WREG32(index_reg, 0x30000);
  826. WREG32(data_reg, 0x90008000);
  827. WREG32(index_reg, 0x30001);
  828. WREG32(data_reg, 0x80008000);
  829. WREG32(index_reg, 0x30100);
  830. WREG32(data_reg, 0x8FE0BF90);
  831. WREG32(index_reg, 0x30101);
  832. WREG32(data_reg, 0xBFF880A0);
  833. WREG32(index_reg, 0x30200);
  834. WREG32(data_reg, 0x8F60BF40);
  835. WREG32(index_reg, 0x30201);
  836. WREG32(data_reg, 0xBFE88180);
  837. WREG32(index_reg, 0x30300);
  838. WREG32(data_reg, 0x8EC0BF00);
  839. WREG32(index_reg, 0x30301);
  840. WREG32(data_reg, 0xBFC88280);
  841. WREG32(index_reg, 0x30400);
  842. WREG32(data_reg, 0x8DE0BEE0);
  843. WREG32(index_reg, 0x30401);
  844. WREG32(data_reg, 0xBFA083A0);
  845. WREG32(index_reg, 0x30500);
  846. WREG32(data_reg, 0x8CE0BED0);
  847. WREG32(index_reg, 0x30501);
  848. WREG32(data_reg, 0xBF7884E0);
  849. WREG32(index_reg, 0x30600);
  850. WREG32(data_reg, 0x8BA0BED8);
  851. WREG32(index_reg, 0x30601);
  852. WREG32(data_reg, 0xBF508640);
  853. WREG32(index_reg, 0x30700);
  854. WREG32(data_reg, 0x8A60BEE8);
  855. WREG32(index_reg, 0x30701);
  856. WREG32(data_reg, 0xBF2087A0);
  857. WREG32(index_reg, 0x30800);
  858. WREG32(data_reg, 0x8900BF00);
  859. WREG32(index_reg, 0x30801);
  860. WREG32(data_reg, 0xBF008900);
  861. }
  862. struct rv515_watermark {
  863. u32 lb_request_fifo_depth;
  864. fixed20_12 num_line_pair;
  865. fixed20_12 estimated_width;
  866. fixed20_12 worst_case_latency;
  867. fixed20_12 consumption_rate;
  868. fixed20_12 active_time;
  869. fixed20_12 dbpp;
  870. fixed20_12 priority_mark_max;
  871. fixed20_12 priority_mark;
  872. fixed20_12 sclk;
  873. };
  874. static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
  875. struct radeon_crtc *crtc,
  876. struct rv515_watermark *wm)
  877. {
  878. struct drm_display_mode *mode = &crtc->base.mode;
  879. fixed20_12 a, b, c;
  880. fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
  881. fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
  882. if (!crtc->base.enabled) {
  883. /* FIXME: wouldn't it better to set priority mark to maximum */
  884. wm->lb_request_fifo_depth = 4;
  885. return;
  886. }
  887. if (crtc->vsc.full > dfixed_const(2))
  888. wm->num_line_pair.full = dfixed_const(2);
  889. else
  890. wm->num_line_pair.full = dfixed_const(1);
  891. b.full = dfixed_const(mode->crtc_hdisplay);
  892. c.full = dfixed_const(256);
  893. a.full = dfixed_div(b, c);
  894. request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
  895. request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
  896. if (a.full < dfixed_const(4)) {
  897. wm->lb_request_fifo_depth = 4;
  898. } else {
  899. wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
  900. }
  901. /* Determine consumption rate
  902. * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
  903. * vtaps = number of vertical taps,
  904. * vsc = vertical scaling ratio, defined as source/destination
  905. * hsc = horizontal scaling ration, defined as source/destination
  906. */
  907. a.full = dfixed_const(mode->clock);
  908. b.full = dfixed_const(1000);
  909. a.full = dfixed_div(a, b);
  910. pclk.full = dfixed_div(b, a);
  911. if (crtc->rmx_type != RMX_OFF) {
  912. b.full = dfixed_const(2);
  913. if (crtc->vsc.full > b.full)
  914. b.full = crtc->vsc.full;
  915. b.full = dfixed_mul(b, crtc->hsc);
  916. c.full = dfixed_const(2);
  917. b.full = dfixed_div(b, c);
  918. consumption_time.full = dfixed_div(pclk, b);
  919. } else {
  920. consumption_time.full = pclk.full;
  921. }
  922. a.full = dfixed_const(1);
  923. wm->consumption_rate.full = dfixed_div(a, consumption_time);
  924. /* Determine line time
  925. * LineTime = total time for one line of displayhtotal
  926. * LineTime = total number of horizontal pixels
  927. * pclk = pixel clock period(ns)
  928. */
  929. a.full = dfixed_const(crtc->base.mode.crtc_htotal);
  930. line_time.full = dfixed_mul(a, pclk);
  931. /* Determine active time
  932. * ActiveTime = time of active region of display within one line,
  933. * hactive = total number of horizontal active pixels
  934. * htotal = total number of horizontal pixels
  935. */
  936. a.full = dfixed_const(crtc->base.mode.crtc_htotal);
  937. b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
  938. wm->active_time.full = dfixed_mul(line_time, b);
  939. wm->active_time.full = dfixed_div(wm->active_time, a);
  940. /* Determine chunk time
  941. * ChunkTime = the time it takes the DCP to send one chunk of data
  942. * to the LB which consists of pipeline delay and inter chunk gap
  943. * sclk = system clock(Mhz)
  944. */
  945. a.full = dfixed_const(600 * 1000);
  946. chunk_time.full = dfixed_div(a, rdev->pm.sclk);
  947. read_delay_latency.full = dfixed_const(1000);
  948. /* Determine the worst case latency
  949. * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
  950. * WorstCaseLatency = worst case time from urgent to when the MC starts
  951. * to return data
  952. * READ_DELAY_IDLE_MAX = constant of 1us
  953. * ChunkTime = time it takes the DCP to send one chunk of data to the LB
  954. * which consists of pipeline delay and inter chunk gap
  955. */
  956. if (dfixed_trunc(wm->num_line_pair) > 1) {
  957. a.full = dfixed_const(3);
  958. wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
  959. wm->worst_case_latency.full += read_delay_latency.full;
  960. } else {
  961. wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
  962. }
  963. /* Determine the tolerable latency
  964. * TolerableLatency = Any given request has only 1 line time
  965. * for the data to be returned
  966. * LBRequestFifoDepth = Number of chunk requests the LB can
  967. * put into the request FIFO for a display
  968. * LineTime = total time for one line of display
  969. * ChunkTime = the time it takes the DCP to send one chunk
  970. * of data to the LB which consists of
  971. * pipeline delay and inter chunk gap
  972. */
  973. if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
  974. tolerable_latency.full = line_time.full;
  975. } else {
  976. tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
  977. tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
  978. tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
  979. tolerable_latency.full = line_time.full - tolerable_latency.full;
  980. }
  981. /* We assume worst case 32bits (4 bytes) */
  982. wm->dbpp.full = dfixed_const(2 * 16);
  983. /* Determine the maximum priority mark
  984. * width = viewport width in pixels
  985. */
  986. a.full = dfixed_const(16);
  987. wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
  988. wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
  989. wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
  990. /* Determine estimated width */
  991. estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
  992. estimated_width.full = dfixed_div(estimated_width, consumption_time);
  993. if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
  994. wm->priority_mark.full = wm->priority_mark_max.full;
  995. } else {
  996. a.full = dfixed_const(16);
  997. wm->priority_mark.full = dfixed_div(estimated_width, a);
  998. wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
  999. wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
  1000. }
  1001. }
  1002. void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
  1003. {
  1004. struct drm_display_mode *mode0 = NULL;
  1005. struct drm_display_mode *mode1 = NULL;
  1006. struct rv515_watermark wm0;
  1007. struct rv515_watermark wm1;
  1008. u32 tmp;
  1009. u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
  1010. u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
  1011. fixed20_12 priority_mark02, priority_mark12, fill_rate;
  1012. fixed20_12 a, b;
  1013. if (rdev->mode_info.crtcs[0]->base.enabled)
  1014. mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  1015. if (rdev->mode_info.crtcs[1]->base.enabled)
  1016. mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  1017. rs690_line_buffer_adjust(rdev, mode0, mode1);
  1018. rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
  1019. rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
  1020. tmp = wm0.lb_request_fifo_depth;
  1021. tmp |= wm1.lb_request_fifo_depth << 16;
  1022. WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
  1023. if (mode0 && mode1) {
  1024. if (dfixed_trunc(wm0.dbpp) > 64)
  1025. a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
  1026. else
  1027. a.full = wm0.num_line_pair.full;
  1028. if (dfixed_trunc(wm1.dbpp) > 64)
  1029. b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
  1030. else
  1031. b.full = wm1.num_line_pair.full;
  1032. a.full += b.full;
  1033. fill_rate.full = dfixed_div(wm0.sclk, a);
  1034. if (wm0.consumption_rate.full > fill_rate.full) {
  1035. b.full = wm0.consumption_rate.full - fill_rate.full;
  1036. b.full = dfixed_mul(b, wm0.active_time);
  1037. a.full = dfixed_const(16);
  1038. b.full = dfixed_div(b, a);
  1039. a.full = dfixed_mul(wm0.worst_case_latency,
  1040. wm0.consumption_rate);
  1041. priority_mark02.full = a.full + b.full;
  1042. } else {
  1043. a.full = dfixed_mul(wm0.worst_case_latency,
  1044. wm0.consumption_rate);
  1045. b.full = dfixed_const(16 * 1000);
  1046. priority_mark02.full = dfixed_div(a, b);
  1047. }
  1048. if (wm1.consumption_rate.full > fill_rate.full) {
  1049. b.full = wm1.consumption_rate.full - fill_rate.full;
  1050. b.full = dfixed_mul(b, wm1.active_time);
  1051. a.full = dfixed_const(16);
  1052. b.full = dfixed_div(b, a);
  1053. a.full = dfixed_mul(wm1.worst_case_latency,
  1054. wm1.consumption_rate);
  1055. priority_mark12.full = a.full + b.full;
  1056. } else {
  1057. a.full = dfixed_mul(wm1.worst_case_latency,
  1058. wm1.consumption_rate);
  1059. b.full = dfixed_const(16 * 1000);
  1060. priority_mark12.full = dfixed_div(a, b);
  1061. }
  1062. if (wm0.priority_mark.full > priority_mark02.full)
  1063. priority_mark02.full = wm0.priority_mark.full;
  1064. if (dfixed_trunc(priority_mark02) < 0)
  1065. priority_mark02.full = 0;
  1066. if (wm0.priority_mark_max.full > priority_mark02.full)
  1067. priority_mark02.full = wm0.priority_mark_max.full;
  1068. if (wm1.priority_mark.full > priority_mark12.full)
  1069. priority_mark12.full = wm1.priority_mark.full;
  1070. if (dfixed_trunc(priority_mark12) < 0)
  1071. priority_mark12.full = 0;
  1072. if (wm1.priority_mark_max.full > priority_mark12.full)
  1073. priority_mark12.full = wm1.priority_mark_max.full;
  1074. d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
  1075. d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
  1076. if (rdev->disp_priority == 2) {
  1077. d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1078. d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1079. }
  1080. } else if (mode0) {
  1081. if (dfixed_trunc(wm0.dbpp) > 64)
  1082. a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
  1083. else
  1084. a.full = wm0.num_line_pair.full;
  1085. fill_rate.full = dfixed_div(wm0.sclk, a);
  1086. if (wm0.consumption_rate.full > fill_rate.full) {
  1087. b.full = wm0.consumption_rate.full - fill_rate.full;
  1088. b.full = dfixed_mul(b, wm0.active_time);
  1089. a.full = dfixed_const(16);
  1090. b.full = dfixed_div(b, a);
  1091. a.full = dfixed_mul(wm0.worst_case_latency,
  1092. wm0.consumption_rate);
  1093. priority_mark02.full = a.full + b.full;
  1094. } else {
  1095. a.full = dfixed_mul(wm0.worst_case_latency,
  1096. wm0.consumption_rate);
  1097. b.full = dfixed_const(16);
  1098. priority_mark02.full = dfixed_div(a, b);
  1099. }
  1100. if (wm0.priority_mark.full > priority_mark02.full)
  1101. priority_mark02.full = wm0.priority_mark.full;
  1102. if (dfixed_trunc(priority_mark02) < 0)
  1103. priority_mark02.full = 0;
  1104. if (wm0.priority_mark_max.full > priority_mark02.full)
  1105. priority_mark02.full = wm0.priority_mark_max.full;
  1106. d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
  1107. if (rdev->disp_priority == 2)
  1108. d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1109. } else if (mode1) {
  1110. if (dfixed_trunc(wm1.dbpp) > 64)
  1111. a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
  1112. else
  1113. a.full = wm1.num_line_pair.full;
  1114. fill_rate.full = dfixed_div(wm1.sclk, a);
  1115. if (wm1.consumption_rate.full > fill_rate.full) {
  1116. b.full = wm1.consumption_rate.full - fill_rate.full;
  1117. b.full = dfixed_mul(b, wm1.active_time);
  1118. a.full = dfixed_const(16);
  1119. b.full = dfixed_div(b, a);
  1120. a.full = dfixed_mul(wm1.worst_case_latency,
  1121. wm1.consumption_rate);
  1122. priority_mark12.full = a.full + b.full;
  1123. } else {
  1124. a.full = dfixed_mul(wm1.worst_case_latency,
  1125. wm1.consumption_rate);
  1126. b.full = dfixed_const(16 * 1000);
  1127. priority_mark12.full = dfixed_div(a, b);
  1128. }
  1129. if (wm1.priority_mark.full > priority_mark12.full)
  1130. priority_mark12.full = wm1.priority_mark.full;
  1131. if (dfixed_trunc(priority_mark12) < 0)
  1132. priority_mark12.full = 0;
  1133. if (wm1.priority_mark_max.full > priority_mark12.full)
  1134. priority_mark12.full = wm1.priority_mark_max.full;
  1135. d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
  1136. if (rdev->disp_priority == 2)
  1137. d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
  1138. }
  1139. WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
  1140. WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
  1141. WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
  1142. WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
  1143. }
  1144. void rv515_bandwidth_update(struct radeon_device *rdev)
  1145. {
  1146. uint32_t tmp;
  1147. struct drm_display_mode *mode0 = NULL;
  1148. struct drm_display_mode *mode1 = NULL;
  1149. radeon_update_display_priority(rdev);
  1150. if (rdev->mode_info.crtcs[0]->base.enabled)
  1151. mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  1152. if (rdev->mode_info.crtcs[1]->base.enabled)
  1153. mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  1154. /*
  1155. * Set display0/1 priority up in the memory controller for
  1156. * modes if the user specifies HIGH for displaypriority
  1157. * option.
  1158. */
  1159. if ((rdev->disp_priority == 2) &&
  1160. (rdev->family == CHIP_RV515)) {
  1161. tmp = RREG32_MC(MC_MISC_LAT_TIMER);
  1162. tmp &= ~MC_DISP1R_INIT_LAT_MASK;
  1163. tmp &= ~MC_DISP0R_INIT_LAT_MASK;
  1164. if (mode1)
  1165. tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
  1166. if (mode0)
  1167. tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
  1168. WREG32_MC(MC_MISC_LAT_TIMER, tmp);
  1169. }
  1170. rv515_bandwidth_avivo_update(rdev);
  1171. }