cx23885-cards.c 31 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include "cx23885.h"
  27. #include "tuner-xc2028.h"
  28. #include "netup-init.h"
  29. #include "cx23888-ir.h"
  30. /* ------------------------------------------------------------------ */
  31. /* board config info */
  32. struct cx23885_board cx23885_boards[] = {
  33. [CX23885_BOARD_UNKNOWN] = {
  34. .name = "UNKNOWN/GENERIC",
  35. /* Ensure safe default for unknown boards */
  36. .clk_freq = 0,
  37. .input = {{
  38. .type = CX23885_VMUX_COMPOSITE1,
  39. .vmux = 0,
  40. }, {
  41. .type = CX23885_VMUX_COMPOSITE2,
  42. .vmux = 1,
  43. }, {
  44. .type = CX23885_VMUX_COMPOSITE3,
  45. .vmux = 2,
  46. }, {
  47. .type = CX23885_VMUX_COMPOSITE4,
  48. .vmux = 3,
  49. } },
  50. },
  51. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  52. .name = "Hauppauge WinTV-HVR1800lp",
  53. .portc = CX23885_MPEG_DVB,
  54. .input = {{
  55. .type = CX23885_VMUX_TELEVISION,
  56. .vmux = 0,
  57. .gpio0 = 0xff00,
  58. }, {
  59. .type = CX23885_VMUX_DEBUG,
  60. .vmux = 0,
  61. .gpio0 = 0xff01,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE1,
  64. .vmux = 1,
  65. .gpio0 = 0xff02,
  66. }, {
  67. .type = CX23885_VMUX_SVIDEO,
  68. .vmux = 2,
  69. .gpio0 = 0xff02,
  70. } },
  71. },
  72. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  73. .name = "Hauppauge WinTV-HVR1800",
  74. .porta = CX23885_ANALOG_VIDEO,
  75. .portb = CX23885_MPEG_ENCODER,
  76. .portc = CX23885_MPEG_DVB,
  77. .tuner_type = TUNER_PHILIPS_TDA8290,
  78. .tuner_addr = 0x42, /* 0x84 >> 1 */
  79. .input = {{
  80. .type = CX23885_VMUX_TELEVISION,
  81. .vmux = CX25840_VIN7_CH3 |
  82. CX25840_VIN5_CH2 |
  83. CX25840_VIN2_CH1,
  84. .gpio0 = 0,
  85. }, {
  86. .type = CX23885_VMUX_COMPOSITE1,
  87. .vmux = CX25840_VIN7_CH3 |
  88. CX25840_VIN4_CH2 |
  89. CX25840_VIN6_CH1,
  90. .gpio0 = 0,
  91. }, {
  92. .type = CX23885_VMUX_SVIDEO,
  93. .vmux = CX25840_VIN7_CH3 |
  94. CX25840_VIN4_CH2 |
  95. CX25840_VIN8_CH1 |
  96. CX25840_SVIDEO_ON,
  97. .gpio0 = 0,
  98. } },
  99. },
  100. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  101. .name = "Hauppauge WinTV-HVR1250",
  102. .portc = CX23885_MPEG_DVB,
  103. .input = {{
  104. .type = CX23885_VMUX_TELEVISION,
  105. .vmux = 0,
  106. .gpio0 = 0xff00,
  107. }, {
  108. .type = CX23885_VMUX_DEBUG,
  109. .vmux = 0,
  110. .gpio0 = 0xff01,
  111. }, {
  112. .type = CX23885_VMUX_COMPOSITE1,
  113. .vmux = 1,
  114. .gpio0 = 0xff02,
  115. }, {
  116. .type = CX23885_VMUX_SVIDEO,
  117. .vmux = 2,
  118. .gpio0 = 0xff02,
  119. } },
  120. },
  121. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  122. .name = "DViCO FusionHDTV5 Express",
  123. .portb = CX23885_MPEG_DVB,
  124. },
  125. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  126. .name = "Hauppauge WinTV-HVR1500Q",
  127. .portc = CX23885_MPEG_DVB,
  128. },
  129. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  130. .name = "Hauppauge WinTV-HVR1500",
  131. .portc = CX23885_MPEG_DVB,
  132. },
  133. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  134. .name = "Hauppauge WinTV-HVR1200",
  135. .portc = CX23885_MPEG_DVB,
  136. },
  137. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  138. .name = "Hauppauge WinTV-HVR1700",
  139. .portc = CX23885_MPEG_DVB,
  140. },
  141. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  142. .name = "Hauppauge WinTV-HVR1400",
  143. .portc = CX23885_MPEG_DVB,
  144. },
  145. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  146. .name = "DViCO FusionHDTV7 Dual Express",
  147. .portb = CX23885_MPEG_DVB,
  148. .portc = CX23885_MPEG_DVB,
  149. },
  150. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  151. .name = "DViCO FusionHDTV DVB-T Dual Express",
  152. .portb = CX23885_MPEG_DVB,
  153. .portc = CX23885_MPEG_DVB,
  154. },
  155. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  156. .name = "Leadtek Winfast PxDVR3200 H",
  157. .portc = CX23885_MPEG_DVB,
  158. },
  159. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  160. .name = "Compro VideoMate E650F",
  161. .portc = CX23885_MPEG_DVB,
  162. },
  163. [CX23885_BOARD_TBS_6920] = {
  164. .name = "TurboSight TBS 6920",
  165. .portb = CX23885_MPEG_DVB,
  166. },
  167. [CX23885_BOARD_TEVII_S470] = {
  168. .name = "TeVii S470",
  169. .portb = CX23885_MPEG_DVB,
  170. },
  171. [CX23885_BOARD_DVBWORLD_2005] = {
  172. .name = "DVBWorld DVB-S2 2005",
  173. .portb = CX23885_MPEG_DVB,
  174. },
  175. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  176. .cimax = 1,
  177. .name = "NetUP Dual DVB-S2 CI",
  178. .portb = CX23885_MPEG_DVB,
  179. .portc = CX23885_MPEG_DVB,
  180. },
  181. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  182. .name = "Hauppauge WinTV-HVR1270",
  183. .portc = CX23885_MPEG_DVB,
  184. },
  185. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  186. .name = "Hauppauge WinTV-HVR1275",
  187. .portc = CX23885_MPEG_DVB,
  188. },
  189. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  190. .name = "Hauppauge WinTV-HVR1255",
  191. .portc = CX23885_MPEG_DVB,
  192. },
  193. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  194. .name = "Hauppauge WinTV-HVR1210",
  195. .portc = CX23885_MPEG_DVB,
  196. },
  197. [CX23885_BOARD_MYGICA_X8506] = {
  198. .name = "Mygica X8506 DMB-TH",
  199. .tuner_type = TUNER_XC5000,
  200. .tuner_addr = 0x61,
  201. .porta = CX23885_ANALOG_VIDEO,
  202. .portb = CX23885_MPEG_DVB,
  203. .input = {
  204. {
  205. .type = CX23885_VMUX_TELEVISION,
  206. .vmux = CX25840_COMPOSITE2,
  207. },
  208. {
  209. .type = CX23885_VMUX_COMPOSITE1,
  210. .vmux = CX25840_COMPOSITE8,
  211. },
  212. {
  213. .type = CX23885_VMUX_SVIDEO,
  214. .vmux = CX25840_SVIDEO_LUMA3 |
  215. CX25840_SVIDEO_CHROMA4,
  216. },
  217. {
  218. .type = CX23885_VMUX_COMPONENT,
  219. .vmux = CX25840_COMPONENT_ON |
  220. CX25840_VIN1_CH1 |
  221. CX25840_VIN6_CH2 |
  222. CX25840_VIN7_CH3,
  223. },
  224. },
  225. },
  226. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  227. .name = "Magic-Pro ProHDTV Extreme 2",
  228. .tuner_type = TUNER_XC5000,
  229. .tuner_addr = 0x61,
  230. .porta = CX23885_ANALOG_VIDEO,
  231. .portb = CX23885_MPEG_DVB,
  232. .input = {
  233. {
  234. .type = CX23885_VMUX_TELEVISION,
  235. .vmux = CX25840_COMPOSITE2,
  236. },
  237. {
  238. .type = CX23885_VMUX_COMPOSITE1,
  239. .vmux = CX25840_COMPOSITE8,
  240. },
  241. {
  242. .type = CX23885_VMUX_SVIDEO,
  243. .vmux = CX25840_SVIDEO_LUMA3 |
  244. CX25840_SVIDEO_CHROMA4,
  245. },
  246. {
  247. .type = CX23885_VMUX_COMPONENT,
  248. .vmux = CX25840_COMPONENT_ON |
  249. CX25840_VIN1_CH1 |
  250. CX25840_VIN6_CH2 |
  251. CX25840_VIN7_CH3,
  252. },
  253. },
  254. },
  255. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  256. .name = "Hauppauge WinTV-HVR1850",
  257. .portb = CX23885_MPEG_ENCODER,
  258. .portc = CX23885_MPEG_DVB,
  259. },
  260. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  261. .name = "Compro VideoMate E800",
  262. .portc = CX23885_MPEG_DVB,
  263. },
  264. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  265. .name = "Hauppauge WinTV-HVR1290",
  266. .portc = CX23885_MPEG_DVB,
  267. },
  268. [CX23885_BOARD_MYGICA_X8558PRO] = {
  269. .name = "Mygica X8558 PRO DMB-TH",
  270. .portb = CX23885_MPEG_DVB,
  271. .portc = CX23885_MPEG_DVB,
  272. },
  273. };
  274. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  275. /* ------------------------------------------------------------------ */
  276. /* PCI subsystem IDs */
  277. struct cx23885_subid cx23885_subids[] = {
  278. {
  279. .subvendor = 0x0070,
  280. .subdevice = 0x3400,
  281. .card = CX23885_BOARD_UNKNOWN,
  282. }, {
  283. .subvendor = 0x0070,
  284. .subdevice = 0x7600,
  285. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  286. }, {
  287. .subvendor = 0x0070,
  288. .subdevice = 0x7800,
  289. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  290. }, {
  291. .subvendor = 0x0070,
  292. .subdevice = 0x7801,
  293. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  294. }, {
  295. .subvendor = 0x0070,
  296. .subdevice = 0x7809,
  297. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  298. }, {
  299. .subvendor = 0x0070,
  300. .subdevice = 0x7911,
  301. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  302. }, {
  303. .subvendor = 0x18ac,
  304. .subdevice = 0xd500,
  305. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  306. }, {
  307. .subvendor = 0x0070,
  308. .subdevice = 0x7790,
  309. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  310. }, {
  311. .subvendor = 0x0070,
  312. .subdevice = 0x7797,
  313. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  314. }, {
  315. .subvendor = 0x0070,
  316. .subdevice = 0x7710,
  317. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  318. }, {
  319. .subvendor = 0x0070,
  320. .subdevice = 0x7717,
  321. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  322. }, {
  323. .subvendor = 0x0070,
  324. .subdevice = 0x71d1,
  325. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  326. }, {
  327. .subvendor = 0x0070,
  328. .subdevice = 0x71d3,
  329. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  330. }, {
  331. .subvendor = 0x0070,
  332. .subdevice = 0x8101,
  333. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  334. }, {
  335. .subvendor = 0x0070,
  336. .subdevice = 0x8010,
  337. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  338. }, {
  339. .subvendor = 0x18ac,
  340. .subdevice = 0xd618,
  341. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  342. }, {
  343. .subvendor = 0x18ac,
  344. .subdevice = 0xdb78,
  345. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  346. }, {
  347. .subvendor = 0x107d,
  348. .subdevice = 0x6681,
  349. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  350. }, {
  351. .subvendor = 0x185b,
  352. .subdevice = 0xe800,
  353. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  354. }, {
  355. .subvendor = 0x6920,
  356. .subdevice = 0x8888,
  357. .card = CX23885_BOARD_TBS_6920,
  358. }, {
  359. .subvendor = 0xd470,
  360. .subdevice = 0x9022,
  361. .card = CX23885_BOARD_TEVII_S470,
  362. }, {
  363. .subvendor = 0x0001,
  364. .subdevice = 0x2005,
  365. .card = CX23885_BOARD_DVBWORLD_2005,
  366. }, {
  367. .subvendor = 0x1b55,
  368. .subdevice = 0x2a2c,
  369. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  370. }, {
  371. .subvendor = 0x0070,
  372. .subdevice = 0x2211,
  373. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  374. }, {
  375. .subvendor = 0x0070,
  376. .subdevice = 0x2215,
  377. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  378. }, {
  379. .subvendor = 0x0070,
  380. .subdevice = 0x2251,
  381. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  382. }, {
  383. .subvendor = 0x0070,
  384. .subdevice = 0x2291,
  385. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  386. }, {
  387. .subvendor = 0x0070,
  388. .subdevice = 0x2295,
  389. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  390. }, {
  391. .subvendor = 0x14f1,
  392. .subdevice = 0x8651,
  393. .card = CX23885_BOARD_MYGICA_X8506,
  394. }, {
  395. .subvendor = 0x14f1,
  396. .subdevice = 0x8657,
  397. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  398. }, {
  399. .subvendor = 0x0070,
  400. .subdevice = 0x8541,
  401. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  402. }, {
  403. .subvendor = 0x1858,
  404. .subdevice = 0xe800,
  405. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  406. }, {
  407. .subvendor = 0x0070,
  408. .subdevice = 0x8551,
  409. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  410. }, {
  411. .subvendor = 0x14f1,
  412. .subdevice = 0x8578,
  413. .card = CX23885_BOARD_MYGICA_X8558PRO,
  414. },
  415. };
  416. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  417. void cx23885_card_list(struct cx23885_dev *dev)
  418. {
  419. int i;
  420. if (0 == dev->pci->subsystem_vendor &&
  421. 0 == dev->pci->subsystem_device) {
  422. printk(KERN_INFO
  423. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  424. "%s: be autodetected. Pass card=<n> insmod option\n"
  425. "%s: to workaround that. Redirect complaints to the\n"
  426. "%s: vendor of the TV card. Best regards,\n"
  427. "%s: -- tux\n",
  428. dev->name, dev->name, dev->name, dev->name, dev->name);
  429. } else {
  430. printk(KERN_INFO
  431. "%s: Your board isn't known (yet) to the driver.\n"
  432. "%s: Try to pick one of the existing card configs via\n"
  433. "%s: card=<n> insmod option. Updating to the latest\n"
  434. "%s: version might help as well.\n",
  435. dev->name, dev->name, dev->name, dev->name);
  436. }
  437. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  438. dev->name);
  439. for (i = 0; i < cx23885_bcount; i++)
  440. printk(KERN_INFO "%s: card=%d -> %s\n",
  441. dev->name, i, cx23885_boards[i].name);
  442. }
  443. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  444. {
  445. struct tveeprom tv;
  446. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  447. eeprom_data);
  448. /* Make sure we support the board model */
  449. switch (tv.model) {
  450. case 22001:
  451. /* WinTV-HVR1270 (PCIe, Retail, half height)
  452. * ATSC/QAM and basic analog, IR Blast */
  453. case 22009:
  454. /* WinTV-HVR1210 (PCIe, Retail, half height)
  455. * DVB-T and basic analog, IR Blast */
  456. case 22011:
  457. /* WinTV-HVR1270 (PCIe, Retail, half height)
  458. * ATSC/QAM and basic analog, IR Recv */
  459. case 22019:
  460. /* WinTV-HVR1210 (PCIe, Retail, half height)
  461. * DVB-T and basic analog, IR Recv */
  462. case 22021:
  463. /* WinTV-HVR1275 (PCIe, Retail, half height)
  464. * ATSC/QAM and basic analog, IR Recv */
  465. case 22029:
  466. /* WinTV-HVR1210 (PCIe, Retail, half height)
  467. * DVB-T and basic analog, IR Recv */
  468. case 22101:
  469. /* WinTV-HVR1270 (PCIe, Retail, full height)
  470. * ATSC/QAM and basic analog, IR Blast */
  471. case 22109:
  472. /* WinTV-HVR1210 (PCIe, Retail, full height)
  473. * DVB-T and basic analog, IR Blast */
  474. case 22111:
  475. /* WinTV-HVR1270 (PCIe, Retail, full height)
  476. * ATSC/QAM and basic analog, IR Recv */
  477. case 22119:
  478. /* WinTV-HVR1210 (PCIe, Retail, full height)
  479. * DVB-T and basic analog, IR Recv */
  480. case 22121:
  481. /* WinTV-HVR1275 (PCIe, Retail, full height)
  482. * ATSC/QAM and basic analog, IR Recv */
  483. case 22129:
  484. /* WinTV-HVR1210 (PCIe, Retail, full height)
  485. * DVB-T and basic analog, IR Recv */
  486. case 71009:
  487. /* WinTV-HVR1200 (PCIe, Retail, full height)
  488. * DVB-T and basic analog */
  489. case 71359:
  490. /* WinTV-HVR1200 (PCIe, OEM, half height)
  491. * DVB-T and basic analog */
  492. case 71439:
  493. /* WinTV-HVR1200 (PCIe, OEM, half height)
  494. * DVB-T and basic analog */
  495. case 71449:
  496. /* WinTV-HVR1200 (PCIe, OEM, full height)
  497. * DVB-T and basic analog */
  498. case 71939:
  499. /* WinTV-HVR1200 (PCIe, OEM, half height)
  500. * DVB-T and basic analog */
  501. case 71949:
  502. /* WinTV-HVR1200 (PCIe, OEM, full height)
  503. * DVB-T and basic analog */
  504. case 71959:
  505. /* WinTV-HVR1200 (PCIe, OEM, full height)
  506. * DVB-T and basic analog */
  507. case 71979:
  508. /* WinTV-HVR1200 (PCIe, OEM, half height)
  509. * DVB-T and basic analog */
  510. case 71999:
  511. /* WinTV-HVR1200 (PCIe, OEM, full height)
  512. * DVB-T and basic analog */
  513. case 76601:
  514. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  515. channel ATSC and MPEG2 HW Encoder */
  516. case 77001:
  517. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  518. and Basic analog */
  519. case 77011:
  520. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  521. and Basic analog */
  522. case 77041:
  523. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  524. and Basic analog */
  525. case 77051:
  526. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  527. and Basic analog */
  528. case 78011:
  529. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  530. Dual channel ATSC and MPEG2 HW Encoder */
  531. case 78501:
  532. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  533. Dual channel ATSC and MPEG2 HW Encoder */
  534. case 78521:
  535. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  536. Dual channel ATSC and MPEG2 HW Encoder */
  537. case 78531:
  538. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  539. Dual channel ATSC and MPEG2 HW Encoder */
  540. case 78631:
  541. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  542. Dual channel ATSC and MPEG2 HW Encoder */
  543. case 79001:
  544. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  545. ATSC and Basic analog */
  546. case 79101:
  547. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  548. ATSC and Basic analog */
  549. case 79561:
  550. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  551. ATSC and Basic analog */
  552. case 79571:
  553. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  554. ATSC and Basic analog */
  555. case 79671:
  556. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  557. ATSC and Basic analog */
  558. case 80019:
  559. /* WinTV-HVR1400 (Express Card, Retail, IR,
  560. * DVB-T and Basic analog */
  561. case 81509:
  562. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  563. * DVB-T and MPEG2 HW Encoder */
  564. case 81519:
  565. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  566. * DVB-T and MPEG2 HW Encoder */
  567. break;
  568. case 85021:
  569. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  570. Dual channel ATSC and MPEG2 HW Encoder */
  571. break;
  572. case 85721:
  573. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  574. Dual channel ATSC and Basic analog */
  575. break;
  576. default:
  577. printk(KERN_WARNING "%s: warning: "
  578. "unknown hauppauge model #%d\n",
  579. dev->name, tv.model);
  580. break;
  581. }
  582. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  583. dev->name, tv.model);
  584. }
  585. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  586. {
  587. struct cx23885_tsport *port = priv;
  588. struct cx23885_dev *dev = port->dev;
  589. u32 bitmask = 0;
  590. if (command == XC2028_RESET_CLK)
  591. return 0;
  592. if (command != 0) {
  593. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  594. __func__, command);
  595. return -EINVAL;
  596. }
  597. switch (dev->board) {
  598. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  599. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  600. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  601. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  602. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  603. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  604. /* Tuner Reset Command */
  605. bitmask = 0x04;
  606. break;
  607. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  608. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  609. /* Two identical tuners on two different i2c buses,
  610. * we need to reset the correct gpio. */
  611. if (port->nr == 1)
  612. bitmask = 0x01;
  613. else if (port->nr == 2)
  614. bitmask = 0x04;
  615. break;
  616. }
  617. if (bitmask) {
  618. /* Drive the tuner into reset and back out */
  619. cx_clear(GP0_IO, bitmask);
  620. mdelay(200);
  621. cx_set(GP0_IO, bitmask);
  622. }
  623. return 0;
  624. }
  625. void cx23885_gpio_setup(struct cx23885_dev *dev)
  626. {
  627. switch (dev->board) {
  628. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  629. /* GPIO-0 cx24227 demodulator reset */
  630. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  631. break;
  632. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  633. /* GPIO-0 cx24227 demodulator */
  634. /* GPIO-2 xc3028 tuner */
  635. /* Put the parts into reset */
  636. cx_set(GP0_IO, 0x00050000);
  637. cx_clear(GP0_IO, 0x00000005);
  638. msleep(5);
  639. /* Bring the parts out of reset */
  640. cx_set(GP0_IO, 0x00050005);
  641. break;
  642. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  643. /* GPIO-0 cx24227 demodulator reset */
  644. /* GPIO-2 xc5000 tuner reset */
  645. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  646. break;
  647. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  648. /* GPIO-0 656_CLK */
  649. /* GPIO-1 656_D0 */
  650. /* GPIO-2 8295A Reset */
  651. /* GPIO-3-10 cx23417 data0-7 */
  652. /* GPIO-11-14 cx23417 addr0-3 */
  653. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  654. /* GPIO-19 IR_RX */
  655. /* CX23417 GPIO's */
  656. /* EIO15 Zilog Reset */
  657. /* EIO14 S5H1409/CX24227 Reset */
  658. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  659. /* Put the demod into reset and protect the eeprom */
  660. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  661. mdelay(100);
  662. /* Bring the demod and blaster out of reset */
  663. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  664. mdelay(100);
  665. /* Force the TDA8295A into reset and back */
  666. cx23885_gpio_enable(dev, GPIO_2, 1);
  667. cx23885_gpio_set(dev, GPIO_2);
  668. mdelay(20);
  669. cx23885_gpio_clear(dev, GPIO_2);
  670. mdelay(20);
  671. cx23885_gpio_set(dev, GPIO_2);
  672. mdelay(20);
  673. break;
  674. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  675. /* GPIO-0 tda10048 demodulator reset */
  676. /* GPIO-2 tda18271 tuner reset */
  677. /* Put the parts into reset and back */
  678. cx_set(GP0_IO, 0x00050000);
  679. mdelay(20);
  680. cx_clear(GP0_IO, 0x00000005);
  681. mdelay(20);
  682. cx_set(GP0_IO, 0x00050005);
  683. break;
  684. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  685. /* GPIO-0 TDA10048 demodulator reset */
  686. /* GPIO-2 TDA8295A Reset */
  687. /* GPIO-3-10 cx23417 data0-7 */
  688. /* GPIO-11-14 cx23417 addr0-3 */
  689. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  690. /* The following GPIO's are on the interna AVCore (cx25840) */
  691. /* GPIO-19 IR_RX */
  692. /* GPIO-20 IR_TX 416/DVBT Select */
  693. /* GPIO-21 IIS DAT */
  694. /* GPIO-22 IIS WCLK */
  695. /* GPIO-23 IIS BCLK */
  696. /* Put the parts into reset and back */
  697. cx_set(GP0_IO, 0x00050000);
  698. mdelay(20);
  699. cx_clear(GP0_IO, 0x00000005);
  700. mdelay(20);
  701. cx_set(GP0_IO, 0x00050005);
  702. break;
  703. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  704. /* GPIO-0 Dibcom7000p demodulator reset */
  705. /* GPIO-2 xc3028L tuner reset */
  706. /* GPIO-13 LED */
  707. /* Put the parts into reset and back */
  708. cx_set(GP0_IO, 0x00050000);
  709. mdelay(20);
  710. cx_clear(GP0_IO, 0x00000005);
  711. mdelay(20);
  712. cx_set(GP0_IO, 0x00050005);
  713. break;
  714. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  715. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  716. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  717. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  718. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  719. /* Put the parts into reset and back */
  720. cx_set(GP0_IO, 0x000f0000);
  721. mdelay(20);
  722. cx_clear(GP0_IO, 0x0000000f);
  723. mdelay(20);
  724. cx_set(GP0_IO, 0x000f000f);
  725. break;
  726. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  727. /* GPIO-0 portb xc3028 reset */
  728. /* GPIO-1 portb zl10353 reset */
  729. /* GPIO-2 portc xc3028 reset */
  730. /* GPIO-3 portc zl10353 reset */
  731. /* Put the parts into reset and back */
  732. cx_set(GP0_IO, 0x000f0000);
  733. mdelay(20);
  734. cx_clear(GP0_IO, 0x0000000f);
  735. mdelay(20);
  736. cx_set(GP0_IO, 0x000f000f);
  737. break;
  738. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  739. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  740. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  741. /* GPIO-2 xc3028 tuner reset */
  742. /* The following GPIO's are on the internal AVCore (cx25840) */
  743. /* GPIO-? zl10353 demod reset */
  744. /* Put the parts into reset and back */
  745. cx_set(GP0_IO, 0x00040000);
  746. mdelay(20);
  747. cx_clear(GP0_IO, 0x00000004);
  748. mdelay(20);
  749. cx_set(GP0_IO, 0x00040004);
  750. break;
  751. case CX23885_BOARD_TBS_6920:
  752. cx_write(MC417_CTL, 0x00000036);
  753. cx_write(MC417_OEN, 0x00001000);
  754. cx_set(MC417_RWD, 0x00000002);
  755. mdelay(200);
  756. cx_clear(MC417_RWD, 0x00000800);
  757. mdelay(200);
  758. cx_set(MC417_RWD, 0x00000800);
  759. mdelay(200);
  760. break;
  761. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  762. /* GPIO-0 INTA from CiMax1
  763. GPIO-1 INTB from CiMax2
  764. GPIO-2 reset chips
  765. GPIO-3 to GPIO-10 data/addr for CA
  766. GPIO-11 ~CS0 to CiMax1
  767. GPIO-12 ~CS1 to CiMax2
  768. GPIO-13 ADL0 load LSB addr
  769. GPIO-14 ADL1 load MSB addr
  770. GPIO-15 ~RDY from CiMax
  771. GPIO-17 ~RD to CiMax
  772. GPIO-18 ~WR to CiMax
  773. */
  774. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  775. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  776. cx_clear(GP0_IO, 0x00030004);
  777. mdelay(100);/* reset delay */
  778. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  779. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  780. /* GPIO-15 IN as ~ACK, rest as OUT */
  781. cx_write(MC417_OEN, 0x00001000);
  782. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  783. cx_write(MC417_RWD, 0x0000c300);
  784. /* enable irq */
  785. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  786. break;
  787. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  788. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  789. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  790. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  791. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  792. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  793. /* GPIO-9 Demod reset */
  794. /* Put the parts into reset and back */
  795. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  796. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  797. cx23885_gpio_clear(dev, GPIO_9);
  798. mdelay(20);
  799. cx23885_gpio_set(dev, GPIO_9);
  800. break;
  801. case CX23885_BOARD_MYGICA_X8506:
  802. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  803. /* GPIO-0 (0)Analog / (1)Digital TV */
  804. /* GPIO-1 reset XC5000 */
  805. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  806. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  807. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  808. mdelay(100);
  809. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  810. mdelay(100);
  811. break;
  812. case CX23885_BOARD_MYGICA_X8558PRO:
  813. /* GPIO-0 reset first ATBM8830 */
  814. /* GPIO-1 reset second ATBM8830 */
  815. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  816. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  817. mdelay(100);
  818. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  819. mdelay(100);
  820. break;
  821. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  822. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  823. /* GPIO-0 656_CLK */
  824. /* GPIO-1 656_D0 */
  825. /* GPIO-2 Wake# */
  826. /* GPIO-3-10 cx23417 data0-7 */
  827. /* GPIO-11-14 cx23417 addr0-3 */
  828. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  829. /* GPIO-19 IR_RX */
  830. /* GPIO-20 C_IR_TX */
  831. /* GPIO-21 I2S DAT */
  832. /* GPIO-22 I2S WCLK */
  833. /* GPIO-23 I2S BCLK */
  834. /* ALT GPIO: EXP GPIO LATCH */
  835. /* CX23417 GPIO's */
  836. /* GPIO-14 S5H1411/CX24228 Reset */
  837. /* GPIO-13 EEPROM write protect */
  838. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  839. /* Put the demod into reset and protect the eeprom */
  840. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  841. mdelay(100);
  842. /* Bring the demod out of reset */
  843. mc417_gpio_set(dev, GPIO_14);
  844. mdelay(100);
  845. /* CX24228 GPIO */
  846. /* Connected to IF / Mux */
  847. break;
  848. }
  849. }
  850. int cx23885_ir_init(struct cx23885_dev *dev)
  851. {
  852. int ret = 0;
  853. switch (dev->board) {
  854. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  855. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  856. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  857. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  858. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  859. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  860. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  861. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  862. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  863. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  864. /* FIXME: Implement me */
  865. break;
  866. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  867. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  868. ret = cx23888_ir_probe(dev);
  869. if (ret)
  870. break;
  871. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  872. dev->pci_irqmask |= PCI_MSK_IR;
  873. break;
  874. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  875. request_module("ir-kbd-i2c");
  876. break;
  877. }
  878. return ret;
  879. }
  880. void cx23885_ir_fini(struct cx23885_dev *dev)
  881. {
  882. switch (dev->board) {
  883. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  884. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  885. dev->pci_irqmask &= ~PCI_MSK_IR;
  886. cx_clear(PCI_INT_MSK, PCI_MSK_IR);
  887. cx23888_ir_remove(dev);
  888. dev->sd_ir = NULL;
  889. break;
  890. }
  891. }
  892. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  893. {
  894. switch (dev->board) {
  895. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  896. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  897. if (dev->sd_ir && (dev->pci_irqmask & PCI_MSK_IR))
  898. cx_set(PCI_INT_MSK, PCI_MSK_IR);
  899. break;
  900. }
  901. }
  902. void cx23885_card_setup(struct cx23885_dev *dev)
  903. {
  904. struct cx23885_tsport *ts1 = &dev->ts1;
  905. struct cx23885_tsport *ts2 = &dev->ts2;
  906. static u8 eeprom[256];
  907. if (dev->i2c_bus[0].i2c_rc == 0) {
  908. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  909. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  910. eeprom, sizeof(eeprom));
  911. }
  912. switch (dev->board) {
  913. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  914. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  915. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  916. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  917. if (dev->i2c_bus[0].i2c_rc == 0)
  918. hauppauge_eeprom(dev, eeprom+0x80);
  919. break;
  920. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  921. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  922. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  923. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  924. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  925. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  926. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  927. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  928. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  929. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  930. if (dev->i2c_bus[0].i2c_rc == 0)
  931. hauppauge_eeprom(dev, eeprom+0xc0);
  932. break;
  933. }
  934. switch (dev->board) {
  935. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  936. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  937. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  938. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  939. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  940. /* break omitted intentionally */
  941. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  942. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  943. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  944. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  945. break;
  946. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  947. /* Defaults for VID B - Analog encoder */
  948. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  949. ts1->gen_ctrl_val = 0x10e;
  950. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  951. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  952. /* APB_TSVALERR_POL (active low)*/
  953. ts1->vld_misc_val = 0x2000;
  954. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  955. /* Defaults for VID C */
  956. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  957. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  958. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  959. break;
  960. case CX23885_BOARD_TBS_6920:
  961. ts1->gen_ctrl_val = 0x4; /* Parallel */
  962. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  963. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  964. break;
  965. case CX23885_BOARD_TEVII_S470:
  966. case CX23885_BOARD_DVBWORLD_2005:
  967. ts1->gen_ctrl_val = 0x5; /* Parallel */
  968. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  969. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  970. break;
  971. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  972. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  973. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  974. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  975. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  976. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  977. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  978. break;
  979. case CX23885_BOARD_MYGICA_X8506:
  980. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  981. ts1->gen_ctrl_val = 0x5; /* Parallel */
  982. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  983. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  984. break;
  985. case CX23885_BOARD_MYGICA_X8558PRO:
  986. ts1->gen_ctrl_val = 0x5; /* Parallel */
  987. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  988. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  989. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  990. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  991. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  992. break;
  993. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  994. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  995. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  996. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  997. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  998. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  999. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1000. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1001. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1002. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1003. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1004. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1005. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1006. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1007. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1008. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1009. default:
  1010. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1011. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1012. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1013. }
  1014. /* Certain boards support analog, or require the avcore to be
  1015. * loaded, ensure this happens.
  1016. */
  1017. switch (dev->board) {
  1018. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1019. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1020. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1021. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1022. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1023. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1024. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1025. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1026. case CX23885_BOARD_MYGICA_X8506:
  1027. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1028. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1029. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1030. &dev->i2c_bus[2].i2c_adap,
  1031. "cx25840", "cx25840", 0x88 >> 1, NULL);
  1032. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1033. break;
  1034. }
  1035. /* AUX-PLL 27MHz CLK */
  1036. switch (dev->board) {
  1037. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1038. netup_initialize(dev);
  1039. break;
  1040. }
  1041. }
  1042. /* ------------------------------------------------------------------ */