head.S 7.0 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/head.S
  3. * Based on:
  4. * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
  5. *
  6. * Created: 1998
  7. * Description: bf533 startup file
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/linkage.h>
  30. #include <linux/init.h>
  31. #include <asm/blackfin.h>
  32. #include <asm/trace.h>
  33. #ifdef CONFIG_BFIN_KERNEL_CLOCK
  34. #include <asm/mach-common/clocks.h>
  35. #include <asm/mach/mem_init.h>
  36. #endif
  37. .extern ___bss_stop
  38. .extern ___bss_start
  39. .extern _bf53x_relocate_l1_mem
  40. #define INITIAL_STACK 0xFFB01000
  41. __INIT
  42. ENTRY(__start)
  43. /* R0: argument of command line string, passed from uboot, save it */
  44. R7 = R0;
  45. /* Enable Cycle Counter and Nesting Of Interrupts */
  46. #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
  47. R0 = SYSCFG_SNEN;
  48. #else
  49. R0 = SYSCFG_SNEN | SYSCFG_CCEN;
  50. #endif
  51. SYSCFG = R0;
  52. R0 = 0;
  53. /* Clear Out All the data and pointer Registers */
  54. R1 = R0;
  55. R2 = R0;
  56. R3 = R0;
  57. R4 = R0;
  58. R5 = R0;
  59. R6 = R0;
  60. P0 = R0;
  61. P1 = R0;
  62. P2 = R0;
  63. P3 = R0;
  64. P4 = R0;
  65. P5 = R0;
  66. LC0 = r0;
  67. LC1 = r0;
  68. L0 = r0;
  69. L1 = r0;
  70. L2 = r0;
  71. L3 = r0;
  72. /* Clear Out All the DAG Registers */
  73. B0 = r0;
  74. B1 = r0;
  75. B2 = r0;
  76. B3 = r0;
  77. I0 = r0;
  78. I1 = r0;
  79. I2 = r0;
  80. I3 = r0;
  81. M0 = r0;
  82. M1 = r0;
  83. M2 = r0;
  84. M3 = r0;
  85. trace_buffer_init(p0,r0);
  86. P0 = R1;
  87. R0 = R1;
  88. p0.h = hi(FIO_MASKA_C);
  89. p0.l = lo(FIO_MASKA_C);
  90. r0 = 0xFFFF(Z);
  91. w[p0] = r0.L; /* Disable all interrupts */
  92. ssync;
  93. p0.h = hi(FIO_MASKB_C);
  94. p0.l = lo(FIO_MASKB_C);
  95. r0 = 0xFFFF(Z);
  96. w[p0] = r0.L; /* Disable all interrupts */
  97. ssync;
  98. /* Turn off the icache */
  99. p0.l = LO(IMEM_CONTROL);
  100. p0.h = HI(IMEM_CONTROL);
  101. R1 = [p0];
  102. R0 = ~ENICPLB;
  103. R0 = R0 & R1;
  104. [p0] = R0;
  105. SSYNC;
  106. /* Turn off the dcache */
  107. p0.l = LO(DMEM_CONTROL);
  108. p0.h = HI(DMEM_CONTROL);
  109. R1 = [p0];
  110. R0 = ~ENDCPLB;
  111. R0 = R0 & R1;
  112. [p0] = R0;
  113. SSYNC;
  114. /* Initialise UART - when booting from u-boot, the UART is not disabled
  115. * so if we dont initalize here, our serial console gets hosed */
  116. p0.h = hi(BFIN_UART_LCR);
  117. p0.l = lo(BFIN_UART_LCR);
  118. r0 = 0x0(Z);
  119. w[p0] = r0.L; /* To enable DLL writes */
  120. ssync;
  121. p0.h = hi(BFIN_UART_DLL);
  122. p0.l = lo(BFIN_UART_DLL);
  123. r0 = 0x0(Z);
  124. w[p0] = r0.L;
  125. ssync;
  126. p0.h = hi(BFIN_UART_DLH);
  127. p0.l = lo(BFIN_UART_DLH);
  128. r0 = 0x00(Z);
  129. w[p0] = r0.L;
  130. ssync;
  131. p0.h = hi(BFIN_UART_GCTL);
  132. p0.l = lo(BFIN_UART_GCTL);
  133. r0 = 0x0(Z);
  134. w[p0] = r0.L; /* To enable UART clock */
  135. ssync;
  136. /* Initialize stack pointer */
  137. sp.l = lo(INITIAL_STACK);
  138. sp.h = hi(INITIAL_STACK);
  139. fp = sp;
  140. usp = sp;
  141. #ifdef CONFIG_EARLY_PRINTK
  142. SP += -12;
  143. call _init_early_exception_vectors;
  144. SP += 12;
  145. #endif
  146. /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
  147. call _bf53x_relocate_l1_mem;
  148. #ifdef CONFIG_BFIN_KERNEL_CLOCK
  149. call _start_dma_code;
  150. #endif
  151. /* Code for initializing Async memory banks */
  152. p2.h = hi(EBIU_AMBCTL1);
  153. p2.l = lo(EBIU_AMBCTL1);
  154. r0.h = hi(AMBCTL1VAL);
  155. r0.l = lo(AMBCTL1VAL);
  156. [p2] = r0;
  157. ssync;
  158. p2.h = hi(EBIU_AMBCTL0);
  159. p2.l = lo(EBIU_AMBCTL0);
  160. r0.h = hi(AMBCTL0VAL);
  161. r0.l = lo(AMBCTL0VAL);
  162. [p2] = r0;
  163. ssync;
  164. p2.h = hi(EBIU_AMGCTL);
  165. p2.l = lo(EBIU_AMGCTL);
  166. r0 = AMGCTLVAL;
  167. w[p2] = r0;
  168. ssync;
  169. /* This section keeps the processor in supervisor mode
  170. * during kernel boot. Switches to user mode at end of boot.
  171. * See page 3-9 of Hardware Reference manual for documentation.
  172. */
  173. /* EVT15 = _real_start */
  174. p0.l = lo(EVT15);
  175. p0.h = hi(EVT15);
  176. p1.l = _real_start;
  177. p1.h = _real_start;
  178. [p0] = p1;
  179. csync;
  180. p0.l = lo(IMASK);
  181. p0.h = hi(IMASK);
  182. p1.l = IMASK_IVG15;
  183. p1.h = 0x0;
  184. [p0] = p1;
  185. csync;
  186. raise 15;
  187. p0.l = .LWAIT_HERE;
  188. p0.h = .LWAIT_HERE;
  189. reti = p0;
  190. #if ANOMALY_05000281
  191. nop; nop; nop;
  192. #endif
  193. rti;
  194. .LWAIT_HERE:
  195. jump .LWAIT_HERE;
  196. ENDPROC(__start)
  197. __FINIT
  198. .section .l1.text
  199. #ifdef CONFIG_BFIN_KERNEL_CLOCK
  200. ENTRY(_start_dma_code)
  201. p0.h = hi(SIC_IWR);
  202. p0.l = lo(SIC_IWR);
  203. r0.l = 0x1;
  204. r0.h = 0x0;
  205. [p0] = r0;
  206. SSYNC;
  207. /*
  208. * Set PLL_CTL
  209. * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
  210. * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
  211. * - [7] = output delay (add 200ps of delay to mem signals)
  212. * - [6] = input delay (add 200ps of input delay to mem signals)
  213. * - [5] = PDWN : 1=All Clocks off
  214. * - [3] = STOPCK : 1=Core Clock off
  215. * - [1] = PLL_OFF : 1=Disable Power to PLL
  216. * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
  217. * all other bits set to zero
  218. */
  219. p0.h = hi(PLL_LOCKCNT);
  220. p0.l = lo(PLL_LOCKCNT);
  221. r0 = 0x300(Z);
  222. w[p0] = r0.l;
  223. ssync;
  224. P2.H = hi(EBIU_SDGCTL);
  225. P2.L = lo(EBIU_SDGCTL);
  226. R0 = [P2];
  227. BITSET (R0, 24);
  228. [P2] = R0;
  229. SSYNC;
  230. r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
  231. r0 = r0 << 9; /* Shift it over, */
  232. r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
  233. r0 = r1 | r0;
  234. r1 = PLL_BYPASS; /* Bypass the PLL? */
  235. r1 = r1 << 8; /* Shift it over */
  236. r0 = r1 | r0; /* add them all together */
  237. p0.h = hi(PLL_CTL);
  238. p0.l = lo(PLL_CTL); /* Load the address */
  239. cli r2; /* Disable interrupts */
  240. ssync;
  241. w[p0] = r0.l; /* Set the value */
  242. idle; /* Wait for the PLL to stablize */
  243. sti r2; /* Enable interrupts */
  244. .Lcheck_again:
  245. p0.h = hi(PLL_STAT);
  246. p0.l = lo(PLL_STAT);
  247. R0 = W[P0](Z);
  248. CC = BITTST(R0,5);
  249. if ! CC jump .Lcheck_again;
  250. /* Configure SCLK & CCLK Dividers */
  251. r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
  252. p0.h = hi(PLL_DIV);
  253. p0.l = lo(PLL_DIV);
  254. w[p0] = r0.l;
  255. ssync;
  256. p0.l = lo(EBIU_SDRRC);
  257. p0.h = hi(EBIU_SDRRC);
  258. r0 = mem_SDRRC;
  259. w[p0] = r0.l;
  260. ssync;
  261. P2.H = hi(EBIU_SDGCTL);
  262. P2.L = lo(EBIU_SDGCTL);
  263. R0 = [P2];
  264. BITCLR (R0, 24);
  265. p0.h = hi(EBIU_SDSTAT);
  266. p0.l = lo(EBIU_SDSTAT);
  267. r2.l = w[p0];
  268. cc = bittst(r2,3);
  269. if !cc jump .Lskip;
  270. NOP;
  271. BITSET (R0, 23);
  272. .Lskip:
  273. [P2] = R0;
  274. SSYNC;
  275. R0.L = lo(mem_SDGCTL);
  276. R0.H = hi(mem_SDGCTL);
  277. R1 = [p2];
  278. R1 = R1 | R0;
  279. [P2] = R1;
  280. SSYNC;
  281. p0.h = hi(SIC_IWR);
  282. p0.l = lo(SIC_IWR);
  283. r0.l = lo(IWR_ENABLE_ALL);
  284. r0.h = hi(IWR_ENABLE_ALL);
  285. [p0] = r0;
  286. SSYNC;
  287. RTS;
  288. ENDPROC(_start_dma_code)
  289. #endif /* CONFIG_BFIN_KERNEL_CLOCK */