qla_os.c 108 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO|S_IRUSR);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO|S_IRUSR);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO|S_IRUSR);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO|S_IRUSR);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO|S_IRUSR);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO|S_IRUSR);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO|S_IRUSR);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO|S_IRUSR);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO|S_IRUSR);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO|S_IRUSR);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO|S_IRUSR);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO|S_IRUSR);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xdontresethba;
  126. module_param(ql2xdontresethba, int, S_IRUGO|S_IRUSR);
  127. MODULE_PARM_DESC(ql2xdontresethba,
  128. "Option to specify reset behaviour\n"
  129. " 0 (Default) -- Reset on failure.\n"
  130. " 1 -- Do not reset on failure.\n");
  131. int ql2xtargetreset = 1;
  132. module_param(ql2xtargetreset, int, S_IRUGO|S_IRUSR);
  133. MODULE_PARM_DESC(ql2xtargetreset,
  134. "Enable target reset."
  135. "Default is 1 - use hw defaults.");
  136. int ql2xgffidenable;
  137. module_param(ql2xgffidenable, int, S_IRUGO|S_IRUSR);
  138. MODULE_PARM_DESC(ql2xgffidenable,
  139. "Enables GFF_ID checks of port type. "
  140. "Default is 0 - Do not use GFF_ID information.");
  141. int ql2xasynctmfenable;
  142. module_param(ql2xasynctmfenable, int, S_IRUGO|S_IRUSR);
  143. MODULE_PARM_DESC(ql2xasynctmfenable,
  144. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  145. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  146. /*
  147. * SCSI host template entry points
  148. */
  149. static int qla2xxx_slave_configure(struct scsi_device * device);
  150. static int qla2xxx_slave_alloc(struct scsi_device *);
  151. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  152. static void qla2xxx_scan_start(struct Scsi_Host *);
  153. static void qla2xxx_slave_destroy(struct scsi_device *);
  154. static int qla2xxx_queuecommand(struct scsi_cmnd *cmd,
  155. void (*fn)(struct scsi_cmnd *));
  156. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  157. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  158. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  159. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  160. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  161. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  162. static int qla2x00_change_queue_type(struct scsi_device *, int);
  163. struct scsi_host_template qla2xxx_driver_template = {
  164. .module = THIS_MODULE,
  165. .name = QLA2XXX_DRIVER_NAME,
  166. .queuecommand = qla2xxx_queuecommand,
  167. .eh_abort_handler = qla2xxx_eh_abort,
  168. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  169. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  170. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  171. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  172. .slave_configure = qla2xxx_slave_configure,
  173. .slave_alloc = qla2xxx_slave_alloc,
  174. .slave_destroy = qla2xxx_slave_destroy,
  175. .scan_finished = qla2xxx_scan_finished,
  176. .scan_start = qla2xxx_scan_start,
  177. .change_queue_depth = qla2x00_change_queue_depth,
  178. .change_queue_type = qla2x00_change_queue_type,
  179. .this_id = -1,
  180. .cmd_per_lun = 3,
  181. .use_clustering = ENABLE_CLUSTERING,
  182. .sg_tablesize = SG_ALL,
  183. .max_sectors = 0xFFFF,
  184. .shost_attrs = qla2x00_host_attrs,
  185. };
  186. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  187. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  188. /* TODO Convert to inlines
  189. *
  190. * Timer routines
  191. */
  192. __inline__ void
  193. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  194. {
  195. init_timer(&vha->timer);
  196. vha->timer.expires = jiffies + interval * HZ;
  197. vha->timer.data = (unsigned long)vha;
  198. vha->timer.function = (void (*)(unsigned long))func;
  199. add_timer(&vha->timer);
  200. vha->timer_active = 1;
  201. }
  202. static inline void
  203. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  204. {
  205. /* Currently used for 82XX only. */
  206. if (vha->device_flags & DFLG_DEV_FAILED)
  207. return;
  208. mod_timer(&vha->timer, jiffies + interval * HZ);
  209. }
  210. static __inline__ void
  211. qla2x00_stop_timer(scsi_qla_host_t *vha)
  212. {
  213. del_timer_sync(&vha->timer);
  214. vha->timer_active = 0;
  215. }
  216. static int qla2x00_do_dpc(void *data);
  217. static void qla2x00_rst_aen(scsi_qla_host_t *);
  218. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  219. struct req_que **, struct rsp_que **);
  220. static void qla2x00_mem_free(struct qla_hw_data *);
  221. static void qla2x00_sp_free_dma(srb_t *);
  222. /* -------------------------------------------------------------------------- */
  223. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  224. {
  225. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  226. GFP_KERNEL);
  227. if (!ha->req_q_map) {
  228. qla_printk(KERN_WARNING, ha,
  229. "Unable to allocate memory for request queue ptrs\n");
  230. goto fail_req_map;
  231. }
  232. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  233. GFP_KERNEL);
  234. if (!ha->rsp_q_map) {
  235. qla_printk(KERN_WARNING, ha,
  236. "Unable to allocate memory for response queue ptrs\n");
  237. goto fail_rsp_map;
  238. }
  239. set_bit(0, ha->rsp_qid_map);
  240. set_bit(0, ha->req_qid_map);
  241. return 1;
  242. fail_rsp_map:
  243. kfree(ha->req_q_map);
  244. ha->req_q_map = NULL;
  245. fail_req_map:
  246. return -ENOMEM;
  247. }
  248. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  249. {
  250. if (req && req->ring)
  251. dma_free_coherent(&ha->pdev->dev,
  252. (req->length + 1) * sizeof(request_t),
  253. req->ring, req->dma);
  254. kfree(req);
  255. req = NULL;
  256. }
  257. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  258. {
  259. if (rsp && rsp->ring)
  260. dma_free_coherent(&ha->pdev->dev,
  261. (rsp->length + 1) * sizeof(response_t),
  262. rsp->ring, rsp->dma);
  263. kfree(rsp);
  264. rsp = NULL;
  265. }
  266. static void qla2x00_free_queues(struct qla_hw_data *ha)
  267. {
  268. struct req_que *req;
  269. struct rsp_que *rsp;
  270. int cnt;
  271. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  272. req = ha->req_q_map[cnt];
  273. qla2x00_free_req_que(ha, req);
  274. }
  275. kfree(ha->req_q_map);
  276. ha->req_q_map = NULL;
  277. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  278. rsp = ha->rsp_q_map[cnt];
  279. qla2x00_free_rsp_que(ha, rsp);
  280. }
  281. kfree(ha->rsp_q_map);
  282. ha->rsp_q_map = NULL;
  283. }
  284. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  285. {
  286. uint16_t options = 0;
  287. int ques, req, ret;
  288. struct qla_hw_data *ha = vha->hw;
  289. if (!(ha->fw_attributes & BIT_6)) {
  290. qla_printk(KERN_INFO, ha,
  291. "Firmware is not multi-queue capable\n");
  292. goto fail;
  293. }
  294. if (ql2xmultique_tag) {
  295. /* create a request queue for IO */
  296. options |= BIT_7;
  297. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  298. QLA_DEFAULT_QUE_QOS);
  299. if (!req) {
  300. qla_printk(KERN_WARNING, ha,
  301. "Can't create request queue\n");
  302. goto fail;
  303. }
  304. ha->wq = create_workqueue("qla2xxx_wq");
  305. vha->req = ha->req_q_map[req];
  306. options |= BIT_1;
  307. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  308. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  309. if (!ret) {
  310. qla_printk(KERN_WARNING, ha,
  311. "Response Queue create failed\n");
  312. goto fail2;
  313. }
  314. }
  315. ha->flags.cpu_affinity_enabled = 1;
  316. DEBUG2(qla_printk(KERN_INFO, ha,
  317. "CPU affinity mode enabled, no. of response"
  318. " queues:%d, no. of request queues:%d\n",
  319. ha->max_rsp_queues, ha->max_req_queues));
  320. }
  321. return 0;
  322. fail2:
  323. qla25xx_delete_queues(vha);
  324. destroy_workqueue(ha->wq);
  325. ha->wq = NULL;
  326. fail:
  327. ha->mqenable = 0;
  328. kfree(ha->req_q_map);
  329. kfree(ha->rsp_q_map);
  330. ha->max_req_queues = ha->max_rsp_queues = 1;
  331. return 1;
  332. }
  333. static char *
  334. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  335. {
  336. struct qla_hw_data *ha = vha->hw;
  337. static char *pci_bus_modes[] = {
  338. "33", "66", "100", "133",
  339. };
  340. uint16_t pci_bus;
  341. strcpy(str, "PCI");
  342. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  343. if (pci_bus) {
  344. strcat(str, "-X (");
  345. strcat(str, pci_bus_modes[pci_bus]);
  346. } else {
  347. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  348. strcat(str, " (");
  349. strcat(str, pci_bus_modes[pci_bus]);
  350. }
  351. strcat(str, " MHz)");
  352. return (str);
  353. }
  354. static char *
  355. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  356. {
  357. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  358. struct qla_hw_data *ha = vha->hw;
  359. uint32_t pci_bus;
  360. int pcie_reg;
  361. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  362. if (pcie_reg) {
  363. char lwstr[6];
  364. uint16_t pcie_lstat, lspeed, lwidth;
  365. pcie_reg += 0x12;
  366. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  367. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  368. lwidth = (pcie_lstat &
  369. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  370. strcpy(str, "PCIe (");
  371. if (lspeed == 1)
  372. strcat(str, "2.5GT/s ");
  373. else if (lspeed == 2)
  374. strcat(str, "5.0GT/s ");
  375. else
  376. strcat(str, "<unknown> ");
  377. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  378. strcat(str, lwstr);
  379. return str;
  380. }
  381. strcpy(str, "PCI");
  382. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  383. if (pci_bus == 0 || pci_bus == 8) {
  384. strcat(str, " (");
  385. strcat(str, pci_bus_modes[pci_bus >> 3]);
  386. } else {
  387. strcat(str, "-X ");
  388. if (pci_bus & BIT_2)
  389. strcat(str, "Mode 2");
  390. else
  391. strcat(str, "Mode 1");
  392. strcat(str, " (");
  393. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  394. }
  395. strcat(str, " MHz)");
  396. return str;
  397. }
  398. static char *
  399. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  400. {
  401. char un_str[10];
  402. struct qla_hw_data *ha = vha->hw;
  403. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  404. ha->fw_minor_version,
  405. ha->fw_subminor_version);
  406. if (ha->fw_attributes & BIT_9) {
  407. strcat(str, "FLX");
  408. return (str);
  409. }
  410. switch (ha->fw_attributes & 0xFF) {
  411. case 0x7:
  412. strcat(str, "EF");
  413. break;
  414. case 0x17:
  415. strcat(str, "TP");
  416. break;
  417. case 0x37:
  418. strcat(str, "IP");
  419. break;
  420. case 0x77:
  421. strcat(str, "VI");
  422. break;
  423. default:
  424. sprintf(un_str, "(%x)", ha->fw_attributes);
  425. strcat(str, un_str);
  426. break;
  427. }
  428. if (ha->fw_attributes & 0x100)
  429. strcat(str, "X");
  430. return (str);
  431. }
  432. static char *
  433. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  434. {
  435. struct qla_hw_data *ha = vha->hw;
  436. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  437. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  438. return str;
  439. }
  440. static inline srb_t *
  441. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  442. struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  443. {
  444. srb_t *sp;
  445. struct qla_hw_data *ha = vha->hw;
  446. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  447. if (!sp)
  448. return sp;
  449. atomic_set(&sp->ref_count, 1);
  450. sp->fcport = fcport;
  451. sp->cmd = cmd;
  452. sp->flags = 0;
  453. CMD_SP(cmd) = (void *)sp;
  454. cmd->scsi_done = done;
  455. sp->ctx = NULL;
  456. return sp;
  457. }
  458. static int
  459. qla2xxx_queuecommand(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
  460. {
  461. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  462. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  463. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  464. struct qla_hw_data *ha = vha->hw;
  465. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  466. srb_t *sp;
  467. int rval;
  468. if (ha->flags.eeh_busy) {
  469. if (ha->flags.pci_channel_io_perm_failure)
  470. cmd->result = DID_NO_CONNECT << 16;
  471. else
  472. cmd->result = DID_REQUEUE << 16;
  473. goto qc24_fail_command;
  474. }
  475. rval = fc_remote_port_chkready(rport);
  476. if (rval) {
  477. cmd->result = rval;
  478. goto qc24_fail_command;
  479. }
  480. /* Close window on fcport/rport state-transitioning. */
  481. if (fcport->drport)
  482. goto qc24_target_busy;
  483. if (!vha->flags.difdix_supported &&
  484. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  485. DEBUG2(qla_printk(KERN_ERR, ha,
  486. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  487. cmd->cmnd[0]));
  488. cmd->result = DID_NO_CONNECT << 16;
  489. goto qc24_fail_command;
  490. }
  491. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  492. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  493. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  494. cmd->result = DID_NO_CONNECT << 16;
  495. goto qc24_fail_command;
  496. }
  497. goto qc24_target_busy;
  498. }
  499. spin_unlock_irq(vha->host->host_lock);
  500. sp = qla2x00_get_new_sp(base_vha, fcport, cmd, done);
  501. if (!sp)
  502. goto qc24_host_busy_lock;
  503. rval = ha->isp_ops->start_scsi(sp);
  504. if (rval != QLA_SUCCESS)
  505. goto qc24_host_busy_free_sp;
  506. spin_lock_irq(vha->host->host_lock);
  507. return 0;
  508. qc24_host_busy_free_sp:
  509. qla2x00_sp_free_dma(sp);
  510. mempool_free(sp, ha->srb_mempool);
  511. qc24_host_busy_lock:
  512. spin_lock_irq(vha->host->host_lock);
  513. return SCSI_MLQUEUE_HOST_BUSY;
  514. qc24_target_busy:
  515. return SCSI_MLQUEUE_TARGET_BUSY;
  516. qc24_fail_command:
  517. done(cmd);
  518. return 0;
  519. }
  520. /*
  521. * qla2x00_eh_wait_on_command
  522. * Waits for the command to be returned by the Firmware for some
  523. * max time.
  524. *
  525. * Input:
  526. * cmd = Scsi Command to wait on.
  527. *
  528. * Return:
  529. * Not Found : 0
  530. * Found : 1
  531. */
  532. static int
  533. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  534. {
  535. #define ABORT_POLLING_PERIOD 1000
  536. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  537. unsigned long wait_iter = ABORT_WAIT_ITER;
  538. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  539. struct qla_hw_data *ha = vha->hw;
  540. int ret = QLA_SUCCESS;
  541. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  542. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  543. return ret;
  544. }
  545. while (CMD_SP(cmd) && wait_iter--) {
  546. msleep(ABORT_POLLING_PERIOD);
  547. }
  548. if (CMD_SP(cmd))
  549. ret = QLA_FUNCTION_FAILED;
  550. return ret;
  551. }
  552. /*
  553. * qla2x00_wait_for_hba_online
  554. * Wait till the HBA is online after going through
  555. * <= MAX_RETRIES_OF_ISP_ABORT or
  556. * finally HBA is disabled ie marked offline
  557. *
  558. * Input:
  559. * ha - pointer to host adapter structure
  560. *
  561. * Note:
  562. * Does context switching-Release SPIN_LOCK
  563. * (if any) before calling this routine.
  564. *
  565. * Return:
  566. * Success (Adapter is online) : 0
  567. * Failed (Adapter is offline/disabled) : 1
  568. */
  569. int
  570. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  571. {
  572. int return_status;
  573. unsigned long wait_online;
  574. struct qla_hw_data *ha = vha->hw;
  575. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  576. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  577. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  578. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  579. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  580. ha->dpc_active) && time_before(jiffies, wait_online)) {
  581. msleep(1000);
  582. }
  583. if (base_vha->flags.online)
  584. return_status = QLA_SUCCESS;
  585. else
  586. return_status = QLA_FUNCTION_FAILED;
  587. return (return_status);
  588. }
  589. /*
  590. * qla2x00_wait_for_reset_ready
  591. * Wait till the HBA is online after going through
  592. * <= MAX_RETRIES_OF_ISP_ABORT or
  593. * finally HBA is disabled ie marked offline or flash
  594. * operations are in progress.
  595. *
  596. * Input:
  597. * ha - pointer to host adapter structure
  598. *
  599. * Note:
  600. * Does context switching-Release SPIN_LOCK
  601. * (if any) before calling this routine.
  602. *
  603. * Return:
  604. * Success (Adapter is online/no flash ops) : 0
  605. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  606. */
  607. static int
  608. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  609. {
  610. int return_status;
  611. unsigned long wait_online;
  612. struct qla_hw_data *ha = vha->hw;
  613. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  614. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  615. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  616. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  617. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  618. ha->optrom_state != QLA_SWAITING ||
  619. ha->dpc_active) && time_before(jiffies, wait_online))
  620. msleep(1000);
  621. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  622. return_status = QLA_SUCCESS;
  623. else
  624. return_status = QLA_FUNCTION_FAILED;
  625. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  626. return return_status;
  627. }
  628. int
  629. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  630. {
  631. int return_status;
  632. unsigned long wait_reset;
  633. struct qla_hw_data *ha = vha->hw;
  634. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  635. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  636. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  637. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  638. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  639. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  640. msleep(1000);
  641. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  642. ha->flags.chip_reset_done)
  643. break;
  644. }
  645. if (ha->flags.chip_reset_done)
  646. return_status = QLA_SUCCESS;
  647. else
  648. return_status = QLA_FUNCTION_FAILED;
  649. return return_status;
  650. }
  651. /*
  652. * qla2x00_wait_for_loop_ready
  653. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  654. * to be in LOOP_READY state.
  655. * Input:
  656. * ha - pointer to host adapter structure
  657. *
  658. * Note:
  659. * Does context switching-Release SPIN_LOCK
  660. * (if any) before calling this routine.
  661. *
  662. *
  663. * Return:
  664. * Success (LOOP_READY) : 0
  665. * Failed (LOOP_NOT_READY) : 1
  666. */
  667. static inline int
  668. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  669. {
  670. int return_status = QLA_SUCCESS;
  671. unsigned long loop_timeout ;
  672. struct qla_hw_data *ha = vha->hw;
  673. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  674. /* wait for 5 min at the max for loop to be ready */
  675. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  676. while ((!atomic_read(&base_vha->loop_down_timer) &&
  677. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  678. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  679. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  680. return_status = QLA_FUNCTION_FAILED;
  681. break;
  682. }
  683. msleep(1000);
  684. if (time_after_eq(jiffies, loop_timeout)) {
  685. return_status = QLA_FUNCTION_FAILED;
  686. break;
  687. }
  688. }
  689. return (return_status);
  690. }
  691. static void
  692. sp_get(struct srb *sp)
  693. {
  694. atomic_inc(&sp->ref_count);
  695. }
  696. /**************************************************************************
  697. * qla2xxx_eh_abort
  698. *
  699. * Description:
  700. * The abort function will abort the specified command.
  701. *
  702. * Input:
  703. * cmd = Linux SCSI command packet to be aborted.
  704. *
  705. * Returns:
  706. * Either SUCCESS or FAILED.
  707. *
  708. * Note:
  709. * Only return FAILED if command not returned by firmware.
  710. **************************************************************************/
  711. static int
  712. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  713. {
  714. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  715. srb_t *sp;
  716. int ret, i;
  717. unsigned int id, lun;
  718. unsigned long flags;
  719. int wait = 0;
  720. struct qla_hw_data *ha = vha->hw;
  721. struct req_que *req = vha->req;
  722. srb_t *spt;
  723. int got_ref = 0;
  724. fc_block_scsi_eh(cmd);
  725. if (!CMD_SP(cmd))
  726. return SUCCESS;
  727. ret = SUCCESS;
  728. id = cmd->device->id;
  729. lun = cmd->device->lun;
  730. spt = (srb_t *) CMD_SP(cmd);
  731. if (!spt)
  732. return SUCCESS;
  733. /* Check active list for command command. */
  734. spin_lock_irqsave(&ha->hardware_lock, flags);
  735. for (i = 1; i < MAX_OUTSTANDING_COMMANDS; i++) {
  736. sp = req->outstanding_cmds[i];
  737. if (sp == NULL)
  738. continue;
  739. if ((sp->ctx) && !(sp->flags & SRB_FCP_CMND_DMA_VALID) &&
  740. !IS_PROT_IO(sp))
  741. continue;
  742. if (sp->cmd != cmd)
  743. continue;
  744. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  745. __func__, vha->host_no, sp));
  746. /* Get a reference to the sp and drop the lock.*/
  747. sp_get(sp);
  748. got_ref++;
  749. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  750. if (ha->isp_ops->abort_command(sp)) {
  751. DEBUG2(printk("%s(%ld): abort_command "
  752. "mbx failed.\n", __func__, vha->host_no));
  753. ret = FAILED;
  754. } else {
  755. DEBUG3(printk("%s(%ld): abort_command "
  756. "mbx success.\n", __func__, vha->host_no));
  757. wait = 1;
  758. }
  759. spin_lock_irqsave(&ha->hardware_lock, flags);
  760. break;
  761. }
  762. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  763. /* Wait for the command to be returned. */
  764. if (wait) {
  765. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  766. qla_printk(KERN_ERR, ha,
  767. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  768. vha->host_no, id, lun, ret);
  769. ret = FAILED;
  770. }
  771. }
  772. if (got_ref)
  773. qla2x00_sp_compl(ha, sp);
  774. qla_printk(KERN_INFO, ha,
  775. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  776. vha->host_no, id, lun, wait, ret);
  777. return ret;
  778. }
  779. int
  780. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  781. unsigned int l, enum nexus_wait_type type)
  782. {
  783. int cnt, match, status;
  784. unsigned long flags;
  785. struct qla_hw_data *ha = vha->hw;
  786. struct req_que *req;
  787. srb_t *sp;
  788. status = QLA_SUCCESS;
  789. spin_lock_irqsave(&ha->hardware_lock, flags);
  790. req = vha->req;
  791. for (cnt = 1; status == QLA_SUCCESS &&
  792. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  793. sp = req->outstanding_cmds[cnt];
  794. if (!sp)
  795. continue;
  796. if ((sp->ctx) && !IS_PROT_IO(sp))
  797. continue;
  798. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  799. continue;
  800. match = 0;
  801. switch (type) {
  802. case WAIT_HOST:
  803. match = 1;
  804. break;
  805. case WAIT_TARGET:
  806. match = sp->cmd->device->id == t;
  807. break;
  808. case WAIT_LUN:
  809. match = (sp->cmd->device->id == t &&
  810. sp->cmd->device->lun == l);
  811. break;
  812. }
  813. if (!match)
  814. continue;
  815. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  816. status = qla2x00_eh_wait_on_command(sp->cmd);
  817. spin_lock_irqsave(&ha->hardware_lock, flags);
  818. }
  819. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  820. return status;
  821. }
  822. static char *reset_errors[] = {
  823. "HBA not online",
  824. "HBA not ready",
  825. "Task management failed",
  826. "Waiting for command completions",
  827. };
  828. static int
  829. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  830. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  831. {
  832. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  833. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  834. int err;
  835. fc_block_scsi_eh(cmd);
  836. if (!fcport)
  837. return FAILED;
  838. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  839. vha->host_no, cmd->device->id, cmd->device->lun, name);
  840. err = 0;
  841. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  842. goto eh_reset_failed;
  843. err = 1;
  844. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  845. goto eh_reset_failed;
  846. err = 2;
  847. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  848. != QLA_SUCCESS)
  849. goto eh_reset_failed;
  850. err = 3;
  851. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  852. cmd->device->lun, type) != QLA_SUCCESS)
  853. goto eh_reset_failed;
  854. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  855. vha->host_no, cmd->device->id, cmd->device->lun, name);
  856. return SUCCESS;
  857. eh_reset_failed:
  858. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  859. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  860. reset_errors[err]);
  861. return FAILED;
  862. }
  863. static int
  864. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  865. {
  866. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  867. struct qla_hw_data *ha = vha->hw;
  868. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  869. ha->isp_ops->lun_reset);
  870. }
  871. static int
  872. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  873. {
  874. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  875. struct qla_hw_data *ha = vha->hw;
  876. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  877. ha->isp_ops->target_reset);
  878. }
  879. /**************************************************************************
  880. * qla2xxx_eh_bus_reset
  881. *
  882. * Description:
  883. * The bus reset function will reset the bus and abort any executing
  884. * commands.
  885. *
  886. * Input:
  887. * cmd = Linux SCSI command packet of the command that cause the
  888. * bus reset.
  889. *
  890. * Returns:
  891. * SUCCESS/FAILURE (defined as macro in scsi.h).
  892. *
  893. **************************************************************************/
  894. static int
  895. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  896. {
  897. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  898. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  899. int ret = FAILED;
  900. unsigned int id, lun;
  901. fc_block_scsi_eh(cmd);
  902. id = cmd->device->id;
  903. lun = cmd->device->lun;
  904. if (!fcport)
  905. return ret;
  906. qla_printk(KERN_INFO, vha->hw,
  907. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  908. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  909. DEBUG2(printk("%s failed:board disabled\n",__func__));
  910. goto eh_bus_reset_done;
  911. }
  912. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  913. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  914. ret = SUCCESS;
  915. }
  916. if (ret == FAILED)
  917. goto eh_bus_reset_done;
  918. /* Flush outstanding commands. */
  919. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  920. QLA_SUCCESS)
  921. ret = FAILED;
  922. eh_bus_reset_done:
  923. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  924. (ret == FAILED) ? "failed" : "succeded");
  925. return ret;
  926. }
  927. /**************************************************************************
  928. * qla2xxx_eh_host_reset
  929. *
  930. * Description:
  931. * The reset function will reset the Adapter.
  932. *
  933. * Input:
  934. * cmd = Linux SCSI command packet of the command that cause the
  935. * adapter reset.
  936. *
  937. * Returns:
  938. * Either SUCCESS or FAILED.
  939. *
  940. * Note:
  941. **************************************************************************/
  942. static int
  943. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  944. {
  945. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  946. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  947. struct qla_hw_data *ha = vha->hw;
  948. int ret = FAILED;
  949. unsigned int id, lun;
  950. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  951. fc_block_scsi_eh(cmd);
  952. id = cmd->device->id;
  953. lun = cmd->device->lun;
  954. if (!fcport)
  955. return ret;
  956. qla_printk(KERN_INFO, ha,
  957. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  958. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  959. goto eh_host_reset_lock;
  960. /*
  961. * Fixme-may be dpc thread is active and processing
  962. * loop_resync,so wait a while for it to
  963. * be completed and then issue big hammer.Otherwise
  964. * it may cause I/O failure as big hammer marks the
  965. * devices as lost kicking of the port_down_timer
  966. * while dpc is stuck for the mailbox to complete.
  967. */
  968. qla2x00_wait_for_loop_ready(vha);
  969. if (vha != base_vha) {
  970. if (qla2x00_vp_abort_isp(vha))
  971. goto eh_host_reset_lock;
  972. } else {
  973. if (IS_QLA82XX(vha->hw)) {
  974. if (!qla82xx_fcoe_ctx_reset(vha)) {
  975. /* Ctx reset success */
  976. ret = SUCCESS;
  977. goto eh_host_reset_lock;
  978. }
  979. /* fall thru if ctx reset failed */
  980. }
  981. if (ha->wq)
  982. flush_workqueue(ha->wq);
  983. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  984. if (ha->isp_ops->abort_isp(base_vha)) {
  985. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  986. /* failed. schedule dpc to try */
  987. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  988. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  989. goto eh_host_reset_lock;
  990. }
  991. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  992. }
  993. /* Waiting for command to be returned to OS.*/
  994. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  995. QLA_SUCCESS)
  996. ret = SUCCESS;
  997. eh_host_reset_lock:
  998. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  999. (ret == FAILED) ? "failed" : "succeded");
  1000. return ret;
  1001. }
  1002. /*
  1003. * qla2x00_loop_reset
  1004. * Issue loop reset.
  1005. *
  1006. * Input:
  1007. * ha = adapter block pointer.
  1008. *
  1009. * Returns:
  1010. * 0 = success
  1011. */
  1012. int
  1013. qla2x00_loop_reset(scsi_qla_host_t *vha)
  1014. {
  1015. int ret;
  1016. struct fc_port *fcport;
  1017. struct qla_hw_data *ha = vha->hw;
  1018. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  1019. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1020. if (fcport->port_type != FCT_TARGET)
  1021. continue;
  1022. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  1023. if (ret != QLA_SUCCESS) {
  1024. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  1025. "target_reset=%d d_id=%x.\n", __func__,
  1026. vha->host_no, ret, fcport->d_id.b24));
  1027. }
  1028. }
  1029. }
  1030. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1031. ret = qla2x00_full_login_lip(vha);
  1032. if (ret != QLA_SUCCESS) {
  1033. DEBUG2_3(printk("%s(%ld): failed: "
  1034. "full_login_lip=%d.\n", __func__, vha->host_no,
  1035. ret));
  1036. }
  1037. atomic_set(&vha->loop_state, LOOP_DOWN);
  1038. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1039. qla2x00_mark_all_devices_lost(vha, 0);
  1040. qla2x00_wait_for_loop_ready(vha);
  1041. }
  1042. if (ha->flags.enable_lip_reset) {
  1043. ret = qla2x00_lip_reset(vha);
  1044. if (ret != QLA_SUCCESS) {
  1045. DEBUG2_3(printk("%s(%ld): failed: "
  1046. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1047. } else
  1048. qla2x00_wait_for_loop_ready(vha);
  1049. }
  1050. /* Issue marker command only when we are going to start the I/O */
  1051. vha->marker_needed = 1;
  1052. return QLA_SUCCESS;
  1053. }
  1054. void
  1055. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1056. {
  1057. int que, cnt;
  1058. unsigned long flags;
  1059. srb_t *sp;
  1060. struct srb_ctx *ctx;
  1061. struct qla_hw_data *ha = vha->hw;
  1062. struct req_que *req;
  1063. spin_lock_irqsave(&ha->hardware_lock, flags);
  1064. for (que = 0; que < ha->max_req_queues; que++) {
  1065. req = ha->req_q_map[que];
  1066. if (!req)
  1067. continue;
  1068. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1069. sp = req->outstanding_cmds[cnt];
  1070. if (sp) {
  1071. req->outstanding_cmds[cnt] = NULL;
  1072. if (!sp->ctx ||
  1073. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1074. IS_PROT_IO(sp)) {
  1075. sp->cmd->result = res;
  1076. qla2x00_sp_compl(ha, sp);
  1077. } else {
  1078. ctx = sp->ctx;
  1079. if (ctx->type == SRB_LOGIN_CMD ||
  1080. ctx->type == SRB_LOGOUT_CMD) {
  1081. ctx->u.iocb_cmd->free(sp);
  1082. } else {
  1083. struct fc_bsg_job *bsg_job =
  1084. ctx->u.bsg_job;
  1085. if (bsg_job->request->msgcode
  1086. == FC_BSG_HST_CT)
  1087. kfree(sp->fcport);
  1088. bsg_job->req->errors = 0;
  1089. bsg_job->reply->result = res;
  1090. bsg_job->job_done(bsg_job);
  1091. kfree(sp->ctx);
  1092. mempool_free(sp,
  1093. ha->srb_mempool);
  1094. }
  1095. }
  1096. }
  1097. }
  1098. }
  1099. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1100. }
  1101. static int
  1102. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1103. {
  1104. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1105. if (!rport || fc_remote_port_chkready(rport))
  1106. return -ENXIO;
  1107. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1108. return 0;
  1109. }
  1110. static int
  1111. qla2xxx_slave_configure(struct scsi_device *sdev)
  1112. {
  1113. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1114. struct req_que *req = vha->req;
  1115. if (sdev->tagged_supported)
  1116. scsi_activate_tcq(sdev, req->max_q_depth);
  1117. else
  1118. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1119. return 0;
  1120. }
  1121. static void
  1122. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1123. {
  1124. sdev->hostdata = NULL;
  1125. }
  1126. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1127. {
  1128. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1129. if (!scsi_track_queue_full(sdev, qdepth))
  1130. return;
  1131. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1132. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1133. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1134. sdev->queue_depth));
  1135. }
  1136. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1137. {
  1138. fc_port_t *fcport = sdev->hostdata;
  1139. struct scsi_qla_host *vha = fcport->vha;
  1140. struct qla_hw_data *ha = vha->hw;
  1141. struct req_que *req = NULL;
  1142. req = vha->req;
  1143. if (!req)
  1144. return;
  1145. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1146. return;
  1147. if (sdev->ordered_tags)
  1148. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1149. else
  1150. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1151. DEBUG2(qla_printk(KERN_INFO, ha,
  1152. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1153. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1154. sdev->queue_depth));
  1155. }
  1156. static int
  1157. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1158. {
  1159. switch (reason) {
  1160. case SCSI_QDEPTH_DEFAULT:
  1161. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1162. break;
  1163. case SCSI_QDEPTH_QFULL:
  1164. qla2x00_handle_queue_full(sdev, qdepth);
  1165. break;
  1166. case SCSI_QDEPTH_RAMP_UP:
  1167. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1168. break;
  1169. default:
  1170. return -EOPNOTSUPP;
  1171. }
  1172. return sdev->queue_depth;
  1173. }
  1174. static int
  1175. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1176. {
  1177. if (sdev->tagged_supported) {
  1178. scsi_set_tag_type(sdev, tag_type);
  1179. if (tag_type)
  1180. scsi_activate_tcq(sdev, sdev->queue_depth);
  1181. else
  1182. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1183. } else
  1184. tag_type = 0;
  1185. return tag_type;
  1186. }
  1187. /**
  1188. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1189. * @ha: HA context
  1190. *
  1191. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1192. * supported addressing method.
  1193. */
  1194. static void
  1195. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1196. {
  1197. /* Assume a 32bit DMA mask. */
  1198. ha->flags.enable_64bit_addressing = 0;
  1199. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1200. /* Any upper-dword bits set? */
  1201. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1202. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1203. /* Ok, a 64bit DMA mask is applicable. */
  1204. ha->flags.enable_64bit_addressing = 1;
  1205. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1206. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1207. return;
  1208. }
  1209. }
  1210. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1211. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1212. }
  1213. static void
  1214. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1215. {
  1216. unsigned long flags = 0;
  1217. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1218. spin_lock_irqsave(&ha->hardware_lock, flags);
  1219. ha->interrupts_on = 1;
  1220. /* enable risc and host interrupts */
  1221. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1222. RD_REG_WORD(&reg->ictrl);
  1223. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1224. }
  1225. static void
  1226. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1227. {
  1228. unsigned long flags = 0;
  1229. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1230. spin_lock_irqsave(&ha->hardware_lock, flags);
  1231. ha->interrupts_on = 0;
  1232. /* disable risc and host interrupts */
  1233. WRT_REG_WORD(&reg->ictrl, 0);
  1234. RD_REG_WORD(&reg->ictrl);
  1235. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1236. }
  1237. static void
  1238. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1239. {
  1240. unsigned long flags = 0;
  1241. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1242. spin_lock_irqsave(&ha->hardware_lock, flags);
  1243. ha->interrupts_on = 1;
  1244. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1245. RD_REG_DWORD(&reg->ictrl);
  1246. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1247. }
  1248. static void
  1249. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1250. {
  1251. unsigned long flags = 0;
  1252. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1253. if (IS_NOPOLLING_TYPE(ha))
  1254. return;
  1255. spin_lock_irqsave(&ha->hardware_lock, flags);
  1256. ha->interrupts_on = 0;
  1257. WRT_REG_DWORD(&reg->ictrl, 0);
  1258. RD_REG_DWORD(&reg->ictrl);
  1259. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1260. }
  1261. static struct isp_operations qla2100_isp_ops = {
  1262. .pci_config = qla2100_pci_config,
  1263. .reset_chip = qla2x00_reset_chip,
  1264. .chip_diag = qla2x00_chip_diag,
  1265. .config_rings = qla2x00_config_rings,
  1266. .reset_adapter = qla2x00_reset_adapter,
  1267. .nvram_config = qla2x00_nvram_config,
  1268. .update_fw_options = qla2x00_update_fw_options,
  1269. .load_risc = qla2x00_load_risc,
  1270. .pci_info_str = qla2x00_pci_info_str,
  1271. .fw_version_str = qla2x00_fw_version_str,
  1272. .intr_handler = qla2100_intr_handler,
  1273. .enable_intrs = qla2x00_enable_intrs,
  1274. .disable_intrs = qla2x00_disable_intrs,
  1275. .abort_command = qla2x00_abort_command,
  1276. .target_reset = qla2x00_abort_target,
  1277. .lun_reset = qla2x00_lun_reset,
  1278. .fabric_login = qla2x00_login_fabric,
  1279. .fabric_logout = qla2x00_fabric_logout,
  1280. .calc_req_entries = qla2x00_calc_iocbs_32,
  1281. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1282. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1283. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1284. .read_nvram = qla2x00_read_nvram_data,
  1285. .write_nvram = qla2x00_write_nvram_data,
  1286. .fw_dump = qla2100_fw_dump,
  1287. .beacon_on = NULL,
  1288. .beacon_off = NULL,
  1289. .beacon_blink = NULL,
  1290. .read_optrom = qla2x00_read_optrom_data,
  1291. .write_optrom = qla2x00_write_optrom_data,
  1292. .get_flash_version = qla2x00_get_flash_version,
  1293. .start_scsi = qla2x00_start_scsi,
  1294. .abort_isp = qla2x00_abort_isp,
  1295. };
  1296. static struct isp_operations qla2300_isp_ops = {
  1297. .pci_config = qla2300_pci_config,
  1298. .reset_chip = qla2x00_reset_chip,
  1299. .chip_diag = qla2x00_chip_diag,
  1300. .config_rings = qla2x00_config_rings,
  1301. .reset_adapter = qla2x00_reset_adapter,
  1302. .nvram_config = qla2x00_nvram_config,
  1303. .update_fw_options = qla2x00_update_fw_options,
  1304. .load_risc = qla2x00_load_risc,
  1305. .pci_info_str = qla2x00_pci_info_str,
  1306. .fw_version_str = qla2x00_fw_version_str,
  1307. .intr_handler = qla2300_intr_handler,
  1308. .enable_intrs = qla2x00_enable_intrs,
  1309. .disable_intrs = qla2x00_disable_intrs,
  1310. .abort_command = qla2x00_abort_command,
  1311. .target_reset = qla2x00_abort_target,
  1312. .lun_reset = qla2x00_lun_reset,
  1313. .fabric_login = qla2x00_login_fabric,
  1314. .fabric_logout = qla2x00_fabric_logout,
  1315. .calc_req_entries = qla2x00_calc_iocbs_32,
  1316. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1317. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1318. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1319. .read_nvram = qla2x00_read_nvram_data,
  1320. .write_nvram = qla2x00_write_nvram_data,
  1321. .fw_dump = qla2300_fw_dump,
  1322. .beacon_on = qla2x00_beacon_on,
  1323. .beacon_off = qla2x00_beacon_off,
  1324. .beacon_blink = qla2x00_beacon_blink,
  1325. .read_optrom = qla2x00_read_optrom_data,
  1326. .write_optrom = qla2x00_write_optrom_data,
  1327. .get_flash_version = qla2x00_get_flash_version,
  1328. .start_scsi = qla2x00_start_scsi,
  1329. .abort_isp = qla2x00_abort_isp,
  1330. };
  1331. static struct isp_operations qla24xx_isp_ops = {
  1332. .pci_config = qla24xx_pci_config,
  1333. .reset_chip = qla24xx_reset_chip,
  1334. .chip_diag = qla24xx_chip_diag,
  1335. .config_rings = qla24xx_config_rings,
  1336. .reset_adapter = qla24xx_reset_adapter,
  1337. .nvram_config = qla24xx_nvram_config,
  1338. .update_fw_options = qla24xx_update_fw_options,
  1339. .load_risc = qla24xx_load_risc,
  1340. .pci_info_str = qla24xx_pci_info_str,
  1341. .fw_version_str = qla24xx_fw_version_str,
  1342. .intr_handler = qla24xx_intr_handler,
  1343. .enable_intrs = qla24xx_enable_intrs,
  1344. .disable_intrs = qla24xx_disable_intrs,
  1345. .abort_command = qla24xx_abort_command,
  1346. .target_reset = qla24xx_abort_target,
  1347. .lun_reset = qla24xx_lun_reset,
  1348. .fabric_login = qla24xx_login_fabric,
  1349. .fabric_logout = qla24xx_fabric_logout,
  1350. .calc_req_entries = NULL,
  1351. .build_iocbs = NULL,
  1352. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1353. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1354. .read_nvram = qla24xx_read_nvram_data,
  1355. .write_nvram = qla24xx_write_nvram_data,
  1356. .fw_dump = qla24xx_fw_dump,
  1357. .beacon_on = qla24xx_beacon_on,
  1358. .beacon_off = qla24xx_beacon_off,
  1359. .beacon_blink = qla24xx_beacon_blink,
  1360. .read_optrom = qla24xx_read_optrom_data,
  1361. .write_optrom = qla24xx_write_optrom_data,
  1362. .get_flash_version = qla24xx_get_flash_version,
  1363. .start_scsi = qla24xx_start_scsi,
  1364. .abort_isp = qla2x00_abort_isp,
  1365. };
  1366. static struct isp_operations qla25xx_isp_ops = {
  1367. .pci_config = qla25xx_pci_config,
  1368. .reset_chip = qla24xx_reset_chip,
  1369. .chip_diag = qla24xx_chip_diag,
  1370. .config_rings = qla24xx_config_rings,
  1371. .reset_adapter = qla24xx_reset_adapter,
  1372. .nvram_config = qla24xx_nvram_config,
  1373. .update_fw_options = qla24xx_update_fw_options,
  1374. .load_risc = qla24xx_load_risc,
  1375. .pci_info_str = qla24xx_pci_info_str,
  1376. .fw_version_str = qla24xx_fw_version_str,
  1377. .intr_handler = qla24xx_intr_handler,
  1378. .enable_intrs = qla24xx_enable_intrs,
  1379. .disable_intrs = qla24xx_disable_intrs,
  1380. .abort_command = qla24xx_abort_command,
  1381. .target_reset = qla24xx_abort_target,
  1382. .lun_reset = qla24xx_lun_reset,
  1383. .fabric_login = qla24xx_login_fabric,
  1384. .fabric_logout = qla24xx_fabric_logout,
  1385. .calc_req_entries = NULL,
  1386. .build_iocbs = NULL,
  1387. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1388. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1389. .read_nvram = qla25xx_read_nvram_data,
  1390. .write_nvram = qla25xx_write_nvram_data,
  1391. .fw_dump = qla25xx_fw_dump,
  1392. .beacon_on = qla24xx_beacon_on,
  1393. .beacon_off = qla24xx_beacon_off,
  1394. .beacon_blink = qla24xx_beacon_blink,
  1395. .read_optrom = qla25xx_read_optrom_data,
  1396. .write_optrom = qla24xx_write_optrom_data,
  1397. .get_flash_version = qla24xx_get_flash_version,
  1398. .start_scsi = qla24xx_dif_start_scsi,
  1399. .abort_isp = qla2x00_abort_isp,
  1400. };
  1401. static struct isp_operations qla81xx_isp_ops = {
  1402. .pci_config = qla25xx_pci_config,
  1403. .reset_chip = qla24xx_reset_chip,
  1404. .chip_diag = qla24xx_chip_diag,
  1405. .config_rings = qla24xx_config_rings,
  1406. .reset_adapter = qla24xx_reset_adapter,
  1407. .nvram_config = qla81xx_nvram_config,
  1408. .update_fw_options = qla81xx_update_fw_options,
  1409. .load_risc = qla81xx_load_risc,
  1410. .pci_info_str = qla24xx_pci_info_str,
  1411. .fw_version_str = qla24xx_fw_version_str,
  1412. .intr_handler = qla24xx_intr_handler,
  1413. .enable_intrs = qla24xx_enable_intrs,
  1414. .disable_intrs = qla24xx_disable_intrs,
  1415. .abort_command = qla24xx_abort_command,
  1416. .target_reset = qla24xx_abort_target,
  1417. .lun_reset = qla24xx_lun_reset,
  1418. .fabric_login = qla24xx_login_fabric,
  1419. .fabric_logout = qla24xx_fabric_logout,
  1420. .calc_req_entries = NULL,
  1421. .build_iocbs = NULL,
  1422. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1423. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1424. .read_nvram = NULL,
  1425. .write_nvram = NULL,
  1426. .fw_dump = qla81xx_fw_dump,
  1427. .beacon_on = qla24xx_beacon_on,
  1428. .beacon_off = qla24xx_beacon_off,
  1429. .beacon_blink = qla24xx_beacon_blink,
  1430. .read_optrom = qla25xx_read_optrom_data,
  1431. .write_optrom = qla24xx_write_optrom_data,
  1432. .get_flash_version = qla24xx_get_flash_version,
  1433. .start_scsi = qla24xx_dif_start_scsi,
  1434. .abort_isp = qla2x00_abort_isp,
  1435. };
  1436. static struct isp_operations qla82xx_isp_ops = {
  1437. .pci_config = qla82xx_pci_config,
  1438. .reset_chip = qla82xx_reset_chip,
  1439. .chip_diag = qla24xx_chip_diag,
  1440. .config_rings = qla82xx_config_rings,
  1441. .reset_adapter = qla24xx_reset_adapter,
  1442. .nvram_config = qla81xx_nvram_config,
  1443. .update_fw_options = qla24xx_update_fw_options,
  1444. .load_risc = qla82xx_load_risc,
  1445. .pci_info_str = qla82xx_pci_info_str,
  1446. .fw_version_str = qla24xx_fw_version_str,
  1447. .intr_handler = qla82xx_intr_handler,
  1448. .enable_intrs = qla82xx_enable_intrs,
  1449. .disable_intrs = qla82xx_disable_intrs,
  1450. .abort_command = qla24xx_abort_command,
  1451. .target_reset = qla24xx_abort_target,
  1452. .lun_reset = qla24xx_lun_reset,
  1453. .fabric_login = qla24xx_login_fabric,
  1454. .fabric_logout = qla24xx_fabric_logout,
  1455. .calc_req_entries = NULL,
  1456. .build_iocbs = NULL,
  1457. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1458. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1459. .read_nvram = qla24xx_read_nvram_data,
  1460. .write_nvram = qla24xx_write_nvram_data,
  1461. .fw_dump = qla24xx_fw_dump,
  1462. .beacon_on = qla24xx_beacon_on,
  1463. .beacon_off = qla24xx_beacon_off,
  1464. .beacon_blink = qla24xx_beacon_blink,
  1465. .read_optrom = qla82xx_read_optrom_data,
  1466. .write_optrom = qla82xx_write_optrom_data,
  1467. .get_flash_version = qla24xx_get_flash_version,
  1468. .start_scsi = qla82xx_start_scsi,
  1469. .abort_isp = qla82xx_abort_isp,
  1470. };
  1471. static inline void
  1472. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1473. {
  1474. ha->device_type = DT_EXTENDED_IDS;
  1475. switch (ha->pdev->device) {
  1476. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1477. ha->device_type |= DT_ISP2100;
  1478. ha->device_type &= ~DT_EXTENDED_IDS;
  1479. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1480. break;
  1481. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1482. ha->device_type |= DT_ISP2200;
  1483. ha->device_type &= ~DT_EXTENDED_IDS;
  1484. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1485. break;
  1486. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1487. ha->device_type |= DT_ISP2300;
  1488. ha->device_type |= DT_ZIO_SUPPORTED;
  1489. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1490. break;
  1491. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1492. ha->device_type |= DT_ISP2312;
  1493. ha->device_type |= DT_ZIO_SUPPORTED;
  1494. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1495. break;
  1496. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1497. ha->device_type |= DT_ISP2322;
  1498. ha->device_type |= DT_ZIO_SUPPORTED;
  1499. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1500. ha->pdev->subsystem_device == 0x0170)
  1501. ha->device_type |= DT_OEM_001;
  1502. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1503. break;
  1504. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1505. ha->device_type |= DT_ISP6312;
  1506. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1507. break;
  1508. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1509. ha->device_type |= DT_ISP6322;
  1510. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1511. break;
  1512. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1513. ha->device_type |= DT_ISP2422;
  1514. ha->device_type |= DT_ZIO_SUPPORTED;
  1515. ha->device_type |= DT_FWI2;
  1516. ha->device_type |= DT_IIDMA;
  1517. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1518. break;
  1519. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1520. ha->device_type |= DT_ISP2432;
  1521. ha->device_type |= DT_ZIO_SUPPORTED;
  1522. ha->device_type |= DT_FWI2;
  1523. ha->device_type |= DT_IIDMA;
  1524. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1525. break;
  1526. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1527. ha->device_type |= DT_ISP8432;
  1528. ha->device_type |= DT_ZIO_SUPPORTED;
  1529. ha->device_type |= DT_FWI2;
  1530. ha->device_type |= DT_IIDMA;
  1531. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1532. break;
  1533. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1534. ha->device_type |= DT_ISP5422;
  1535. ha->device_type |= DT_FWI2;
  1536. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1537. break;
  1538. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1539. ha->device_type |= DT_ISP5432;
  1540. ha->device_type |= DT_FWI2;
  1541. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1542. break;
  1543. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1544. ha->device_type |= DT_ISP2532;
  1545. ha->device_type |= DT_ZIO_SUPPORTED;
  1546. ha->device_type |= DT_FWI2;
  1547. ha->device_type |= DT_IIDMA;
  1548. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1549. break;
  1550. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1551. ha->device_type |= DT_ISP8001;
  1552. ha->device_type |= DT_ZIO_SUPPORTED;
  1553. ha->device_type |= DT_FWI2;
  1554. ha->device_type |= DT_IIDMA;
  1555. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1556. break;
  1557. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1558. ha->device_type |= DT_ISP8021;
  1559. ha->device_type |= DT_ZIO_SUPPORTED;
  1560. ha->device_type |= DT_FWI2;
  1561. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1562. /* Initialize 82XX ISP flags */
  1563. qla82xx_init_flags(ha);
  1564. break;
  1565. }
  1566. if (IS_QLA82XX(ha))
  1567. ha->port_no = !(ha->portnum & 1);
  1568. else
  1569. /* Get adapter physical port no from interrupt pin register. */
  1570. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1571. if (ha->port_no & 1)
  1572. ha->flags.port0 = 1;
  1573. else
  1574. ha->flags.port0 = 0;
  1575. }
  1576. static int
  1577. qla2x00_iospace_config(struct qla_hw_data *ha)
  1578. {
  1579. resource_size_t pio;
  1580. uint16_t msix;
  1581. int cpus;
  1582. if (IS_QLA82XX(ha))
  1583. return qla82xx_iospace_config(ha);
  1584. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1585. QLA2XXX_DRIVER_NAME)) {
  1586. qla_printk(KERN_WARNING, ha,
  1587. "Failed to reserve PIO/MMIO regions (%s)\n",
  1588. pci_name(ha->pdev));
  1589. goto iospace_error_exit;
  1590. }
  1591. if (!(ha->bars & 1))
  1592. goto skip_pio;
  1593. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1594. pio = pci_resource_start(ha->pdev, 0);
  1595. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1596. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1597. qla_printk(KERN_WARNING, ha,
  1598. "Invalid PCI I/O region size (%s)...\n",
  1599. pci_name(ha->pdev));
  1600. pio = 0;
  1601. }
  1602. } else {
  1603. qla_printk(KERN_WARNING, ha,
  1604. "region #0 not a PIO resource (%s)...\n",
  1605. pci_name(ha->pdev));
  1606. pio = 0;
  1607. }
  1608. ha->pio_address = pio;
  1609. skip_pio:
  1610. /* Use MMIO operations for all accesses. */
  1611. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1612. qla_printk(KERN_ERR, ha,
  1613. "region #1 not an MMIO resource (%s), aborting\n",
  1614. pci_name(ha->pdev));
  1615. goto iospace_error_exit;
  1616. }
  1617. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1618. qla_printk(KERN_ERR, ha,
  1619. "Invalid PCI mem region size (%s), aborting\n",
  1620. pci_name(ha->pdev));
  1621. goto iospace_error_exit;
  1622. }
  1623. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1624. if (!ha->iobase) {
  1625. qla_printk(KERN_ERR, ha,
  1626. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1627. goto iospace_error_exit;
  1628. }
  1629. /* Determine queue resources */
  1630. ha->max_req_queues = ha->max_rsp_queues = 1;
  1631. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1632. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1633. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1634. goto mqiobase_exit;
  1635. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1636. pci_resource_len(ha->pdev, 3));
  1637. if (ha->mqiobase) {
  1638. /* Read MSIX vector size of the board */
  1639. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1640. ha->msix_count = msix;
  1641. /* Max queues are bounded by available msix vectors */
  1642. /* queue 0 uses two msix vectors */
  1643. if (ql2xmultique_tag) {
  1644. cpus = num_online_cpus();
  1645. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1646. (cpus + 1) : (ha->msix_count - 1);
  1647. ha->max_req_queues = 2;
  1648. } else if (ql2xmaxqueues > 1) {
  1649. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1650. QLA_MQ_SIZE : ql2xmaxqueues;
  1651. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1652. " of request queues:%d\n", ha->max_req_queues));
  1653. }
  1654. qla_printk(KERN_INFO, ha,
  1655. "MSI-X vector count: %d\n", msix);
  1656. } else
  1657. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1658. mqiobase_exit:
  1659. ha->msix_count = ha->max_rsp_queues + 1;
  1660. return (0);
  1661. iospace_error_exit:
  1662. return (-ENOMEM);
  1663. }
  1664. static void
  1665. qla2xxx_scan_start(struct Scsi_Host *shost)
  1666. {
  1667. scsi_qla_host_t *vha = shost_priv(shost);
  1668. if (vha->hw->flags.running_gold_fw)
  1669. return;
  1670. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1671. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1672. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1673. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1674. }
  1675. static int
  1676. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1677. {
  1678. scsi_qla_host_t *vha = shost_priv(shost);
  1679. if (!vha->host)
  1680. return 1;
  1681. if (time > vha->hw->loop_reset_delay * HZ)
  1682. return 1;
  1683. return atomic_read(&vha->loop_state) == LOOP_READY;
  1684. }
  1685. /*
  1686. * PCI driver interface
  1687. */
  1688. static int __devinit
  1689. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1690. {
  1691. int ret = -ENODEV;
  1692. struct Scsi_Host *host;
  1693. scsi_qla_host_t *base_vha = NULL;
  1694. struct qla_hw_data *ha;
  1695. char pci_info[30];
  1696. char fw_str[30];
  1697. struct scsi_host_template *sht;
  1698. int bars, max_id, mem_only = 0;
  1699. uint16_t req_length = 0, rsp_length = 0;
  1700. struct req_que *req = NULL;
  1701. struct rsp_que *rsp = NULL;
  1702. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1703. sht = &qla2xxx_driver_template;
  1704. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1705. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1706. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1707. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1708. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1709. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1710. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1711. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1712. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1713. mem_only = 1;
  1714. }
  1715. if (mem_only) {
  1716. if (pci_enable_device_mem(pdev))
  1717. goto probe_out;
  1718. } else {
  1719. if (pci_enable_device(pdev))
  1720. goto probe_out;
  1721. }
  1722. /* This may fail but that's ok */
  1723. pci_enable_pcie_error_reporting(pdev);
  1724. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1725. if (!ha) {
  1726. DEBUG(printk("Unable to allocate memory for ha\n"));
  1727. goto probe_out;
  1728. }
  1729. ha->pdev = pdev;
  1730. /* Clear our data area */
  1731. ha->bars = bars;
  1732. ha->mem_only = mem_only;
  1733. spin_lock_init(&ha->hardware_lock);
  1734. /* Set ISP-type information. */
  1735. qla2x00_set_isp_flags(ha);
  1736. /* Set EEH reset type to fundamental if required by hba */
  1737. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1738. pdev->needs_freset = 1;
  1739. }
  1740. /* Configure PCI I/O space */
  1741. ret = qla2x00_iospace_config(ha);
  1742. if (ret)
  1743. goto probe_hw_failed;
  1744. qla_printk(KERN_INFO, ha,
  1745. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1746. ha->iobase);
  1747. ha->prev_topology = 0;
  1748. ha->init_cb_size = sizeof(init_cb_t);
  1749. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1750. ha->optrom_size = OPTROM_SIZE_2300;
  1751. /* Assign ISP specific operations. */
  1752. max_id = MAX_TARGETS_2200;
  1753. if (IS_QLA2100(ha)) {
  1754. max_id = MAX_TARGETS_2100;
  1755. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1756. req_length = REQUEST_ENTRY_CNT_2100;
  1757. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1758. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1759. ha->gid_list_info_size = 4;
  1760. ha->flash_conf_off = ~0;
  1761. ha->flash_data_off = ~0;
  1762. ha->nvram_conf_off = ~0;
  1763. ha->nvram_data_off = ~0;
  1764. ha->isp_ops = &qla2100_isp_ops;
  1765. } else if (IS_QLA2200(ha)) {
  1766. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1767. req_length = REQUEST_ENTRY_CNT_2200;
  1768. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1769. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1770. ha->gid_list_info_size = 4;
  1771. ha->flash_conf_off = ~0;
  1772. ha->flash_data_off = ~0;
  1773. ha->nvram_conf_off = ~0;
  1774. ha->nvram_data_off = ~0;
  1775. ha->isp_ops = &qla2100_isp_ops;
  1776. } else if (IS_QLA23XX(ha)) {
  1777. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1778. req_length = REQUEST_ENTRY_CNT_2200;
  1779. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1780. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1781. ha->gid_list_info_size = 6;
  1782. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1783. ha->optrom_size = OPTROM_SIZE_2322;
  1784. ha->flash_conf_off = ~0;
  1785. ha->flash_data_off = ~0;
  1786. ha->nvram_conf_off = ~0;
  1787. ha->nvram_data_off = ~0;
  1788. ha->isp_ops = &qla2300_isp_ops;
  1789. } else if (IS_QLA24XX_TYPE(ha)) {
  1790. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1791. req_length = REQUEST_ENTRY_CNT_24XX;
  1792. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1793. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1794. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1795. ha->gid_list_info_size = 8;
  1796. ha->optrom_size = OPTROM_SIZE_24XX;
  1797. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1798. ha->isp_ops = &qla24xx_isp_ops;
  1799. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1800. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1801. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1802. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1803. } else if (IS_QLA25XX(ha)) {
  1804. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1805. req_length = REQUEST_ENTRY_CNT_24XX;
  1806. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1807. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1808. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1809. ha->gid_list_info_size = 8;
  1810. ha->optrom_size = OPTROM_SIZE_25XX;
  1811. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1812. ha->isp_ops = &qla25xx_isp_ops;
  1813. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1814. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1815. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1816. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1817. } else if (IS_QLA81XX(ha)) {
  1818. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1819. req_length = REQUEST_ENTRY_CNT_24XX;
  1820. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1821. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1822. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1823. ha->gid_list_info_size = 8;
  1824. ha->optrom_size = OPTROM_SIZE_81XX;
  1825. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1826. ha->isp_ops = &qla81xx_isp_ops;
  1827. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1828. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1829. ha->nvram_conf_off = ~0;
  1830. ha->nvram_data_off = ~0;
  1831. } else if (IS_QLA82XX(ha)) {
  1832. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1833. req_length = REQUEST_ENTRY_CNT_82XX;
  1834. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1835. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1836. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1837. ha->gid_list_info_size = 8;
  1838. ha->optrom_size = OPTROM_SIZE_82XX;
  1839. ha->isp_ops = &qla82xx_isp_ops;
  1840. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1841. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1842. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1843. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1844. }
  1845. mutex_init(&ha->vport_lock);
  1846. init_completion(&ha->mbx_cmd_comp);
  1847. complete(&ha->mbx_cmd_comp);
  1848. init_completion(&ha->mbx_intr_comp);
  1849. init_completion(&ha->dcbx_comp);
  1850. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1851. qla2x00_config_dma_addressing(ha);
  1852. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1853. if (!ret) {
  1854. qla_printk(KERN_WARNING, ha,
  1855. "[ERROR] Failed to allocate memory for adapter\n");
  1856. goto probe_hw_failed;
  1857. }
  1858. req->max_q_depth = MAX_Q_DEPTH;
  1859. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1860. req->max_q_depth = ql2xmaxqdepth;
  1861. base_vha = qla2x00_create_host(sht, ha);
  1862. if (!base_vha) {
  1863. qla_printk(KERN_WARNING, ha,
  1864. "[ERROR] Failed to allocate memory for scsi_host\n");
  1865. ret = -ENOMEM;
  1866. qla2x00_mem_free(ha);
  1867. qla2x00_free_req_que(ha, req);
  1868. qla2x00_free_rsp_que(ha, rsp);
  1869. goto probe_hw_failed;
  1870. }
  1871. pci_set_drvdata(pdev, base_vha);
  1872. host = base_vha->host;
  1873. base_vha->req = req;
  1874. host->can_queue = req->length + 128;
  1875. if (IS_QLA2XXX_MIDTYPE(ha))
  1876. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1877. else
  1878. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1879. base_vha->vp_idx;
  1880. /* Set the SG table size based on ISP type */
  1881. if (!IS_FWI2_CAPABLE(ha)) {
  1882. if (IS_QLA2100(ha))
  1883. host->sg_tablesize = 32;
  1884. } else {
  1885. if (!IS_QLA82XX(ha))
  1886. host->sg_tablesize = QLA_SG_ALL;
  1887. }
  1888. host->max_id = max_id;
  1889. host->this_id = 255;
  1890. host->cmd_per_lun = 3;
  1891. host->unique_id = host->host_no;
  1892. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1893. host->max_cmd_len = 32;
  1894. else
  1895. host->max_cmd_len = MAX_CMDSZ;
  1896. host->max_channel = MAX_BUSES - 1;
  1897. host->max_lun = MAX_LUNS;
  1898. host->transportt = qla2xxx_transport_template;
  1899. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1900. /* Set up the irqs */
  1901. ret = qla2x00_request_irqs(ha, rsp);
  1902. if (ret)
  1903. goto probe_init_failed;
  1904. pci_save_state(pdev);
  1905. /* Alloc arrays of request and response ring ptrs */
  1906. que_init:
  1907. if (!qla2x00_alloc_queues(ha)) {
  1908. qla_printk(KERN_WARNING, ha,
  1909. "[ERROR] Failed to allocate memory for queue"
  1910. " pointers\n");
  1911. goto probe_init_failed;
  1912. }
  1913. ha->rsp_q_map[0] = rsp;
  1914. ha->req_q_map[0] = req;
  1915. rsp->req = req;
  1916. req->rsp = rsp;
  1917. set_bit(0, ha->req_qid_map);
  1918. set_bit(0, ha->rsp_qid_map);
  1919. /* FWI2-capable only. */
  1920. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1921. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1922. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1923. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1924. if (ha->mqenable) {
  1925. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1926. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1927. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1928. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1929. }
  1930. if (IS_QLA82XX(ha)) {
  1931. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1932. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1933. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1934. }
  1935. if (qla2x00_initialize_adapter(base_vha)) {
  1936. qla_printk(KERN_WARNING, ha,
  1937. "Failed to initialize adapter\n");
  1938. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1939. "Adapter flags %x.\n",
  1940. base_vha->host_no, base_vha->device_flags));
  1941. if (IS_QLA82XX(ha)) {
  1942. qla82xx_idc_lock(ha);
  1943. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1944. QLA82XX_DEV_FAILED);
  1945. qla82xx_idc_unlock(ha);
  1946. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1947. }
  1948. ret = -ENODEV;
  1949. goto probe_failed;
  1950. }
  1951. if (ha->mqenable) {
  1952. if (qla25xx_setup_mode(base_vha)) {
  1953. qla_printk(KERN_WARNING, ha,
  1954. "Can't create queues, falling back to single"
  1955. " queue mode\n");
  1956. goto que_init;
  1957. }
  1958. }
  1959. if (ha->flags.running_gold_fw)
  1960. goto skip_dpc;
  1961. /*
  1962. * Startup the kernel thread for this host adapter
  1963. */
  1964. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1965. "%s_dpc", base_vha->host_str);
  1966. if (IS_ERR(ha->dpc_thread)) {
  1967. qla_printk(KERN_WARNING, ha,
  1968. "Unable to start DPC thread!\n");
  1969. ret = PTR_ERR(ha->dpc_thread);
  1970. goto probe_failed;
  1971. }
  1972. skip_dpc:
  1973. list_add_tail(&base_vha->list, &ha->vp_list);
  1974. base_vha->host->irq = ha->pdev->irq;
  1975. /* Initialized the timer */
  1976. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1977. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1978. base_vha->host_no, ha));
  1979. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1980. if (ha->fw_attributes & BIT_4) {
  1981. base_vha->flags.difdix_supported = 1;
  1982. DEBUG18(qla_printk(KERN_INFO, ha,
  1983. "Registering for DIF/DIX type 1 and 3"
  1984. " protection.\n"));
  1985. scsi_host_set_prot(host,
  1986. SHOST_DIF_TYPE1_PROTECTION
  1987. | SHOST_DIF_TYPE2_PROTECTION
  1988. | SHOST_DIF_TYPE3_PROTECTION
  1989. | SHOST_DIX_TYPE1_PROTECTION
  1990. | SHOST_DIX_TYPE2_PROTECTION
  1991. | SHOST_DIX_TYPE3_PROTECTION);
  1992. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1993. } else
  1994. base_vha->flags.difdix_supported = 0;
  1995. }
  1996. ha->isp_ops->enable_intrs(ha);
  1997. ret = scsi_add_host(host, &pdev->dev);
  1998. if (ret)
  1999. goto probe_failed;
  2000. base_vha->flags.init_done = 1;
  2001. base_vha->flags.online = 1;
  2002. scsi_scan_host(host);
  2003. qla2x00_alloc_sysfs_attr(base_vha);
  2004. qla2x00_init_host_attr(base_vha);
  2005. qla2x00_dfs_setup(base_vha);
  2006. qla_printk(KERN_INFO, ha, "\n"
  2007. " QLogic Fibre Channel HBA Driver: %s\n"
  2008. " QLogic %s - %s\n"
  2009. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  2010. qla2x00_version_str, ha->model_number,
  2011. ha->model_desc ? ha->model_desc : "", pdev->device,
  2012. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  2013. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  2014. ha->isp_ops->fw_version_str(base_vha, fw_str));
  2015. return 0;
  2016. probe_init_failed:
  2017. qla2x00_free_req_que(ha, req);
  2018. qla2x00_free_rsp_que(ha, rsp);
  2019. ha->max_req_queues = ha->max_rsp_queues = 0;
  2020. probe_failed:
  2021. if (base_vha->timer_active)
  2022. qla2x00_stop_timer(base_vha);
  2023. base_vha->flags.online = 0;
  2024. if (ha->dpc_thread) {
  2025. struct task_struct *t = ha->dpc_thread;
  2026. ha->dpc_thread = NULL;
  2027. kthread_stop(t);
  2028. }
  2029. qla2x00_free_device(base_vha);
  2030. scsi_host_put(base_vha->host);
  2031. probe_hw_failed:
  2032. if (IS_QLA82XX(ha)) {
  2033. qla82xx_idc_lock(ha);
  2034. qla82xx_clear_drv_active(ha);
  2035. qla82xx_idc_unlock(ha);
  2036. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2037. if (!ql2xdbwr)
  2038. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2039. } else {
  2040. if (ha->iobase)
  2041. iounmap(ha->iobase);
  2042. }
  2043. pci_release_selected_regions(ha->pdev, ha->bars);
  2044. kfree(ha);
  2045. ha = NULL;
  2046. probe_out:
  2047. pci_disable_device(pdev);
  2048. return ret;
  2049. }
  2050. static void
  2051. qla2x00_remove_one(struct pci_dev *pdev)
  2052. {
  2053. scsi_qla_host_t *base_vha, *vha;
  2054. struct qla_hw_data *ha;
  2055. unsigned long flags;
  2056. base_vha = pci_get_drvdata(pdev);
  2057. ha = base_vha->hw;
  2058. spin_lock_irqsave(&ha->vport_slock, flags);
  2059. list_for_each_entry(vha, &ha->vp_list, list) {
  2060. atomic_inc(&vha->vref_count);
  2061. if (vha && vha->fc_vport) {
  2062. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2063. fc_vport_terminate(vha->fc_vport);
  2064. spin_lock_irqsave(&ha->vport_slock, flags);
  2065. }
  2066. atomic_dec(&vha->vref_count);
  2067. }
  2068. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2069. set_bit(UNLOADING, &base_vha->dpc_flags);
  2070. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2071. qla2x00_dfs_remove(base_vha);
  2072. qla84xx_put_chip(base_vha);
  2073. /* Disable timer */
  2074. if (base_vha->timer_active)
  2075. qla2x00_stop_timer(base_vha);
  2076. base_vha->flags.online = 0;
  2077. /* Flush the work queue and remove it */
  2078. if (ha->wq) {
  2079. flush_workqueue(ha->wq);
  2080. destroy_workqueue(ha->wq);
  2081. ha->wq = NULL;
  2082. }
  2083. /* Kill the kernel thread for this host */
  2084. if (ha->dpc_thread) {
  2085. struct task_struct *t = ha->dpc_thread;
  2086. /*
  2087. * qla2xxx_wake_dpc checks for ->dpc_thread
  2088. * so we need to zero it out.
  2089. */
  2090. ha->dpc_thread = NULL;
  2091. kthread_stop(t);
  2092. }
  2093. qla2x00_free_sysfs_attr(base_vha);
  2094. fc_remove_host(base_vha->host);
  2095. scsi_remove_host(base_vha->host);
  2096. qla2x00_free_device(base_vha);
  2097. scsi_host_put(base_vha->host);
  2098. if (IS_QLA82XX(ha)) {
  2099. qla82xx_idc_lock(ha);
  2100. qla82xx_clear_drv_active(ha);
  2101. qla82xx_idc_unlock(ha);
  2102. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2103. if (!ql2xdbwr)
  2104. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2105. } else {
  2106. if (ha->iobase)
  2107. iounmap(ha->iobase);
  2108. if (ha->mqiobase)
  2109. iounmap(ha->mqiobase);
  2110. }
  2111. pci_release_selected_regions(ha->pdev, ha->bars);
  2112. kfree(ha);
  2113. ha = NULL;
  2114. pci_disable_pcie_error_reporting(pdev);
  2115. pci_disable_device(pdev);
  2116. pci_set_drvdata(pdev, NULL);
  2117. }
  2118. static void
  2119. qla2x00_free_device(scsi_qla_host_t *vha)
  2120. {
  2121. struct qla_hw_data *ha = vha->hw;
  2122. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2123. /* Disable timer */
  2124. if (vha->timer_active)
  2125. qla2x00_stop_timer(vha);
  2126. /* Kill the kernel thread for this host */
  2127. if (ha->dpc_thread) {
  2128. struct task_struct *t = ha->dpc_thread;
  2129. /*
  2130. * qla2xxx_wake_dpc checks for ->dpc_thread
  2131. * so we need to zero it out.
  2132. */
  2133. ha->dpc_thread = NULL;
  2134. kthread_stop(t);
  2135. }
  2136. qla25xx_delete_queues(vha);
  2137. if (ha->flags.fce_enabled)
  2138. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2139. if (ha->eft)
  2140. qla2x00_disable_eft_trace(vha);
  2141. /* Stop currently executing firmware. */
  2142. qla2x00_try_to_stop_firmware(vha);
  2143. vha->flags.online = 0;
  2144. /* turn-off interrupts on the card */
  2145. if (ha->interrupts_on) {
  2146. vha->flags.init_done = 0;
  2147. ha->isp_ops->disable_intrs(ha);
  2148. }
  2149. qla2x00_free_irqs(vha);
  2150. qla2x00_free_fcports(vha);
  2151. qla2x00_mem_free(ha);
  2152. qla2x00_free_queues(ha);
  2153. }
  2154. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2155. {
  2156. fc_port_t *fcport, *tfcport;
  2157. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2158. list_del(&fcport->list);
  2159. kfree(fcport);
  2160. fcport = NULL;
  2161. }
  2162. }
  2163. static inline void
  2164. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2165. int defer)
  2166. {
  2167. struct fc_rport *rport;
  2168. scsi_qla_host_t *base_vha;
  2169. if (!fcport->rport)
  2170. return;
  2171. rport = fcport->rport;
  2172. if (defer) {
  2173. base_vha = pci_get_drvdata(vha->hw->pdev);
  2174. spin_lock_irq(vha->host->host_lock);
  2175. fcport->drport = rport;
  2176. spin_unlock_irq(vha->host->host_lock);
  2177. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2178. qla2xxx_wake_dpc(base_vha);
  2179. } else
  2180. fc_remote_port_delete(rport);
  2181. }
  2182. /*
  2183. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2184. *
  2185. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2186. *
  2187. * Return: None.
  2188. *
  2189. * Context:
  2190. */
  2191. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2192. int do_login, int defer)
  2193. {
  2194. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2195. vha->vp_idx == fcport->vp_idx) {
  2196. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2197. qla2x00_schedule_rport_del(vha, fcport, defer);
  2198. }
  2199. /*
  2200. * We may need to retry the login, so don't change the state of the
  2201. * port but do the retries.
  2202. */
  2203. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2204. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2205. if (!do_login)
  2206. return;
  2207. if (fcport->login_retry == 0) {
  2208. fcport->login_retry = vha->hw->login_retry_count;
  2209. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2210. DEBUG(printk("scsi(%ld): Port login retry: "
  2211. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2212. "id = 0x%04x retry cnt=%d\n",
  2213. vha->host_no,
  2214. fcport->port_name[0],
  2215. fcport->port_name[1],
  2216. fcport->port_name[2],
  2217. fcport->port_name[3],
  2218. fcport->port_name[4],
  2219. fcport->port_name[5],
  2220. fcport->port_name[6],
  2221. fcport->port_name[7],
  2222. fcport->loop_id,
  2223. fcport->login_retry));
  2224. }
  2225. }
  2226. /*
  2227. * qla2x00_mark_all_devices_lost
  2228. * Updates fcport state when device goes offline.
  2229. *
  2230. * Input:
  2231. * ha = adapter block pointer.
  2232. * fcport = port structure pointer.
  2233. *
  2234. * Return:
  2235. * None.
  2236. *
  2237. * Context:
  2238. */
  2239. void
  2240. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2241. {
  2242. fc_port_t *fcport;
  2243. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2244. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2245. continue;
  2246. /*
  2247. * No point in marking the device as lost, if the device is
  2248. * already DEAD.
  2249. */
  2250. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2251. continue;
  2252. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2253. if (defer)
  2254. qla2x00_schedule_rport_del(vha, fcport, defer);
  2255. else if (vha->vp_idx == fcport->vp_idx)
  2256. qla2x00_schedule_rport_del(vha, fcport, defer);
  2257. }
  2258. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2259. }
  2260. }
  2261. /*
  2262. * qla2x00_mem_alloc
  2263. * Allocates adapter memory.
  2264. *
  2265. * Returns:
  2266. * 0 = success.
  2267. * !0 = failure.
  2268. */
  2269. static int
  2270. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2271. struct req_que **req, struct rsp_que **rsp)
  2272. {
  2273. char name[16];
  2274. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2275. &ha->init_cb_dma, GFP_KERNEL);
  2276. if (!ha->init_cb)
  2277. goto fail;
  2278. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2279. &ha->gid_list_dma, GFP_KERNEL);
  2280. if (!ha->gid_list)
  2281. goto fail_free_init_cb;
  2282. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2283. if (!ha->srb_mempool)
  2284. goto fail_free_gid_list;
  2285. if (IS_QLA82XX(ha)) {
  2286. /* Allocate cache for CT6 Ctx. */
  2287. if (!ctx_cachep) {
  2288. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2289. sizeof(struct ct6_dsd), 0,
  2290. SLAB_HWCACHE_ALIGN, NULL);
  2291. if (!ctx_cachep)
  2292. goto fail_free_gid_list;
  2293. }
  2294. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2295. ctx_cachep);
  2296. if (!ha->ctx_mempool)
  2297. goto fail_free_srb_mempool;
  2298. }
  2299. /* Get memory for cached NVRAM */
  2300. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2301. if (!ha->nvram)
  2302. goto fail_free_ctx_mempool;
  2303. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2304. ha->pdev->device);
  2305. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2306. DMA_POOL_SIZE, 8, 0);
  2307. if (!ha->s_dma_pool)
  2308. goto fail_free_nvram;
  2309. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2310. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2311. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2312. if (!ha->dl_dma_pool) {
  2313. qla_printk(KERN_WARNING, ha,
  2314. "Memory Allocation failed - dl_dma_pool\n");
  2315. goto fail_s_dma_pool;
  2316. }
  2317. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2318. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2319. if (!ha->fcp_cmnd_dma_pool) {
  2320. qla_printk(KERN_WARNING, ha,
  2321. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2322. goto fail_dl_dma_pool;
  2323. }
  2324. }
  2325. /* Allocate memory for SNS commands */
  2326. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2327. /* Get consistent memory allocated for SNS commands */
  2328. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2329. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2330. if (!ha->sns_cmd)
  2331. goto fail_dma_pool;
  2332. } else {
  2333. /* Get consistent memory allocated for MS IOCB */
  2334. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2335. &ha->ms_iocb_dma);
  2336. if (!ha->ms_iocb)
  2337. goto fail_dma_pool;
  2338. /* Get consistent memory allocated for CT SNS commands */
  2339. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2340. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2341. if (!ha->ct_sns)
  2342. goto fail_free_ms_iocb;
  2343. }
  2344. /* Allocate memory for request ring */
  2345. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2346. if (!*req) {
  2347. DEBUG(printk("Unable to allocate memory for req\n"));
  2348. goto fail_req;
  2349. }
  2350. (*req)->length = req_len;
  2351. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2352. ((*req)->length + 1) * sizeof(request_t),
  2353. &(*req)->dma, GFP_KERNEL);
  2354. if (!(*req)->ring) {
  2355. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2356. goto fail_req_ring;
  2357. }
  2358. /* Allocate memory for response ring */
  2359. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2360. if (!*rsp) {
  2361. qla_printk(KERN_WARNING, ha,
  2362. "Unable to allocate memory for rsp\n");
  2363. goto fail_rsp;
  2364. }
  2365. (*rsp)->hw = ha;
  2366. (*rsp)->length = rsp_len;
  2367. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2368. ((*rsp)->length + 1) * sizeof(response_t),
  2369. &(*rsp)->dma, GFP_KERNEL);
  2370. if (!(*rsp)->ring) {
  2371. qla_printk(KERN_WARNING, ha,
  2372. "Unable to allocate memory for rsp_ring\n");
  2373. goto fail_rsp_ring;
  2374. }
  2375. (*req)->rsp = *rsp;
  2376. (*rsp)->req = *req;
  2377. /* Allocate memory for NVRAM data for vports */
  2378. if (ha->nvram_npiv_size) {
  2379. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2380. ha->nvram_npiv_size, GFP_KERNEL);
  2381. if (!ha->npiv_info) {
  2382. qla_printk(KERN_WARNING, ha,
  2383. "Unable to allocate memory for npiv info\n");
  2384. goto fail_npiv_info;
  2385. }
  2386. } else
  2387. ha->npiv_info = NULL;
  2388. /* Get consistent memory allocated for EX-INIT-CB. */
  2389. if (IS_QLA8XXX_TYPE(ha)) {
  2390. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2391. &ha->ex_init_cb_dma);
  2392. if (!ha->ex_init_cb)
  2393. goto fail_ex_init_cb;
  2394. }
  2395. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2396. /* Get consistent memory allocated for Async Port-Database. */
  2397. if (!IS_FWI2_CAPABLE(ha)) {
  2398. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2399. &ha->async_pd_dma);
  2400. if (!ha->async_pd)
  2401. goto fail_async_pd;
  2402. }
  2403. INIT_LIST_HEAD(&ha->vp_list);
  2404. return 1;
  2405. fail_async_pd:
  2406. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2407. fail_ex_init_cb:
  2408. kfree(ha->npiv_info);
  2409. fail_npiv_info:
  2410. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2411. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2412. (*rsp)->ring = NULL;
  2413. (*rsp)->dma = 0;
  2414. fail_rsp_ring:
  2415. kfree(*rsp);
  2416. fail_rsp:
  2417. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2418. sizeof(request_t), (*req)->ring, (*req)->dma);
  2419. (*req)->ring = NULL;
  2420. (*req)->dma = 0;
  2421. fail_req_ring:
  2422. kfree(*req);
  2423. fail_req:
  2424. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2425. ha->ct_sns, ha->ct_sns_dma);
  2426. ha->ct_sns = NULL;
  2427. ha->ct_sns_dma = 0;
  2428. fail_free_ms_iocb:
  2429. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2430. ha->ms_iocb = NULL;
  2431. ha->ms_iocb_dma = 0;
  2432. fail_dma_pool:
  2433. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2434. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2435. ha->fcp_cmnd_dma_pool = NULL;
  2436. }
  2437. fail_dl_dma_pool:
  2438. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2439. dma_pool_destroy(ha->dl_dma_pool);
  2440. ha->dl_dma_pool = NULL;
  2441. }
  2442. fail_s_dma_pool:
  2443. dma_pool_destroy(ha->s_dma_pool);
  2444. ha->s_dma_pool = NULL;
  2445. fail_free_nvram:
  2446. kfree(ha->nvram);
  2447. ha->nvram = NULL;
  2448. fail_free_ctx_mempool:
  2449. mempool_destroy(ha->ctx_mempool);
  2450. ha->ctx_mempool = NULL;
  2451. fail_free_srb_mempool:
  2452. mempool_destroy(ha->srb_mempool);
  2453. ha->srb_mempool = NULL;
  2454. fail_free_gid_list:
  2455. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2456. ha->gid_list_dma);
  2457. ha->gid_list = NULL;
  2458. ha->gid_list_dma = 0;
  2459. fail_free_init_cb:
  2460. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2461. ha->init_cb_dma);
  2462. ha->init_cb = NULL;
  2463. ha->init_cb_dma = 0;
  2464. fail:
  2465. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2466. return -ENOMEM;
  2467. }
  2468. /*
  2469. * qla2x00_mem_free
  2470. * Frees all adapter allocated memory.
  2471. *
  2472. * Input:
  2473. * ha = adapter block pointer.
  2474. */
  2475. static void
  2476. qla2x00_mem_free(struct qla_hw_data *ha)
  2477. {
  2478. if (ha->srb_mempool)
  2479. mempool_destroy(ha->srb_mempool);
  2480. if (ha->fce)
  2481. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2482. ha->fce_dma);
  2483. if (ha->fw_dump) {
  2484. if (ha->eft)
  2485. dma_free_coherent(&ha->pdev->dev,
  2486. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2487. vfree(ha->fw_dump);
  2488. }
  2489. if (ha->dcbx_tlv)
  2490. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2491. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2492. if (ha->xgmac_data)
  2493. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2494. ha->xgmac_data, ha->xgmac_data_dma);
  2495. if (ha->sns_cmd)
  2496. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2497. ha->sns_cmd, ha->sns_cmd_dma);
  2498. if (ha->ct_sns)
  2499. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2500. ha->ct_sns, ha->ct_sns_dma);
  2501. if (ha->sfp_data)
  2502. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2503. if (ha->edc_data)
  2504. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2505. if (ha->ms_iocb)
  2506. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2507. if (ha->ex_init_cb)
  2508. dma_pool_free(ha->s_dma_pool,
  2509. ha->ex_init_cb, ha->ex_init_cb_dma);
  2510. if (ha->async_pd)
  2511. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2512. if (ha->s_dma_pool)
  2513. dma_pool_destroy(ha->s_dma_pool);
  2514. if (ha->gid_list)
  2515. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2516. ha->gid_list_dma);
  2517. if (IS_QLA82XX(ha)) {
  2518. if (!list_empty(&ha->gbl_dsd_list)) {
  2519. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2520. /* clean up allocated prev pool */
  2521. list_for_each_entry_safe(dsd_ptr,
  2522. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2523. dma_pool_free(ha->dl_dma_pool,
  2524. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2525. list_del(&dsd_ptr->list);
  2526. kfree(dsd_ptr);
  2527. }
  2528. }
  2529. }
  2530. if (ha->dl_dma_pool)
  2531. dma_pool_destroy(ha->dl_dma_pool);
  2532. if (ha->fcp_cmnd_dma_pool)
  2533. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2534. if (ha->ctx_mempool)
  2535. mempool_destroy(ha->ctx_mempool);
  2536. if (ha->init_cb)
  2537. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2538. ha->init_cb, ha->init_cb_dma);
  2539. vfree(ha->optrom_buffer);
  2540. kfree(ha->nvram);
  2541. kfree(ha->npiv_info);
  2542. ha->srb_mempool = NULL;
  2543. ha->ctx_mempool = NULL;
  2544. ha->eft = NULL;
  2545. ha->eft_dma = 0;
  2546. ha->sns_cmd = NULL;
  2547. ha->sns_cmd_dma = 0;
  2548. ha->ct_sns = NULL;
  2549. ha->ct_sns_dma = 0;
  2550. ha->ms_iocb = NULL;
  2551. ha->ms_iocb_dma = 0;
  2552. ha->init_cb = NULL;
  2553. ha->init_cb_dma = 0;
  2554. ha->ex_init_cb = NULL;
  2555. ha->ex_init_cb_dma = 0;
  2556. ha->async_pd = NULL;
  2557. ha->async_pd_dma = 0;
  2558. ha->s_dma_pool = NULL;
  2559. ha->dl_dma_pool = NULL;
  2560. ha->fcp_cmnd_dma_pool = NULL;
  2561. ha->gid_list = NULL;
  2562. ha->gid_list_dma = 0;
  2563. ha->fw_dump = NULL;
  2564. ha->fw_dumped = 0;
  2565. ha->fw_dump_reading = 0;
  2566. }
  2567. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2568. struct qla_hw_data *ha)
  2569. {
  2570. struct Scsi_Host *host;
  2571. struct scsi_qla_host *vha = NULL;
  2572. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2573. if (host == NULL) {
  2574. printk(KERN_WARNING
  2575. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2576. goto fail;
  2577. }
  2578. /* Clear our data area */
  2579. vha = shost_priv(host);
  2580. memset(vha, 0, sizeof(scsi_qla_host_t));
  2581. vha->host = host;
  2582. vha->host_no = host->host_no;
  2583. vha->hw = ha;
  2584. INIT_LIST_HEAD(&vha->vp_fcports);
  2585. INIT_LIST_HEAD(&vha->work_list);
  2586. INIT_LIST_HEAD(&vha->list);
  2587. spin_lock_init(&vha->work_lock);
  2588. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2589. return vha;
  2590. fail:
  2591. return vha;
  2592. }
  2593. static struct qla_work_evt *
  2594. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2595. {
  2596. struct qla_work_evt *e;
  2597. uint8_t bail;
  2598. QLA_VHA_MARK_BUSY(vha, bail);
  2599. if (bail)
  2600. return NULL;
  2601. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2602. if (!e) {
  2603. QLA_VHA_MARK_NOT_BUSY(vha);
  2604. return NULL;
  2605. }
  2606. INIT_LIST_HEAD(&e->list);
  2607. e->type = type;
  2608. e->flags = QLA_EVT_FLAG_FREE;
  2609. return e;
  2610. }
  2611. static int
  2612. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2613. {
  2614. unsigned long flags;
  2615. spin_lock_irqsave(&vha->work_lock, flags);
  2616. list_add_tail(&e->list, &vha->work_list);
  2617. spin_unlock_irqrestore(&vha->work_lock, flags);
  2618. qla2xxx_wake_dpc(vha);
  2619. return QLA_SUCCESS;
  2620. }
  2621. int
  2622. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2623. u32 data)
  2624. {
  2625. struct qla_work_evt *e;
  2626. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2627. if (!e)
  2628. return QLA_FUNCTION_FAILED;
  2629. e->u.aen.code = code;
  2630. e->u.aen.data = data;
  2631. return qla2x00_post_work(vha, e);
  2632. }
  2633. int
  2634. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2635. {
  2636. struct qla_work_evt *e;
  2637. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2638. if (!e)
  2639. return QLA_FUNCTION_FAILED;
  2640. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2641. return qla2x00_post_work(vha, e);
  2642. }
  2643. #define qla2x00_post_async_work(name, type) \
  2644. int qla2x00_post_async_##name##_work( \
  2645. struct scsi_qla_host *vha, \
  2646. fc_port_t *fcport, uint16_t *data) \
  2647. { \
  2648. struct qla_work_evt *e; \
  2649. \
  2650. e = qla2x00_alloc_work(vha, type); \
  2651. if (!e) \
  2652. return QLA_FUNCTION_FAILED; \
  2653. \
  2654. e->u.logio.fcport = fcport; \
  2655. if (data) { \
  2656. e->u.logio.data[0] = data[0]; \
  2657. e->u.logio.data[1] = data[1]; \
  2658. } \
  2659. return qla2x00_post_work(vha, e); \
  2660. }
  2661. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2662. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2663. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2664. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2665. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2666. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2667. int
  2668. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2669. {
  2670. struct qla_work_evt *e;
  2671. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2672. if (!e)
  2673. return QLA_FUNCTION_FAILED;
  2674. e->u.uevent.code = code;
  2675. return qla2x00_post_work(vha, e);
  2676. }
  2677. static void
  2678. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2679. {
  2680. char event_string[40];
  2681. char *envp[] = { event_string, NULL };
  2682. switch (code) {
  2683. case QLA_UEVENT_CODE_FW_DUMP:
  2684. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2685. vha->host_no);
  2686. break;
  2687. default:
  2688. /* do nothing */
  2689. break;
  2690. }
  2691. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2692. }
  2693. void
  2694. qla2x00_do_work(struct scsi_qla_host *vha)
  2695. {
  2696. struct qla_work_evt *e, *tmp;
  2697. unsigned long flags;
  2698. LIST_HEAD(work);
  2699. spin_lock_irqsave(&vha->work_lock, flags);
  2700. list_splice_init(&vha->work_list, &work);
  2701. spin_unlock_irqrestore(&vha->work_lock, flags);
  2702. list_for_each_entry_safe(e, tmp, &work, list) {
  2703. list_del_init(&e->list);
  2704. switch (e->type) {
  2705. case QLA_EVT_AEN:
  2706. fc_host_post_event(vha->host, fc_get_event_number(),
  2707. e->u.aen.code, e->u.aen.data);
  2708. break;
  2709. case QLA_EVT_IDC_ACK:
  2710. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2711. break;
  2712. case QLA_EVT_ASYNC_LOGIN:
  2713. qla2x00_async_login(vha, e->u.logio.fcport,
  2714. e->u.logio.data);
  2715. break;
  2716. case QLA_EVT_ASYNC_LOGIN_DONE:
  2717. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2718. e->u.logio.data);
  2719. break;
  2720. case QLA_EVT_ASYNC_LOGOUT:
  2721. qla2x00_async_logout(vha, e->u.logio.fcport);
  2722. break;
  2723. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2724. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2725. e->u.logio.data);
  2726. break;
  2727. case QLA_EVT_ASYNC_ADISC:
  2728. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2729. e->u.logio.data);
  2730. break;
  2731. case QLA_EVT_ASYNC_ADISC_DONE:
  2732. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2733. e->u.logio.data);
  2734. break;
  2735. case QLA_EVT_UEVENT:
  2736. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2737. break;
  2738. }
  2739. if (e->flags & QLA_EVT_FLAG_FREE)
  2740. kfree(e);
  2741. /* For each work completed decrement vha ref count */
  2742. QLA_VHA_MARK_NOT_BUSY(vha);
  2743. }
  2744. }
  2745. /* Relogins all the fcports of a vport
  2746. * Context: dpc thread
  2747. */
  2748. void qla2x00_relogin(struct scsi_qla_host *vha)
  2749. {
  2750. fc_port_t *fcport;
  2751. int status;
  2752. uint16_t next_loopid = 0;
  2753. struct qla_hw_data *ha = vha->hw;
  2754. uint16_t data[2];
  2755. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2756. /*
  2757. * If the port is not ONLINE then try to login
  2758. * to it if we haven't run out of retries.
  2759. */
  2760. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2761. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2762. fcport->login_retry--;
  2763. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2764. if (fcport->flags & FCF_FCP2_DEVICE)
  2765. ha->isp_ops->fabric_logout(vha,
  2766. fcport->loop_id,
  2767. fcport->d_id.b.domain,
  2768. fcport->d_id.b.area,
  2769. fcport->d_id.b.al_pa);
  2770. if (IS_ALOGIO_CAPABLE(ha)) {
  2771. fcport->flags |= FCF_ASYNC_SENT;
  2772. data[0] = 0;
  2773. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2774. status = qla2x00_post_async_login_work(
  2775. vha, fcport, data);
  2776. if (status == QLA_SUCCESS)
  2777. continue;
  2778. /* Attempt a retry. */
  2779. status = 1;
  2780. } else
  2781. status = qla2x00_fabric_login(vha,
  2782. fcport, &next_loopid);
  2783. } else
  2784. status = qla2x00_local_device_login(vha,
  2785. fcport);
  2786. if (status == QLA_SUCCESS) {
  2787. fcport->old_loop_id = fcport->loop_id;
  2788. DEBUG(printk("scsi(%ld): port login OK: logged "
  2789. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2790. qla2x00_update_fcport(vha, fcport);
  2791. } else if (status == 1) {
  2792. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2793. /* retry the login again */
  2794. DEBUG(printk("scsi(%ld): Retrying"
  2795. " %d login again loop_id 0x%x\n",
  2796. vha->host_no, fcport->login_retry,
  2797. fcport->loop_id));
  2798. } else {
  2799. fcport->login_retry = 0;
  2800. }
  2801. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2802. fcport->loop_id = FC_NO_LOOP_ID;
  2803. }
  2804. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2805. break;
  2806. }
  2807. }
  2808. /**************************************************************************
  2809. * qla2x00_do_dpc
  2810. * This kernel thread is a task that is schedule by the interrupt handler
  2811. * to perform the background processing for interrupts.
  2812. *
  2813. * Notes:
  2814. * This task always run in the context of a kernel thread. It
  2815. * is kick-off by the driver's detect code and starts up
  2816. * up one per adapter. It immediately goes to sleep and waits for
  2817. * some fibre event. When either the interrupt handler or
  2818. * the timer routine detects a event it will one of the task
  2819. * bits then wake us up.
  2820. **************************************************************************/
  2821. static int
  2822. qla2x00_do_dpc(void *data)
  2823. {
  2824. int rval;
  2825. scsi_qla_host_t *base_vha;
  2826. struct qla_hw_data *ha;
  2827. ha = (struct qla_hw_data *)data;
  2828. base_vha = pci_get_drvdata(ha->pdev);
  2829. set_user_nice(current, -20);
  2830. while (!kthread_should_stop()) {
  2831. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2832. set_current_state(TASK_INTERRUPTIBLE);
  2833. schedule();
  2834. __set_current_state(TASK_RUNNING);
  2835. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2836. /* Initialization not yet finished. Don't do anything yet. */
  2837. if (!base_vha->flags.init_done)
  2838. continue;
  2839. if (ha->flags.eeh_busy) {
  2840. DEBUG17(qla_printk(KERN_WARNING, ha,
  2841. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2842. base_vha->dpc_flags));
  2843. continue;
  2844. }
  2845. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2846. ha->dpc_active = 1;
  2847. if (ha->flags.mbox_busy) {
  2848. ha->dpc_active = 0;
  2849. continue;
  2850. }
  2851. qla2x00_do_work(base_vha);
  2852. if (IS_QLA82XX(ha)) {
  2853. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2854. &base_vha->dpc_flags)) {
  2855. qla82xx_idc_lock(ha);
  2856. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2857. QLA82XX_DEV_FAILED);
  2858. qla82xx_idc_unlock(ha);
  2859. qla_printk(KERN_INFO, ha,
  2860. "HW State: FAILED\n");
  2861. qla82xx_device_state_handler(base_vha);
  2862. continue;
  2863. }
  2864. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2865. &base_vha->dpc_flags)) {
  2866. DEBUG(printk(KERN_INFO
  2867. "scsi(%ld): dpc: sched "
  2868. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2869. base_vha->host_no, ha));
  2870. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2871. &base_vha->dpc_flags))) {
  2872. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2873. /* FCoE-ctx reset failed.
  2874. * Escalate to chip-reset
  2875. */
  2876. set_bit(ISP_ABORT_NEEDED,
  2877. &base_vha->dpc_flags);
  2878. }
  2879. clear_bit(ABORT_ISP_ACTIVE,
  2880. &base_vha->dpc_flags);
  2881. }
  2882. DEBUG(printk("scsi(%ld): dpc:"
  2883. " qla82xx_fcoe_ctx_reset end\n",
  2884. base_vha->host_no));
  2885. }
  2886. }
  2887. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2888. &base_vha->dpc_flags)) {
  2889. DEBUG(printk("scsi(%ld): dpc: sched "
  2890. "qla2x00_abort_isp ha = %p\n",
  2891. base_vha->host_no, ha));
  2892. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2893. &base_vha->dpc_flags))) {
  2894. if (ha->isp_ops->abort_isp(base_vha)) {
  2895. /* failed. retry later */
  2896. set_bit(ISP_ABORT_NEEDED,
  2897. &base_vha->dpc_flags);
  2898. }
  2899. clear_bit(ABORT_ISP_ACTIVE,
  2900. &base_vha->dpc_flags);
  2901. }
  2902. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2903. base_vha->host_no));
  2904. }
  2905. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2906. qla2x00_update_fcports(base_vha);
  2907. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2908. }
  2909. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2910. &base_vha->dpc_flags) &&
  2911. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2912. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2913. base_vha->host_no));
  2914. qla2x00_rst_aen(base_vha);
  2915. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2916. }
  2917. /* Retry each device up to login retry count */
  2918. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2919. &base_vha->dpc_flags)) &&
  2920. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2921. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2922. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2923. base_vha->host_no));
  2924. qla2x00_relogin(base_vha);
  2925. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2926. base_vha->host_no));
  2927. }
  2928. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2929. &base_vha->dpc_flags)) {
  2930. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2931. base_vha->host_no));
  2932. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2933. &base_vha->dpc_flags))) {
  2934. rval = qla2x00_loop_resync(base_vha);
  2935. clear_bit(LOOP_RESYNC_ACTIVE,
  2936. &base_vha->dpc_flags);
  2937. }
  2938. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2939. base_vha->host_no));
  2940. }
  2941. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2942. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  2943. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  2944. qla2xxx_flash_npiv_conf(base_vha);
  2945. }
  2946. if (!ha->interrupts_on)
  2947. ha->isp_ops->enable_intrs(ha);
  2948. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  2949. &base_vha->dpc_flags))
  2950. ha->isp_ops->beacon_blink(base_vha);
  2951. qla2x00_do_dpc_all_vps(base_vha);
  2952. ha->dpc_active = 0;
  2953. } /* End of while(1) */
  2954. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  2955. /*
  2956. * Make sure that nobody tries to wake us up again.
  2957. */
  2958. ha->dpc_active = 0;
  2959. /* Cleanup any residual CTX SRBs. */
  2960. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2961. return 0;
  2962. }
  2963. void
  2964. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  2965. {
  2966. struct qla_hw_data *ha = vha->hw;
  2967. struct task_struct *t = ha->dpc_thread;
  2968. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  2969. wake_up_process(t);
  2970. }
  2971. /*
  2972. * qla2x00_rst_aen
  2973. * Processes asynchronous reset.
  2974. *
  2975. * Input:
  2976. * ha = adapter block pointer.
  2977. */
  2978. static void
  2979. qla2x00_rst_aen(scsi_qla_host_t *vha)
  2980. {
  2981. if (vha->flags.online && !vha->flags.reset_active &&
  2982. !atomic_read(&vha->loop_down_timer) &&
  2983. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  2984. do {
  2985. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  2986. /*
  2987. * Issue marker command only when we are going to start
  2988. * the I/O.
  2989. */
  2990. vha->marker_needed = 1;
  2991. } while (!atomic_read(&vha->loop_down_timer) &&
  2992. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  2993. }
  2994. }
  2995. static void
  2996. qla2x00_sp_free_dma(srb_t *sp)
  2997. {
  2998. struct scsi_cmnd *cmd = sp->cmd;
  2999. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3000. if (sp->flags & SRB_DMA_VALID) {
  3001. scsi_dma_unmap(cmd);
  3002. sp->flags &= ~SRB_DMA_VALID;
  3003. }
  3004. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3005. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3006. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3007. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3008. }
  3009. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3010. /* List assured to be having elements */
  3011. qla2x00_clean_dsd_pool(ha, sp);
  3012. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3013. }
  3014. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3015. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3016. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3017. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3018. }
  3019. CMD_SP(cmd) = NULL;
  3020. }
  3021. static void
  3022. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3023. {
  3024. struct scsi_cmnd *cmd = sp->cmd;
  3025. qla2x00_sp_free_dma(sp);
  3026. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3027. struct ct6_dsd *ctx = sp->ctx;
  3028. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3029. ctx->fcp_cmnd_dma);
  3030. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3031. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3032. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3033. mempool_free(sp->ctx, ha->ctx_mempool);
  3034. sp->ctx = NULL;
  3035. }
  3036. mempool_free(sp, ha->srb_mempool);
  3037. cmd->scsi_done(cmd);
  3038. }
  3039. void
  3040. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3041. {
  3042. if (atomic_read(&sp->ref_count) == 0) {
  3043. DEBUG2(qla_printk(KERN_WARNING, ha,
  3044. "SP reference-count to ZERO -- sp=%p\n", sp));
  3045. DEBUG2(BUG());
  3046. return;
  3047. }
  3048. if (!atomic_dec_and_test(&sp->ref_count))
  3049. return;
  3050. qla2x00_sp_final_compl(ha, sp);
  3051. }
  3052. /**************************************************************************
  3053. * qla2x00_timer
  3054. *
  3055. * Description:
  3056. * One second timer
  3057. *
  3058. * Context: Interrupt
  3059. ***************************************************************************/
  3060. void
  3061. qla2x00_timer(scsi_qla_host_t *vha)
  3062. {
  3063. unsigned long cpu_flags = 0;
  3064. int start_dpc = 0;
  3065. int index;
  3066. srb_t *sp;
  3067. uint16_t w;
  3068. struct qla_hw_data *ha = vha->hw;
  3069. struct req_que *req;
  3070. if (ha->flags.eeh_busy) {
  3071. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3072. return;
  3073. }
  3074. if (IS_QLA82XX(ha))
  3075. qla82xx_watchdog(vha);
  3076. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3077. if (!pci_channel_offline(ha->pdev))
  3078. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3079. /* Loop down handler. */
  3080. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3081. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
  3082. && vha->flags.online) {
  3083. if (atomic_read(&vha->loop_down_timer) ==
  3084. vha->loop_down_abort_time) {
  3085. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3086. "queues before time expire\n",
  3087. vha->host_no));
  3088. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3089. atomic_set(&vha->loop_state, LOOP_DEAD);
  3090. /*
  3091. * Schedule an ISP abort to return any FCP2-device
  3092. * commands.
  3093. */
  3094. /* NPIV - scan physical port only */
  3095. if (!vha->vp_idx) {
  3096. spin_lock_irqsave(&ha->hardware_lock,
  3097. cpu_flags);
  3098. req = ha->req_q_map[0];
  3099. for (index = 1;
  3100. index < MAX_OUTSTANDING_COMMANDS;
  3101. index++) {
  3102. fc_port_t *sfcp;
  3103. sp = req->outstanding_cmds[index];
  3104. if (!sp)
  3105. continue;
  3106. if (sp->ctx && !IS_PROT_IO(sp))
  3107. continue;
  3108. sfcp = sp->fcport;
  3109. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3110. continue;
  3111. set_bit(ISP_ABORT_NEEDED,
  3112. &vha->dpc_flags);
  3113. break;
  3114. }
  3115. spin_unlock_irqrestore(&ha->hardware_lock,
  3116. cpu_flags);
  3117. }
  3118. start_dpc++;
  3119. }
  3120. /* if the loop has been down for 4 minutes, reinit adapter */
  3121. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3122. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3123. DEBUG(printk("scsi(%ld): Loop down - "
  3124. "aborting ISP.\n",
  3125. vha->host_no));
  3126. qla_printk(KERN_WARNING, ha,
  3127. "Loop down - aborting ISP.\n");
  3128. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3129. }
  3130. }
  3131. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3132. vha->host_no,
  3133. atomic_read(&vha->loop_down_timer)));
  3134. }
  3135. /* Check if beacon LED needs to be blinked */
  3136. if (ha->beacon_blink_led == 1) {
  3137. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3138. start_dpc++;
  3139. }
  3140. /* Process any deferred work. */
  3141. if (!list_empty(&vha->work_list))
  3142. start_dpc++;
  3143. /* Schedule the DPC routine if needed */
  3144. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3145. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3146. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3147. start_dpc ||
  3148. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3149. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3150. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3151. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3152. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3153. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3154. qla2xxx_wake_dpc(vha);
  3155. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3156. }
  3157. /* Firmware interface routines. */
  3158. #define FW_BLOBS 8
  3159. #define FW_ISP21XX 0
  3160. #define FW_ISP22XX 1
  3161. #define FW_ISP2300 2
  3162. #define FW_ISP2322 3
  3163. #define FW_ISP24XX 4
  3164. #define FW_ISP25XX 5
  3165. #define FW_ISP81XX 6
  3166. #define FW_ISP82XX 7
  3167. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3168. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3169. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3170. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3171. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3172. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3173. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3174. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3175. static DEFINE_MUTEX(qla_fw_lock);
  3176. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3177. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3178. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3179. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3180. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3181. { .name = FW_FILE_ISP24XX, },
  3182. { .name = FW_FILE_ISP25XX, },
  3183. { .name = FW_FILE_ISP81XX, },
  3184. { .name = FW_FILE_ISP82XX, },
  3185. };
  3186. struct fw_blob *
  3187. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3188. {
  3189. struct qla_hw_data *ha = vha->hw;
  3190. struct fw_blob *blob;
  3191. blob = NULL;
  3192. if (IS_QLA2100(ha)) {
  3193. blob = &qla_fw_blobs[FW_ISP21XX];
  3194. } else if (IS_QLA2200(ha)) {
  3195. blob = &qla_fw_blobs[FW_ISP22XX];
  3196. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3197. blob = &qla_fw_blobs[FW_ISP2300];
  3198. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3199. blob = &qla_fw_blobs[FW_ISP2322];
  3200. } else if (IS_QLA24XX_TYPE(ha)) {
  3201. blob = &qla_fw_blobs[FW_ISP24XX];
  3202. } else if (IS_QLA25XX(ha)) {
  3203. blob = &qla_fw_blobs[FW_ISP25XX];
  3204. } else if (IS_QLA81XX(ha)) {
  3205. blob = &qla_fw_blobs[FW_ISP81XX];
  3206. } else if (IS_QLA82XX(ha)) {
  3207. blob = &qla_fw_blobs[FW_ISP82XX];
  3208. }
  3209. mutex_lock(&qla_fw_lock);
  3210. if (blob->fw)
  3211. goto out;
  3212. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3213. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3214. "(%s).\n", vha->host_no, blob->name));
  3215. blob->fw = NULL;
  3216. blob = NULL;
  3217. goto out;
  3218. }
  3219. out:
  3220. mutex_unlock(&qla_fw_lock);
  3221. return blob;
  3222. }
  3223. static void
  3224. qla2x00_release_firmware(void)
  3225. {
  3226. int idx;
  3227. mutex_lock(&qla_fw_lock);
  3228. for (idx = 0; idx < FW_BLOBS; idx++)
  3229. if (qla_fw_blobs[idx].fw)
  3230. release_firmware(qla_fw_blobs[idx].fw);
  3231. mutex_unlock(&qla_fw_lock);
  3232. }
  3233. static pci_ers_result_t
  3234. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3235. {
  3236. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3237. struct qla_hw_data *ha = vha->hw;
  3238. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3239. state));
  3240. switch (state) {
  3241. case pci_channel_io_normal:
  3242. ha->flags.eeh_busy = 0;
  3243. return PCI_ERS_RESULT_CAN_RECOVER;
  3244. case pci_channel_io_frozen:
  3245. ha->flags.eeh_busy = 1;
  3246. /* For ISP82XX complete any pending mailbox cmd */
  3247. if (IS_QLA82XX(ha)) {
  3248. ha->flags.fw_hung = 1;
  3249. if (ha->flags.mbox_busy) {
  3250. ha->flags.mbox_int = 1;
  3251. DEBUG2(qla_printk(KERN_ERR, ha,
  3252. "Due to pci channel io frozen, doing premature "
  3253. "completion of mbx command\n"));
  3254. complete(&ha->mbx_intr_comp);
  3255. }
  3256. }
  3257. qla2x00_free_irqs(vha);
  3258. pci_disable_device(pdev);
  3259. /* Return back all IOs */
  3260. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3261. return PCI_ERS_RESULT_NEED_RESET;
  3262. case pci_channel_io_perm_failure:
  3263. ha->flags.pci_channel_io_perm_failure = 1;
  3264. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3265. return PCI_ERS_RESULT_DISCONNECT;
  3266. }
  3267. return PCI_ERS_RESULT_NEED_RESET;
  3268. }
  3269. static pci_ers_result_t
  3270. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3271. {
  3272. int risc_paused = 0;
  3273. uint32_t stat;
  3274. unsigned long flags;
  3275. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3276. struct qla_hw_data *ha = base_vha->hw;
  3277. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3278. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3279. if (IS_QLA82XX(ha))
  3280. return PCI_ERS_RESULT_RECOVERED;
  3281. spin_lock_irqsave(&ha->hardware_lock, flags);
  3282. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3283. stat = RD_REG_DWORD(&reg->hccr);
  3284. if (stat & HCCR_RISC_PAUSE)
  3285. risc_paused = 1;
  3286. } else if (IS_QLA23XX(ha)) {
  3287. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3288. if (stat & HSR_RISC_PAUSED)
  3289. risc_paused = 1;
  3290. } else if (IS_FWI2_CAPABLE(ha)) {
  3291. stat = RD_REG_DWORD(&reg24->host_status);
  3292. if (stat & HSRX_RISC_PAUSED)
  3293. risc_paused = 1;
  3294. }
  3295. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3296. if (risc_paused) {
  3297. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3298. "Dumping firmware!\n");
  3299. ha->isp_ops->fw_dump(base_vha, 0);
  3300. return PCI_ERS_RESULT_NEED_RESET;
  3301. } else
  3302. return PCI_ERS_RESULT_RECOVERED;
  3303. }
  3304. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3305. {
  3306. uint32_t rval = QLA_FUNCTION_FAILED;
  3307. uint32_t drv_active = 0;
  3308. struct qla_hw_data *ha = base_vha->hw;
  3309. int fn;
  3310. struct pci_dev *other_pdev = NULL;
  3311. DEBUG17(qla_printk(KERN_INFO, ha,
  3312. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3313. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3314. if (base_vha->flags.online) {
  3315. /* Abort all outstanding commands,
  3316. * so as to be requeued later */
  3317. qla2x00_abort_isp_cleanup(base_vha);
  3318. }
  3319. fn = PCI_FUNC(ha->pdev->devfn);
  3320. while (fn > 0) {
  3321. fn--;
  3322. DEBUG17(qla_printk(KERN_INFO, ha,
  3323. "Finding pci device at function = 0x%x\n", fn));
  3324. other_pdev =
  3325. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3326. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3327. fn));
  3328. if (!other_pdev)
  3329. continue;
  3330. if (atomic_read(&other_pdev->enable_cnt)) {
  3331. DEBUG17(qla_printk(KERN_INFO, ha,
  3332. "Found PCI func availabe and enabled at 0x%x\n",
  3333. fn));
  3334. pci_dev_put(other_pdev);
  3335. break;
  3336. }
  3337. pci_dev_put(other_pdev);
  3338. }
  3339. if (!fn) {
  3340. /* Reset owner */
  3341. DEBUG17(qla_printk(KERN_INFO, ha,
  3342. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3343. qla82xx_idc_lock(ha);
  3344. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3345. QLA82XX_DEV_INITIALIZING);
  3346. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3347. QLA82XX_IDC_VERSION);
  3348. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3349. DEBUG17(qla_printk(KERN_INFO, ha,
  3350. "drv_active = 0x%x\n", drv_active));
  3351. qla82xx_idc_unlock(ha);
  3352. /* Reset if device is not already reset
  3353. * drv_active would be 0 if a reset has already been done
  3354. */
  3355. if (drv_active)
  3356. rval = qla82xx_start_firmware(base_vha);
  3357. else
  3358. rval = QLA_SUCCESS;
  3359. qla82xx_idc_lock(ha);
  3360. if (rval != QLA_SUCCESS) {
  3361. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3362. qla82xx_clear_drv_active(ha);
  3363. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3364. QLA82XX_DEV_FAILED);
  3365. } else {
  3366. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3367. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3368. QLA82XX_DEV_READY);
  3369. qla82xx_idc_unlock(ha);
  3370. ha->flags.fw_hung = 0;
  3371. rval = qla82xx_restart_isp(base_vha);
  3372. qla82xx_idc_lock(ha);
  3373. /* Clear driver state register */
  3374. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3375. qla82xx_set_drv_active(base_vha);
  3376. }
  3377. qla82xx_idc_unlock(ha);
  3378. } else {
  3379. DEBUG17(qla_printk(KERN_INFO, ha,
  3380. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3381. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3382. QLA82XX_DEV_READY)) {
  3383. ha->flags.fw_hung = 0;
  3384. rval = qla82xx_restart_isp(base_vha);
  3385. qla82xx_idc_lock(ha);
  3386. qla82xx_set_drv_active(base_vha);
  3387. qla82xx_idc_unlock(ha);
  3388. }
  3389. }
  3390. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3391. return rval;
  3392. }
  3393. static pci_ers_result_t
  3394. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3395. {
  3396. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3397. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3398. struct qla_hw_data *ha = base_vha->hw;
  3399. struct rsp_que *rsp;
  3400. int rc, retries = 10;
  3401. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3402. /* Workaround: qla2xxx driver which access hardware earlier
  3403. * needs error state to be pci_channel_io_online.
  3404. * Otherwise mailbox command timesout.
  3405. */
  3406. pdev->error_state = pci_channel_io_normal;
  3407. pci_restore_state(pdev);
  3408. /* pci_restore_state() clears the saved_state flag of the device
  3409. * save restored state which resets saved_state flag
  3410. */
  3411. pci_save_state(pdev);
  3412. if (ha->mem_only)
  3413. rc = pci_enable_device_mem(pdev);
  3414. else
  3415. rc = pci_enable_device(pdev);
  3416. if (rc) {
  3417. qla_printk(KERN_WARNING, ha,
  3418. "Can't re-enable PCI device after reset.\n");
  3419. goto exit_slot_reset;
  3420. }
  3421. rsp = ha->rsp_q_map[0];
  3422. if (qla2x00_request_irqs(ha, rsp))
  3423. goto exit_slot_reset;
  3424. if (ha->isp_ops->pci_config(base_vha))
  3425. goto exit_slot_reset;
  3426. if (IS_QLA82XX(ha)) {
  3427. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3428. ret = PCI_ERS_RESULT_RECOVERED;
  3429. goto exit_slot_reset;
  3430. } else
  3431. goto exit_slot_reset;
  3432. }
  3433. while (ha->flags.mbox_busy && retries--)
  3434. msleep(1000);
  3435. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3436. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3437. ret = PCI_ERS_RESULT_RECOVERED;
  3438. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3439. exit_slot_reset:
  3440. DEBUG17(qla_printk(KERN_WARNING, ha,
  3441. "slot_reset-return:ret=%x\n", ret));
  3442. return ret;
  3443. }
  3444. static void
  3445. qla2xxx_pci_resume(struct pci_dev *pdev)
  3446. {
  3447. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3448. struct qla_hw_data *ha = base_vha->hw;
  3449. int ret;
  3450. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3451. ret = qla2x00_wait_for_hba_online(base_vha);
  3452. if (ret != QLA_SUCCESS) {
  3453. qla_printk(KERN_ERR, ha,
  3454. "the device failed to resume I/O "
  3455. "from slot/link_reset");
  3456. }
  3457. pci_cleanup_aer_uncorrect_error_status(pdev);
  3458. ha->flags.eeh_busy = 0;
  3459. }
  3460. static struct pci_error_handlers qla2xxx_err_handler = {
  3461. .error_detected = qla2xxx_pci_error_detected,
  3462. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3463. .slot_reset = qla2xxx_pci_slot_reset,
  3464. .resume = qla2xxx_pci_resume,
  3465. };
  3466. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3467. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3468. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3469. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3470. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3471. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3472. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3473. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3474. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3475. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3476. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3477. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3478. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3479. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3480. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3481. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3482. { 0 },
  3483. };
  3484. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3485. static struct pci_driver qla2xxx_pci_driver = {
  3486. .name = QLA2XXX_DRIVER_NAME,
  3487. .driver = {
  3488. .owner = THIS_MODULE,
  3489. },
  3490. .id_table = qla2xxx_pci_tbl,
  3491. .probe = qla2x00_probe_one,
  3492. .remove = qla2x00_remove_one,
  3493. .err_handler = &qla2xxx_err_handler,
  3494. };
  3495. static struct file_operations apidev_fops = {
  3496. .owner = THIS_MODULE,
  3497. .llseek = noop_llseek,
  3498. };
  3499. /**
  3500. * qla2x00_module_init - Module initialization.
  3501. **/
  3502. static int __init
  3503. qla2x00_module_init(void)
  3504. {
  3505. int ret = 0;
  3506. /* Allocate cache for SRBs. */
  3507. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3508. SLAB_HWCACHE_ALIGN, NULL);
  3509. if (srb_cachep == NULL) {
  3510. printk(KERN_ERR
  3511. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3512. return -ENOMEM;
  3513. }
  3514. /* Derive version string. */
  3515. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3516. if (ql2xextended_error_logging)
  3517. strcat(qla2x00_version_str, "-debug");
  3518. qla2xxx_transport_template =
  3519. fc_attach_transport(&qla2xxx_transport_functions);
  3520. if (!qla2xxx_transport_template) {
  3521. kmem_cache_destroy(srb_cachep);
  3522. return -ENODEV;
  3523. }
  3524. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3525. if (apidev_major < 0) {
  3526. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3527. "%s\n", QLA2XXX_APIDEV);
  3528. }
  3529. qla2xxx_transport_vport_template =
  3530. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3531. if (!qla2xxx_transport_vport_template) {
  3532. kmem_cache_destroy(srb_cachep);
  3533. fc_release_transport(qla2xxx_transport_template);
  3534. return -ENODEV;
  3535. }
  3536. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3537. qla2x00_version_str);
  3538. ret = pci_register_driver(&qla2xxx_pci_driver);
  3539. if (ret) {
  3540. kmem_cache_destroy(srb_cachep);
  3541. fc_release_transport(qla2xxx_transport_template);
  3542. fc_release_transport(qla2xxx_transport_vport_template);
  3543. }
  3544. return ret;
  3545. }
  3546. /**
  3547. * qla2x00_module_exit - Module cleanup.
  3548. **/
  3549. static void __exit
  3550. qla2x00_module_exit(void)
  3551. {
  3552. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3553. pci_unregister_driver(&qla2xxx_pci_driver);
  3554. qla2x00_release_firmware();
  3555. kmem_cache_destroy(srb_cachep);
  3556. if (ctx_cachep)
  3557. kmem_cache_destroy(ctx_cachep);
  3558. fc_release_transport(qla2xxx_transport_template);
  3559. fc_release_transport(qla2xxx_transport_vport_template);
  3560. }
  3561. module_init(qla2x00_module_init);
  3562. module_exit(qla2x00_module_exit);
  3563. MODULE_AUTHOR("QLogic Corporation");
  3564. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3565. MODULE_LICENSE("GPL");
  3566. MODULE_VERSION(QLA2XXX_VERSION);
  3567. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3568. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3569. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3570. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3571. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3572. MODULE_FIRMWARE(FW_FILE_ISP25XX);