hpsa.c 130 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12. * NON INFRINGEMENT. See the GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. *
  18. * Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/pci.h>
  25. #include <linux/pci-aspm.h>
  26. #include <linux/kernel.h>
  27. #include <linux/slab.h>
  28. #include <linux/delay.h>
  29. #include <linux/fs.h>
  30. #include <linux/timer.h>
  31. #include <linux/seq_file.h>
  32. #include <linux/init.h>
  33. #include <linux/spinlock.h>
  34. #include <linux/compat.h>
  35. #include <linux/blktrace_api.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/completion.h>
  40. #include <linux/moduleparam.h>
  41. #include <scsi/scsi.h>
  42. #include <scsi/scsi_cmnd.h>
  43. #include <scsi/scsi_device.h>
  44. #include <scsi/scsi_host.h>
  45. #include <scsi/scsi_tcq.h>
  46. #include <linux/cciss_ioctl.h>
  47. #include <linux/string.h>
  48. #include <linux/bitmap.h>
  49. #include <linux/atomic.h>
  50. #include <linux/kthread.h>
  51. #include <linux/jiffies.h>
  52. #include "hpsa_cmd.h"
  53. #include "hpsa.h"
  54. /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
  55. #define HPSA_DRIVER_VERSION "2.0.2-1"
  56. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  57. /* How long to wait (in milliseconds) for board to go into simple mode */
  58. #define MAX_CONFIG_WAIT 30000
  59. #define MAX_IOCTL_CONFIG_WAIT 1000
  60. /*define how many times we will try a command because of bus resets */
  61. #define MAX_CMD_RETRIES 3
  62. /* Embedded module documentation macros - see modules.h */
  63. MODULE_AUTHOR("Hewlett-Packard Company");
  64. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  65. HPSA_DRIVER_VERSION);
  66. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  67. MODULE_VERSION(HPSA_DRIVER_VERSION);
  68. MODULE_LICENSE("GPL");
  69. static int hpsa_allow_any;
  70. module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
  71. MODULE_PARM_DESC(hpsa_allow_any,
  72. "Allow hpsa driver to access unknown HP Smart Array hardware");
  73. static int hpsa_simple_mode;
  74. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  75. MODULE_PARM_DESC(hpsa_simple_mode,
  76. "Use 'simple mode' rather than 'performant mode'");
  77. /* define the PCI info for the cards we can control */
  78. static const struct pci_device_id hpsa_pci_device_id[] = {
  79. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  80. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  81. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  82. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  83. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  84. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324a},
  85. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324b},
  86. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  93. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  94. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  95. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  96. {0,}
  97. };
  98. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  99. /* board_id = Subsystem Device ID & Vendor ID
  100. * product = Marketing Name for the board
  101. * access = Address of the struct of function pointers
  102. */
  103. static struct board_type products[] = {
  104. {0x3241103C, "Smart Array P212", &SA5_access},
  105. {0x3243103C, "Smart Array P410", &SA5_access},
  106. {0x3245103C, "Smart Array P410i", &SA5_access},
  107. {0x3247103C, "Smart Array P411", &SA5_access},
  108. {0x3249103C, "Smart Array P812", &SA5_access},
  109. {0x324a103C, "Smart Array P712m", &SA5_access},
  110. {0x324b103C, "Smart Array P711m", &SA5_access},
  111. {0x3350103C, "Smart Array", &SA5_access},
  112. {0x3351103C, "Smart Array", &SA5_access},
  113. {0x3352103C, "Smart Array", &SA5_access},
  114. {0x3353103C, "Smart Array", &SA5_access},
  115. {0x3354103C, "Smart Array", &SA5_access},
  116. {0x3355103C, "Smart Array", &SA5_access},
  117. {0x3356103C, "Smart Array", &SA5_access},
  118. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  119. };
  120. static int number_of_controllers;
  121. static struct list_head hpsa_ctlr_list = LIST_HEAD_INIT(hpsa_ctlr_list);
  122. static spinlock_t lockup_detector_lock;
  123. static struct task_struct *hpsa_lockup_detector;
  124. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  125. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  126. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
  127. static void start_io(struct ctlr_info *h);
  128. #ifdef CONFIG_COMPAT
  129. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
  130. #endif
  131. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  132. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
  133. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  134. static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
  135. static void fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  136. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  137. int cmd_type);
  138. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  139. static void hpsa_scan_start(struct Scsi_Host *);
  140. static int hpsa_scan_finished(struct Scsi_Host *sh,
  141. unsigned long elapsed_time);
  142. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  143. int qdepth, int reason);
  144. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  145. static int hpsa_slave_alloc(struct scsi_device *sdev);
  146. static void hpsa_slave_destroy(struct scsi_device *sdev);
  147. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
  148. static int check_for_unit_attention(struct ctlr_info *h,
  149. struct CommandList *c);
  150. static void check_ioctl_unit_attention(struct ctlr_info *h,
  151. struct CommandList *c);
  152. /* performant mode helper functions */
  153. static void calc_bucket_map(int *bucket, int num_buckets,
  154. int nsgs, int *bucket_map);
  155. static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  156. static inline u32 next_command(struct ctlr_info *h);
  157. static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
  158. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  159. u64 *cfg_offset);
  160. static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  161. unsigned long *memory_bar);
  162. static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
  163. static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
  164. void __iomem *vaddr, int wait_for_ready);
  165. #define BOARD_NOT_READY 0
  166. #define BOARD_READY 1
  167. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  168. {
  169. unsigned long *priv = shost_priv(sdev->host);
  170. return (struct ctlr_info *) *priv;
  171. }
  172. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  173. {
  174. unsigned long *priv = shost_priv(sh);
  175. return (struct ctlr_info *) *priv;
  176. }
  177. static int check_for_unit_attention(struct ctlr_info *h,
  178. struct CommandList *c)
  179. {
  180. if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
  181. return 0;
  182. switch (c->err_info->SenseInfo[12]) {
  183. case STATE_CHANGED:
  184. dev_warn(&h->pdev->dev, "hpsa%d: a state change "
  185. "detected, command retried\n", h->ctlr);
  186. break;
  187. case LUN_FAILED:
  188. dev_warn(&h->pdev->dev, "hpsa%d: LUN failure "
  189. "detected, action required\n", h->ctlr);
  190. break;
  191. case REPORT_LUNS_CHANGED:
  192. dev_warn(&h->pdev->dev, "hpsa%d: report LUN data "
  193. "changed, action required\n", h->ctlr);
  194. /*
  195. * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
  196. */
  197. break;
  198. case POWER_OR_RESET:
  199. dev_warn(&h->pdev->dev, "hpsa%d: a power on "
  200. "or device reset detected\n", h->ctlr);
  201. break;
  202. case UNIT_ATTENTION_CLEARED:
  203. dev_warn(&h->pdev->dev, "hpsa%d: unit attention "
  204. "cleared by another initiator\n", h->ctlr);
  205. break;
  206. default:
  207. dev_warn(&h->pdev->dev, "hpsa%d: unknown "
  208. "unit attention detected\n", h->ctlr);
  209. break;
  210. }
  211. return 1;
  212. }
  213. static ssize_t host_store_rescan(struct device *dev,
  214. struct device_attribute *attr,
  215. const char *buf, size_t count)
  216. {
  217. struct ctlr_info *h;
  218. struct Scsi_Host *shost = class_to_shost(dev);
  219. h = shost_to_hba(shost);
  220. hpsa_scan_start(h->scsi_host);
  221. return count;
  222. }
  223. static ssize_t host_show_firmware_revision(struct device *dev,
  224. struct device_attribute *attr, char *buf)
  225. {
  226. struct ctlr_info *h;
  227. struct Scsi_Host *shost = class_to_shost(dev);
  228. unsigned char *fwrev;
  229. h = shost_to_hba(shost);
  230. if (!h->hba_inquiry_data)
  231. return 0;
  232. fwrev = &h->hba_inquiry_data[32];
  233. return snprintf(buf, 20, "%c%c%c%c\n",
  234. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  235. }
  236. static ssize_t host_show_commands_outstanding(struct device *dev,
  237. struct device_attribute *attr, char *buf)
  238. {
  239. struct Scsi_Host *shost = class_to_shost(dev);
  240. struct ctlr_info *h = shost_to_hba(shost);
  241. return snprintf(buf, 20, "%d\n", h->commands_outstanding);
  242. }
  243. static ssize_t host_show_transport_mode(struct device *dev,
  244. struct device_attribute *attr, char *buf)
  245. {
  246. struct ctlr_info *h;
  247. struct Scsi_Host *shost = class_to_shost(dev);
  248. h = shost_to_hba(shost);
  249. return snprintf(buf, 20, "%s\n",
  250. h->transMethod & CFGTBL_Trans_Performant ?
  251. "performant" : "simple");
  252. }
  253. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  254. static u32 unresettable_controller[] = {
  255. 0x324a103C, /* Smart Array P712m */
  256. 0x324b103C, /* SmartArray P711m */
  257. 0x3223103C, /* Smart Array P800 */
  258. 0x3234103C, /* Smart Array P400 */
  259. 0x3235103C, /* Smart Array P400i */
  260. 0x3211103C, /* Smart Array E200i */
  261. 0x3212103C, /* Smart Array E200 */
  262. 0x3213103C, /* Smart Array E200i */
  263. 0x3214103C, /* Smart Array E200i */
  264. 0x3215103C, /* Smart Array E200i */
  265. 0x3237103C, /* Smart Array E500 */
  266. 0x323D103C, /* Smart Array P700m */
  267. 0x40800E11, /* Smart Array 5i */
  268. 0x409C0E11, /* Smart Array 6400 */
  269. 0x409D0E11, /* Smart Array 6400 EM */
  270. };
  271. /* List of controllers which cannot even be soft reset */
  272. static u32 soft_unresettable_controller[] = {
  273. 0x40800E11, /* Smart Array 5i */
  274. /* Exclude 640x boards. These are two pci devices in one slot
  275. * which share a battery backed cache module. One controls the
  276. * cache, the other accesses the cache through the one that controls
  277. * it. If we reset the one controlling the cache, the other will
  278. * likely not be happy. Just forbid resetting this conjoined mess.
  279. * The 640x isn't really supported by hpsa anyway.
  280. */
  281. 0x409C0E11, /* Smart Array 6400 */
  282. 0x409D0E11, /* Smart Array 6400 EM */
  283. };
  284. static int ctlr_is_hard_resettable(u32 board_id)
  285. {
  286. int i;
  287. for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
  288. if (unresettable_controller[i] == board_id)
  289. return 0;
  290. return 1;
  291. }
  292. static int ctlr_is_soft_resettable(u32 board_id)
  293. {
  294. int i;
  295. for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
  296. if (soft_unresettable_controller[i] == board_id)
  297. return 0;
  298. return 1;
  299. }
  300. static int ctlr_is_resettable(u32 board_id)
  301. {
  302. return ctlr_is_hard_resettable(board_id) ||
  303. ctlr_is_soft_resettable(board_id);
  304. }
  305. static ssize_t host_show_resettable(struct device *dev,
  306. struct device_attribute *attr, char *buf)
  307. {
  308. struct ctlr_info *h;
  309. struct Scsi_Host *shost = class_to_shost(dev);
  310. h = shost_to_hba(shost);
  311. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  312. }
  313. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  314. {
  315. return (scsi3addr[3] & 0xC0) == 0x40;
  316. }
  317. static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
  318. "UNKNOWN"
  319. };
  320. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
  321. static ssize_t raid_level_show(struct device *dev,
  322. struct device_attribute *attr, char *buf)
  323. {
  324. ssize_t l = 0;
  325. unsigned char rlevel;
  326. struct ctlr_info *h;
  327. struct scsi_device *sdev;
  328. struct hpsa_scsi_dev_t *hdev;
  329. unsigned long flags;
  330. sdev = to_scsi_device(dev);
  331. h = sdev_to_hba(sdev);
  332. spin_lock_irqsave(&h->lock, flags);
  333. hdev = sdev->hostdata;
  334. if (!hdev) {
  335. spin_unlock_irqrestore(&h->lock, flags);
  336. return -ENODEV;
  337. }
  338. /* Is this even a logical drive? */
  339. if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
  340. spin_unlock_irqrestore(&h->lock, flags);
  341. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  342. return l;
  343. }
  344. rlevel = hdev->raid_level;
  345. spin_unlock_irqrestore(&h->lock, flags);
  346. if (rlevel > RAID_UNKNOWN)
  347. rlevel = RAID_UNKNOWN;
  348. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  349. return l;
  350. }
  351. static ssize_t lunid_show(struct device *dev,
  352. struct device_attribute *attr, char *buf)
  353. {
  354. struct ctlr_info *h;
  355. struct scsi_device *sdev;
  356. struct hpsa_scsi_dev_t *hdev;
  357. unsigned long flags;
  358. unsigned char lunid[8];
  359. sdev = to_scsi_device(dev);
  360. h = sdev_to_hba(sdev);
  361. spin_lock_irqsave(&h->lock, flags);
  362. hdev = sdev->hostdata;
  363. if (!hdev) {
  364. spin_unlock_irqrestore(&h->lock, flags);
  365. return -ENODEV;
  366. }
  367. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  368. spin_unlock_irqrestore(&h->lock, flags);
  369. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  370. lunid[0], lunid[1], lunid[2], lunid[3],
  371. lunid[4], lunid[5], lunid[6], lunid[7]);
  372. }
  373. static ssize_t unique_id_show(struct device *dev,
  374. struct device_attribute *attr, char *buf)
  375. {
  376. struct ctlr_info *h;
  377. struct scsi_device *sdev;
  378. struct hpsa_scsi_dev_t *hdev;
  379. unsigned long flags;
  380. unsigned char sn[16];
  381. sdev = to_scsi_device(dev);
  382. h = sdev_to_hba(sdev);
  383. spin_lock_irqsave(&h->lock, flags);
  384. hdev = sdev->hostdata;
  385. if (!hdev) {
  386. spin_unlock_irqrestore(&h->lock, flags);
  387. return -ENODEV;
  388. }
  389. memcpy(sn, hdev->device_id, sizeof(sn));
  390. spin_unlock_irqrestore(&h->lock, flags);
  391. return snprintf(buf, 16 * 2 + 2,
  392. "%02X%02X%02X%02X%02X%02X%02X%02X"
  393. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  394. sn[0], sn[1], sn[2], sn[3],
  395. sn[4], sn[5], sn[6], sn[7],
  396. sn[8], sn[9], sn[10], sn[11],
  397. sn[12], sn[13], sn[14], sn[15]);
  398. }
  399. static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
  400. static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
  401. static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
  402. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  403. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  404. host_show_firmware_revision, NULL);
  405. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  406. host_show_commands_outstanding, NULL);
  407. static DEVICE_ATTR(transport_mode, S_IRUGO,
  408. host_show_transport_mode, NULL);
  409. static DEVICE_ATTR(resettable, S_IRUGO,
  410. host_show_resettable, NULL);
  411. static struct device_attribute *hpsa_sdev_attrs[] = {
  412. &dev_attr_raid_level,
  413. &dev_attr_lunid,
  414. &dev_attr_unique_id,
  415. NULL,
  416. };
  417. static struct device_attribute *hpsa_shost_attrs[] = {
  418. &dev_attr_rescan,
  419. &dev_attr_firmware_revision,
  420. &dev_attr_commands_outstanding,
  421. &dev_attr_transport_mode,
  422. &dev_attr_resettable,
  423. NULL,
  424. };
  425. static struct scsi_host_template hpsa_driver_template = {
  426. .module = THIS_MODULE,
  427. .name = "hpsa",
  428. .proc_name = "hpsa",
  429. .queuecommand = hpsa_scsi_queue_command,
  430. .scan_start = hpsa_scan_start,
  431. .scan_finished = hpsa_scan_finished,
  432. .change_queue_depth = hpsa_change_queue_depth,
  433. .this_id = -1,
  434. .use_clustering = ENABLE_CLUSTERING,
  435. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  436. .ioctl = hpsa_ioctl,
  437. .slave_alloc = hpsa_slave_alloc,
  438. .slave_destroy = hpsa_slave_destroy,
  439. #ifdef CONFIG_COMPAT
  440. .compat_ioctl = hpsa_compat_ioctl,
  441. #endif
  442. .sdev_attrs = hpsa_sdev_attrs,
  443. .shost_attrs = hpsa_shost_attrs,
  444. .max_sectors = 8192,
  445. };
  446. /* Enqueuing and dequeuing functions for cmdlists. */
  447. static inline void addQ(struct list_head *list, struct CommandList *c)
  448. {
  449. list_add_tail(&c->list, list);
  450. }
  451. static inline u32 next_command(struct ctlr_info *h)
  452. {
  453. u32 a;
  454. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  455. return h->access.command_completed(h);
  456. if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
  457. a = *(h->reply_pool_head); /* Next cmd in ring buffer */
  458. (h->reply_pool_head)++;
  459. h->commands_outstanding--;
  460. } else {
  461. a = FIFO_EMPTY;
  462. }
  463. /* Check for wraparound */
  464. if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
  465. h->reply_pool_head = h->reply_pool;
  466. h->reply_pool_wraparound ^= 1;
  467. }
  468. return a;
  469. }
  470. /* set_performant_mode: Modify the tag for cciss performant
  471. * set bit 0 for pull model, bits 3-1 for block fetch
  472. * register number
  473. */
  474. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
  475. {
  476. if (likely(h->transMethod & CFGTBL_Trans_Performant))
  477. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  478. }
  479. static void enqueue_cmd_and_start_io(struct ctlr_info *h,
  480. struct CommandList *c)
  481. {
  482. unsigned long flags;
  483. set_performant_mode(h, c);
  484. spin_lock_irqsave(&h->lock, flags);
  485. addQ(&h->reqQ, c);
  486. h->Qdepth++;
  487. start_io(h);
  488. spin_unlock_irqrestore(&h->lock, flags);
  489. }
  490. static inline void removeQ(struct CommandList *c)
  491. {
  492. if (WARN_ON(list_empty(&c->list)))
  493. return;
  494. list_del_init(&c->list);
  495. }
  496. static inline int is_hba_lunid(unsigned char scsi3addr[])
  497. {
  498. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  499. }
  500. static inline int is_scsi_rev_5(struct ctlr_info *h)
  501. {
  502. if (!h->hba_inquiry_data)
  503. return 0;
  504. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  505. return 1;
  506. return 0;
  507. }
  508. static int hpsa_find_target_lun(struct ctlr_info *h,
  509. unsigned char scsi3addr[], int bus, int *target, int *lun)
  510. {
  511. /* finds an unused bus, target, lun for a new physical device
  512. * assumes h->devlock is held
  513. */
  514. int i, found = 0;
  515. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  516. memset(&lun_taken[0], 0, HPSA_MAX_DEVICES >> 3);
  517. for (i = 0; i < h->ndevices; i++) {
  518. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  519. set_bit(h->dev[i]->target, lun_taken);
  520. }
  521. for (i = 0; i < HPSA_MAX_DEVICES; i++) {
  522. if (!test_bit(i, lun_taken)) {
  523. /* *bus = 1; */
  524. *target = i;
  525. *lun = 0;
  526. found = 1;
  527. break;
  528. }
  529. }
  530. return !found;
  531. }
  532. /* Add an entry into h->dev[] array. */
  533. static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
  534. struct hpsa_scsi_dev_t *device,
  535. struct hpsa_scsi_dev_t *added[], int *nadded)
  536. {
  537. /* assumes h->devlock is held */
  538. int n = h->ndevices;
  539. int i;
  540. unsigned char addr1[8], addr2[8];
  541. struct hpsa_scsi_dev_t *sd;
  542. if (n >= HPSA_MAX_DEVICES) {
  543. dev_err(&h->pdev->dev, "too many devices, some will be "
  544. "inaccessible.\n");
  545. return -1;
  546. }
  547. /* physical devices do not have lun or target assigned until now. */
  548. if (device->lun != -1)
  549. /* Logical device, lun is already assigned. */
  550. goto lun_assigned;
  551. /* If this device a non-zero lun of a multi-lun device
  552. * byte 4 of the 8-byte LUN addr will contain the logical
  553. * unit no, zero otherise.
  554. */
  555. if (device->scsi3addr[4] == 0) {
  556. /* This is not a non-zero lun of a multi-lun device */
  557. if (hpsa_find_target_lun(h, device->scsi3addr,
  558. device->bus, &device->target, &device->lun) != 0)
  559. return -1;
  560. goto lun_assigned;
  561. }
  562. /* This is a non-zero lun of a multi-lun device.
  563. * Search through our list and find the device which
  564. * has the same 8 byte LUN address, excepting byte 4.
  565. * Assign the same bus and target for this new LUN.
  566. * Use the logical unit number from the firmware.
  567. */
  568. memcpy(addr1, device->scsi3addr, 8);
  569. addr1[4] = 0;
  570. for (i = 0; i < n; i++) {
  571. sd = h->dev[i];
  572. memcpy(addr2, sd->scsi3addr, 8);
  573. addr2[4] = 0;
  574. /* differ only in byte 4? */
  575. if (memcmp(addr1, addr2, 8) == 0) {
  576. device->bus = sd->bus;
  577. device->target = sd->target;
  578. device->lun = device->scsi3addr[4];
  579. break;
  580. }
  581. }
  582. if (device->lun == -1) {
  583. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  584. " suspect firmware bug or unsupported hardware "
  585. "configuration.\n");
  586. return -1;
  587. }
  588. lun_assigned:
  589. h->dev[n] = device;
  590. h->ndevices++;
  591. added[*nadded] = device;
  592. (*nadded)++;
  593. /* initially, (before registering with scsi layer) we don't
  594. * know our hostno and we don't want to print anything first
  595. * time anyway (the scsi layer's inquiries will show that info)
  596. */
  597. /* if (hostno != -1) */
  598. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
  599. scsi_device_type(device->devtype), hostno,
  600. device->bus, device->target, device->lun);
  601. return 0;
  602. }
  603. /* Replace an entry from h->dev[] array. */
  604. static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
  605. int entry, struct hpsa_scsi_dev_t *new_entry,
  606. struct hpsa_scsi_dev_t *added[], int *nadded,
  607. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  608. {
  609. /* assumes h->devlock is held */
  610. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  611. removed[*nremoved] = h->dev[entry];
  612. (*nremoved)++;
  613. /*
  614. * New physical devices won't have target/lun assigned yet
  615. * so we need to preserve the values in the slot we are replacing.
  616. */
  617. if (new_entry->target == -1) {
  618. new_entry->target = h->dev[entry]->target;
  619. new_entry->lun = h->dev[entry]->lun;
  620. }
  621. h->dev[entry] = new_entry;
  622. added[*nadded] = new_entry;
  623. (*nadded)++;
  624. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
  625. scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
  626. new_entry->target, new_entry->lun);
  627. }
  628. /* Remove an entry from h->dev[] array. */
  629. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
  630. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  631. {
  632. /* assumes h->devlock is held */
  633. int i;
  634. struct hpsa_scsi_dev_t *sd;
  635. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  636. sd = h->dev[entry];
  637. removed[*nremoved] = h->dev[entry];
  638. (*nremoved)++;
  639. for (i = entry; i < h->ndevices-1; i++)
  640. h->dev[i] = h->dev[i+1];
  641. h->ndevices--;
  642. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
  643. scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
  644. sd->lun);
  645. }
  646. #define SCSI3ADDR_EQ(a, b) ( \
  647. (a)[7] == (b)[7] && \
  648. (a)[6] == (b)[6] && \
  649. (a)[5] == (b)[5] && \
  650. (a)[4] == (b)[4] && \
  651. (a)[3] == (b)[3] && \
  652. (a)[2] == (b)[2] && \
  653. (a)[1] == (b)[1] && \
  654. (a)[0] == (b)[0])
  655. static void fixup_botched_add(struct ctlr_info *h,
  656. struct hpsa_scsi_dev_t *added)
  657. {
  658. /* called when scsi_add_device fails in order to re-adjust
  659. * h->dev[] to match the mid layer's view.
  660. */
  661. unsigned long flags;
  662. int i, j;
  663. spin_lock_irqsave(&h->lock, flags);
  664. for (i = 0; i < h->ndevices; i++) {
  665. if (h->dev[i] == added) {
  666. for (j = i; j < h->ndevices-1; j++)
  667. h->dev[j] = h->dev[j+1];
  668. h->ndevices--;
  669. break;
  670. }
  671. }
  672. spin_unlock_irqrestore(&h->lock, flags);
  673. kfree(added);
  674. }
  675. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  676. struct hpsa_scsi_dev_t *dev2)
  677. {
  678. /* we compare everything except lun and target as these
  679. * are not yet assigned. Compare parts likely
  680. * to differ first
  681. */
  682. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  683. sizeof(dev1->scsi3addr)) != 0)
  684. return 0;
  685. if (memcmp(dev1->device_id, dev2->device_id,
  686. sizeof(dev1->device_id)) != 0)
  687. return 0;
  688. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  689. return 0;
  690. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  691. return 0;
  692. if (dev1->devtype != dev2->devtype)
  693. return 0;
  694. if (dev1->bus != dev2->bus)
  695. return 0;
  696. return 1;
  697. }
  698. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  699. * and return needle location in *index. If scsi3addr matches, but not
  700. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  701. * location in *index. If needle not found, return DEVICE_NOT_FOUND.
  702. */
  703. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  704. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  705. int *index)
  706. {
  707. int i;
  708. #define DEVICE_NOT_FOUND 0
  709. #define DEVICE_CHANGED 1
  710. #define DEVICE_SAME 2
  711. for (i = 0; i < haystack_size; i++) {
  712. if (haystack[i] == NULL) /* previously removed. */
  713. continue;
  714. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  715. *index = i;
  716. if (device_is_the_same(needle, haystack[i]))
  717. return DEVICE_SAME;
  718. else
  719. return DEVICE_CHANGED;
  720. }
  721. }
  722. *index = -1;
  723. return DEVICE_NOT_FOUND;
  724. }
  725. static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
  726. struct hpsa_scsi_dev_t *sd[], int nsds)
  727. {
  728. /* sd contains scsi3 addresses and devtypes, and inquiry
  729. * data. This function takes what's in sd to be the current
  730. * reality and updates h->dev[] to reflect that reality.
  731. */
  732. int i, entry, device_change, changes = 0;
  733. struct hpsa_scsi_dev_t *csd;
  734. unsigned long flags;
  735. struct hpsa_scsi_dev_t **added, **removed;
  736. int nadded, nremoved;
  737. struct Scsi_Host *sh = NULL;
  738. added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
  739. removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
  740. if (!added || !removed) {
  741. dev_warn(&h->pdev->dev, "out of memory in "
  742. "adjust_hpsa_scsi_table\n");
  743. goto free_and_out;
  744. }
  745. spin_lock_irqsave(&h->devlock, flags);
  746. /* find any devices in h->dev[] that are not in
  747. * sd[] and remove them from h->dev[], and for any
  748. * devices which have changed, remove the old device
  749. * info and add the new device info.
  750. */
  751. i = 0;
  752. nremoved = 0;
  753. nadded = 0;
  754. while (i < h->ndevices) {
  755. csd = h->dev[i];
  756. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  757. if (device_change == DEVICE_NOT_FOUND) {
  758. changes++;
  759. hpsa_scsi_remove_entry(h, hostno, i,
  760. removed, &nremoved);
  761. continue; /* remove ^^^, hence i not incremented */
  762. } else if (device_change == DEVICE_CHANGED) {
  763. changes++;
  764. hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
  765. added, &nadded, removed, &nremoved);
  766. /* Set it to NULL to prevent it from being freed
  767. * at the bottom of hpsa_update_scsi_devices()
  768. */
  769. sd[entry] = NULL;
  770. }
  771. i++;
  772. }
  773. /* Now, make sure every device listed in sd[] is also
  774. * listed in h->dev[], adding them if they aren't found
  775. */
  776. for (i = 0; i < nsds; i++) {
  777. if (!sd[i]) /* if already added above. */
  778. continue;
  779. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  780. h->ndevices, &entry);
  781. if (device_change == DEVICE_NOT_FOUND) {
  782. changes++;
  783. if (hpsa_scsi_add_entry(h, hostno, sd[i],
  784. added, &nadded) != 0)
  785. break;
  786. sd[i] = NULL; /* prevent from being freed later. */
  787. } else if (device_change == DEVICE_CHANGED) {
  788. /* should never happen... */
  789. changes++;
  790. dev_warn(&h->pdev->dev,
  791. "device unexpectedly changed.\n");
  792. /* but if it does happen, we just ignore that device */
  793. }
  794. }
  795. spin_unlock_irqrestore(&h->devlock, flags);
  796. /* Don't notify scsi mid layer of any changes the first time through
  797. * (or if there are no changes) scsi_scan_host will do it later the
  798. * first time through.
  799. */
  800. if (hostno == -1 || !changes)
  801. goto free_and_out;
  802. sh = h->scsi_host;
  803. /* Notify scsi mid layer of any removed devices */
  804. for (i = 0; i < nremoved; i++) {
  805. struct scsi_device *sdev =
  806. scsi_device_lookup(sh, removed[i]->bus,
  807. removed[i]->target, removed[i]->lun);
  808. if (sdev != NULL) {
  809. scsi_remove_device(sdev);
  810. scsi_device_put(sdev);
  811. } else {
  812. /* We don't expect to get here.
  813. * future cmds to this device will get selection
  814. * timeout as if the device was gone.
  815. */
  816. dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
  817. " for removal.", hostno, removed[i]->bus,
  818. removed[i]->target, removed[i]->lun);
  819. }
  820. kfree(removed[i]);
  821. removed[i] = NULL;
  822. }
  823. /* Notify scsi mid layer of any added devices */
  824. for (i = 0; i < nadded; i++) {
  825. if (scsi_add_device(sh, added[i]->bus,
  826. added[i]->target, added[i]->lun) == 0)
  827. continue;
  828. dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
  829. "device not added.\n", hostno, added[i]->bus,
  830. added[i]->target, added[i]->lun);
  831. /* now we have to remove it from h->dev,
  832. * since it didn't get added to scsi mid layer
  833. */
  834. fixup_botched_add(h, added[i]);
  835. }
  836. free_and_out:
  837. kfree(added);
  838. kfree(removed);
  839. }
  840. /*
  841. * Lookup bus/target/lun and retrun corresponding struct hpsa_scsi_dev_t *
  842. * Assume's h->devlock is held.
  843. */
  844. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  845. int bus, int target, int lun)
  846. {
  847. int i;
  848. struct hpsa_scsi_dev_t *sd;
  849. for (i = 0; i < h->ndevices; i++) {
  850. sd = h->dev[i];
  851. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  852. return sd;
  853. }
  854. return NULL;
  855. }
  856. /* link sdev->hostdata to our per-device structure. */
  857. static int hpsa_slave_alloc(struct scsi_device *sdev)
  858. {
  859. struct hpsa_scsi_dev_t *sd;
  860. unsigned long flags;
  861. struct ctlr_info *h;
  862. h = sdev_to_hba(sdev);
  863. spin_lock_irqsave(&h->devlock, flags);
  864. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  865. sdev_id(sdev), sdev->lun);
  866. if (sd != NULL)
  867. sdev->hostdata = sd;
  868. spin_unlock_irqrestore(&h->devlock, flags);
  869. return 0;
  870. }
  871. static void hpsa_slave_destroy(struct scsi_device *sdev)
  872. {
  873. /* nothing to do. */
  874. }
  875. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  876. {
  877. int i;
  878. if (!h->cmd_sg_list)
  879. return;
  880. for (i = 0; i < h->nr_cmds; i++) {
  881. kfree(h->cmd_sg_list[i]);
  882. h->cmd_sg_list[i] = NULL;
  883. }
  884. kfree(h->cmd_sg_list);
  885. h->cmd_sg_list = NULL;
  886. }
  887. static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
  888. {
  889. int i;
  890. if (h->chainsize <= 0)
  891. return 0;
  892. h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
  893. GFP_KERNEL);
  894. if (!h->cmd_sg_list)
  895. return -ENOMEM;
  896. for (i = 0; i < h->nr_cmds; i++) {
  897. h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
  898. h->chainsize, GFP_KERNEL);
  899. if (!h->cmd_sg_list[i])
  900. goto clean;
  901. }
  902. return 0;
  903. clean:
  904. hpsa_free_sg_chain_blocks(h);
  905. return -ENOMEM;
  906. }
  907. static void hpsa_map_sg_chain_block(struct ctlr_info *h,
  908. struct CommandList *c)
  909. {
  910. struct SGDescriptor *chain_sg, *chain_block;
  911. u64 temp64;
  912. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  913. chain_block = h->cmd_sg_list[c->cmdindex];
  914. chain_sg->Ext = HPSA_SG_CHAIN;
  915. chain_sg->Len = sizeof(*chain_sg) *
  916. (c->Header.SGTotal - h->max_cmd_sg_entries);
  917. temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
  918. PCI_DMA_TODEVICE);
  919. chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
  920. chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
  921. }
  922. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  923. struct CommandList *c)
  924. {
  925. struct SGDescriptor *chain_sg;
  926. union u64bit temp64;
  927. if (c->Header.SGTotal <= h->max_cmd_sg_entries)
  928. return;
  929. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  930. temp64.val32.lower = chain_sg->Addr.lower;
  931. temp64.val32.upper = chain_sg->Addr.upper;
  932. pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
  933. }
  934. static void complete_scsi_command(struct CommandList *cp)
  935. {
  936. struct scsi_cmnd *cmd;
  937. struct ctlr_info *h;
  938. struct ErrorInfo *ei;
  939. unsigned char sense_key;
  940. unsigned char asc; /* additional sense code */
  941. unsigned char ascq; /* additional sense code qualifier */
  942. unsigned long sense_data_size;
  943. ei = cp->err_info;
  944. cmd = (struct scsi_cmnd *) cp->scsi_cmd;
  945. h = cp->h;
  946. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  947. if (cp->Header.SGTotal > h->max_cmd_sg_entries)
  948. hpsa_unmap_sg_chain_block(h, cp);
  949. cmd->result = (DID_OK << 16); /* host byte */
  950. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  951. cmd->result |= ei->ScsiStatus;
  952. /* copy the sense data whether we need to or not. */
  953. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  954. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  955. else
  956. sense_data_size = sizeof(ei->SenseInfo);
  957. if (ei->SenseLen < sense_data_size)
  958. sense_data_size = ei->SenseLen;
  959. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  960. scsi_set_resid(cmd, ei->ResidualCnt);
  961. if (ei->CommandStatus == 0) {
  962. cmd->scsi_done(cmd);
  963. cmd_free(h, cp);
  964. return;
  965. }
  966. /* an error has occurred */
  967. switch (ei->CommandStatus) {
  968. case CMD_TARGET_STATUS:
  969. if (ei->ScsiStatus) {
  970. /* Get sense key */
  971. sense_key = 0xf & ei->SenseInfo[2];
  972. /* Get additional sense code */
  973. asc = ei->SenseInfo[12];
  974. /* Get addition sense code qualifier */
  975. ascq = ei->SenseInfo[13];
  976. }
  977. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  978. if (check_for_unit_attention(h, cp)) {
  979. cmd->result = DID_SOFT_ERROR << 16;
  980. break;
  981. }
  982. if (sense_key == ILLEGAL_REQUEST) {
  983. /*
  984. * SCSI REPORT_LUNS is commonly unsupported on
  985. * Smart Array. Suppress noisy complaint.
  986. */
  987. if (cp->Request.CDB[0] == REPORT_LUNS)
  988. break;
  989. /* If ASC/ASCQ indicate Logical Unit
  990. * Not Supported condition,
  991. */
  992. if ((asc == 0x25) && (ascq == 0x0)) {
  993. dev_warn(&h->pdev->dev, "cp %p "
  994. "has check condition\n", cp);
  995. break;
  996. }
  997. }
  998. if (sense_key == NOT_READY) {
  999. /* If Sense is Not Ready, Logical Unit
  1000. * Not ready, Manual Intervention
  1001. * required
  1002. */
  1003. if ((asc == 0x04) && (ascq == 0x03)) {
  1004. dev_warn(&h->pdev->dev, "cp %p "
  1005. "has check condition: unit "
  1006. "not ready, manual "
  1007. "intervention required\n", cp);
  1008. break;
  1009. }
  1010. }
  1011. if (sense_key == ABORTED_COMMAND) {
  1012. /* Aborted command is retryable */
  1013. dev_warn(&h->pdev->dev, "cp %p "
  1014. "has check condition: aborted command: "
  1015. "ASC: 0x%x, ASCQ: 0x%x\n",
  1016. cp, asc, ascq);
  1017. cmd->result = DID_SOFT_ERROR << 16;
  1018. break;
  1019. }
  1020. /* Must be some other type of check condition */
  1021. dev_warn(&h->pdev->dev, "cp %p has check condition: "
  1022. "unknown type: "
  1023. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1024. "Returning result: 0x%x, "
  1025. "cmd=[%02x %02x %02x %02x %02x "
  1026. "%02x %02x %02x %02x %02x %02x "
  1027. "%02x %02x %02x %02x %02x]\n",
  1028. cp, sense_key, asc, ascq,
  1029. cmd->result,
  1030. cmd->cmnd[0], cmd->cmnd[1],
  1031. cmd->cmnd[2], cmd->cmnd[3],
  1032. cmd->cmnd[4], cmd->cmnd[5],
  1033. cmd->cmnd[6], cmd->cmnd[7],
  1034. cmd->cmnd[8], cmd->cmnd[9],
  1035. cmd->cmnd[10], cmd->cmnd[11],
  1036. cmd->cmnd[12], cmd->cmnd[13],
  1037. cmd->cmnd[14], cmd->cmnd[15]);
  1038. break;
  1039. }
  1040. /* Problem was not a check condition
  1041. * Pass it up to the upper layers...
  1042. */
  1043. if (ei->ScsiStatus) {
  1044. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  1045. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1046. "Returning result: 0x%x\n",
  1047. cp, ei->ScsiStatus,
  1048. sense_key, asc, ascq,
  1049. cmd->result);
  1050. } else { /* scsi status is zero??? How??? */
  1051. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  1052. "Returning no connection.\n", cp),
  1053. /* Ordinarily, this case should never happen,
  1054. * but there is a bug in some released firmware
  1055. * revisions that allows it to happen if, for
  1056. * example, a 4100 backplane loses power and
  1057. * the tape drive is in it. We assume that
  1058. * it's a fatal error of some kind because we
  1059. * can't show that it wasn't. We will make it
  1060. * look like selection timeout since that is
  1061. * the most common reason for this to occur,
  1062. * and it's severe enough.
  1063. */
  1064. cmd->result = DID_NO_CONNECT << 16;
  1065. }
  1066. break;
  1067. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1068. break;
  1069. case CMD_DATA_OVERRUN:
  1070. dev_warn(&h->pdev->dev, "cp %p has"
  1071. " completed with data overrun "
  1072. "reported\n", cp);
  1073. break;
  1074. case CMD_INVALID: {
  1075. /* print_bytes(cp, sizeof(*cp), 1, 0);
  1076. print_cmd(cp); */
  1077. /* We get CMD_INVALID if you address a non-existent device
  1078. * instead of a selection timeout (no response). You will
  1079. * see this if you yank out a drive, then try to access it.
  1080. * This is kind of a shame because it means that any other
  1081. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  1082. * missing target. */
  1083. cmd->result = DID_NO_CONNECT << 16;
  1084. }
  1085. break;
  1086. case CMD_PROTOCOL_ERR:
  1087. dev_warn(&h->pdev->dev, "cp %p has "
  1088. "protocol error \n", cp);
  1089. break;
  1090. case CMD_HARDWARE_ERR:
  1091. cmd->result = DID_ERROR << 16;
  1092. dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
  1093. break;
  1094. case CMD_CONNECTION_LOST:
  1095. cmd->result = DID_ERROR << 16;
  1096. dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
  1097. break;
  1098. case CMD_ABORTED:
  1099. cmd->result = DID_ABORT << 16;
  1100. dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
  1101. cp, ei->ScsiStatus);
  1102. break;
  1103. case CMD_ABORT_FAILED:
  1104. cmd->result = DID_ERROR << 16;
  1105. dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
  1106. break;
  1107. case CMD_UNSOLICITED_ABORT:
  1108. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  1109. dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
  1110. "abort\n", cp);
  1111. break;
  1112. case CMD_TIMEOUT:
  1113. cmd->result = DID_TIME_OUT << 16;
  1114. dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
  1115. break;
  1116. case CMD_UNABORTABLE:
  1117. cmd->result = DID_ERROR << 16;
  1118. dev_warn(&h->pdev->dev, "Command unabortable\n");
  1119. break;
  1120. default:
  1121. cmd->result = DID_ERROR << 16;
  1122. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  1123. cp, ei->CommandStatus);
  1124. }
  1125. cmd->scsi_done(cmd);
  1126. cmd_free(h, cp);
  1127. }
  1128. static int hpsa_scsi_detect(struct ctlr_info *h)
  1129. {
  1130. struct Scsi_Host *sh;
  1131. int error;
  1132. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
  1133. if (sh == NULL)
  1134. goto fail;
  1135. sh->io_port = 0;
  1136. sh->n_io_port = 0;
  1137. sh->this_id = -1;
  1138. sh->max_channel = 3;
  1139. sh->max_cmd_len = MAX_COMMAND_SIZE;
  1140. sh->max_lun = HPSA_MAX_LUN;
  1141. sh->max_id = HPSA_MAX_LUN;
  1142. sh->can_queue = h->nr_cmds;
  1143. sh->cmd_per_lun = h->nr_cmds;
  1144. sh->sg_tablesize = h->maxsgentries;
  1145. h->scsi_host = sh;
  1146. sh->hostdata[0] = (unsigned long) h;
  1147. sh->irq = h->intr[h->intr_mode];
  1148. sh->unique_id = sh->irq;
  1149. error = scsi_add_host(sh, &h->pdev->dev);
  1150. if (error)
  1151. goto fail_host_put;
  1152. scsi_scan_host(sh);
  1153. return 0;
  1154. fail_host_put:
  1155. dev_err(&h->pdev->dev, "hpsa_scsi_detect: scsi_add_host"
  1156. " failed for controller %d\n", h->ctlr);
  1157. scsi_host_put(sh);
  1158. return error;
  1159. fail:
  1160. dev_err(&h->pdev->dev, "hpsa_scsi_detect: scsi_host_alloc"
  1161. " failed for controller %d\n", h->ctlr);
  1162. return -ENOMEM;
  1163. }
  1164. static void hpsa_pci_unmap(struct pci_dev *pdev,
  1165. struct CommandList *c, int sg_used, int data_direction)
  1166. {
  1167. int i;
  1168. union u64bit addr64;
  1169. for (i = 0; i < sg_used; i++) {
  1170. addr64.val32.lower = c->SG[i].Addr.lower;
  1171. addr64.val32.upper = c->SG[i].Addr.upper;
  1172. pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
  1173. data_direction);
  1174. }
  1175. }
  1176. static void hpsa_map_one(struct pci_dev *pdev,
  1177. struct CommandList *cp,
  1178. unsigned char *buf,
  1179. size_t buflen,
  1180. int data_direction)
  1181. {
  1182. u64 addr64;
  1183. if (buflen == 0 || data_direction == PCI_DMA_NONE) {
  1184. cp->Header.SGList = 0;
  1185. cp->Header.SGTotal = 0;
  1186. return;
  1187. }
  1188. addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
  1189. cp->SG[0].Addr.lower =
  1190. (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
  1191. cp->SG[0].Addr.upper =
  1192. (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
  1193. cp->SG[0].Len = buflen;
  1194. cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
  1195. cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
  1196. }
  1197. static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  1198. struct CommandList *c)
  1199. {
  1200. DECLARE_COMPLETION_ONSTACK(wait);
  1201. c->waiting = &wait;
  1202. enqueue_cmd_and_start_io(h, c);
  1203. wait_for_completion(&wait);
  1204. }
  1205. static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
  1206. struct CommandList *c)
  1207. {
  1208. unsigned long flags;
  1209. /* If controller lockup detected, fake a hardware error. */
  1210. spin_lock_irqsave(&h->lock, flags);
  1211. if (unlikely(h->lockup_detected)) {
  1212. spin_unlock_irqrestore(&h->lock, flags);
  1213. c->err_info->CommandStatus = CMD_HARDWARE_ERR;
  1214. } else {
  1215. spin_unlock_irqrestore(&h->lock, flags);
  1216. hpsa_scsi_do_simple_cmd_core(h, c);
  1217. }
  1218. }
  1219. static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  1220. struct CommandList *c, int data_direction)
  1221. {
  1222. int retry_count = 0;
  1223. do {
  1224. memset(c->err_info, 0, sizeof(*c->err_info));
  1225. hpsa_scsi_do_simple_cmd_core(h, c);
  1226. retry_count++;
  1227. } while (check_for_unit_attention(h, c) && retry_count <= 3);
  1228. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  1229. }
  1230. static void hpsa_scsi_interpret_error(struct CommandList *cp)
  1231. {
  1232. struct ErrorInfo *ei;
  1233. struct device *d = &cp->h->pdev->dev;
  1234. ei = cp->err_info;
  1235. switch (ei->CommandStatus) {
  1236. case CMD_TARGET_STATUS:
  1237. dev_warn(d, "cmd %p has completed with errors\n", cp);
  1238. dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
  1239. ei->ScsiStatus);
  1240. if (ei->ScsiStatus == 0)
  1241. dev_warn(d, "SCSI status is abnormally zero. "
  1242. "(probably indicates selection timeout "
  1243. "reported incorrectly due to a known "
  1244. "firmware bug, circa July, 2001.)\n");
  1245. break;
  1246. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1247. dev_info(d, "UNDERRUN\n");
  1248. break;
  1249. case CMD_DATA_OVERRUN:
  1250. dev_warn(d, "cp %p has completed with data overrun\n", cp);
  1251. break;
  1252. case CMD_INVALID: {
  1253. /* controller unfortunately reports SCSI passthru's
  1254. * to non-existent targets as invalid commands.
  1255. */
  1256. dev_warn(d, "cp %p is reported invalid (probably means "
  1257. "target device no longer present)\n", cp);
  1258. /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
  1259. print_cmd(cp); */
  1260. }
  1261. break;
  1262. case CMD_PROTOCOL_ERR:
  1263. dev_warn(d, "cp %p has protocol error \n", cp);
  1264. break;
  1265. case CMD_HARDWARE_ERR:
  1266. /* cmd->result = DID_ERROR << 16; */
  1267. dev_warn(d, "cp %p had hardware error\n", cp);
  1268. break;
  1269. case CMD_CONNECTION_LOST:
  1270. dev_warn(d, "cp %p had connection lost\n", cp);
  1271. break;
  1272. case CMD_ABORTED:
  1273. dev_warn(d, "cp %p was aborted\n", cp);
  1274. break;
  1275. case CMD_ABORT_FAILED:
  1276. dev_warn(d, "cp %p reports abort failed\n", cp);
  1277. break;
  1278. case CMD_UNSOLICITED_ABORT:
  1279. dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
  1280. break;
  1281. case CMD_TIMEOUT:
  1282. dev_warn(d, "cp %p timed out\n", cp);
  1283. break;
  1284. case CMD_UNABORTABLE:
  1285. dev_warn(d, "Command unabortable\n");
  1286. break;
  1287. default:
  1288. dev_warn(d, "cp %p returned unknown status %x\n", cp,
  1289. ei->CommandStatus);
  1290. }
  1291. }
  1292. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  1293. unsigned char page, unsigned char *buf,
  1294. unsigned char bufsize)
  1295. {
  1296. int rc = IO_OK;
  1297. struct CommandList *c;
  1298. struct ErrorInfo *ei;
  1299. c = cmd_special_alloc(h);
  1300. if (c == NULL) { /* trouble... */
  1301. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1302. return -ENOMEM;
  1303. }
  1304. fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, page, scsi3addr, TYPE_CMD);
  1305. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1306. ei = c->err_info;
  1307. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1308. hpsa_scsi_interpret_error(c);
  1309. rc = -1;
  1310. }
  1311. cmd_special_free(h, c);
  1312. return rc;
  1313. }
  1314. static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
  1315. {
  1316. int rc = IO_OK;
  1317. struct CommandList *c;
  1318. struct ErrorInfo *ei;
  1319. c = cmd_special_alloc(h);
  1320. if (c == NULL) { /* trouble... */
  1321. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1322. return -ENOMEM;
  1323. }
  1324. fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, scsi3addr, TYPE_MSG);
  1325. hpsa_scsi_do_simple_cmd_core(h, c);
  1326. /* no unmap needed here because no data xfer. */
  1327. ei = c->err_info;
  1328. if (ei->CommandStatus != 0) {
  1329. hpsa_scsi_interpret_error(c);
  1330. rc = -1;
  1331. }
  1332. cmd_special_free(h, c);
  1333. return rc;
  1334. }
  1335. static void hpsa_get_raid_level(struct ctlr_info *h,
  1336. unsigned char *scsi3addr, unsigned char *raid_level)
  1337. {
  1338. int rc;
  1339. unsigned char *buf;
  1340. *raid_level = RAID_UNKNOWN;
  1341. buf = kzalloc(64, GFP_KERNEL);
  1342. if (!buf)
  1343. return;
  1344. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
  1345. if (rc == 0)
  1346. *raid_level = buf[8];
  1347. if (*raid_level > RAID_UNKNOWN)
  1348. *raid_level = RAID_UNKNOWN;
  1349. kfree(buf);
  1350. return;
  1351. }
  1352. /* Get the device id from inquiry page 0x83 */
  1353. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  1354. unsigned char *device_id, int buflen)
  1355. {
  1356. int rc;
  1357. unsigned char *buf;
  1358. if (buflen > 16)
  1359. buflen = 16;
  1360. buf = kzalloc(64, GFP_KERNEL);
  1361. if (!buf)
  1362. return -1;
  1363. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
  1364. if (rc == 0)
  1365. memcpy(device_id, &buf[8], buflen);
  1366. kfree(buf);
  1367. return rc != 0;
  1368. }
  1369. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  1370. struct ReportLUNdata *buf, int bufsize,
  1371. int extended_response)
  1372. {
  1373. int rc = IO_OK;
  1374. struct CommandList *c;
  1375. unsigned char scsi3addr[8];
  1376. struct ErrorInfo *ei;
  1377. c = cmd_special_alloc(h);
  1378. if (c == NULL) { /* trouble... */
  1379. dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1380. return -1;
  1381. }
  1382. /* address the controller */
  1383. memset(scsi3addr, 0, sizeof(scsi3addr));
  1384. fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  1385. buf, bufsize, 0, scsi3addr, TYPE_CMD);
  1386. if (extended_response)
  1387. c->Request.CDB[1] = extended_response;
  1388. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1389. ei = c->err_info;
  1390. if (ei->CommandStatus != 0 &&
  1391. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1392. hpsa_scsi_interpret_error(c);
  1393. rc = -1;
  1394. }
  1395. cmd_special_free(h, c);
  1396. return rc;
  1397. }
  1398. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  1399. struct ReportLUNdata *buf,
  1400. int bufsize, int extended_response)
  1401. {
  1402. return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
  1403. }
  1404. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  1405. struct ReportLUNdata *buf, int bufsize)
  1406. {
  1407. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  1408. }
  1409. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  1410. int bus, int target, int lun)
  1411. {
  1412. device->bus = bus;
  1413. device->target = target;
  1414. device->lun = lun;
  1415. }
  1416. static int hpsa_update_device_info(struct ctlr_info *h,
  1417. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  1418. unsigned char *is_OBDR_device)
  1419. {
  1420. #define OBDR_SIG_OFFSET 43
  1421. #define OBDR_TAPE_SIG "$DR-10"
  1422. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  1423. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  1424. unsigned char *inq_buff;
  1425. unsigned char *obdr_sig;
  1426. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  1427. if (!inq_buff)
  1428. goto bail_out;
  1429. /* Do an inquiry to the device to see what it is. */
  1430. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  1431. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  1432. /* Inquiry failed (msg printed already) */
  1433. dev_err(&h->pdev->dev,
  1434. "hpsa_update_device_info: inquiry failed\n");
  1435. goto bail_out;
  1436. }
  1437. this_device->devtype = (inq_buff[0] & 0x1f);
  1438. memcpy(this_device->scsi3addr, scsi3addr, 8);
  1439. memcpy(this_device->vendor, &inq_buff[8],
  1440. sizeof(this_device->vendor));
  1441. memcpy(this_device->model, &inq_buff[16],
  1442. sizeof(this_device->model));
  1443. memset(this_device->device_id, 0,
  1444. sizeof(this_device->device_id));
  1445. hpsa_get_device_id(h, scsi3addr, this_device->device_id,
  1446. sizeof(this_device->device_id));
  1447. if (this_device->devtype == TYPE_DISK &&
  1448. is_logical_dev_addr_mode(scsi3addr))
  1449. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  1450. else
  1451. this_device->raid_level = RAID_UNKNOWN;
  1452. if (is_OBDR_device) {
  1453. /* See if this is a One-Button-Disaster-Recovery device
  1454. * by looking for "$DR-10" at offset 43 in inquiry data.
  1455. */
  1456. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  1457. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  1458. strncmp(obdr_sig, OBDR_TAPE_SIG,
  1459. OBDR_SIG_LEN) == 0);
  1460. }
  1461. kfree(inq_buff);
  1462. return 0;
  1463. bail_out:
  1464. kfree(inq_buff);
  1465. return 1;
  1466. }
  1467. static unsigned char *msa2xxx_model[] = {
  1468. "MSA2012",
  1469. "MSA2024",
  1470. "MSA2312",
  1471. "MSA2324",
  1472. "P2000 G3 SAS",
  1473. NULL,
  1474. };
  1475. static int is_msa2xxx(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1476. {
  1477. int i;
  1478. for (i = 0; msa2xxx_model[i]; i++)
  1479. if (strncmp(device->model, msa2xxx_model[i],
  1480. strlen(msa2xxx_model[i])) == 0)
  1481. return 1;
  1482. return 0;
  1483. }
  1484. /* Helper function to assign bus, target, lun mapping of devices.
  1485. * Puts non-msa2xxx logical volumes on bus 0, msa2xxx logical
  1486. * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
  1487. * Logical drive target and lun are assigned at this time, but
  1488. * physical device lun and target assignment are deferred (assigned
  1489. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  1490. */
  1491. static void figure_bus_target_lun(struct ctlr_info *h,
  1492. u8 *lunaddrbytes, int *bus, int *target, int *lun,
  1493. struct hpsa_scsi_dev_t *device)
  1494. {
  1495. u32 lunid;
  1496. if (is_logical_dev_addr_mode(lunaddrbytes)) {
  1497. /* logical device */
  1498. if (unlikely(is_scsi_rev_5(h))) {
  1499. /* p1210m, logical drives lun assignments
  1500. * match SCSI REPORT LUNS data.
  1501. */
  1502. lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1503. *bus = 0;
  1504. *target = 0;
  1505. *lun = (lunid & 0x3fff) + 1;
  1506. } else {
  1507. /* not p1210m... */
  1508. lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1509. if (is_msa2xxx(h, device)) {
  1510. /* msa2xxx way, put logicals on bus 1
  1511. * and match target/lun numbers box
  1512. * reports.
  1513. */
  1514. *bus = 1;
  1515. *target = (lunid >> 16) & 0x3fff;
  1516. *lun = lunid & 0x00ff;
  1517. } else {
  1518. /* Traditional smart array way. */
  1519. *bus = 0;
  1520. *lun = 0;
  1521. *target = lunid & 0x3fff;
  1522. }
  1523. }
  1524. } else {
  1525. /* physical device */
  1526. if (is_hba_lunid(lunaddrbytes))
  1527. if (unlikely(is_scsi_rev_5(h))) {
  1528. *bus = 0; /* put p1210m ctlr at 0,0,0 */
  1529. *target = 0;
  1530. *lun = 0;
  1531. return;
  1532. } else
  1533. *bus = 3; /* traditional smartarray */
  1534. else
  1535. *bus = 2; /* physical disk */
  1536. *target = -1;
  1537. *lun = -1; /* we will fill these in later. */
  1538. }
  1539. }
  1540. /*
  1541. * If there is no lun 0 on a target, linux won't find any devices.
  1542. * For the MSA2xxx boxes, we have to manually detect the enclosure
  1543. * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
  1544. * it for some reason. *tmpdevice is the target we're adding,
  1545. * this_device is a pointer into the current element of currentsd[]
  1546. * that we're building up in update_scsi_devices(), below.
  1547. * lunzerobits is a bitmap that tracks which targets already have a
  1548. * lun 0 assigned.
  1549. * Returns 1 if an enclosure was added, 0 if not.
  1550. */
  1551. static int add_msa2xxx_enclosure_device(struct ctlr_info *h,
  1552. struct hpsa_scsi_dev_t *tmpdevice,
  1553. struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
  1554. int bus, int target, int lun, unsigned long lunzerobits[],
  1555. int *nmsa2xxx_enclosures)
  1556. {
  1557. unsigned char scsi3addr[8];
  1558. if (test_bit(target, lunzerobits))
  1559. return 0; /* There is already a lun 0 on this target. */
  1560. if (!is_logical_dev_addr_mode(lunaddrbytes))
  1561. return 0; /* It's the logical targets that may lack lun 0. */
  1562. if (!is_msa2xxx(h, tmpdevice))
  1563. return 0; /* It's only the MSA2xxx that have this problem. */
  1564. if (lun == 0) /* if lun is 0, then obviously we have a lun 0. */
  1565. return 0;
  1566. memset(scsi3addr, 0, 8);
  1567. scsi3addr[3] = target;
  1568. if (is_hba_lunid(scsi3addr))
  1569. return 0; /* Don't add the RAID controller here. */
  1570. if (is_scsi_rev_5(h))
  1571. return 0; /* p1210m doesn't need to do this. */
  1572. if (*nmsa2xxx_enclosures >= MAX_MSA2XXX_ENCLOSURES) {
  1573. dev_warn(&h->pdev->dev, "Maximum number of MSA2XXX "
  1574. "enclosures exceeded. Check your hardware "
  1575. "configuration.");
  1576. return 0;
  1577. }
  1578. if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
  1579. return 0;
  1580. (*nmsa2xxx_enclosures)++;
  1581. hpsa_set_bus_target_lun(this_device, bus, target, 0);
  1582. set_bit(target, lunzerobits);
  1583. return 1;
  1584. }
  1585. /*
  1586. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  1587. * logdev. The number of luns in physdev and logdev are returned in
  1588. * *nphysicals and *nlogicals, respectively.
  1589. * Returns 0 on success, -1 otherwise.
  1590. */
  1591. static int hpsa_gather_lun_info(struct ctlr_info *h,
  1592. int reportlunsize,
  1593. struct ReportLUNdata *physdev, u32 *nphysicals,
  1594. struct ReportLUNdata *logdev, u32 *nlogicals)
  1595. {
  1596. if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize, 0)) {
  1597. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  1598. return -1;
  1599. }
  1600. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 8;
  1601. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  1602. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
  1603. " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1604. *nphysicals - HPSA_MAX_PHYS_LUN);
  1605. *nphysicals = HPSA_MAX_PHYS_LUN;
  1606. }
  1607. if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
  1608. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  1609. return -1;
  1610. }
  1611. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  1612. /* Reject Logicals in excess of our max capability. */
  1613. if (*nlogicals > HPSA_MAX_LUN) {
  1614. dev_warn(&h->pdev->dev,
  1615. "maximum logical LUNs (%d) exceeded. "
  1616. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  1617. *nlogicals - HPSA_MAX_LUN);
  1618. *nlogicals = HPSA_MAX_LUN;
  1619. }
  1620. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  1621. dev_warn(&h->pdev->dev,
  1622. "maximum logical + physical LUNs (%d) exceeded. "
  1623. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1624. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  1625. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  1626. }
  1627. return 0;
  1628. }
  1629. u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
  1630. int nphysicals, int nlogicals, struct ReportLUNdata *physdev_list,
  1631. struct ReportLUNdata *logdev_list)
  1632. {
  1633. /* Helper function, figure out where the LUN ID info is coming from
  1634. * given index i, lists of physical and logical devices, where in
  1635. * the list the raid controller is supposed to appear (first or last)
  1636. */
  1637. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  1638. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  1639. if (i == raid_ctlr_position)
  1640. return RAID_CTLR_LUNID;
  1641. if (i < logicals_start)
  1642. return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
  1643. if (i < last_device)
  1644. return &logdev_list->LUN[i - nphysicals -
  1645. (raid_ctlr_position == 0)][0];
  1646. BUG();
  1647. return NULL;
  1648. }
  1649. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
  1650. {
  1651. /* the idea here is we could get notified
  1652. * that some devices have changed, so we do a report
  1653. * physical luns and report logical luns cmd, and adjust
  1654. * our list of devices accordingly.
  1655. *
  1656. * The scsi3addr's of devices won't change so long as the
  1657. * adapter is not reset. That means we can rescan and
  1658. * tell which devices we already know about, vs. new
  1659. * devices, vs. disappearing devices.
  1660. */
  1661. struct ReportLUNdata *physdev_list = NULL;
  1662. struct ReportLUNdata *logdev_list = NULL;
  1663. u32 nphysicals = 0;
  1664. u32 nlogicals = 0;
  1665. u32 ndev_allocated = 0;
  1666. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  1667. int ncurrent = 0;
  1668. int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 8;
  1669. int i, nmsa2xxx_enclosures, ndevs_to_allocate;
  1670. int bus, target, lun;
  1671. int raid_ctlr_position;
  1672. DECLARE_BITMAP(lunzerobits, HPSA_MAX_TARGETS_PER_CTLR);
  1673. currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1674. physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1675. logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1676. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  1677. if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
  1678. dev_err(&h->pdev->dev, "out of memory\n");
  1679. goto out;
  1680. }
  1681. memset(lunzerobits, 0, sizeof(lunzerobits));
  1682. if (hpsa_gather_lun_info(h, reportlunsize, physdev_list, &nphysicals,
  1683. logdev_list, &nlogicals))
  1684. goto out;
  1685. /* We might see up to 32 MSA2xxx enclosures, actually 8 of them
  1686. * but each of them 4 times through different paths. The plus 1
  1687. * is for the RAID controller.
  1688. */
  1689. ndevs_to_allocate = nphysicals + nlogicals + MAX_MSA2XXX_ENCLOSURES + 1;
  1690. /* Allocate the per device structures */
  1691. for (i = 0; i < ndevs_to_allocate; i++) {
  1692. if (i >= HPSA_MAX_DEVICES) {
  1693. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  1694. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  1695. ndevs_to_allocate - HPSA_MAX_DEVICES);
  1696. break;
  1697. }
  1698. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  1699. if (!currentsd[i]) {
  1700. dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
  1701. __FILE__, __LINE__);
  1702. goto out;
  1703. }
  1704. ndev_allocated++;
  1705. }
  1706. if (unlikely(is_scsi_rev_5(h)))
  1707. raid_ctlr_position = 0;
  1708. else
  1709. raid_ctlr_position = nphysicals + nlogicals;
  1710. /* adjust our table of devices */
  1711. nmsa2xxx_enclosures = 0;
  1712. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  1713. u8 *lunaddrbytes, is_OBDR = 0;
  1714. /* Figure out where the LUN ID info is coming from */
  1715. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  1716. i, nphysicals, nlogicals, physdev_list, logdev_list);
  1717. /* skip masked physical devices. */
  1718. if (lunaddrbytes[3] & 0xC0 &&
  1719. i < nphysicals + (raid_ctlr_position == 0))
  1720. continue;
  1721. /* Get device type, vendor, model, device id */
  1722. if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  1723. &is_OBDR))
  1724. continue; /* skip it if we can't talk to it. */
  1725. figure_bus_target_lun(h, lunaddrbytes, &bus, &target, &lun,
  1726. tmpdevice);
  1727. this_device = currentsd[ncurrent];
  1728. /*
  1729. * For the msa2xxx boxes, we have to insert a LUN 0 which
  1730. * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
  1731. * is nonetheless an enclosure device there. We have to
  1732. * present that otherwise linux won't find anything if
  1733. * there is no lun 0.
  1734. */
  1735. if (add_msa2xxx_enclosure_device(h, tmpdevice, this_device,
  1736. lunaddrbytes, bus, target, lun, lunzerobits,
  1737. &nmsa2xxx_enclosures)) {
  1738. ncurrent++;
  1739. this_device = currentsd[ncurrent];
  1740. }
  1741. *this_device = *tmpdevice;
  1742. hpsa_set_bus_target_lun(this_device, bus, target, lun);
  1743. switch (this_device->devtype) {
  1744. case TYPE_ROM:
  1745. /* We don't *really* support actual CD-ROM devices,
  1746. * just "One Button Disaster Recovery" tape drive
  1747. * which temporarily pretends to be a CD-ROM drive.
  1748. * So we check that the device is really an OBDR tape
  1749. * device by checking for "$DR-10" in bytes 43-48 of
  1750. * the inquiry data.
  1751. */
  1752. if (is_OBDR)
  1753. ncurrent++;
  1754. break;
  1755. case TYPE_DISK:
  1756. if (i < nphysicals)
  1757. break;
  1758. ncurrent++;
  1759. break;
  1760. case TYPE_TAPE:
  1761. case TYPE_MEDIUM_CHANGER:
  1762. ncurrent++;
  1763. break;
  1764. case TYPE_RAID:
  1765. /* Only present the Smartarray HBA as a RAID controller.
  1766. * If it's a RAID controller other than the HBA itself
  1767. * (an external RAID controller, MSA500 or similar)
  1768. * don't present it.
  1769. */
  1770. if (!is_hba_lunid(lunaddrbytes))
  1771. break;
  1772. ncurrent++;
  1773. break;
  1774. default:
  1775. break;
  1776. }
  1777. if (ncurrent >= HPSA_MAX_DEVICES)
  1778. break;
  1779. }
  1780. adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
  1781. out:
  1782. kfree(tmpdevice);
  1783. for (i = 0; i < ndev_allocated; i++)
  1784. kfree(currentsd[i]);
  1785. kfree(currentsd);
  1786. kfree(physdev_list);
  1787. kfree(logdev_list);
  1788. }
  1789. /* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  1790. * dma mapping and fills in the scatter gather entries of the
  1791. * hpsa command, cp.
  1792. */
  1793. static int hpsa_scatter_gather(struct ctlr_info *h,
  1794. struct CommandList *cp,
  1795. struct scsi_cmnd *cmd)
  1796. {
  1797. unsigned int len;
  1798. struct scatterlist *sg;
  1799. u64 addr64;
  1800. int use_sg, i, sg_index, chained;
  1801. struct SGDescriptor *curr_sg;
  1802. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  1803. use_sg = scsi_dma_map(cmd);
  1804. if (use_sg < 0)
  1805. return use_sg;
  1806. if (!use_sg)
  1807. goto sglist_finished;
  1808. curr_sg = cp->SG;
  1809. chained = 0;
  1810. sg_index = 0;
  1811. scsi_for_each_sg(cmd, sg, use_sg, i) {
  1812. if (i == h->max_cmd_sg_entries - 1 &&
  1813. use_sg > h->max_cmd_sg_entries) {
  1814. chained = 1;
  1815. curr_sg = h->cmd_sg_list[cp->cmdindex];
  1816. sg_index = 0;
  1817. }
  1818. addr64 = (u64) sg_dma_address(sg);
  1819. len = sg_dma_len(sg);
  1820. curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
  1821. curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
  1822. curr_sg->Len = len;
  1823. curr_sg->Ext = 0; /* we are not chaining */
  1824. curr_sg++;
  1825. }
  1826. if (use_sg + chained > h->maxSG)
  1827. h->maxSG = use_sg + chained;
  1828. if (chained) {
  1829. cp->Header.SGList = h->max_cmd_sg_entries;
  1830. cp->Header.SGTotal = (u16) (use_sg + 1);
  1831. hpsa_map_sg_chain_block(h, cp);
  1832. return 0;
  1833. }
  1834. sglist_finished:
  1835. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  1836. cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
  1837. return 0;
  1838. }
  1839. static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
  1840. void (*done)(struct scsi_cmnd *))
  1841. {
  1842. struct ctlr_info *h;
  1843. struct hpsa_scsi_dev_t *dev;
  1844. unsigned char scsi3addr[8];
  1845. struct CommandList *c;
  1846. unsigned long flags;
  1847. /* Get the ptr to our adapter structure out of cmd->host. */
  1848. h = sdev_to_hba(cmd->device);
  1849. dev = cmd->device->hostdata;
  1850. if (!dev) {
  1851. cmd->result = DID_NO_CONNECT << 16;
  1852. done(cmd);
  1853. return 0;
  1854. }
  1855. memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
  1856. spin_lock_irqsave(&h->lock, flags);
  1857. if (unlikely(h->lockup_detected)) {
  1858. spin_unlock_irqrestore(&h->lock, flags);
  1859. cmd->result = DID_ERROR << 16;
  1860. done(cmd);
  1861. return 0;
  1862. }
  1863. /* Need a lock as this is being allocated from the pool */
  1864. c = cmd_alloc(h);
  1865. spin_unlock_irqrestore(&h->lock, flags);
  1866. if (c == NULL) { /* trouble... */
  1867. dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
  1868. return SCSI_MLQUEUE_HOST_BUSY;
  1869. }
  1870. /* Fill in the command list header */
  1871. cmd->scsi_done = done; /* save this for use by completion code */
  1872. /* save c in case we have to abort it */
  1873. cmd->host_scribble = (unsigned char *) c;
  1874. c->cmd_type = CMD_SCSI;
  1875. c->scsi_cmd = cmd;
  1876. c->Header.ReplyQueue = 0; /* unused in simple mode */
  1877. memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
  1878. c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
  1879. c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
  1880. /* Fill in the request block... */
  1881. c->Request.Timeout = 0;
  1882. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  1883. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  1884. c->Request.CDBLen = cmd->cmd_len;
  1885. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  1886. c->Request.Type.Type = TYPE_CMD;
  1887. c->Request.Type.Attribute = ATTR_SIMPLE;
  1888. switch (cmd->sc_data_direction) {
  1889. case DMA_TO_DEVICE:
  1890. c->Request.Type.Direction = XFER_WRITE;
  1891. break;
  1892. case DMA_FROM_DEVICE:
  1893. c->Request.Type.Direction = XFER_READ;
  1894. break;
  1895. case DMA_NONE:
  1896. c->Request.Type.Direction = XFER_NONE;
  1897. break;
  1898. case DMA_BIDIRECTIONAL:
  1899. /* This can happen if a buggy application does a scsi passthru
  1900. * and sets both inlen and outlen to non-zero. ( see
  1901. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  1902. */
  1903. c->Request.Type.Direction = XFER_RSVD;
  1904. /* This is technically wrong, and hpsa controllers should
  1905. * reject it with CMD_INVALID, which is the most correct
  1906. * response, but non-fibre backends appear to let it
  1907. * slide by, and give the same results as if this field
  1908. * were set correctly. Either way is acceptable for
  1909. * our purposes here.
  1910. */
  1911. break;
  1912. default:
  1913. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  1914. cmd->sc_data_direction);
  1915. BUG();
  1916. break;
  1917. }
  1918. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  1919. cmd_free(h, c);
  1920. return SCSI_MLQUEUE_HOST_BUSY;
  1921. }
  1922. enqueue_cmd_and_start_io(h, c);
  1923. /* the cmd'll come back via intr handler in complete_scsi_command() */
  1924. return 0;
  1925. }
  1926. static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
  1927. static void hpsa_scan_start(struct Scsi_Host *sh)
  1928. {
  1929. struct ctlr_info *h = shost_to_hba(sh);
  1930. unsigned long flags;
  1931. /* wait until any scan already in progress is finished. */
  1932. while (1) {
  1933. spin_lock_irqsave(&h->scan_lock, flags);
  1934. if (h->scan_finished)
  1935. break;
  1936. spin_unlock_irqrestore(&h->scan_lock, flags);
  1937. wait_event(h->scan_wait_queue, h->scan_finished);
  1938. /* Note: We don't need to worry about a race between this
  1939. * thread and driver unload because the midlayer will
  1940. * have incremented the reference count, so unload won't
  1941. * happen if we're in here.
  1942. */
  1943. }
  1944. h->scan_finished = 0; /* mark scan as in progress */
  1945. spin_unlock_irqrestore(&h->scan_lock, flags);
  1946. hpsa_update_scsi_devices(h, h->scsi_host->host_no);
  1947. spin_lock_irqsave(&h->scan_lock, flags);
  1948. h->scan_finished = 1; /* mark scan as finished. */
  1949. wake_up_all(&h->scan_wait_queue);
  1950. spin_unlock_irqrestore(&h->scan_lock, flags);
  1951. }
  1952. static int hpsa_scan_finished(struct Scsi_Host *sh,
  1953. unsigned long elapsed_time)
  1954. {
  1955. struct ctlr_info *h = shost_to_hba(sh);
  1956. unsigned long flags;
  1957. int finished;
  1958. spin_lock_irqsave(&h->scan_lock, flags);
  1959. finished = h->scan_finished;
  1960. spin_unlock_irqrestore(&h->scan_lock, flags);
  1961. return finished;
  1962. }
  1963. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  1964. int qdepth, int reason)
  1965. {
  1966. struct ctlr_info *h = sdev_to_hba(sdev);
  1967. if (reason != SCSI_QDEPTH_DEFAULT)
  1968. return -ENOTSUPP;
  1969. if (qdepth < 1)
  1970. qdepth = 1;
  1971. else
  1972. if (qdepth > h->nr_cmds)
  1973. qdepth = h->nr_cmds;
  1974. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1975. return sdev->queue_depth;
  1976. }
  1977. static void hpsa_unregister_scsi(struct ctlr_info *h)
  1978. {
  1979. /* we are being forcibly unloaded, and may not refuse. */
  1980. scsi_remove_host(h->scsi_host);
  1981. scsi_host_put(h->scsi_host);
  1982. h->scsi_host = NULL;
  1983. }
  1984. static int hpsa_register_scsi(struct ctlr_info *h)
  1985. {
  1986. int rc;
  1987. rc = hpsa_scsi_detect(h);
  1988. if (rc != 0)
  1989. dev_err(&h->pdev->dev, "hpsa_register_scsi: failed"
  1990. " hpsa_scsi_detect(), rc is %d\n", rc);
  1991. return rc;
  1992. }
  1993. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  1994. unsigned char lunaddr[])
  1995. {
  1996. int rc = 0;
  1997. int count = 0;
  1998. int waittime = 1; /* seconds */
  1999. struct CommandList *c;
  2000. c = cmd_special_alloc(h);
  2001. if (!c) {
  2002. dev_warn(&h->pdev->dev, "out of memory in "
  2003. "wait_for_device_to_become_ready.\n");
  2004. return IO_ERROR;
  2005. }
  2006. /* Send test unit ready until device ready, or give up. */
  2007. while (count < HPSA_TUR_RETRY_LIMIT) {
  2008. /* Wait for a bit. do this first, because if we send
  2009. * the TUR right away, the reset will just abort it.
  2010. */
  2011. msleep(1000 * waittime);
  2012. count++;
  2013. /* Increase wait time with each try, up to a point. */
  2014. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  2015. waittime = waittime * 2;
  2016. /* Send the Test Unit Ready */
  2017. fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, lunaddr, TYPE_CMD);
  2018. hpsa_scsi_do_simple_cmd_core(h, c);
  2019. /* no unmap needed here because no data xfer. */
  2020. if (c->err_info->CommandStatus == CMD_SUCCESS)
  2021. break;
  2022. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2023. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  2024. (c->err_info->SenseInfo[2] == NO_SENSE ||
  2025. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  2026. break;
  2027. dev_warn(&h->pdev->dev, "waiting %d secs "
  2028. "for device to become ready.\n", waittime);
  2029. rc = 1; /* device not ready. */
  2030. }
  2031. if (rc)
  2032. dev_warn(&h->pdev->dev, "giving up on device.\n");
  2033. else
  2034. dev_warn(&h->pdev->dev, "device is ready.\n");
  2035. cmd_special_free(h, c);
  2036. return rc;
  2037. }
  2038. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  2039. * complaining. Doing a host- or bus-reset can't do anything good here.
  2040. */
  2041. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  2042. {
  2043. int rc;
  2044. struct ctlr_info *h;
  2045. struct hpsa_scsi_dev_t *dev;
  2046. /* find the controller to which the command to be aborted was sent */
  2047. h = sdev_to_hba(scsicmd->device);
  2048. if (h == NULL) /* paranoia */
  2049. return FAILED;
  2050. dev = scsicmd->device->hostdata;
  2051. if (!dev) {
  2052. dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
  2053. "device lookup failed.\n");
  2054. return FAILED;
  2055. }
  2056. dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
  2057. h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
  2058. /* send a reset to the SCSI LUN which the command was sent to */
  2059. rc = hpsa_send_reset(h, dev->scsi3addr);
  2060. if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
  2061. return SUCCESS;
  2062. dev_warn(&h->pdev->dev, "resetting device failed.\n");
  2063. return FAILED;
  2064. }
  2065. /*
  2066. * For operations that cannot sleep, a command block is allocated at init,
  2067. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  2068. * which ones are free or in use. Lock must be held when calling this.
  2069. * cmd_free() is the complement.
  2070. */
  2071. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  2072. {
  2073. struct CommandList *c;
  2074. int i;
  2075. union u64bit temp64;
  2076. dma_addr_t cmd_dma_handle, err_dma_handle;
  2077. do {
  2078. i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
  2079. if (i == h->nr_cmds)
  2080. return NULL;
  2081. } while (test_and_set_bit
  2082. (i & (BITS_PER_LONG - 1),
  2083. h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
  2084. c = h->cmd_pool + i;
  2085. memset(c, 0, sizeof(*c));
  2086. cmd_dma_handle = h->cmd_pool_dhandle
  2087. + i * sizeof(*c);
  2088. c->err_info = h->errinfo_pool + i;
  2089. memset(c->err_info, 0, sizeof(*c->err_info));
  2090. err_dma_handle = h->errinfo_pool_dhandle
  2091. + i * sizeof(*c->err_info);
  2092. h->nr_allocs++;
  2093. c->cmdindex = i;
  2094. INIT_LIST_HEAD(&c->list);
  2095. c->busaddr = (u32) cmd_dma_handle;
  2096. temp64.val = (u64) err_dma_handle;
  2097. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2098. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2099. c->ErrDesc.Len = sizeof(*c->err_info);
  2100. c->h = h;
  2101. return c;
  2102. }
  2103. /* For operations that can wait for kmalloc to possibly sleep,
  2104. * this routine can be called. Lock need not be held to call
  2105. * cmd_special_alloc. cmd_special_free() is the complement.
  2106. */
  2107. static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
  2108. {
  2109. struct CommandList *c;
  2110. union u64bit temp64;
  2111. dma_addr_t cmd_dma_handle, err_dma_handle;
  2112. c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
  2113. if (c == NULL)
  2114. return NULL;
  2115. memset(c, 0, sizeof(*c));
  2116. c->cmdindex = -1;
  2117. c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
  2118. &err_dma_handle);
  2119. if (c->err_info == NULL) {
  2120. pci_free_consistent(h->pdev,
  2121. sizeof(*c), c, cmd_dma_handle);
  2122. return NULL;
  2123. }
  2124. memset(c->err_info, 0, sizeof(*c->err_info));
  2125. INIT_LIST_HEAD(&c->list);
  2126. c->busaddr = (u32) cmd_dma_handle;
  2127. temp64.val = (u64) err_dma_handle;
  2128. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2129. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2130. c->ErrDesc.Len = sizeof(*c->err_info);
  2131. c->h = h;
  2132. return c;
  2133. }
  2134. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  2135. {
  2136. int i;
  2137. i = c - h->cmd_pool;
  2138. clear_bit(i & (BITS_PER_LONG - 1),
  2139. h->cmd_pool_bits + (i / BITS_PER_LONG));
  2140. h->nr_frees++;
  2141. }
  2142. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
  2143. {
  2144. union u64bit temp64;
  2145. temp64.val32.lower = c->ErrDesc.Addr.lower;
  2146. temp64.val32.upper = c->ErrDesc.Addr.upper;
  2147. pci_free_consistent(h->pdev, sizeof(*c->err_info),
  2148. c->err_info, (dma_addr_t) temp64.val);
  2149. pci_free_consistent(h->pdev, sizeof(*c),
  2150. c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
  2151. }
  2152. #ifdef CONFIG_COMPAT
  2153. static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
  2154. {
  2155. IOCTL32_Command_struct __user *arg32 =
  2156. (IOCTL32_Command_struct __user *) arg;
  2157. IOCTL_Command_struct arg64;
  2158. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  2159. int err;
  2160. u32 cp;
  2161. memset(&arg64, 0, sizeof(arg64));
  2162. err = 0;
  2163. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2164. sizeof(arg64.LUN_info));
  2165. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2166. sizeof(arg64.Request));
  2167. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2168. sizeof(arg64.error_info));
  2169. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2170. err |= get_user(cp, &arg32->buf);
  2171. arg64.buf = compat_ptr(cp);
  2172. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2173. if (err)
  2174. return -EFAULT;
  2175. err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
  2176. if (err)
  2177. return err;
  2178. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2179. sizeof(arg32->error_info));
  2180. if (err)
  2181. return -EFAULT;
  2182. return err;
  2183. }
  2184. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  2185. int cmd, void *arg)
  2186. {
  2187. BIG_IOCTL32_Command_struct __user *arg32 =
  2188. (BIG_IOCTL32_Command_struct __user *) arg;
  2189. BIG_IOCTL_Command_struct arg64;
  2190. BIG_IOCTL_Command_struct __user *p =
  2191. compat_alloc_user_space(sizeof(arg64));
  2192. int err;
  2193. u32 cp;
  2194. memset(&arg64, 0, sizeof(arg64));
  2195. err = 0;
  2196. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2197. sizeof(arg64.LUN_info));
  2198. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2199. sizeof(arg64.Request));
  2200. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2201. sizeof(arg64.error_info));
  2202. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2203. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  2204. err |= get_user(cp, &arg32->buf);
  2205. arg64.buf = compat_ptr(cp);
  2206. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2207. if (err)
  2208. return -EFAULT;
  2209. err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
  2210. if (err)
  2211. return err;
  2212. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2213. sizeof(arg32->error_info));
  2214. if (err)
  2215. return -EFAULT;
  2216. return err;
  2217. }
  2218. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2219. {
  2220. switch (cmd) {
  2221. case CCISS_GETPCIINFO:
  2222. case CCISS_GETINTINFO:
  2223. case CCISS_SETINTINFO:
  2224. case CCISS_GETNODENAME:
  2225. case CCISS_SETNODENAME:
  2226. case CCISS_GETHEARTBEAT:
  2227. case CCISS_GETBUSTYPES:
  2228. case CCISS_GETFIRMVER:
  2229. case CCISS_GETDRIVVER:
  2230. case CCISS_REVALIDVOLS:
  2231. case CCISS_DEREGDISK:
  2232. case CCISS_REGNEWDISK:
  2233. case CCISS_REGNEWD:
  2234. case CCISS_RESCANDISK:
  2235. case CCISS_GETLUNINFO:
  2236. return hpsa_ioctl(dev, cmd, arg);
  2237. case CCISS_PASSTHRU32:
  2238. return hpsa_ioctl32_passthru(dev, cmd, arg);
  2239. case CCISS_BIG_PASSTHRU32:
  2240. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  2241. default:
  2242. return -ENOIOCTLCMD;
  2243. }
  2244. }
  2245. #endif
  2246. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  2247. {
  2248. struct hpsa_pci_info pciinfo;
  2249. if (!argp)
  2250. return -EINVAL;
  2251. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  2252. pciinfo.bus = h->pdev->bus->number;
  2253. pciinfo.dev_fn = h->pdev->devfn;
  2254. pciinfo.board_id = h->board_id;
  2255. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  2256. return -EFAULT;
  2257. return 0;
  2258. }
  2259. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  2260. {
  2261. DriverVer_type DriverVer;
  2262. unsigned char vmaj, vmin, vsubmin;
  2263. int rc;
  2264. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  2265. &vmaj, &vmin, &vsubmin);
  2266. if (rc != 3) {
  2267. dev_info(&h->pdev->dev, "driver version string '%s' "
  2268. "unrecognized.", HPSA_DRIVER_VERSION);
  2269. vmaj = 0;
  2270. vmin = 0;
  2271. vsubmin = 0;
  2272. }
  2273. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  2274. if (!argp)
  2275. return -EINVAL;
  2276. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  2277. return -EFAULT;
  2278. return 0;
  2279. }
  2280. static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2281. {
  2282. IOCTL_Command_struct iocommand;
  2283. struct CommandList *c;
  2284. char *buff = NULL;
  2285. union u64bit temp64;
  2286. if (!argp)
  2287. return -EINVAL;
  2288. if (!capable(CAP_SYS_RAWIO))
  2289. return -EPERM;
  2290. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  2291. return -EFAULT;
  2292. if ((iocommand.buf_size < 1) &&
  2293. (iocommand.Request.Type.Direction != XFER_NONE)) {
  2294. return -EINVAL;
  2295. }
  2296. if (iocommand.buf_size > 0) {
  2297. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  2298. if (buff == NULL)
  2299. return -EFAULT;
  2300. if (iocommand.Request.Type.Direction == XFER_WRITE) {
  2301. /* Copy the data into the buffer we created */
  2302. if (copy_from_user(buff, iocommand.buf,
  2303. iocommand.buf_size)) {
  2304. kfree(buff);
  2305. return -EFAULT;
  2306. }
  2307. } else {
  2308. memset(buff, 0, iocommand.buf_size);
  2309. }
  2310. }
  2311. c = cmd_special_alloc(h);
  2312. if (c == NULL) {
  2313. kfree(buff);
  2314. return -ENOMEM;
  2315. }
  2316. /* Fill in the command type */
  2317. c->cmd_type = CMD_IOCTL_PEND;
  2318. /* Fill in Command Header */
  2319. c->Header.ReplyQueue = 0; /* unused in simple mode */
  2320. if (iocommand.buf_size > 0) { /* buffer to fill */
  2321. c->Header.SGList = 1;
  2322. c->Header.SGTotal = 1;
  2323. } else { /* no buffers to fill */
  2324. c->Header.SGList = 0;
  2325. c->Header.SGTotal = 0;
  2326. }
  2327. memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
  2328. /* use the kernel address the cmd block for tag */
  2329. c->Header.Tag.lower = c->busaddr;
  2330. /* Fill in Request block */
  2331. memcpy(&c->Request, &iocommand.Request,
  2332. sizeof(c->Request));
  2333. /* Fill in the scatter gather information */
  2334. if (iocommand.buf_size > 0) {
  2335. temp64.val = pci_map_single(h->pdev, buff,
  2336. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  2337. c->SG[0].Addr.lower = temp64.val32.lower;
  2338. c->SG[0].Addr.upper = temp64.val32.upper;
  2339. c->SG[0].Len = iocommand.buf_size;
  2340. c->SG[0].Ext = 0; /* we are not chaining*/
  2341. }
  2342. hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
  2343. if (iocommand.buf_size > 0)
  2344. hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
  2345. check_ioctl_unit_attention(h, c);
  2346. /* Copy the error information out */
  2347. memcpy(&iocommand.error_info, c->err_info,
  2348. sizeof(iocommand.error_info));
  2349. if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
  2350. kfree(buff);
  2351. cmd_special_free(h, c);
  2352. return -EFAULT;
  2353. }
  2354. if (iocommand.Request.Type.Direction == XFER_READ &&
  2355. iocommand.buf_size > 0) {
  2356. /* Copy the data out of the buffer we created */
  2357. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  2358. kfree(buff);
  2359. cmd_special_free(h, c);
  2360. return -EFAULT;
  2361. }
  2362. }
  2363. kfree(buff);
  2364. cmd_special_free(h, c);
  2365. return 0;
  2366. }
  2367. static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2368. {
  2369. BIG_IOCTL_Command_struct *ioc;
  2370. struct CommandList *c;
  2371. unsigned char **buff = NULL;
  2372. int *buff_size = NULL;
  2373. union u64bit temp64;
  2374. BYTE sg_used = 0;
  2375. int status = 0;
  2376. int i;
  2377. u32 left;
  2378. u32 sz;
  2379. BYTE __user *data_ptr;
  2380. if (!argp)
  2381. return -EINVAL;
  2382. if (!capable(CAP_SYS_RAWIO))
  2383. return -EPERM;
  2384. ioc = (BIG_IOCTL_Command_struct *)
  2385. kmalloc(sizeof(*ioc), GFP_KERNEL);
  2386. if (!ioc) {
  2387. status = -ENOMEM;
  2388. goto cleanup1;
  2389. }
  2390. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  2391. status = -EFAULT;
  2392. goto cleanup1;
  2393. }
  2394. if ((ioc->buf_size < 1) &&
  2395. (ioc->Request.Type.Direction != XFER_NONE)) {
  2396. status = -EINVAL;
  2397. goto cleanup1;
  2398. }
  2399. /* Check kmalloc limits using all SGs */
  2400. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  2401. status = -EINVAL;
  2402. goto cleanup1;
  2403. }
  2404. if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
  2405. status = -EINVAL;
  2406. goto cleanup1;
  2407. }
  2408. buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
  2409. if (!buff) {
  2410. status = -ENOMEM;
  2411. goto cleanup1;
  2412. }
  2413. buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
  2414. if (!buff_size) {
  2415. status = -ENOMEM;
  2416. goto cleanup1;
  2417. }
  2418. left = ioc->buf_size;
  2419. data_ptr = ioc->buf;
  2420. while (left) {
  2421. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  2422. buff_size[sg_used] = sz;
  2423. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  2424. if (buff[sg_used] == NULL) {
  2425. status = -ENOMEM;
  2426. goto cleanup1;
  2427. }
  2428. if (ioc->Request.Type.Direction == XFER_WRITE) {
  2429. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  2430. status = -ENOMEM;
  2431. goto cleanup1;
  2432. }
  2433. } else
  2434. memset(buff[sg_used], 0, sz);
  2435. left -= sz;
  2436. data_ptr += sz;
  2437. sg_used++;
  2438. }
  2439. c = cmd_special_alloc(h);
  2440. if (c == NULL) {
  2441. status = -ENOMEM;
  2442. goto cleanup1;
  2443. }
  2444. c->cmd_type = CMD_IOCTL_PEND;
  2445. c->Header.ReplyQueue = 0;
  2446. c->Header.SGList = c->Header.SGTotal = sg_used;
  2447. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  2448. c->Header.Tag.lower = c->busaddr;
  2449. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  2450. if (ioc->buf_size > 0) {
  2451. int i;
  2452. for (i = 0; i < sg_used; i++) {
  2453. temp64.val = pci_map_single(h->pdev, buff[i],
  2454. buff_size[i], PCI_DMA_BIDIRECTIONAL);
  2455. c->SG[i].Addr.lower = temp64.val32.lower;
  2456. c->SG[i].Addr.upper = temp64.val32.upper;
  2457. c->SG[i].Len = buff_size[i];
  2458. /* we are not chaining */
  2459. c->SG[i].Ext = 0;
  2460. }
  2461. }
  2462. hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
  2463. if (sg_used)
  2464. hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
  2465. check_ioctl_unit_attention(h, c);
  2466. /* Copy the error information out */
  2467. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  2468. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  2469. cmd_special_free(h, c);
  2470. status = -EFAULT;
  2471. goto cleanup1;
  2472. }
  2473. if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
  2474. /* Copy the data out of the buffer we created */
  2475. BYTE __user *ptr = ioc->buf;
  2476. for (i = 0; i < sg_used; i++) {
  2477. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  2478. cmd_special_free(h, c);
  2479. status = -EFAULT;
  2480. goto cleanup1;
  2481. }
  2482. ptr += buff_size[i];
  2483. }
  2484. }
  2485. cmd_special_free(h, c);
  2486. status = 0;
  2487. cleanup1:
  2488. if (buff) {
  2489. for (i = 0; i < sg_used; i++)
  2490. kfree(buff[i]);
  2491. kfree(buff);
  2492. }
  2493. kfree(buff_size);
  2494. kfree(ioc);
  2495. return status;
  2496. }
  2497. static void check_ioctl_unit_attention(struct ctlr_info *h,
  2498. struct CommandList *c)
  2499. {
  2500. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2501. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  2502. (void) check_for_unit_attention(h, c);
  2503. }
  2504. /*
  2505. * ioctl
  2506. */
  2507. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2508. {
  2509. struct ctlr_info *h;
  2510. void __user *argp = (void __user *)arg;
  2511. h = sdev_to_hba(dev);
  2512. switch (cmd) {
  2513. case CCISS_DEREGDISK:
  2514. case CCISS_REGNEWDISK:
  2515. case CCISS_REGNEWD:
  2516. hpsa_scan_start(h->scsi_host);
  2517. return 0;
  2518. case CCISS_GETPCIINFO:
  2519. return hpsa_getpciinfo_ioctl(h, argp);
  2520. case CCISS_GETDRIVVER:
  2521. return hpsa_getdrivver_ioctl(h, argp);
  2522. case CCISS_PASSTHRU:
  2523. return hpsa_passthru_ioctl(h, argp);
  2524. case CCISS_BIG_PASSTHRU:
  2525. return hpsa_big_passthru_ioctl(h, argp);
  2526. default:
  2527. return -ENOTTY;
  2528. }
  2529. }
  2530. static int __devinit hpsa_send_host_reset(struct ctlr_info *h,
  2531. unsigned char *scsi3addr, u8 reset_type)
  2532. {
  2533. struct CommandList *c;
  2534. c = cmd_alloc(h);
  2535. if (!c)
  2536. return -ENOMEM;
  2537. fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  2538. RAID_CTLR_LUNID, TYPE_MSG);
  2539. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  2540. c->waiting = NULL;
  2541. enqueue_cmd_and_start_io(h, c);
  2542. /* Don't wait for completion, the reset won't complete. Don't free
  2543. * the command either. This is the last command we will send before
  2544. * re-initializing everything, so it doesn't matter and won't leak.
  2545. */
  2546. return 0;
  2547. }
  2548. static void fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  2549. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  2550. int cmd_type)
  2551. {
  2552. int pci_dir = XFER_NONE;
  2553. c->cmd_type = CMD_IOCTL_PEND;
  2554. c->Header.ReplyQueue = 0;
  2555. if (buff != NULL && size > 0) {
  2556. c->Header.SGList = 1;
  2557. c->Header.SGTotal = 1;
  2558. } else {
  2559. c->Header.SGList = 0;
  2560. c->Header.SGTotal = 0;
  2561. }
  2562. c->Header.Tag.lower = c->busaddr;
  2563. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  2564. c->Request.Type.Type = cmd_type;
  2565. if (cmd_type == TYPE_CMD) {
  2566. switch (cmd) {
  2567. case HPSA_INQUIRY:
  2568. /* are we trying to read a vital product page */
  2569. if (page_code != 0) {
  2570. c->Request.CDB[1] = 0x01;
  2571. c->Request.CDB[2] = page_code;
  2572. }
  2573. c->Request.CDBLen = 6;
  2574. c->Request.Type.Attribute = ATTR_SIMPLE;
  2575. c->Request.Type.Direction = XFER_READ;
  2576. c->Request.Timeout = 0;
  2577. c->Request.CDB[0] = HPSA_INQUIRY;
  2578. c->Request.CDB[4] = size & 0xFF;
  2579. break;
  2580. case HPSA_REPORT_LOG:
  2581. case HPSA_REPORT_PHYS:
  2582. /* Talking to controller so It's a physical command
  2583. mode = 00 target = 0. Nothing to write.
  2584. */
  2585. c->Request.CDBLen = 12;
  2586. c->Request.Type.Attribute = ATTR_SIMPLE;
  2587. c->Request.Type.Direction = XFER_READ;
  2588. c->Request.Timeout = 0;
  2589. c->Request.CDB[0] = cmd;
  2590. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  2591. c->Request.CDB[7] = (size >> 16) & 0xFF;
  2592. c->Request.CDB[8] = (size >> 8) & 0xFF;
  2593. c->Request.CDB[9] = size & 0xFF;
  2594. break;
  2595. case HPSA_CACHE_FLUSH:
  2596. c->Request.CDBLen = 12;
  2597. c->Request.Type.Attribute = ATTR_SIMPLE;
  2598. c->Request.Type.Direction = XFER_WRITE;
  2599. c->Request.Timeout = 0;
  2600. c->Request.CDB[0] = BMIC_WRITE;
  2601. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  2602. c->Request.CDB[7] = (size >> 8) & 0xFF;
  2603. c->Request.CDB[8] = size & 0xFF;
  2604. break;
  2605. case TEST_UNIT_READY:
  2606. c->Request.CDBLen = 6;
  2607. c->Request.Type.Attribute = ATTR_SIMPLE;
  2608. c->Request.Type.Direction = XFER_NONE;
  2609. c->Request.Timeout = 0;
  2610. break;
  2611. default:
  2612. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  2613. BUG();
  2614. return;
  2615. }
  2616. } else if (cmd_type == TYPE_MSG) {
  2617. switch (cmd) {
  2618. case HPSA_DEVICE_RESET_MSG:
  2619. c->Request.CDBLen = 16;
  2620. c->Request.Type.Type = 1; /* It is a MSG not a CMD */
  2621. c->Request.Type.Attribute = ATTR_SIMPLE;
  2622. c->Request.Type.Direction = XFER_NONE;
  2623. c->Request.Timeout = 0; /* Don't time out */
  2624. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  2625. c->Request.CDB[0] = cmd;
  2626. c->Request.CDB[1] = 0x03; /* Reset target above */
  2627. /* If bytes 4-7 are zero, it means reset the */
  2628. /* LunID device */
  2629. c->Request.CDB[4] = 0x00;
  2630. c->Request.CDB[5] = 0x00;
  2631. c->Request.CDB[6] = 0x00;
  2632. c->Request.CDB[7] = 0x00;
  2633. break;
  2634. default:
  2635. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  2636. cmd);
  2637. BUG();
  2638. }
  2639. } else {
  2640. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  2641. BUG();
  2642. }
  2643. switch (c->Request.Type.Direction) {
  2644. case XFER_READ:
  2645. pci_dir = PCI_DMA_FROMDEVICE;
  2646. break;
  2647. case XFER_WRITE:
  2648. pci_dir = PCI_DMA_TODEVICE;
  2649. break;
  2650. case XFER_NONE:
  2651. pci_dir = PCI_DMA_NONE;
  2652. break;
  2653. default:
  2654. pci_dir = PCI_DMA_BIDIRECTIONAL;
  2655. }
  2656. hpsa_map_one(h->pdev, c, buff, size, pci_dir);
  2657. return;
  2658. }
  2659. /*
  2660. * Map (physical) PCI mem into (virtual) kernel space
  2661. */
  2662. static void __iomem *remap_pci_mem(ulong base, ulong size)
  2663. {
  2664. ulong page_base = ((ulong) base) & PAGE_MASK;
  2665. ulong page_offs = ((ulong) base) - page_base;
  2666. void __iomem *page_remapped = ioremap(page_base, page_offs + size);
  2667. return page_remapped ? (page_remapped + page_offs) : NULL;
  2668. }
  2669. /* Takes cmds off the submission queue and sends them to the hardware,
  2670. * then puts them on the queue of cmds waiting for completion.
  2671. */
  2672. static void start_io(struct ctlr_info *h)
  2673. {
  2674. struct CommandList *c;
  2675. while (!list_empty(&h->reqQ)) {
  2676. c = list_entry(h->reqQ.next, struct CommandList, list);
  2677. /* can't do anything if fifo is full */
  2678. if ((h->access.fifo_full(h))) {
  2679. dev_warn(&h->pdev->dev, "fifo full\n");
  2680. break;
  2681. }
  2682. /* Get the first entry from the Request Q */
  2683. removeQ(c);
  2684. h->Qdepth--;
  2685. /* Tell the controller execute command */
  2686. h->access.submit_command(h, c);
  2687. /* Put job onto the completed Q */
  2688. addQ(&h->cmpQ, c);
  2689. }
  2690. }
  2691. static inline unsigned long get_next_completion(struct ctlr_info *h)
  2692. {
  2693. return h->access.command_completed(h);
  2694. }
  2695. static inline bool interrupt_pending(struct ctlr_info *h)
  2696. {
  2697. return h->access.intr_pending(h);
  2698. }
  2699. static inline long interrupt_not_for_us(struct ctlr_info *h)
  2700. {
  2701. return (h->access.intr_pending(h) == 0) ||
  2702. (h->interrupts_enabled == 0);
  2703. }
  2704. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  2705. u32 raw_tag)
  2706. {
  2707. if (unlikely(tag_index >= h->nr_cmds)) {
  2708. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  2709. return 1;
  2710. }
  2711. return 0;
  2712. }
  2713. static inline void finish_cmd(struct CommandList *c, u32 raw_tag)
  2714. {
  2715. removeQ(c);
  2716. if (likely(c->cmd_type == CMD_SCSI))
  2717. complete_scsi_command(c);
  2718. else if (c->cmd_type == CMD_IOCTL_PEND)
  2719. complete(c->waiting);
  2720. }
  2721. static inline u32 hpsa_tag_contains_index(u32 tag)
  2722. {
  2723. return tag & DIRECT_LOOKUP_BIT;
  2724. }
  2725. static inline u32 hpsa_tag_to_index(u32 tag)
  2726. {
  2727. return tag >> DIRECT_LOOKUP_SHIFT;
  2728. }
  2729. static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
  2730. {
  2731. #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
  2732. #define HPSA_SIMPLE_ERROR_BITS 0x03
  2733. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  2734. return tag & ~HPSA_SIMPLE_ERROR_BITS;
  2735. return tag & ~HPSA_PERF_ERROR_BITS;
  2736. }
  2737. /* process completion of an indexed ("direct lookup") command */
  2738. static inline u32 process_indexed_cmd(struct ctlr_info *h,
  2739. u32 raw_tag)
  2740. {
  2741. u32 tag_index;
  2742. struct CommandList *c;
  2743. tag_index = hpsa_tag_to_index(raw_tag);
  2744. if (bad_tag(h, tag_index, raw_tag))
  2745. return next_command(h);
  2746. c = h->cmd_pool + tag_index;
  2747. finish_cmd(c, raw_tag);
  2748. return next_command(h);
  2749. }
  2750. /* process completion of a non-indexed command */
  2751. static inline u32 process_nonindexed_cmd(struct ctlr_info *h,
  2752. u32 raw_tag)
  2753. {
  2754. u32 tag;
  2755. struct CommandList *c = NULL;
  2756. tag = hpsa_tag_discard_error_bits(h, raw_tag);
  2757. list_for_each_entry(c, &h->cmpQ, list) {
  2758. if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
  2759. finish_cmd(c, raw_tag);
  2760. return next_command(h);
  2761. }
  2762. }
  2763. bad_tag(h, h->nr_cmds + 1, raw_tag);
  2764. return next_command(h);
  2765. }
  2766. /* Some controllers, like p400, will give us one interrupt
  2767. * after a soft reset, even if we turned interrupts off.
  2768. * Only need to check for this in the hpsa_xxx_discard_completions
  2769. * functions.
  2770. */
  2771. static int ignore_bogus_interrupt(struct ctlr_info *h)
  2772. {
  2773. if (likely(!reset_devices))
  2774. return 0;
  2775. if (likely(h->interrupts_enabled))
  2776. return 0;
  2777. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  2778. "(known firmware bug.) Ignoring.\n");
  2779. return 1;
  2780. }
  2781. static irqreturn_t hpsa_intx_discard_completions(int irq, void *dev_id)
  2782. {
  2783. struct ctlr_info *h = dev_id;
  2784. unsigned long flags;
  2785. u32 raw_tag;
  2786. if (ignore_bogus_interrupt(h))
  2787. return IRQ_NONE;
  2788. if (interrupt_not_for_us(h))
  2789. return IRQ_NONE;
  2790. spin_lock_irqsave(&h->lock, flags);
  2791. h->last_intr_timestamp = get_jiffies_64();
  2792. while (interrupt_pending(h)) {
  2793. raw_tag = get_next_completion(h);
  2794. while (raw_tag != FIFO_EMPTY)
  2795. raw_tag = next_command(h);
  2796. }
  2797. spin_unlock_irqrestore(&h->lock, flags);
  2798. return IRQ_HANDLED;
  2799. }
  2800. static irqreturn_t hpsa_msix_discard_completions(int irq, void *dev_id)
  2801. {
  2802. struct ctlr_info *h = dev_id;
  2803. unsigned long flags;
  2804. u32 raw_tag;
  2805. if (ignore_bogus_interrupt(h))
  2806. return IRQ_NONE;
  2807. spin_lock_irqsave(&h->lock, flags);
  2808. h->last_intr_timestamp = get_jiffies_64();
  2809. raw_tag = get_next_completion(h);
  2810. while (raw_tag != FIFO_EMPTY)
  2811. raw_tag = next_command(h);
  2812. spin_unlock_irqrestore(&h->lock, flags);
  2813. return IRQ_HANDLED;
  2814. }
  2815. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id)
  2816. {
  2817. struct ctlr_info *h = dev_id;
  2818. unsigned long flags;
  2819. u32 raw_tag;
  2820. if (interrupt_not_for_us(h))
  2821. return IRQ_NONE;
  2822. spin_lock_irqsave(&h->lock, flags);
  2823. h->last_intr_timestamp = get_jiffies_64();
  2824. while (interrupt_pending(h)) {
  2825. raw_tag = get_next_completion(h);
  2826. while (raw_tag != FIFO_EMPTY) {
  2827. if (hpsa_tag_contains_index(raw_tag))
  2828. raw_tag = process_indexed_cmd(h, raw_tag);
  2829. else
  2830. raw_tag = process_nonindexed_cmd(h, raw_tag);
  2831. }
  2832. }
  2833. spin_unlock_irqrestore(&h->lock, flags);
  2834. return IRQ_HANDLED;
  2835. }
  2836. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id)
  2837. {
  2838. struct ctlr_info *h = dev_id;
  2839. unsigned long flags;
  2840. u32 raw_tag;
  2841. spin_lock_irqsave(&h->lock, flags);
  2842. h->last_intr_timestamp = get_jiffies_64();
  2843. raw_tag = get_next_completion(h);
  2844. while (raw_tag != FIFO_EMPTY) {
  2845. if (hpsa_tag_contains_index(raw_tag))
  2846. raw_tag = process_indexed_cmd(h, raw_tag);
  2847. else
  2848. raw_tag = process_nonindexed_cmd(h, raw_tag);
  2849. }
  2850. spin_unlock_irqrestore(&h->lock, flags);
  2851. return IRQ_HANDLED;
  2852. }
  2853. /* Send a message CDB to the firmware. Careful, this only works
  2854. * in simple mode, not performant mode due to the tag lookup.
  2855. * We only ever use this immediately after a controller reset.
  2856. */
  2857. static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  2858. unsigned char type)
  2859. {
  2860. struct Command {
  2861. struct CommandListHeader CommandHeader;
  2862. struct RequestBlock Request;
  2863. struct ErrDescriptor ErrorDescriptor;
  2864. };
  2865. struct Command *cmd;
  2866. static const size_t cmd_sz = sizeof(*cmd) +
  2867. sizeof(cmd->ErrorDescriptor);
  2868. dma_addr_t paddr64;
  2869. uint32_t paddr32, tag;
  2870. void __iomem *vaddr;
  2871. int i, err;
  2872. vaddr = pci_ioremap_bar(pdev, 0);
  2873. if (vaddr == NULL)
  2874. return -ENOMEM;
  2875. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  2876. * CCISS commands, so they must be allocated from the lower 4GiB of
  2877. * memory.
  2878. */
  2879. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2880. if (err) {
  2881. iounmap(vaddr);
  2882. return -ENOMEM;
  2883. }
  2884. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  2885. if (cmd == NULL) {
  2886. iounmap(vaddr);
  2887. return -ENOMEM;
  2888. }
  2889. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  2890. * although there's no guarantee, we assume that the address is at
  2891. * least 4-byte aligned (most likely, it's page-aligned).
  2892. */
  2893. paddr32 = paddr64;
  2894. cmd->CommandHeader.ReplyQueue = 0;
  2895. cmd->CommandHeader.SGList = 0;
  2896. cmd->CommandHeader.SGTotal = 0;
  2897. cmd->CommandHeader.Tag.lower = paddr32;
  2898. cmd->CommandHeader.Tag.upper = 0;
  2899. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  2900. cmd->Request.CDBLen = 16;
  2901. cmd->Request.Type.Type = TYPE_MSG;
  2902. cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
  2903. cmd->Request.Type.Direction = XFER_NONE;
  2904. cmd->Request.Timeout = 0; /* Don't time out */
  2905. cmd->Request.CDB[0] = opcode;
  2906. cmd->Request.CDB[1] = type;
  2907. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  2908. cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
  2909. cmd->ErrorDescriptor.Addr.upper = 0;
  2910. cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
  2911. writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
  2912. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  2913. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  2914. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
  2915. break;
  2916. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  2917. }
  2918. iounmap(vaddr);
  2919. /* we leak the DMA buffer here ... no choice since the controller could
  2920. * still complete the command.
  2921. */
  2922. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  2923. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  2924. opcode, type);
  2925. return -ETIMEDOUT;
  2926. }
  2927. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  2928. if (tag & HPSA_ERROR_BIT) {
  2929. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  2930. opcode, type);
  2931. return -EIO;
  2932. }
  2933. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  2934. opcode, type);
  2935. return 0;
  2936. }
  2937. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  2938. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  2939. void * __iomem vaddr, u32 use_doorbell)
  2940. {
  2941. u16 pmcsr;
  2942. int pos;
  2943. if (use_doorbell) {
  2944. /* For everything after the P600, the PCI power state method
  2945. * of resetting the controller doesn't work, so we have this
  2946. * other way using the doorbell register.
  2947. */
  2948. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  2949. writel(use_doorbell, vaddr + SA5_DOORBELL);
  2950. } else { /* Try to do it the PCI power state way */
  2951. /* Quoting from the Open CISS Specification: "The Power
  2952. * Management Control/Status Register (CSR) controls the power
  2953. * state of the device. The normal operating state is D0,
  2954. * CSR=00h. The software off state is D3, CSR=03h. To reset
  2955. * the controller, place the interface device in D3 then to D0,
  2956. * this causes a secondary PCI reset which will reset the
  2957. * controller." */
  2958. pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
  2959. if (pos == 0) {
  2960. dev_err(&pdev->dev,
  2961. "hpsa_reset_controller: "
  2962. "PCI PM not supported\n");
  2963. return -ENODEV;
  2964. }
  2965. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  2966. /* enter the D3hot power management state */
  2967. pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
  2968. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2969. pmcsr |= PCI_D3hot;
  2970. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  2971. msleep(500);
  2972. /* enter the D0 power management state */
  2973. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2974. pmcsr |= PCI_D0;
  2975. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  2976. /*
  2977. * The P600 requires a small delay when changing states.
  2978. * Otherwise we may think the board did not reset and we bail.
  2979. * This for kdump only and is particular to the P600.
  2980. */
  2981. msleep(500);
  2982. }
  2983. return 0;
  2984. }
  2985. static __devinit void init_driver_version(char *driver_version, int len)
  2986. {
  2987. memset(driver_version, 0, len);
  2988. strncpy(driver_version, "hpsa " HPSA_DRIVER_VERSION, len - 1);
  2989. }
  2990. static __devinit int write_driver_ver_to_cfgtable(
  2991. struct CfgTable __iomem *cfgtable)
  2992. {
  2993. char *driver_version;
  2994. int i, size = sizeof(cfgtable->driver_version);
  2995. driver_version = kmalloc(size, GFP_KERNEL);
  2996. if (!driver_version)
  2997. return -ENOMEM;
  2998. init_driver_version(driver_version, size);
  2999. for (i = 0; i < size; i++)
  3000. writeb(driver_version[i], &cfgtable->driver_version[i]);
  3001. kfree(driver_version);
  3002. return 0;
  3003. }
  3004. static __devinit void read_driver_ver_from_cfgtable(
  3005. struct CfgTable __iomem *cfgtable, unsigned char *driver_ver)
  3006. {
  3007. int i;
  3008. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  3009. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  3010. }
  3011. static __devinit int controller_reset_failed(
  3012. struct CfgTable __iomem *cfgtable)
  3013. {
  3014. char *driver_ver, *old_driver_ver;
  3015. int rc, size = sizeof(cfgtable->driver_version);
  3016. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  3017. if (!old_driver_ver)
  3018. return -ENOMEM;
  3019. driver_ver = old_driver_ver + size;
  3020. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  3021. * should have been changed, otherwise we know the reset failed.
  3022. */
  3023. init_driver_version(old_driver_ver, size);
  3024. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  3025. rc = !memcmp(driver_ver, old_driver_ver, size);
  3026. kfree(old_driver_ver);
  3027. return rc;
  3028. }
  3029. /* This does a hard reset of the controller using PCI power management
  3030. * states or the using the doorbell register.
  3031. */
  3032. static __devinit int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
  3033. {
  3034. u64 cfg_offset;
  3035. u32 cfg_base_addr;
  3036. u64 cfg_base_addr_index;
  3037. void __iomem *vaddr;
  3038. unsigned long paddr;
  3039. u32 misc_fw_support;
  3040. int rc;
  3041. struct CfgTable __iomem *cfgtable;
  3042. u32 use_doorbell;
  3043. u32 board_id;
  3044. u16 command_register;
  3045. /* For controllers as old as the P600, this is very nearly
  3046. * the same thing as
  3047. *
  3048. * pci_save_state(pci_dev);
  3049. * pci_set_power_state(pci_dev, PCI_D3hot);
  3050. * pci_set_power_state(pci_dev, PCI_D0);
  3051. * pci_restore_state(pci_dev);
  3052. *
  3053. * For controllers newer than the P600, the pci power state
  3054. * method of resetting doesn't work so we have another way
  3055. * using the doorbell register.
  3056. */
  3057. rc = hpsa_lookup_board_id(pdev, &board_id);
  3058. if (rc < 0 || !ctlr_is_resettable(board_id)) {
  3059. dev_warn(&pdev->dev, "Not resetting device.\n");
  3060. return -ENODEV;
  3061. }
  3062. /* if controller is soft- but not hard resettable... */
  3063. if (!ctlr_is_hard_resettable(board_id))
  3064. return -ENOTSUPP; /* try soft reset later. */
  3065. /* Save the PCI command register */
  3066. pci_read_config_word(pdev, 4, &command_register);
  3067. /* Turn the board off. This is so that later pci_restore_state()
  3068. * won't turn the board on before the rest of config space is ready.
  3069. */
  3070. pci_disable_device(pdev);
  3071. pci_save_state(pdev);
  3072. /* find the first memory BAR, so we can find the cfg table */
  3073. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  3074. if (rc)
  3075. return rc;
  3076. vaddr = remap_pci_mem(paddr, 0x250);
  3077. if (!vaddr)
  3078. return -ENOMEM;
  3079. /* find cfgtable in order to check if reset via doorbell is supported */
  3080. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  3081. &cfg_base_addr_index, &cfg_offset);
  3082. if (rc)
  3083. goto unmap_vaddr;
  3084. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  3085. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  3086. if (!cfgtable) {
  3087. rc = -ENOMEM;
  3088. goto unmap_vaddr;
  3089. }
  3090. rc = write_driver_ver_to_cfgtable(cfgtable);
  3091. if (rc)
  3092. goto unmap_vaddr;
  3093. /* If reset via doorbell register is supported, use that.
  3094. * There are two such methods. Favor the newest method.
  3095. */
  3096. misc_fw_support = readl(&cfgtable->misc_fw_support);
  3097. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  3098. if (use_doorbell) {
  3099. use_doorbell = DOORBELL_CTLR_RESET2;
  3100. } else {
  3101. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  3102. if (use_doorbell) {
  3103. dev_warn(&pdev->dev, "Soft reset not supported. "
  3104. "Firmware update is required.\n");
  3105. rc = -ENOTSUPP; /* try soft reset */
  3106. goto unmap_cfgtable;
  3107. }
  3108. }
  3109. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  3110. if (rc)
  3111. goto unmap_cfgtable;
  3112. pci_restore_state(pdev);
  3113. rc = pci_enable_device(pdev);
  3114. if (rc) {
  3115. dev_warn(&pdev->dev, "failed to enable device.\n");
  3116. goto unmap_cfgtable;
  3117. }
  3118. pci_write_config_word(pdev, 4, command_register);
  3119. /* Some devices (notably the HP Smart Array 5i Controller)
  3120. need a little pause here */
  3121. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  3122. /* Wait for board to become not ready, then ready. */
  3123. dev_info(&pdev->dev, "Waiting for board to reset.\n");
  3124. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
  3125. if (rc) {
  3126. dev_warn(&pdev->dev,
  3127. "failed waiting for board to reset."
  3128. " Will try soft reset.\n");
  3129. rc = -ENOTSUPP; /* Not expected, but try soft reset later */
  3130. goto unmap_cfgtable;
  3131. }
  3132. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  3133. if (rc) {
  3134. dev_warn(&pdev->dev,
  3135. "failed waiting for board to become ready "
  3136. "after hard reset\n");
  3137. goto unmap_cfgtable;
  3138. }
  3139. rc = controller_reset_failed(vaddr);
  3140. if (rc < 0)
  3141. goto unmap_cfgtable;
  3142. if (rc) {
  3143. dev_warn(&pdev->dev, "Unable to successfully reset "
  3144. "controller. Will try soft reset.\n");
  3145. rc = -ENOTSUPP;
  3146. } else {
  3147. dev_info(&pdev->dev, "board ready after hard reset.\n");
  3148. }
  3149. unmap_cfgtable:
  3150. iounmap(cfgtable);
  3151. unmap_vaddr:
  3152. iounmap(vaddr);
  3153. return rc;
  3154. }
  3155. /*
  3156. * We cannot read the structure directly, for portability we must use
  3157. * the io functions.
  3158. * This is for debug only.
  3159. */
  3160. static void print_cfg_table(struct device *dev, struct CfgTable *tb)
  3161. {
  3162. #ifdef HPSA_DEBUG
  3163. int i;
  3164. char temp_name[17];
  3165. dev_info(dev, "Controller Configuration information\n");
  3166. dev_info(dev, "------------------------------------\n");
  3167. for (i = 0; i < 4; i++)
  3168. temp_name[i] = readb(&(tb->Signature[i]));
  3169. temp_name[4] = '\0';
  3170. dev_info(dev, " Signature = %s\n", temp_name);
  3171. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  3172. dev_info(dev, " Transport methods supported = 0x%x\n",
  3173. readl(&(tb->TransportSupport)));
  3174. dev_info(dev, " Transport methods active = 0x%x\n",
  3175. readl(&(tb->TransportActive)));
  3176. dev_info(dev, " Requested transport Method = 0x%x\n",
  3177. readl(&(tb->HostWrite.TransportRequest)));
  3178. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  3179. readl(&(tb->HostWrite.CoalIntDelay)));
  3180. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  3181. readl(&(tb->HostWrite.CoalIntCount)));
  3182. dev_info(dev, " Max outstanding commands = 0x%d\n",
  3183. readl(&(tb->CmdsOutMax)));
  3184. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  3185. for (i = 0; i < 16; i++)
  3186. temp_name[i] = readb(&(tb->ServerName[i]));
  3187. temp_name[16] = '\0';
  3188. dev_info(dev, " Server Name = %s\n", temp_name);
  3189. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  3190. readl(&(tb->HeartBeat)));
  3191. #endif /* HPSA_DEBUG */
  3192. }
  3193. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  3194. {
  3195. int i, offset, mem_type, bar_type;
  3196. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  3197. return 0;
  3198. offset = 0;
  3199. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  3200. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  3201. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  3202. offset += 4;
  3203. else {
  3204. mem_type = pci_resource_flags(pdev, i) &
  3205. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  3206. switch (mem_type) {
  3207. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  3208. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  3209. offset += 4; /* 32 bit */
  3210. break;
  3211. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  3212. offset += 8;
  3213. break;
  3214. default: /* reserved in PCI 2.2 */
  3215. dev_warn(&pdev->dev,
  3216. "base address is invalid\n");
  3217. return -1;
  3218. break;
  3219. }
  3220. }
  3221. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  3222. return i + 1;
  3223. }
  3224. return -1;
  3225. }
  3226. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  3227. * controllers that are capable. If not, we use IO-APIC mode.
  3228. */
  3229. static void __devinit hpsa_interrupt_mode(struct ctlr_info *h)
  3230. {
  3231. #ifdef CONFIG_PCI_MSI
  3232. int err;
  3233. struct msix_entry hpsa_msix_entries[4] = { {0, 0}, {0, 1},
  3234. {0, 2}, {0, 3}
  3235. };
  3236. /* Some boards advertise MSI but don't really support it */
  3237. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  3238. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  3239. goto default_int_mode;
  3240. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  3241. dev_info(&h->pdev->dev, "MSIX\n");
  3242. err = pci_enable_msix(h->pdev, hpsa_msix_entries, 4);
  3243. if (!err) {
  3244. h->intr[0] = hpsa_msix_entries[0].vector;
  3245. h->intr[1] = hpsa_msix_entries[1].vector;
  3246. h->intr[2] = hpsa_msix_entries[2].vector;
  3247. h->intr[3] = hpsa_msix_entries[3].vector;
  3248. h->msix_vector = 1;
  3249. return;
  3250. }
  3251. if (err > 0) {
  3252. dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
  3253. "available\n", err);
  3254. goto default_int_mode;
  3255. } else {
  3256. dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
  3257. err);
  3258. goto default_int_mode;
  3259. }
  3260. }
  3261. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  3262. dev_info(&h->pdev->dev, "MSI\n");
  3263. if (!pci_enable_msi(h->pdev))
  3264. h->msi_vector = 1;
  3265. else
  3266. dev_warn(&h->pdev->dev, "MSI init failed\n");
  3267. }
  3268. default_int_mode:
  3269. #endif /* CONFIG_PCI_MSI */
  3270. /* if we get here we're going to use the default interrupt mode */
  3271. h->intr[h->intr_mode] = h->pdev->irq;
  3272. }
  3273. static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  3274. {
  3275. int i;
  3276. u32 subsystem_vendor_id, subsystem_device_id;
  3277. subsystem_vendor_id = pdev->subsystem_vendor;
  3278. subsystem_device_id = pdev->subsystem_device;
  3279. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  3280. subsystem_vendor_id;
  3281. for (i = 0; i < ARRAY_SIZE(products); i++)
  3282. if (*board_id == products[i].board_id)
  3283. return i;
  3284. if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
  3285. subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
  3286. !hpsa_allow_any) {
  3287. dev_warn(&pdev->dev, "unrecognized board ID: "
  3288. "0x%08x, ignoring.\n", *board_id);
  3289. return -ENODEV;
  3290. }
  3291. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  3292. }
  3293. static inline bool hpsa_board_disabled(struct pci_dev *pdev)
  3294. {
  3295. u16 command;
  3296. (void) pci_read_config_word(pdev, PCI_COMMAND, &command);
  3297. return ((command & PCI_COMMAND_MEMORY) == 0);
  3298. }
  3299. static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  3300. unsigned long *memory_bar)
  3301. {
  3302. int i;
  3303. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  3304. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  3305. /* addressing mode bits already removed */
  3306. *memory_bar = pci_resource_start(pdev, i);
  3307. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  3308. *memory_bar);
  3309. return 0;
  3310. }
  3311. dev_warn(&pdev->dev, "no memory BAR found\n");
  3312. return -ENODEV;
  3313. }
  3314. static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
  3315. void __iomem *vaddr, int wait_for_ready)
  3316. {
  3317. int i, iterations;
  3318. u32 scratchpad;
  3319. if (wait_for_ready)
  3320. iterations = HPSA_BOARD_READY_ITERATIONS;
  3321. else
  3322. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  3323. for (i = 0; i < iterations; i++) {
  3324. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  3325. if (wait_for_ready) {
  3326. if (scratchpad == HPSA_FIRMWARE_READY)
  3327. return 0;
  3328. } else {
  3329. if (scratchpad != HPSA_FIRMWARE_READY)
  3330. return 0;
  3331. }
  3332. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  3333. }
  3334. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  3335. return -ENODEV;
  3336. }
  3337. static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
  3338. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  3339. u64 *cfg_offset)
  3340. {
  3341. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  3342. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  3343. *cfg_base_addr &= (u32) 0x0000ffff;
  3344. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  3345. if (*cfg_base_addr_index == -1) {
  3346. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  3347. return -ENODEV;
  3348. }
  3349. return 0;
  3350. }
  3351. static int __devinit hpsa_find_cfgtables(struct ctlr_info *h)
  3352. {
  3353. u64 cfg_offset;
  3354. u32 cfg_base_addr;
  3355. u64 cfg_base_addr_index;
  3356. u32 trans_offset;
  3357. int rc;
  3358. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  3359. &cfg_base_addr_index, &cfg_offset);
  3360. if (rc)
  3361. return rc;
  3362. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  3363. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  3364. if (!h->cfgtable)
  3365. return -ENOMEM;
  3366. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  3367. if (rc)
  3368. return rc;
  3369. /* Find performant mode table. */
  3370. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  3371. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  3372. cfg_base_addr_index)+cfg_offset+trans_offset,
  3373. sizeof(*h->transtable));
  3374. if (!h->transtable)
  3375. return -ENOMEM;
  3376. return 0;
  3377. }
  3378. static void __devinit hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  3379. {
  3380. h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
  3381. /* Limit commands in memory limited kdump scenario. */
  3382. if (reset_devices && h->max_commands > 32)
  3383. h->max_commands = 32;
  3384. if (h->max_commands < 16) {
  3385. dev_warn(&h->pdev->dev, "Controller reports "
  3386. "max supported commands of %d, an obvious lie. "
  3387. "Using 16. Ensure that firmware is up to date.\n",
  3388. h->max_commands);
  3389. h->max_commands = 16;
  3390. }
  3391. }
  3392. /* Interrogate the hardware for some limits:
  3393. * max commands, max SG elements without chaining, and with chaining,
  3394. * SG chain block size, etc.
  3395. */
  3396. static void __devinit hpsa_find_board_params(struct ctlr_info *h)
  3397. {
  3398. hpsa_get_max_perf_mode_cmds(h);
  3399. h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
  3400. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  3401. /*
  3402. * Limit in-command s/g elements to 32 save dma'able memory.
  3403. * Howvever spec says if 0, use 31
  3404. */
  3405. h->max_cmd_sg_entries = 31;
  3406. if (h->maxsgentries > 512) {
  3407. h->max_cmd_sg_entries = 32;
  3408. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
  3409. h->maxsgentries--; /* save one for chain pointer */
  3410. } else {
  3411. h->maxsgentries = 31; /* default to traditional values */
  3412. h->chainsize = 0;
  3413. }
  3414. }
  3415. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  3416. {
  3417. if ((readb(&h->cfgtable->Signature[0]) != 'C') ||
  3418. (readb(&h->cfgtable->Signature[1]) != 'I') ||
  3419. (readb(&h->cfgtable->Signature[2]) != 'S') ||
  3420. (readb(&h->cfgtable->Signature[3]) != 'S')) {
  3421. dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
  3422. return false;
  3423. }
  3424. return true;
  3425. }
  3426. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  3427. static inline void hpsa_enable_scsi_prefetch(struct ctlr_info *h)
  3428. {
  3429. #ifdef CONFIG_X86
  3430. u32 prefetch;
  3431. prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
  3432. prefetch |= 0x100;
  3433. writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
  3434. #endif
  3435. }
  3436. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  3437. * in a prefetch beyond physical memory.
  3438. */
  3439. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  3440. {
  3441. u32 dma_prefetch;
  3442. if (h->board_id != 0x3225103C)
  3443. return;
  3444. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  3445. dma_prefetch |= 0x8000;
  3446. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  3447. }
  3448. static void __devinit hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  3449. {
  3450. int i;
  3451. u32 doorbell_value;
  3452. unsigned long flags;
  3453. /* under certain very rare conditions, this can take awhile.
  3454. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  3455. * as we enter this code.)
  3456. */
  3457. for (i = 0; i < MAX_CONFIG_WAIT; i++) {
  3458. spin_lock_irqsave(&h->lock, flags);
  3459. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  3460. spin_unlock_irqrestore(&h->lock, flags);
  3461. if (!(doorbell_value & CFGTBL_ChangeReq))
  3462. break;
  3463. /* delay and try again */
  3464. usleep_range(10000, 20000);
  3465. }
  3466. }
  3467. static int __devinit hpsa_enter_simple_mode(struct ctlr_info *h)
  3468. {
  3469. u32 trans_support;
  3470. trans_support = readl(&(h->cfgtable->TransportSupport));
  3471. if (!(trans_support & SIMPLE_MODE))
  3472. return -ENOTSUPP;
  3473. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  3474. /* Update the field, and then ring the doorbell */
  3475. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  3476. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  3477. hpsa_wait_for_mode_change_ack(h);
  3478. print_cfg_table(&h->pdev->dev, h->cfgtable);
  3479. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
  3480. dev_warn(&h->pdev->dev,
  3481. "unable to get board into simple mode\n");
  3482. return -ENODEV;
  3483. }
  3484. h->transMethod = CFGTBL_Trans_Simple;
  3485. return 0;
  3486. }
  3487. static int __devinit hpsa_pci_init(struct ctlr_info *h)
  3488. {
  3489. int prod_index, err;
  3490. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
  3491. if (prod_index < 0)
  3492. return -ENODEV;
  3493. h->product_name = products[prod_index].product_name;
  3494. h->access = *(products[prod_index].access);
  3495. if (hpsa_board_disabled(h->pdev)) {
  3496. dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
  3497. return -ENODEV;
  3498. }
  3499. pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
  3500. PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
  3501. err = pci_enable_device(h->pdev);
  3502. if (err) {
  3503. dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
  3504. return err;
  3505. }
  3506. err = pci_request_regions(h->pdev, "hpsa");
  3507. if (err) {
  3508. dev_err(&h->pdev->dev,
  3509. "cannot obtain PCI resources, aborting\n");
  3510. return err;
  3511. }
  3512. hpsa_interrupt_mode(h);
  3513. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  3514. if (err)
  3515. goto err_out_free_res;
  3516. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  3517. if (!h->vaddr) {
  3518. err = -ENOMEM;
  3519. goto err_out_free_res;
  3520. }
  3521. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  3522. if (err)
  3523. goto err_out_free_res;
  3524. err = hpsa_find_cfgtables(h);
  3525. if (err)
  3526. goto err_out_free_res;
  3527. hpsa_find_board_params(h);
  3528. if (!hpsa_CISS_signature_present(h)) {
  3529. err = -ENODEV;
  3530. goto err_out_free_res;
  3531. }
  3532. hpsa_enable_scsi_prefetch(h);
  3533. hpsa_p600_dma_prefetch_quirk(h);
  3534. err = hpsa_enter_simple_mode(h);
  3535. if (err)
  3536. goto err_out_free_res;
  3537. return 0;
  3538. err_out_free_res:
  3539. if (h->transtable)
  3540. iounmap(h->transtable);
  3541. if (h->cfgtable)
  3542. iounmap(h->cfgtable);
  3543. if (h->vaddr)
  3544. iounmap(h->vaddr);
  3545. /*
  3546. * Deliberately omit pci_disable_device(): it does something nasty to
  3547. * Smart Array controllers that pci_enable_device does not undo
  3548. */
  3549. pci_release_regions(h->pdev);
  3550. return err;
  3551. }
  3552. static void __devinit hpsa_hba_inquiry(struct ctlr_info *h)
  3553. {
  3554. int rc;
  3555. #define HBA_INQUIRY_BYTE_COUNT 64
  3556. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  3557. if (!h->hba_inquiry_data)
  3558. return;
  3559. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  3560. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  3561. if (rc != 0) {
  3562. kfree(h->hba_inquiry_data);
  3563. h->hba_inquiry_data = NULL;
  3564. }
  3565. }
  3566. static __devinit int hpsa_init_reset_devices(struct pci_dev *pdev)
  3567. {
  3568. int rc, i;
  3569. if (!reset_devices)
  3570. return 0;
  3571. /* Reset the controller with a PCI power-cycle or via doorbell */
  3572. rc = hpsa_kdump_hard_reset_controller(pdev);
  3573. /* -ENOTSUPP here means we cannot reset the controller
  3574. * but it's already (and still) up and running in
  3575. * "performant mode". Or, it might be 640x, which can't reset
  3576. * due to concerns about shared bbwc between 6402/6404 pair.
  3577. */
  3578. if (rc == -ENOTSUPP)
  3579. return rc; /* just try to do the kdump anyhow. */
  3580. if (rc)
  3581. return -ENODEV;
  3582. /* Now try to get the controller to respond to a no-op */
  3583. dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
  3584. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  3585. if (hpsa_noop(pdev) == 0)
  3586. break;
  3587. else
  3588. dev_warn(&pdev->dev, "no-op failed%s\n",
  3589. (i < 11 ? "; re-trying" : ""));
  3590. }
  3591. return 0;
  3592. }
  3593. static __devinit int hpsa_allocate_cmd_pool(struct ctlr_info *h)
  3594. {
  3595. h->cmd_pool_bits = kzalloc(
  3596. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  3597. sizeof(unsigned long), GFP_KERNEL);
  3598. h->cmd_pool = pci_alloc_consistent(h->pdev,
  3599. h->nr_cmds * sizeof(*h->cmd_pool),
  3600. &(h->cmd_pool_dhandle));
  3601. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  3602. h->nr_cmds * sizeof(*h->errinfo_pool),
  3603. &(h->errinfo_pool_dhandle));
  3604. if ((h->cmd_pool_bits == NULL)
  3605. || (h->cmd_pool == NULL)
  3606. || (h->errinfo_pool == NULL)) {
  3607. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  3608. return -ENOMEM;
  3609. }
  3610. return 0;
  3611. }
  3612. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  3613. {
  3614. kfree(h->cmd_pool_bits);
  3615. if (h->cmd_pool)
  3616. pci_free_consistent(h->pdev,
  3617. h->nr_cmds * sizeof(struct CommandList),
  3618. h->cmd_pool, h->cmd_pool_dhandle);
  3619. if (h->errinfo_pool)
  3620. pci_free_consistent(h->pdev,
  3621. h->nr_cmds * sizeof(struct ErrorInfo),
  3622. h->errinfo_pool,
  3623. h->errinfo_pool_dhandle);
  3624. }
  3625. static int hpsa_request_irq(struct ctlr_info *h,
  3626. irqreturn_t (*msixhandler)(int, void *),
  3627. irqreturn_t (*intxhandler)(int, void *))
  3628. {
  3629. int rc;
  3630. if (h->msix_vector || h->msi_vector)
  3631. rc = request_irq(h->intr[h->intr_mode], msixhandler,
  3632. 0, h->devname, h);
  3633. else
  3634. rc = request_irq(h->intr[h->intr_mode], intxhandler,
  3635. IRQF_SHARED, h->devname, h);
  3636. if (rc) {
  3637. dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
  3638. h->intr[h->intr_mode], h->devname);
  3639. return -ENODEV;
  3640. }
  3641. return 0;
  3642. }
  3643. static int __devinit hpsa_kdump_soft_reset(struct ctlr_info *h)
  3644. {
  3645. if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
  3646. HPSA_RESET_TYPE_CONTROLLER)) {
  3647. dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
  3648. return -EIO;
  3649. }
  3650. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  3651. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
  3652. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  3653. return -1;
  3654. }
  3655. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  3656. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
  3657. dev_warn(&h->pdev->dev, "Board failed to become ready "
  3658. "after soft reset.\n");
  3659. return -1;
  3660. }
  3661. return 0;
  3662. }
  3663. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  3664. {
  3665. free_irq(h->intr[h->intr_mode], h);
  3666. #ifdef CONFIG_PCI_MSI
  3667. if (h->msix_vector)
  3668. pci_disable_msix(h->pdev);
  3669. else if (h->msi_vector)
  3670. pci_disable_msi(h->pdev);
  3671. #endif /* CONFIG_PCI_MSI */
  3672. hpsa_free_sg_chain_blocks(h);
  3673. hpsa_free_cmd_pool(h);
  3674. kfree(h->blockFetchTable);
  3675. pci_free_consistent(h->pdev, h->reply_pool_size,
  3676. h->reply_pool, h->reply_pool_dhandle);
  3677. if (h->vaddr)
  3678. iounmap(h->vaddr);
  3679. if (h->transtable)
  3680. iounmap(h->transtable);
  3681. if (h->cfgtable)
  3682. iounmap(h->cfgtable);
  3683. pci_release_regions(h->pdev);
  3684. kfree(h);
  3685. }
  3686. static void remove_ctlr_from_lockup_detector_list(struct ctlr_info *h)
  3687. {
  3688. assert_spin_locked(&lockup_detector_lock);
  3689. if (!hpsa_lockup_detector)
  3690. return;
  3691. if (h->lockup_detected)
  3692. return; /* already stopped the lockup detector */
  3693. list_del(&h->lockup_list);
  3694. }
  3695. /* Called when controller lockup detected. */
  3696. static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
  3697. {
  3698. struct CommandList *c = NULL;
  3699. assert_spin_locked(&h->lock);
  3700. /* Mark all outstanding commands as failed and complete them. */
  3701. while (!list_empty(list)) {
  3702. c = list_entry(list->next, struct CommandList, list);
  3703. c->err_info->CommandStatus = CMD_HARDWARE_ERR;
  3704. finish_cmd(c, c->Header.Tag.lower);
  3705. }
  3706. }
  3707. static void controller_lockup_detected(struct ctlr_info *h)
  3708. {
  3709. unsigned long flags;
  3710. assert_spin_locked(&lockup_detector_lock);
  3711. remove_ctlr_from_lockup_detector_list(h);
  3712. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3713. spin_lock_irqsave(&h->lock, flags);
  3714. h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  3715. spin_unlock_irqrestore(&h->lock, flags);
  3716. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
  3717. h->lockup_detected);
  3718. pci_disable_device(h->pdev);
  3719. spin_lock_irqsave(&h->lock, flags);
  3720. fail_all_cmds_on_list(h, &h->cmpQ);
  3721. fail_all_cmds_on_list(h, &h->reqQ);
  3722. spin_unlock_irqrestore(&h->lock, flags);
  3723. }
  3724. #define HEARTBEAT_SAMPLE_INTERVAL (10 * HZ)
  3725. #define HEARTBEAT_CHECK_MINIMUM_INTERVAL (HEARTBEAT_SAMPLE_INTERVAL / 2)
  3726. static void detect_controller_lockup(struct ctlr_info *h)
  3727. {
  3728. u64 now;
  3729. u32 heartbeat;
  3730. unsigned long flags;
  3731. assert_spin_locked(&lockup_detector_lock);
  3732. now = get_jiffies_64();
  3733. /* If we've received an interrupt recently, we're ok. */
  3734. if (time_after64(h->last_intr_timestamp +
  3735. (HEARTBEAT_CHECK_MINIMUM_INTERVAL), now))
  3736. return;
  3737. /*
  3738. * If we've already checked the heartbeat recently, we're ok.
  3739. * This could happen if someone sends us a signal. We
  3740. * otherwise don't care about signals in this thread.
  3741. */
  3742. if (time_after64(h->last_heartbeat_timestamp +
  3743. (HEARTBEAT_CHECK_MINIMUM_INTERVAL), now))
  3744. return;
  3745. /* If heartbeat has not changed since we last looked, we're not ok. */
  3746. spin_lock_irqsave(&h->lock, flags);
  3747. heartbeat = readl(&h->cfgtable->HeartBeat);
  3748. spin_unlock_irqrestore(&h->lock, flags);
  3749. if (h->last_heartbeat == heartbeat) {
  3750. controller_lockup_detected(h);
  3751. return;
  3752. }
  3753. /* We're ok. */
  3754. h->last_heartbeat = heartbeat;
  3755. h->last_heartbeat_timestamp = now;
  3756. }
  3757. static int detect_controller_lockup_thread(void *notused)
  3758. {
  3759. struct ctlr_info *h;
  3760. unsigned long flags;
  3761. while (1) {
  3762. struct list_head *this, *tmp;
  3763. schedule_timeout_interruptible(HEARTBEAT_SAMPLE_INTERVAL);
  3764. if (kthread_should_stop())
  3765. break;
  3766. spin_lock_irqsave(&lockup_detector_lock, flags);
  3767. list_for_each_safe(this, tmp, &hpsa_ctlr_list) {
  3768. h = list_entry(this, struct ctlr_info, lockup_list);
  3769. detect_controller_lockup(h);
  3770. }
  3771. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3772. }
  3773. return 0;
  3774. }
  3775. static void add_ctlr_to_lockup_detector_list(struct ctlr_info *h)
  3776. {
  3777. unsigned long flags;
  3778. spin_lock_irqsave(&lockup_detector_lock, flags);
  3779. list_add_tail(&h->lockup_list, &hpsa_ctlr_list);
  3780. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3781. }
  3782. static void start_controller_lockup_detector(struct ctlr_info *h)
  3783. {
  3784. /* Start the lockup detector thread if not already started */
  3785. if (!hpsa_lockup_detector) {
  3786. spin_lock_init(&lockup_detector_lock);
  3787. hpsa_lockup_detector =
  3788. kthread_run(detect_controller_lockup_thread,
  3789. NULL, "hpsa");
  3790. }
  3791. if (!hpsa_lockup_detector) {
  3792. dev_warn(&h->pdev->dev,
  3793. "Could not start lockup detector thread\n");
  3794. return;
  3795. }
  3796. add_ctlr_to_lockup_detector_list(h);
  3797. }
  3798. static void stop_controller_lockup_detector(struct ctlr_info *h)
  3799. {
  3800. unsigned long flags;
  3801. spin_lock_irqsave(&lockup_detector_lock, flags);
  3802. remove_ctlr_from_lockup_detector_list(h);
  3803. /* If the list of ctlr's to monitor is empty, stop the thread */
  3804. if (list_empty(&hpsa_ctlr_list)) {
  3805. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3806. kthread_stop(hpsa_lockup_detector);
  3807. spin_lock_irqsave(&lockup_detector_lock, flags);
  3808. hpsa_lockup_detector = NULL;
  3809. }
  3810. spin_unlock_irqrestore(&lockup_detector_lock, flags);
  3811. }
  3812. static int __devinit hpsa_init_one(struct pci_dev *pdev,
  3813. const struct pci_device_id *ent)
  3814. {
  3815. int dac, rc;
  3816. struct ctlr_info *h;
  3817. int try_soft_reset = 0;
  3818. unsigned long flags;
  3819. if (number_of_controllers == 0)
  3820. printk(KERN_INFO DRIVER_NAME "\n");
  3821. rc = hpsa_init_reset_devices(pdev);
  3822. if (rc) {
  3823. if (rc != -ENOTSUPP)
  3824. return rc;
  3825. /* If the reset fails in a particular way (it has no way to do
  3826. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  3827. * a soft reset once we get the controller configured up to the
  3828. * point that it can accept a command.
  3829. */
  3830. try_soft_reset = 1;
  3831. rc = 0;
  3832. }
  3833. reinit_after_soft_reset:
  3834. /* Command structures must be aligned on a 32-byte boundary because
  3835. * the 5 lower bits of the address are used by the hardware. and by
  3836. * the driver. See comments in hpsa.h for more info.
  3837. */
  3838. #define COMMANDLIST_ALIGNMENT 32
  3839. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  3840. h = kzalloc(sizeof(*h), GFP_KERNEL);
  3841. if (!h)
  3842. return -ENOMEM;
  3843. h->pdev = pdev;
  3844. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  3845. INIT_LIST_HEAD(&h->cmpQ);
  3846. INIT_LIST_HEAD(&h->reqQ);
  3847. spin_lock_init(&h->lock);
  3848. spin_lock_init(&h->scan_lock);
  3849. rc = hpsa_pci_init(h);
  3850. if (rc != 0)
  3851. goto clean1;
  3852. sprintf(h->devname, "hpsa%d", number_of_controllers);
  3853. h->ctlr = number_of_controllers;
  3854. number_of_controllers++;
  3855. /* configure PCI DMA stuff */
  3856. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  3857. if (rc == 0) {
  3858. dac = 1;
  3859. } else {
  3860. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3861. if (rc == 0) {
  3862. dac = 0;
  3863. } else {
  3864. dev_err(&pdev->dev, "no suitable DMA available\n");
  3865. goto clean1;
  3866. }
  3867. }
  3868. /* make sure the board interrupts are off */
  3869. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3870. if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
  3871. goto clean2;
  3872. dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
  3873. h->devname, pdev->device,
  3874. h->intr[h->intr_mode], dac ? "" : " not");
  3875. if (hpsa_allocate_cmd_pool(h))
  3876. goto clean4;
  3877. if (hpsa_allocate_sg_chain_blocks(h))
  3878. goto clean4;
  3879. init_waitqueue_head(&h->scan_wait_queue);
  3880. h->scan_finished = 1; /* no scan currently in progress */
  3881. pci_set_drvdata(pdev, h);
  3882. h->ndevices = 0;
  3883. h->scsi_host = NULL;
  3884. spin_lock_init(&h->devlock);
  3885. hpsa_put_ctlr_into_performant_mode(h);
  3886. /* At this point, the controller is ready to take commands.
  3887. * Now, if reset_devices and the hard reset didn't work, try
  3888. * the soft reset and see if that works.
  3889. */
  3890. if (try_soft_reset) {
  3891. /* This is kind of gross. We may or may not get a completion
  3892. * from the soft reset command, and if we do, then the value
  3893. * from the fifo may or may not be valid. So, we wait 10 secs
  3894. * after the reset throwing away any completions we get during
  3895. * that time. Unregister the interrupt handler and register
  3896. * fake ones to scoop up any residual completions.
  3897. */
  3898. spin_lock_irqsave(&h->lock, flags);
  3899. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3900. spin_unlock_irqrestore(&h->lock, flags);
  3901. free_irq(h->intr[h->intr_mode], h);
  3902. rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
  3903. hpsa_intx_discard_completions);
  3904. if (rc) {
  3905. dev_warn(&h->pdev->dev, "Failed to request_irq after "
  3906. "soft reset.\n");
  3907. goto clean4;
  3908. }
  3909. rc = hpsa_kdump_soft_reset(h);
  3910. if (rc)
  3911. /* Neither hard nor soft reset worked, we're hosed. */
  3912. goto clean4;
  3913. dev_info(&h->pdev->dev, "Board READY.\n");
  3914. dev_info(&h->pdev->dev,
  3915. "Waiting for stale completions to drain.\n");
  3916. h->access.set_intr_mask(h, HPSA_INTR_ON);
  3917. msleep(10000);
  3918. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3919. rc = controller_reset_failed(h->cfgtable);
  3920. if (rc)
  3921. dev_info(&h->pdev->dev,
  3922. "Soft reset appears to have failed.\n");
  3923. /* since the controller's reset, we have to go back and re-init
  3924. * everything. Easiest to just forget what we've done and do it
  3925. * all over again.
  3926. */
  3927. hpsa_undo_allocations_after_kdump_soft_reset(h);
  3928. try_soft_reset = 0;
  3929. if (rc)
  3930. /* don't go to clean4, we already unallocated */
  3931. return -ENODEV;
  3932. goto reinit_after_soft_reset;
  3933. }
  3934. /* Turn the interrupts on so we can service requests */
  3935. h->access.set_intr_mask(h, HPSA_INTR_ON);
  3936. hpsa_hba_inquiry(h);
  3937. hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
  3938. start_controller_lockup_detector(h);
  3939. return 1;
  3940. clean4:
  3941. hpsa_free_sg_chain_blocks(h);
  3942. hpsa_free_cmd_pool(h);
  3943. free_irq(h->intr[h->intr_mode], h);
  3944. clean2:
  3945. clean1:
  3946. kfree(h);
  3947. return rc;
  3948. }
  3949. static void hpsa_flush_cache(struct ctlr_info *h)
  3950. {
  3951. char *flush_buf;
  3952. struct CommandList *c;
  3953. flush_buf = kzalloc(4, GFP_KERNEL);
  3954. if (!flush_buf)
  3955. return;
  3956. c = cmd_special_alloc(h);
  3957. if (!c) {
  3958. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  3959. goto out_of_memory;
  3960. }
  3961. fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  3962. RAID_CTLR_LUNID, TYPE_CMD);
  3963. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
  3964. if (c->err_info->CommandStatus != 0)
  3965. dev_warn(&h->pdev->dev,
  3966. "error flushing cache on controller\n");
  3967. cmd_special_free(h, c);
  3968. out_of_memory:
  3969. kfree(flush_buf);
  3970. }
  3971. static void hpsa_shutdown(struct pci_dev *pdev)
  3972. {
  3973. struct ctlr_info *h;
  3974. h = pci_get_drvdata(pdev);
  3975. /* Turn board interrupts off and send the flush cache command
  3976. * sendcmd will turn off interrupt, and send the flush...
  3977. * To write all data in the battery backed cache to disks
  3978. */
  3979. hpsa_flush_cache(h);
  3980. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3981. free_irq(h->intr[h->intr_mode], h);
  3982. #ifdef CONFIG_PCI_MSI
  3983. if (h->msix_vector)
  3984. pci_disable_msix(h->pdev);
  3985. else if (h->msi_vector)
  3986. pci_disable_msi(h->pdev);
  3987. #endif /* CONFIG_PCI_MSI */
  3988. }
  3989. static void __devexit hpsa_remove_one(struct pci_dev *pdev)
  3990. {
  3991. struct ctlr_info *h;
  3992. if (pci_get_drvdata(pdev) == NULL) {
  3993. dev_err(&pdev->dev, "unable to remove device\n");
  3994. return;
  3995. }
  3996. h = pci_get_drvdata(pdev);
  3997. stop_controller_lockup_detector(h);
  3998. hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
  3999. hpsa_shutdown(pdev);
  4000. iounmap(h->vaddr);
  4001. iounmap(h->transtable);
  4002. iounmap(h->cfgtable);
  4003. hpsa_free_sg_chain_blocks(h);
  4004. pci_free_consistent(h->pdev,
  4005. h->nr_cmds * sizeof(struct CommandList),
  4006. h->cmd_pool, h->cmd_pool_dhandle);
  4007. pci_free_consistent(h->pdev,
  4008. h->nr_cmds * sizeof(struct ErrorInfo),
  4009. h->errinfo_pool, h->errinfo_pool_dhandle);
  4010. pci_free_consistent(h->pdev, h->reply_pool_size,
  4011. h->reply_pool, h->reply_pool_dhandle);
  4012. kfree(h->cmd_pool_bits);
  4013. kfree(h->blockFetchTable);
  4014. kfree(h->hba_inquiry_data);
  4015. /*
  4016. * Deliberately omit pci_disable_device(): it does something nasty to
  4017. * Smart Array controllers that pci_enable_device does not undo
  4018. */
  4019. pci_release_regions(pdev);
  4020. pci_set_drvdata(pdev, NULL);
  4021. kfree(h);
  4022. }
  4023. static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
  4024. __attribute__((unused)) pm_message_t state)
  4025. {
  4026. return -ENOSYS;
  4027. }
  4028. static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
  4029. {
  4030. return -ENOSYS;
  4031. }
  4032. static struct pci_driver hpsa_pci_driver = {
  4033. .name = "hpsa",
  4034. .probe = hpsa_init_one,
  4035. .remove = __devexit_p(hpsa_remove_one),
  4036. .id_table = hpsa_pci_device_id, /* id_table */
  4037. .shutdown = hpsa_shutdown,
  4038. .suspend = hpsa_suspend,
  4039. .resume = hpsa_resume,
  4040. };
  4041. /* Fill in bucket_map[], given nsgs (the max number of
  4042. * scatter gather elements supported) and bucket[],
  4043. * which is an array of 8 integers. The bucket[] array
  4044. * contains 8 different DMA transfer sizes (in 16
  4045. * byte increments) which the controller uses to fetch
  4046. * commands. This function fills in bucket_map[], which
  4047. * maps a given number of scatter gather elements to one of
  4048. * the 8 DMA transfer sizes. The point of it is to allow the
  4049. * controller to only do as much DMA as needed to fetch the
  4050. * command, with the DMA transfer size encoded in the lower
  4051. * bits of the command address.
  4052. */
  4053. static void calc_bucket_map(int bucket[], int num_buckets,
  4054. int nsgs, int *bucket_map)
  4055. {
  4056. int i, j, b, size;
  4057. /* even a command with 0 SGs requires 4 blocks */
  4058. #define MINIMUM_TRANSFER_BLOCKS 4
  4059. #define NUM_BUCKETS 8
  4060. /* Note, bucket_map must have nsgs+1 entries. */
  4061. for (i = 0; i <= nsgs; i++) {
  4062. /* Compute size of a command with i SG entries */
  4063. size = i + MINIMUM_TRANSFER_BLOCKS;
  4064. b = num_buckets; /* Assume the biggest bucket */
  4065. /* Find the bucket that is just big enough */
  4066. for (j = 0; j < 8; j++) {
  4067. if (bucket[j] >= size) {
  4068. b = j;
  4069. break;
  4070. }
  4071. }
  4072. /* for a command with i SG entries, use bucket b. */
  4073. bucket_map[i] = b;
  4074. }
  4075. }
  4076. static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
  4077. u32 use_short_tags)
  4078. {
  4079. int i;
  4080. unsigned long register_value;
  4081. /* This is a bit complicated. There are 8 registers on
  4082. * the controller which we write to to tell it 8 different
  4083. * sizes of commands which there may be. It's a way of
  4084. * reducing the DMA done to fetch each command. Encoded into
  4085. * each command's tag are 3 bits which communicate to the controller
  4086. * which of the eight sizes that command fits within. The size of
  4087. * each command depends on how many scatter gather entries there are.
  4088. * Each SG entry requires 16 bytes. The eight registers are programmed
  4089. * with the number of 16-byte blocks a command of that size requires.
  4090. * The smallest command possible requires 5 such 16 byte blocks.
  4091. * the largest command possible requires MAXSGENTRIES + 4 16-byte
  4092. * blocks. Note, this only extends to the SG entries contained
  4093. * within the command block, and does not extend to chained blocks
  4094. * of SG elements. bft[] contains the eight values we write to
  4095. * the registers. They are not evenly distributed, but have more
  4096. * sizes for small commands, and fewer sizes for larger commands.
  4097. */
  4098. int bft[8] = {5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
  4099. BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
  4100. /* 5 = 1 s/g entry or 4k
  4101. * 6 = 2 s/g entry or 8k
  4102. * 8 = 4 s/g entry or 16k
  4103. * 10 = 6 s/g entry or 24k
  4104. */
  4105. h->reply_pool_wraparound = 1; /* spec: init to 1 */
  4106. /* Controller spec: zero out this buffer. */
  4107. memset(h->reply_pool, 0, h->reply_pool_size);
  4108. h->reply_pool_head = h->reply_pool;
  4109. bft[7] = h->max_sg_entries + 4;
  4110. calc_bucket_map(bft, ARRAY_SIZE(bft), 32, h->blockFetchTable);
  4111. for (i = 0; i < 8; i++)
  4112. writel(bft[i], &h->transtable->BlockFetch[i]);
  4113. /* size of controller ring buffer */
  4114. writel(h->max_commands, &h->transtable->RepQSize);
  4115. writel(1, &h->transtable->RepQCount);
  4116. writel(0, &h->transtable->RepQCtrAddrLow32);
  4117. writel(0, &h->transtable->RepQCtrAddrHigh32);
  4118. writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
  4119. writel(0, &h->transtable->RepQAddr0High32);
  4120. writel(CFGTBL_Trans_Performant | use_short_tags,
  4121. &(h->cfgtable->HostWrite.TransportRequest));
  4122. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  4123. hpsa_wait_for_mode_change_ack(h);
  4124. register_value = readl(&(h->cfgtable->TransportActive));
  4125. if (!(register_value & CFGTBL_Trans_Performant)) {
  4126. dev_warn(&h->pdev->dev, "unable to get board into"
  4127. " performant mode\n");
  4128. return;
  4129. }
  4130. /* Change the access methods to the performant access methods */
  4131. h->access = SA5_performant_access;
  4132. h->transMethod = CFGTBL_Trans_Performant;
  4133. }
  4134. static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  4135. {
  4136. u32 trans_support;
  4137. if (hpsa_simple_mode)
  4138. return;
  4139. trans_support = readl(&(h->cfgtable->TransportSupport));
  4140. if (!(trans_support & PERFORMANT_MODE))
  4141. return;
  4142. hpsa_get_max_perf_mode_cmds(h);
  4143. h->max_sg_entries = 32;
  4144. /* Performant mode ring buffer and supporting data structures */
  4145. h->reply_pool_size = h->max_commands * sizeof(u64);
  4146. h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
  4147. &(h->reply_pool_dhandle));
  4148. /* Need a block fetch table for performant mode */
  4149. h->blockFetchTable = kmalloc(((h->max_sg_entries+1) *
  4150. sizeof(u32)), GFP_KERNEL);
  4151. if ((h->reply_pool == NULL)
  4152. || (h->blockFetchTable == NULL))
  4153. goto clean_up;
  4154. hpsa_enter_performant_mode(h,
  4155. trans_support & CFGTBL_Trans_use_short_tags);
  4156. return;
  4157. clean_up:
  4158. if (h->reply_pool)
  4159. pci_free_consistent(h->pdev, h->reply_pool_size,
  4160. h->reply_pool, h->reply_pool_dhandle);
  4161. kfree(h->blockFetchTable);
  4162. }
  4163. /*
  4164. * This is it. Register the PCI driver information for the cards we control
  4165. * the OS will call our registered routines when it finds one of our cards.
  4166. */
  4167. static int __init hpsa_init(void)
  4168. {
  4169. return pci_register_driver(&hpsa_pci_driver);
  4170. }
  4171. static void __exit hpsa_cleanup(void)
  4172. {
  4173. pci_unregister_driver(&hpsa_pci_driver);
  4174. }
  4175. module_init(hpsa_init);
  4176. module_exit(hpsa_cleanup);