coda.c 54 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/of.h>
  25. #include <mach/iram.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-ioctl.h>
  29. #include <media/v4l2-mem2mem.h>
  30. #include <media/videobuf2-core.h>
  31. #include <media/videobuf2-dma-contig.h>
  32. #include "coda.h"
  33. #define CODA_NAME "coda"
  34. #define CODA_MAX_INSTANCES 4
  35. #define CODA_FMO_BUF_SIZE 32
  36. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  37. #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  38. #define CODA_PARA_BUF_SIZE (10 * 1024)
  39. #define CODA_ISRAM_SIZE (2048 * 2)
  40. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  41. #define CODA_MAX_FRAMEBUFFERS 2
  42. #define MAX_W 720
  43. #define MAX_H 576
  44. #define CODA_MAX_FRAME_SIZE 0x90000
  45. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  46. #define CODA_DEFAULT_GAMMA 4096
  47. #define MIN_W 176
  48. #define MIN_H 144
  49. #define MAX_W 720
  50. #define MAX_H 576
  51. #define S_ALIGN 1 /* multiple of 2 */
  52. #define W_ALIGN 1 /* multiple of 2 */
  53. #define H_ALIGN 1 /* multiple of 2 */
  54. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  55. static int coda_debug;
  56. module_param(coda_debug, int, 0);
  57. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  58. enum {
  59. V4L2_M2M_SRC = 0,
  60. V4L2_M2M_DST = 1,
  61. };
  62. enum coda_fmt_type {
  63. CODA_FMT_ENC,
  64. CODA_FMT_RAW,
  65. };
  66. enum coda_inst_type {
  67. CODA_INST_ENCODER,
  68. CODA_INST_DECODER,
  69. };
  70. enum coda_product {
  71. CODA_DX6 = 0xf001,
  72. CODA_7541 = 0xf012,
  73. };
  74. struct coda_fmt {
  75. char *name;
  76. u32 fourcc;
  77. enum coda_fmt_type type;
  78. };
  79. struct coda_devtype {
  80. char *firmware;
  81. enum coda_product product;
  82. struct coda_fmt *formats;
  83. unsigned int num_formats;
  84. size_t workbuf_size;
  85. };
  86. /* Per-queue, driver-specific private data */
  87. struct coda_q_data {
  88. unsigned int width;
  89. unsigned int height;
  90. unsigned int sizeimage;
  91. struct coda_fmt *fmt;
  92. };
  93. struct coda_aux_buf {
  94. void *vaddr;
  95. dma_addr_t paddr;
  96. u32 size;
  97. };
  98. struct coda_dev {
  99. struct v4l2_device v4l2_dev;
  100. struct video_device vfd;
  101. struct platform_device *plat_dev;
  102. const struct coda_devtype *devtype;
  103. void __iomem *regs_base;
  104. struct clk *clk_per;
  105. struct clk *clk_ahb;
  106. struct coda_aux_buf codebuf;
  107. struct coda_aux_buf workbuf;
  108. long unsigned int iram_paddr;
  109. spinlock_t irqlock;
  110. struct mutex dev_mutex;
  111. struct v4l2_m2m_dev *m2m_dev;
  112. struct vb2_alloc_ctx *alloc_ctx;
  113. struct list_head instances;
  114. unsigned long instance_mask;
  115. struct delayed_work timeout;
  116. };
  117. struct coda_params {
  118. u8 h264_intra_qp;
  119. u8 h264_inter_qp;
  120. u8 mpeg4_intra_qp;
  121. u8 mpeg4_inter_qp;
  122. u8 gop_size;
  123. int codec_mode;
  124. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  125. u32 framerate;
  126. u16 bitrate;
  127. u32 slice_max_mb;
  128. };
  129. struct coda_ctx {
  130. struct coda_dev *dev;
  131. struct list_head list;
  132. int aborting;
  133. int rawstreamon;
  134. int compstreamon;
  135. u32 isequence;
  136. struct coda_q_data q_data[2];
  137. enum coda_inst_type inst_type;
  138. enum v4l2_colorspace colorspace;
  139. struct coda_params params;
  140. struct v4l2_m2m_ctx *m2m_ctx;
  141. struct v4l2_ctrl_handler ctrls;
  142. struct v4l2_fh fh;
  143. int gopcounter;
  144. char vpu_header[3][64];
  145. int vpu_header_size[3];
  146. struct coda_aux_buf parabuf;
  147. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  148. int num_internal_frames;
  149. int idx;
  150. };
  151. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  152. {
  153. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  154. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  155. writel(data, dev->regs_base + reg);
  156. }
  157. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  158. {
  159. u32 data;
  160. data = readl(dev->regs_base + reg);
  161. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  162. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  163. return data;
  164. }
  165. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  166. {
  167. return coda_read(dev, CODA_REG_BIT_BUSY);
  168. }
  169. static inline int coda_is_initialized(struct coda_dev *dev)
  170. {
  171. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  172. }
  173. static int coda_wait_timeout(struct coda_dev *dev)
  174. {
  175. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  176. while (coda_isbusy(dev)) {
  177. if (time_after(jiffies, timeout))
  178. return -ETIMEDOUT;
  179. }
  180. return 0;
  181. }
  182. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  183. {
  184. struct coda_dev *dev = ctx->dev;
  185. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  186. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  187. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  188. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  189. }
  190. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  191. {
  192. struct coda_dev *dev = ctx->dev;
  193. coda_command_async(ctx, cmd);
  194. return coda_wait_timeout(dev);
  195. }
  196. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  197. enum v4l2_buf_type type)
  198. {
  199. switch (type) {
  200. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  201. return &(ctx->q_data[V4L2_M2M_SRC]);
  202. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  203. return &(ctx->q_data[V4L2_M2M_DST]);
  204. default:
  205. BUG();
  206. }
  207. return NULL;
  208. }
  209. /*
  210. * Add one array of supported formats for each version of Coda:
  211. * i.MX27 -> codadx6
  212. * i.MX51 -> coda7
  213. * i.MX6 -> coda960
  214. */
  215. static struct coda_fmt codadx6_formats[] = {
  216. {
  217. .name = "YUV 4:2:0 Planar",
  218. .fourcc = V4L2_PIX_FMT_YUV420,
  219. .type = CODA_FMT_RAW,
  220. },
  221. {
  222. .name = "H264 Encoded Stream",
  223. .fourcc = V4L2_PIX_FMT_H264,
  224. .type = CODA_FMT_ENC,
  225. },
  226. {
  227. .name = "MPEG4 Encoded Stream",
  228. .fourcc = V4L2_PIX_FMT_MPEG4,
  229. .type = CODA_FMT_ENC,
  230. },
  231. };
  232. static struct coda_fmt coda7_formats[] = {
  233. {
  234. .name = "YUV 4:2:0 Planar",
  235. .fourcc = V4L2_PIX_FMT_YUV420,
  236. .type = CODA_FMT_RAW,
  237. },
  238. {
  239. .name = "H264 Encoded Stream",
  240. .fourcc = V4L2_PIX_FMT_H264,
  241. .type = CODA_FMT_ENC,
  242. },
  243. {
  244. .name = "MPEG4 Encoded Stream",
  245. .fourcc = V4L2_PIX_FMT_MPEG4,
  246. .type = CODA_FMT_ENC,
  247. },
  248. };
  249. static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
  250. {
  251. struct coda_fmt *formats = dev->devtype->formats;
  252. int num_formats = dev->devtype->num_formats;
  253. unsigned int k;
  254. for (k = 0; k < num_formats; k++) {
  255. if (formats[k].fourcc == f->fmt.pix.pixelformat)
  256. break;
  257. }
  258. if (k == num_formats)
  259. return NULL;
  260. return &formats[k];
  261. }
  262. /*
  263. * V4L2 ioctl() operations.
  264. */
  265. static int vidioc_querycap(struct file *file, void *priv,
  266. struct v4l2_capability *cap)
  267. {
  268. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  269. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  270. strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
  271. /*
  272. * This is only a mem-to-mem video device. The capture and output
  273. * device capability flags are left only for backward compatibility
  274. * and are scheduled for removal.
  275. */
  276. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  277. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  278. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  279. return 0;
  280. }
  281. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  282. enum coda_fmt_type type)
  283. {
  284. struct coda_ctx *ctx = fh_to_ctx(priv);
  285. struct coda_dev *dev = ctx->dev;
  286. struct coda_fmt *formats = dev->devtype->formats;
  287. struct coda_fmt *fmt;
  288. int num_formats = dev->devtype->num_formats;
  289. int i, num = 0;
  290. for (i = 0; i < num_formats; i++) {
  291. if (formats[i].type == type) {
  292. if (num == f->index)
  293. break;
  294. ++num;
  295. }
  296. }
  297. if (i < num_formats) {
  298. fmt = &formats[i];
  299. strlcpy(f->description, fmt->name, sizeof(f->description));
  300. f->pixelformat = fmt->fourcc;
  301. return 0;
  302. }
  303. /* Format not found */
  304. return -EINVAL;
  305. }
  306. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  307. struct v4l2_fmtdesc *f)
  308. {
  309. return enum_fmt(priv, f, CODA_FMT_ENC);
  310. }
  311. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  312. struct v4l2_fmtdesc *f)
  313. {
  314. return enum_fmt(priv, f, CODA_FMT_RAW);
  315. }
  316. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  317. {
  318. struct vb2_queue *vq;
  319. struct coda_q_data *q_data;
  320. struct coda_ctx *ctx = fh_to_ctx(priv);
  321. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  322. if (!vq)
  323. return -EINVAL;
  324. q_data = get_q_data(ctx, f->type);
  325. f->fmt.pix.field = V4L2_FIELD_NONE;
  326. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  327. f->fmt.pix.width = q_data->width;
  328. f->fmt.pix.height = q_data->height;
  329. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  330. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  331. else /* encoded formats h.264/mpeg4 */
  332. f->fmt.pix.bytesperline = 0;
  333. f->fmt.pix.sizeimage = q_data->sizeimage;
  334. f->fmt.pix.colorspace = ctx->colorspace;
  335. return 0;
  336. }
  337. static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
  338. {
  339. enum v4l2_field field;
  340. field = f->fmt.pix.field;
  341. if (field == V4L2_FIELD_ANY)
  342. field = V4L2_FIELD_NONE;
  343. else if (V4L2_FIELD_NONE != field)
  344. return -EINVAL;
  345. /* V4L2 specification suggests the driver corrects the format struct
  346. * if any of the dimensions is unsupported */
  347. f->fmt.pix.field = field;
  348. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  349. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  350. W_ALIGN, &f->fmt.pix.height,
  351. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  352. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  353. f->fmt.pix.sizeimage = f->fmt.pix.height *
  354. f->fmt.pix.bytesperline;
  355. } else { /*encoded formats h.264/mpeg4 */
  356. f->fmt.pix.bytesperline = 0;
  357. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  358. }
  359. return 0;
  360. }
  361. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  362. struct v4l2_format *f)
  363. {
  364. int ret;
  365. struct coda_fmt *fmt;
  366. struct coda_ctx *ctx = fh_to_ctx(priv);
  367. fmt = find_format(ctx->dev, f);
  368. /*
  369. * Since decoding support is not implemented yet do not allow
  370. * CODA_FMT_RAW formats in the capture interface.
  371. */
  372. if (!fmt || !(fmt->type == CODA_FMT_ENC))
  373. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  374. f->fmt.pix.colorspace = ctx->colorspace;
  375. ret = vidioc_try_fmt(ctx->dev, f);
  376. if (ret < 0)
  377. return ret;
  378. return 0;
  379. }
  380. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  381. struct v4l2_format *f)
  382. {
  383. struct coda_ctx *ctx = fh_to_ctx(priv);
  384. struct coda_fmt *fmt;
  385. int ret;
  386. fmt = find_format(ctx->dev, f);
  387. /*
  388. * Since decoding support is not implemented yet do not allow
  389. * CODA_FMT formats in the capture interface.
  390. */
  391. if (!fmt || !(fmt->type == CODA_FMT_RAW))
  392. f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
  393. if (!f->fmt.pix.colorspace)
  394. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  395. ret = vidioc_try_fmt(ctx->dev, f);
  396. if (ret < 0)
  397. return ret;
  398. return 0;
  399. }
  400. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  401. {
  402. struct coda_q_data *q_data;
  403. struct vb2_queue *vq;
  404. int ret;
  405. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  406. if (!vq)
  407. return -EINVAL;
  408. q_data = get_q_data(ctx, f->type);
  409. if (!q_data)
  410. return -EINVAL;
  411. if (vb2_is_busy(vq)) {
  412. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  413. return -EBUSY;
  414. }
  415. ret = vidioc_try_fmt(ctx->dev, f);
  416. if (ret)
  417. return ret;
  418. q_data->fmt = find_format(ctx->dev, f);
  419. q_data->width = f->fmt.pix.width;
  420. q_data->height = f->fmt.pix.height;
  421. if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420) {
  422. q_data->sizeimage = q_data->width * q_data->height * 3 / 2;
  423. } else { /* encoded format h.264/mpeg-4 */
  424. q_data->sizeimage = CODA_MAX_FRAME_SIZE;
  425. }
  426. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  427. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  428. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  429. return 0;
  430. }
  431. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  432. struct v4l2_format *f)
  433. {
  434. int ret;
  435. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  436. if (ret)
  437. return ret;
  438. return vidioc_s_fmt(fh_to_ctx(priv), f);
  439. }
  440. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  441. struct v4l2_format *f)
  442. {
  443. struct coda_ctx *ctx = fh_to_ctx(priv);
  444. int ret;
  445. ret = vidioc_try_fmt_vid_out(file, priv, f);
  446. if (ret)
  447. return ret;
  448. ret = vidioc_s_fmt(ctx, f);
  449. if (ret)
  450. ctx->colorspace = f->fmt.pix.colorspace;
  451. return ret;
  452. }
  453. static int vidioc_reqbufs(struct file *file, void *priv,
  454. struct v4l2_requestbuffers *reqbufs)
  455. {
  456. struct coda_ctx *ctx = fh_to_ctx(priv);
  457. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  458. }
  459. static int vidioc_querybuf(struct file *file, void *priv,
  460. struct v4l2_buffer *buf)
  461. {
  462. struct coda_ctx *ctx = fh_to_ctx(priv);
  463. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  464. }
  465. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  466. {
  467. struct coda_ctx *ctx = fh_to_ctx(priv);
  468. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  469. }
  470. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  471. {
  472. struct coda_ctx *ctx = fh_to_ctx(priv);
  473. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  474. }
  475. static int vidioc_streamon(struct file *file, void *priv,
  476. enum v4l2_buf_type type)
  477. {
  478. struct coda_ctx *ctx = fh_to_ctx(priv);
  479. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  480. }
  481. static int vidioc_streamoff(struct file *file, void *priv,
  482. enum v4l2_buf_type type)
  483. {
  484. struct coda_ctx *ctx = fh_to_ctx(priv);
  485. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  486. }
  487. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  488. .vidioc_querycap = vidioc_querycap,
  489. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  490. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  491. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  492. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  493. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  494. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  495. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  496. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  497. .vidioc_reqbufs = vidioc_reqbufs,
  498. .vidioc_querybuf = vidioc_querybuf,
  499. .vidioc_qbuf = vidioc_qbuf,
  500. .vidioc_dqbuf = vidioc_dqbuf,
  501. .vidioc_streamon = vidioc_streamon,
  502. .vidioc_streamoff = vidioc_streamoff,
  503. };
  504. /*
  505. * Mem-to-mem operations.
  506. */
  507. static void coda_device_run(void *m2m_priv)
  508. {
  509. struct coda_ctx *ctx = m2m_priv;
  510. struct coda_q_data *q_data_src, *q_data_dst;
  511. struct vb2_buffer *src_buf, *dst_buf;
  512. struct coda_dev *dev = ctx->dev;
  513. int force_ipicture;
  514. int quant_param = 0;
  515. u32 picture_y, picture_cb, picture_cr;
  516. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  517. u32 dst_fourcc;
  518. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  519. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  520. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  521. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  522. dst_fourcc = q_data_dst->fmt->fourcc;
  523. src_buf->v4l2_buf.sequence = ctx->isequence;
  524. dst_buf->v4l2_buf.sequence = ctx->isequence;
  525. ctx->isequence++;
  526. /*
  527. * Workaround coda firmware BUG that only marks the first
  528. * frame as IDR. This is a problem for some decoders that can't
  529. * recover when a frame is lost.
  530. */
  531. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  532. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  533. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  534. } else {
  535. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  536. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  537. }
  538. /*
  539. * Copy headers at the beginning of the first frame for H.264 only.
  540. * In MPEG4 they are already copied by the coda.
  541. */
  542. if (src_buf->v4l2_buf.sequence == 0) {
  543. pic_stream_buffer_addr =
  544. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  545. ctx->vpu_header_size[0] +
  546. ctx->vpu_header_size[1] +
  547. ctx->vpu_header_size[2];
  548. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  549. ctx->vpu_header_size[0] -
  550. ctx->vpu_header_size[1] -
  551. ctx->vpu_header_size[2];
  552. memcpy(vb2_plane_vaddr(dst_buf, 0),
  553. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  554. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  555. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  556. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  557. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  558. ctx->vpu_header_size[2]);
  559. } else {
  560. pic_stream_buffer_addr =
  561. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  562. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  563. }
  564. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  565. force_ipicture = 1;
  566. switch (dst_fourcc) {
  567. case V4L2_PIX_FMT_H264:
  568. quant_param = ctx->params.h264_intra_qp;
  569. break;
  570. case V4L2_PIX_FMT_MPEG4:
  571. quant_param = ctx->params.mpeg4_intra_qp;
  572. break;
  573. default:
  574. v4l2_warn(&ctx->dev->v4l2_dev,
  575. "cannot set intra qp, fmt not supported\n");
  576. break;
  577. }
  578. } else {
  579. force_ipicture = 0;
  580. switch (dst_fourcc) {
  581. case V4L2_PIX_FMT_H264:
  582. quant_param = ctx->params.h264_inter_qp;
  583. break;
  584. case V4L2_PIX_FMT_MPEG4:
  585. quant_param = ctx->params.mpeg4_inter_qp;
  586. break;
  587. default:
  588. v4l2_warn(&ctx->dev->v4l2_dev,
  589. "cannot set inter qp, fmt not supported\n");
  590. break;
  591. }
  592. }
  593. /* submit */
  594. coda_write(dev, 0, CODA_CMD_ENC_PIC_ROT_MODE);
  595. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  596. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  597. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  598. picture_cr = picture_cb + q_data_src->width / 2 *
  599. q_data_src->height / 2;
  600. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  601. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  602. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  603. coda_write(dev, force_ipicture << 1 & 0x2,
  604. CODA_CMD_ENC_PIC_OPTION);
  605. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  606. coda_write(dev, pic_stream_buffer_size / 1024,
  607. CODA_CMD_ENC_PIC_BB_SIZE);
  608. if (dev->devtype->product == CODA_7541) {
  609. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  610. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  611. CODA7_REG_BIT_AXI_SRAM_USE);
  612. }
  613. /* 1 second timeout in case CODA locks up */
  614. schedule_delayed_work(&dev->timeout, HZ);
  615. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  616. }
  617. static int coda_job_ready(void *m2m_priv)
  618. {
  619. struct coda_ctx *ctx = m2m_priv;
  620. /*
  621. * For both 'P' and 'key' frame cases 1 picture
  622. * and 1 frame are needed.
  623. */
  624. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
  625. !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  626. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  627. "not ready: not enough video buffers.\n");
  628. return 0;
  629. }
  630. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  631. "job ready\n");
  632. return 1;
  633. }
  634. static void coda_job_abort(void *priv)
  635. {
  636. struct coda_ctx *ctx = priv;
  637. struct coda_dev *dev = ctx->dev;
  638. ctx->aborting = 1;
  639. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  640. "Aborting task\n");
  641. v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
  642. }
  643. static void coda_lock(void *m2m_priv)
  644. {
  645. struct coda_ctx *ctx = m2m_priv;
  646. struct coda_dev *pcdev = ctx->dev;
  647. mutex_lock(&pcdev->dev_mutex);
  648. }
  649. static void coda_unlock(void *m2m_priv)
  650. {
  651. struct coda_ctx *ctx = m2m_priv;
  652. struct coda_dev *pcdev = ctx->dev;
  653. mutex_unlock(&pcdev->dev_mutex);
  654. }
  655. static struct v4l2_m2m_ops coda_m2m_ops = {
  656. .device_run = coda_device_run,
  657. .job_ready = coda_job_ready,
  658. .job_abort = coda_job_abort,
  659. .lock = coda_lock,
  660. .unlock = coda_unlock,
  661. };
  662. static void set_default_params(struct coda_ctx *ctx)
  663. {
  664. struct coda_dev *dev = ctx->dev;
  665. ctx->params.codec_mode = CODA_MODE_INVALID;
  666. ctx->colorspace = V4L2_COLORSPACE_REC709;
  667. ctx->params.framerate = 30;
  668. ctx->aborting = 0;
  669. /* Default formats for output and input queues */
  670. ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
  671. ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
  672. ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
  673. ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
  674. ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
  675. ctx->q_data[V4L2_M2M_DST].width = MAX_W;
  676. ctx->q_data[V4L2_M2M_DST].height = MAX_H;
  677. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  678. }
  679. /*
  680. * Queue operations
  681. */
  682. static int coda_queue_setup(struct vb2_queue *vq,
  683. const struct v4l2_format *fmt,
  684. unsigned int *nbuffers, unsigned int *nplanes,
  685. unsigned int sizes[], void *alloc_ctxs[])
  686. {
  687. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  688. unsigned int size;
  689. if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  690. if (fmt)
  691. size = fmt->fmt.pix.width *
  692. fmt->fmt.pix.height * 3 / 2;
  693. else
  694. size = MAX_W *
  695. MAX_H * 3 / 2;
  696. } else {
  697. size = CODA_MAX_FRAME_SIZE;
  698. }
  699. *nplanes = 1;
  700. sizes[0] = size;
  701. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  702. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  703. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  704. return 0;
  705. }
  706. static int coda_buf_prepare(struct vb2_buffer *vb)
  707. {
  708. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  709. struct coda_q_data *q_data;
  710. q_data = get_q_data(ctx, vb->vb2_queue->type);
  711. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  712. v4l2_warn(&ctx->dev->v4l2_dev,
  713. "%s data will not fit into plane (%lu < %lu)\n",
  714. __func__, vb2_plane_size(vb, 0),
  715. (long)q_data->sizeimage);
  716. return -EINVAL;
  717. }
  718. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  719. return 0;
  720. }
  721. static void coda_buf_queue(struct vb2_buffer *vb)
  722. {
  723. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  724. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  725. }
  726. static void coda_wait_prepare(struct vb2_queue *q)
  727. {
  728. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  729. coda_unlock(ctx);
  730. }
  731. static void coda_wait_finish(struct vb2_queue *q)
  732. {
  733. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  734. coda_lock(ctx);
  735. }
  736. static void coda_free_framebuffers(struct coda_ctx *ctx)
  737. {
  738. int i;
  739. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
  740. if (ctx->internal_frames[i].vaddr) {
  741. dma_free_coherent(&ctx->dev->plat_dev->dev,
  742. ctx->internal_frames[i].size,
  743. ctx->internal_frames[i].vaddr,
  744. ctx->internal_frames[i].paddr);
  745. ctx->internal_frames[i].vaddr = NULL;
  746. }
  747. }
  748. }
  749. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  750. {
  751. struct coda_dev *dev = ctx->dev;
  752. int height = q_data->height;
  753. int width = q_data->width;
  754. u32 *p;
  755. int i;
  756. /* Allocate frame buffers */
  757. ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
  758. for (i = 0; i < ctx->num_internal_frames; i++) {
  759. ctx->internal_frames[i].size = q_data->sizeimage;
  760. if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
  761. ctx->internal_frames[i].size += width / 2 * height / 2;
  762. ctx->internal_frames[i].vaddr = dma_alloc_coherent(
  763. &dev->plat_dev->dev, ctx->internal_frames[i].size,
  764. &ctx->internal_frames[i].paddr, GFP_KERNEL);
  765. if (!ctx->internal_frames[i].vaddr) {
  766. coda_free_framebuffers(ctx);
  767. return -ENOMEM;
  768. }
  769. }
  770. /* Register frame buffers in the parameter buffer */
  771. p = ctx->parabuf.vaddr;
  772. if (dev->devtype->product == CODA_DX6) {
  773. for (i = 0; i < ctx->num_internal_frames; i++) {
  774. p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
  775. p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
  776. p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
  777. }
  778. } else {
  779. for (i = 0; i < ctx->num_internal_frames; i += 2) {
  780. p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
  781. p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
  782. p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
  783. if (fourcc == V4L2_PIX_FMT_H264)
  784. p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
  785. if (i + 1 < ctx->num_internal_frames) {
  786. p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
  787. p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
  788. p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
  789. if (fourcc == V4L2_PIX_FMT_H264)
  790. p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
  791. }
  792. }
  793. }
  794. return 0;
  795. }
  796. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  797. {
  798. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  799. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  800. u32 bitstream_buf, bitstream_size;
  801. struct coda_dev *dev = ctx->dev;
  802. struct coda_q_data *q_data_src, *q_data_dst;
  803. struct vb2_buffer *buf;
  804. u32 dst_fourcc;
  805. u32 value;
  806. int ret;
  807. if (count < 1)
  808. return -EINVAL;
  809. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  810. ctx->rawstreamon = 1;
  811. else
  812. ctx->compstreamon = 1;
  813. /* Don't start the coda unless both queues are on */
  814. if (!(ctx->rawstreamon & ctx->compstreamon))
  815. return 0;
  816. ctx->gopcounter = ctx->params.gop_size - 1;
  817. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  818. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  819. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  820. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  821. bitstream_size = q_data_dst->sizeimage;
  822. dst_fourcc = q_data_dst->fmt->fourcc;
  823. /* Find out whether coda must encode or decode */
  824. if (q_data_src->fmt->type == CODA_FMT_RAW &&
  825. q_data_dst->fmt->type == CODA_FMT_ENC) {
  826. ctx->inst_type = CODA_INST_ENCODER;
  827. } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
  828. q_data_dst->fmt->type == CODA_FMT_RAW) {
  829. ctx->inst_type = CODA_INST_DECODER;
  830. v4l2_err(v4l2_dev, "decoding not supported.\n");
  831. return -EINVAL;
  832. } else {
  833. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  834. return -EINVAL;
  835. }
  836. if (!coda_is_initialized(dev)) {
  837. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  838. return -EFAULT;
  839. }
  840. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  841. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
  842. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
  843. switch (dev->devtype->product) {
  844. case CODA_DX6:
  845. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  846. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  847. break;
  848. default:
  849. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  850. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  851. }
  852. if (dev->devtype->product == CODA_DX6) {
  853. /* Configure the coda */
  854. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  855. }
  856. /* Could set rotation here if needed */
  857. switch (dev->devtype->product) {
  858. case CODA_DX6:
  859. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  860. break;
  861. default:
  862. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  863. }
  864. value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  865. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  866. coda_write(dev, ctx->params.framerate,
  867. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  868. switch (dst_fourcc) {
  869. case V4L2_PIX_FMT_MPEG4:
  870. if (dev->devtype->product == CODA_DX6)
  871. ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
  872. else
  873. ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
  874. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  875. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  876. break;
  877. case V4L2_PIX_FMT_H264:
  878. if (dev->devtype->product == CODA_DX6)
  879. ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
  880. else
  881. ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
  882. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  883. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  884. break;
  885. default:
  886. v4l2_err(v4l2_dev,
  887. "dst format (0x%08x) invalid.\n", dst_fourcc);
  888. return -EINVAL;
  889. }
  890. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  891. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  892. if (ctx->params.slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB)
  893. value |= 1 & CODA_SLICING_MODE_MASK;
  894. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  895. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  896. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  897. if (ctx->params.bitrate) {
  898. /* Rate control enabled */
  899. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  900. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  901. } else {
  902. value = 0;
  903. }
  904. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  905. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  906. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  907. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  908. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  909. /* set default gamma */
  910. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  911. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  912. value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
  913. value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
  914. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  915. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  916. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  917. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  918. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  919. if (dev->devtype->product == CODA_DX6) {
  920. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  921. } else {
  922. coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  923. coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  924. }
  925. }
  926. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  927. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  928. return -ETIMEDOUT;
  929. }
  930. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
  931. return -EFAULT;
  932. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  933. if (ret < 0)
  934. return ret;
  935. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  936. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  937. if (dev->devtype->product != CODA_DX6) {
  938. coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  939. coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  940. coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  941. coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  942. coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  943. coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  944. }
  945. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  946. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  947. return -ETIMEDOUT;
  948. }
  949. /* Save stream headers */
  950. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  951. switch (dst_fourcc) {
  952. case V4L2_PIX_FMT_H264:
  953. /*
  954. * Get SPS in the first frame and copy it to an
  955. * intermediate buffer.
  956. */
  957. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  958. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  959. coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
  960. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  961. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  962. return -ETIMEDOUT;
  963. }
  964. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  965. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  966. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  967. ctx->vpu_header_size[0]);
  968. /*
  969. * Get PPS in the first frame and copy it to an
  970. * intermediate buffer.
  971. */
  972. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  973. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  974. coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
  975. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  976. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  977. return -ETIMEDOUT;
  978. }
  979. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  980. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  981. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  982. ctx->vpu_header_size[1]);
  983. ctx->vpu_header_size[2] = 0;
  984. break;
  985. case V4L2_PIX_FMT_MPEG4:
  986. /*
  987. * Get VOS in the first frame and copy it to an
  988. * intermediate buffer
  989. */
  990. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  991. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  992. coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
  993. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  994. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  995. return -ETIMEDOUT;
  996. }
  997. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  998. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  999. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1000. ctx->vpu_header_size[0]);
  1001. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1002. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1003. coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
  1004. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1005. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1006. return -ETIMEDOUT;
  1007. }
  1008. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1009. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1010. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1011. ctx->vpu_header_size[1]);
  1012. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1013. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1014. coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
  1015. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1016. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1017. return -ETIMEDOUT;
  1018. }
  1019. ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1020. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1021. memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
  1022. ctx->vpu_header_size[2]);
  1023. break;
  1024. default:
  1025. /* No more formats need to save headers at the moment */
  1026. break;
  1027. }
  1028. return 0;
  1029. }
  1030. static int coda_stop_streaming(struct vb2_queue *q)
  1031. {
  1032. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1033. struct coda_dev *dev = ctx->dev;
  1034. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1035. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1036. "%s: output\n", __func__);
  1037. ctx->rawstreamon = 0;
  1038. } else {
  1039. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1040. "%s: capture\n", __func__);
  1041. ctx->compstreamon = 0;
  1042. }
  1043. if (!ctx->rawstreamon && !ctx->compstreamon) {
  1044. cancel_delayed_work(&dev->timeout);
  1045. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1046. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1047. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1048. v4l2_err(&ctx->dev->v4l2_dev,
  1049. "CODA_COMMAND_SEQ_END failed\n");
  1050. return -ETIMEDOUT;
  1051. }
  1052. coda_free_framebuffers(ctx);
  1053. }
  1054. return 0;
  1055. }
  1056. static struct vb2_ops coda_qops = {
  1057. .queue_setup = coda_queue_setup,
  1058. .buf_prepare = coda_buf_prepare,
  1059. .buf_queue = coda_buf_queue,
  1060. .wait_prepare = coda_wait_prepare,
  1061. .wait_finish = coda_wait_finish,
  1062. .start_streaming = coda_start_streaming,
  1063. .stop_streaming = coda_stop_streaming,
  1064. };
  1065. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1066. {
  1067. struct coda_ctx *ctx =
  1068. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1069. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1070. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1071. switch (ctrl->id) {
  1072. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1073. ctx->params.bitrate = ctrl->val / 1000;
  1074. break;
  1075. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1076. ctx->params.gop_size = ctrl->val;
  1077. break;
  1078. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1079. ctx->params.h264_intra_qp = ctrl->val;
  1080. break;
  1081. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1082. ctx->params.h264_inter_qp = ctrl->val;
  1083. break;
  1084. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1085. ctx->params.mpeg4_intra_qp = ctrl->val;
  1086. break;
  1087. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1088. ctx->params.mpeg4_inter_qp = ctrl->val;
  1089. break;
  1090. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1091. ctx->params.slice_mode = ctrl->val;
  1092. break;
  1093. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1094. ctx->params.slice_max_mb = ctrl->val;
  1095. break;
  1096. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1097. break;
  1098. default:
  1099. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1100. "Invalid control, id=%d, val=%d\n",
  1101. ctrl->id, ctrl->val);
  1102. return -EINVAL;
  1103. }
  1104. return 0;
  1105. }
  1106. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1107. .s_ctrl = coda_s_ctrl,
  1108. };
  1109. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1110. {
  1111. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1112. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1113. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1114. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1115. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1116. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1117. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1118. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1119. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1120. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1121. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1122. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1123. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1124. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1125. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1126. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB, 0,
  1127. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB);
  1128. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1129. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1130. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1131. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1132. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1133. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1134. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1135. if (ctx->ctrls.error) {
  1136. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1137. ctx->ctrls.error);
  1138. return -EINVAL;
  1139. }
  1140. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1141. }
  1142. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1143. struct vb2_queue *dst_vq)
  1144. {
  1145. struct coda_ctx *ctx = priv;
  1146. int ret;
  1147. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1148. src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1149. src_vq->drv_priv = ctx;
  1150. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1151. src_vq->ops = &coda_qops;
  1152. src_vq->mem_ops = &vb2_dma_contig_memops;
  1153. ret = vb2_queue_init(src_vq);
  1154. if (ret)
  1155. return ret;
  1156. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1157. dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1158. dst_vq->drv_priv = ctx;
  1159. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1160. dst_vq->ops = &coda_qops;
  1161. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1162. return vb2_queue_init(dst_vq);
  1163. }
  1164. static int coda_next_free_instance(struct coda_dev *dev)
  1165. {
  1166. return ffz(dev->instance_mask);
  1167. }
  1168. static int coda_open(struct file *file)
  1169. {
  1170. struct coda_dev *dev = video_drvdata(file);
  1171. struct coda_ctx *ctx = NULL;
  1172. int ret = 0;
  1173. int idx;
  1174. idx = coda_next_free_instance(dev);
  1175. if (idx >= CODA_MAX_INSTANCES)
  1176. return -EBUSY;
  1177. set_bit(idx, &dev->instance_mask);
  1178. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1179. if (!ctx)
  1180. return -ENOMEM;
  1181. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1182. file->private_data = &ctx->fh;
  1183. v4l2_fh_add(&ctx->fh);
  1184. ctx->dev = dev;
  1185. ctx->idx = idx;
  1186. set_default_params(ctx);
  1187. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1188. &coda_queue_init);
  1189. if (IS_ERR(ctx->m2m_ctx)) {
  1190. int ret = PTR_ERR(ctx->m2m_ctx);
  1191. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1192. __func__, ret);
  1193. goto err;
  1194. }
  1195. ret = coda_ctrls_setup(ctx);
  1196. if (ret) {
  1197. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1198. goto err;
  1199. }
  1200. ctx->fh.ctrl_handler = &ctx->ctrls;
  1201. ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
  1202. CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
  1203. if (!ctx->parabuf.vaddr) {
  1204. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1205. ret = -ENOMEM;
  1206. goto err;
  1207. }
  1208. coda_lock(ctx);
  1209. list_add(&ctx->list, &dev->instances);
  1210. coda_unlock(ctx);
  1211. clk_prepare_enable(dev->clk_per);
  1212. clk_prepare_enable(dev->clk_ahb);
  1213. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1214. ctx->idx, ctx);
  1215. return 0;
  1216. err:
  1217. v4l2_fh_del(&ctx->fh);
  1218. v4l2_fh_exit(&ctx->fh);
  1219. kfree(ctx);
  1220. return ret;
  1221. }
  1222. static int coda_release(struct file *file)
  1223. {
  1224. struct coda_dev *dev = video_drvdata(file);
  1225. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1226. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1227. ctx);
  1228. coda_lock(ctx);
  1229. list_del(&ctx->list);
  1230. coda_unlock(ctx);
  1231. dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
  1232. ctx->parabuf.vaddr, ctx->parabuf.paddr);
  1233. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1234. v4l2_ctrl_handler_free(&ctx->ctrls);
  1235. clk_disable_unprepare(dev->clk_per);
  1236. clk_disable_unprepare(dev->clk_ahb);
  1237. v4l2_fh_del(&ctx->fh);
  1238. v4l2_fh_exit(&ctx->fh);
  1239. clear_bit(ctx->idx, &dev->instance_mask);
  1240. kfree(ctx);
  1241. return 0;
  1242. }
  1243. static unsigned int coda_poll(struct file *file,
  1244. struct poll_table_struct *wait)
  1245. {
  1246. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1247. int ret;
  1248. coda_lock(ctx);
  1249. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1250. coda_unlock(ctx);
  1251. return ret;
  1252. }
  1253. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1254. {
  1255. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1256. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1257. }
  1258. static const struct v4l2_file_operations coda_fops = {
  1259. .owner = THIS_MODULE,
  1260. .open = coda_open,
  1261. .release = coda_release,
  1262. .poll = coda_poll,
  1263. .unlocked_ioctl = video_ioctl2,
  1264. .mmap = coda_mmap,
  1265. };
  1266. static irqreturn_t coda_irq_handler(int irq, void *data)
  1267. {
  1268. struct vb2_buffer *src_buf, *dst_buf;
  1269. struct coda_dev *dev = data;
  1270. u32 wr_ptr, start_ptr;
  1271. struct coda_ctx *ctx;
  1272. __cancel_delayed_work(&dev->timeout);
  1273. /* read status register to attend the IRQ */
  1274. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1275. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1276. CODA_REG_BIT_INT_CLEAR);
  1277. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1278. if (ctx == NULL) {
  1279. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1280. return IRQ_HANDLED;
  1281. }
  1282. if (ctx->aborting) {
  1283. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1284. "task has been aborted\n");
  1285. return IRQ_HANDLED;
  1286. }
  1287. if (coda_isbusy(ctx->dev)) {
  1288. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1289. "coda is still busy!!!!\n");
  1290. return IRQ_NONE;
  1291. }
  1292. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1293. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1294. /* Get results from the coda */
  1295. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1296. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1297. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
  1298. /* Calculate bytesused field */
  1299. if (dst_buf->v4l2_buf.sequence == 0) {
  1300. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
  1301. ctx->vpu_header_size[0] +
  1302. ctx->vpu_header_size[1] +
  1303. ctx->vpu_header_size[2];
  1304. } else {
  1305. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
  1306. }
  1307. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1308. wr_ptr - start_ptr);
  1309. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1310. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1311. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1312. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1313. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1314. } else {
  1315. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1316. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1317. }
  1318. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1319. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1320. ctx->gopcounter--;
  1321. if (ctx->gopcounter < 0)
  1322. ctx->gopcounter = ctx->params.gop_size - 1;
  1323. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1324. "job finished: encoding frame (%d) (%s)\n",
  1325. dst_buf->v4l2_buf.sequence,
  1326. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1327. "KEYFRAME" : "PFRAME");
  1328. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1329. return IRQ_HANDLED;
  1330. }
  1331. static void coda_timeout(struct work_struct *work)
  1332. {
  1333. struct coda_ctx *ctx;
  1334. struct coda_dev *dev = container_of(to_delayed_work(work),
  1335. struct coda_dev, timeout);
  1336. v4l2_err(&dev->v4l2_dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1337. mutex_lock(&dev->dev_mutex);
  1338. list_for_each_entry(ctx, &dev->instances, list) {
  1339. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1340. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1341. }
  1342. mutex_unlock(&dev->dev_mutex);
  1343. }
  1344. static u32 coda_supported_firmwares[] = {
  1345. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1346. CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
  1347. };
  1348. static bool coda_firmware_supported(u32 vernum)
  1349. {
  1350. int i;
  1351. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1352. if (vernum == coda_supported_firmwares[i])
  1353. return true;
  1354. return false;
  1355. }
  1356. static char *coda_product_name(int product)
  1357. {
  1358. static char buf[9];
  1359. switch (product) {
  1360. case CODA_DX6:
  1361. return "CodaDx6";
  1362. case CODA_7541:
  1363. return "CODA7541";
  1364. default:
  1365. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1366. return buf;
  1367. }
  1368. }
  1369. static int coda_hw_init(struct coda_dev *dev)
  1370. {
  1371. u16 product, major, minor, release;
  1372. u32 data;
  1373. u16 *p;
  1374. int i;
  1375. clk_prepare_enable(dev->clk_per);
  1376. clk_prepare_enable(dev->clk_ahb);
  1377. /*
  1378. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1379. * The 16-bit chars in the code buffer are in memory access
  1380. * order, re-sort them to CODA order for register download.
  1381. * Data in this SRAM survives a reboot.
  1382. */
  1383. p = (u16 *)dev->codebuf.vaddr;
  1384. if (dev->devtype->product == CODA_DX6) {
  1385. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1386. data = CODA_DOWN_ADDRESS_SET(i) |
  1387. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1388. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1389. }
  1390. } else {
  1391. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1392. data = CODA_DOWN_ADDRESS_SET(i) |
  1393. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1394. 3 - (i % 4)]);
  1395. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1396. }
  1397. }
  1398. /* Tell the BIT where to find everything it needs */
  1399. coda_write(dev, dev->workbuf.paddr,
  1400. CODA_REG_BIT_WORK_BUF_ADDR);
  1401. coda_write(dev, dev->codebuf.paddr,
  1402. CODA_REG_BIT_CODE_BUF_ADDR);
  1403. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1404. /* Set default values */
  1405. switch (dev->devtype->product) {
  1406. case CODA_DX6:
  1407. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1408. break;
  1409. default:
  1410. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1411. }
  1412. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1413. if (dev->devtype->product != CODA_DX6)
  1414. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1415. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1416. CODA_REG_BIT_INT_ENABLE);
  1417. /* Reset VPU and start processor */
  1418. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1419. data |= CODA_REG_RESET_ENABLE;
  1420. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1421. udelay(10);
  1422. data &= ~CODA_REG_RESET_ENABLE;
  1423. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1424. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1425. /* Load firmware */
  1426. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1427. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1428. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1429. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1430. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1431. if (coda_wait_timeout(dev)) {
  1432. clk_disable_unprepare(dev->clk_per);
  1433. clk_disable_unprepare(dev->clk_ahb);
  1434. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1435. return -EIO;
  1436. }
  1437. /* Check we are compatible with the loaded firmware */
  1438. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1439. product = CODA_FIRMWARE_PRODUCT(data);
  1440. major = CODA_FIRMWARE_MAJOR(data);
  1441. minor = CODA_FIRMWARE_MINOR(data);
  1442. release = CODA_FIRMWARE_RELEASE(data);
  1443. clk_disable_unprepare(dev->clk_per);
  1444. clk_disable_unprepare(dev->clk_ahb);
  1445. if (product != dev->devtype->product) {
  1446. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1447. " Version: %u.%u.%u\n",
  1448. coda_product_name(dev->devtype->product),
  1449. coda_product_name(product), major, minor, release);
  1450. return -EINVAL;
  1451. }
  1452. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1453. coda_product_name(product));
  1454. if (coda_firmware_supported(data)) {
  1455. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1456. major, minor, release);
  1457. } else {
  1458. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1459. "%u.%u.%u\n", major, minor, release);
  1460. }
  1461. return 0;
  1462. }
  1463. static void coda_fw_callback(const struct firmware *fw, void *context)
  1464. {
  1465. struct coda_dev *dev = context;
  1466. struct platform_device *pdev = dev->plat_dev;
  1467. int ret;
  1468. if (!fw) {
  1469. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1470. return;
  1471. }
  1472. /* allocate auxiliary per-device code buffer for the BIT processor */
  1473. dev->codebuf.size = fw->size;
  1474. dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
  1475. &dev->codebuf.paddr,
  1476. GFP_KERNEL);
  1477. if (!dev->codebuf.vaddr) {
  1478. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1479. return;
  1480. }
  1481. /* Copy the whole firmware image to the code buffer */
  1482. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1483. release_firmware(fw);
  1484. ret = coda_hw_init(dev);
  1485. if (ret) {
  1486. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1487. return;
  1488. }
  1489. dev->vfd.fops = &coda_fops,
  1490. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1491. dev->vfd.release = video_device_release_empty,
  1492. dev->vfd.lock = &dev->dev_mutex;
  1493. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1494. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1495. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1496. video_set_drvdata(&dev->vfd, dev);
  1497. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1498. if (IS_ERR(dev->alloc_ctx)) {
  1499. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1500. return;
  1501. }
  1502. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1503. if (IS_ERR(dev->m2m_dev)) {
  1504. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1505. goto rel_ctx;
  1506. }
  1507. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1508. if (ret) {
  1509. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1510. goto rel_m2m;
  1511. }
  1512. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1513. dev->vfd.num);
  1514. return;
  1515. rel_m2m:
  1516. v4l2_m2m_release(dev->m2m_dev);
  1517. rel_ctx:
  1518. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1519. }
  1520. static int coda_firmware_request(struct coda_dev *dev)
  1521. {
  1522. char *fw = dev->devtype->firmware;
  1523. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1524. coda_product_name(dev->devtype->product));
  1525. return request_firmware_nowait(THIS_MODULE, true,
  1526. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1527. }
  1528. enum coda_platform {
  1529. CODA_IMX27,
  1530. CODA_IMX53,
  1531. };
  1532. static const struct coda_devtype coda_devdata[] = {
  1533. [CODA_IMX27] = {
  1534. .firmware = "v4l-codadx6-imx27.bin",
  1535. .product = CODA_DX6,
  1536. .formats = codadx6_formats,
  1537. .num_formats = ARRAY_SIZE(codadx6_formats),
  1538. },
  1539. [CODA_IMX53] = {
  1540. .firmware = "v4l-coda7541-imx53.bin",
  1541. .product = CODA_7541,
  1542. .formats = coda7_formats,
  1543. .num_formats = ARRAY_SIZE(coda7_formats),
  1544. },
  1545. };
  1546. static struct platform_device_id coda_platform_ids[] = {
  1547. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  1548. { .name = "coda-imx53", .driver_data = CODA_7541 },
  1549. { /* sentinel */ }
  1550. };
  1551. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  1552. #ifdef CONFIG_OF
  1553. static const struct of_device_id coda_dt_ids[] = {
  1554. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  1555. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  1556. { /* sentinel */ }
  1557. };
  1558. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  1559. #endif
  1560. static int __devinit coda_probe(struct platform_device *pdev)
  1561. {
  1562. const struct of_device_id *of_id =
  1563. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  1564. const struct platform_device_id *pdev_id;
  1565. struct coda_dev *dev;
  1566. struct resource *res;
  1567. int ret, irq;
  1568. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  1569. if (!dev) {
  1570. dev_err(&pdev->dev, "Not enough memory for %s\n",
  1571. CODA_NAME);
  1572. return -ENOMEM;
  1573. }
  1574. spin_lock_init(&dev->irqlock);
  1575. INIT_LIST_HEAD(&dev->instances);
  1576. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  1577. dev->plat_dev = pdev;
  1578. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  1579. if (IS_ERR(dev->clk_per)) {
  1580. dev_err(&pdev->dev, "Could not get per clock\n");
  1581. return PTR_ERR(dev->clk_per);
  1582. }
  1583. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1584. if (IS_ERR(dev->clk_ahb)) {
  1585. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1586. return PTR_ERR(dev->clk_ahb);
  1587. }
  1588. /* Get memory for physical registers */
  1589. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1590. if (res == NULL) {
  1591. dev_err(&pdev->dev, "failed to get memory region resource\n");
  1592. return -ENOENT;
  1593. }
  1594. if (devm_request_mem_region(&pdev->dev, res->start,
  1595. resource_size(res), CODA_NAME) == NULL) {
  1596. dev_err(&pdev->dev, "failed to request memory region\n");
  1597. return -ENOENT;
  1598. }
  1599. dev->regs_base = devm_ioremap(&pdev->dev, res->start,
  1600. resource_size(res));
  1601. if (!dev->regs_base) {
  1602. dev_err(&pdev->dev, "failed to ioremap address region\n");
  1603. return -ENOENT;
  1604. }
  1605. /* IRQ */
  1606. irq = platform_get_irq(pdev, 0);
  1607. if (irq < 0) {
  1608. dev_err(&pdev->dev, "failed to get irq resource\n");
  1609. return -ENOENT;
  1610. }
  1611. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  1612. 0, CODA_NAME, dev) < 0) {
  1613. dev_err(&pdev->dev, "failed to request irq\n");
  1614. return -ENOENT;
  1615. }
  1616. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1617. if (ret)
  1618. return ret;
  1619. mutex_init(&dev->dev_mutex);
  1620. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  1621. if (of_id) {
  1622. dev->devtype = of_id->data;
  1623. } else if (pdev_id) {
  1624. dev->devtype = &coda_devdata[pdev_id->driver_data];
  1625. } else {
  1626. v4l2_device_unregister(&dev->v4l2_dev);
  1627. return -EINVAL;
  1628. }
  1629. /* allocate auxiliary per-device buffers for the BIT processor */
  1630. switch (dev->devtype->product) {
  1631. case CODA_DX6:
  1632. dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
  1633. break;
  1634. default:
  1635. dev->workbuf.size = CODA7_WORK_BUF_SIZE;
  1636. }
  1637. dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
  1638. &dev->workbuf.paddr,
  1639. GFP_KERNEL);
  1640. if (!dev->workbuf.vaddr) {
  1641. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  1642. v4l2_device_unregister(&dev->v4l2_dev);
  1643. return -ENOMEM;
  1644. }
  1645. if (dev->devtype->product == CODA_DX6) {
  1646. dev->iram_paddr = 0xffff4c00;
  1647. } else {
  1648. void __iomem *iram_vaddr;
  1649. iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
  1650. &dev->iram_paddr);
  1651. if (!iram_vaddr) {
  1652. dev_err(&pdev->dev, "unable to alloc iram\n");
  1653. return -ENOMEM;
  1654. }
  1655. }
  1656. platform_set_drvdata(pdev, dev);
  1657. return coda_firmware_request(dev);
  1658. }
  1659. static int coda_remove(struct platform_device *pdev)
  1660. {
  1661. struct coda_dev *dev = platform_get_drvdata(pdev);
  1662. video_unregister_device(&dev->vfd);
  1663. if (dev->m2m_dev)
  1664. v4l2_m2m_release(dev->m2m_dev);
  1665. if (dev->alloc_ctx)
  1666. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1667. v4l2_device_unregister(&dev->v4l2_dev);
  1668. if (dev->iram_paddr)
  1669. iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
  1670. if (dev->codebuf.vaddr)
  1671. dma_free_coherent(&pdev->dev, dev->codebuf.size,
  1672. &dev->codebuf.vaddr, dev->codebuf.paddr);
  1673. if (dev->workbuf.vaddr)
  1674. dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
  1675. dev->workbuf.paddr);
  1676. return 0;
  1677. }
  1678. static struct platform_driver coda_driver = {
  1679. .probe = coda_probe,
  1680. .remove = __devexit_p(coda_remove),
  1681. .driver = {
  1682. .name = CODA_NAME,
  1683. .owner = THIS_MODULE,
  1684. .of_match_table = of_match_ptr(coda_dt_ids),
  1685. },
  1686. .id_table = coda_platform_ids,
  1687. };
  1688. module_platform_driver(coda_driver);
  1689. MODULE_LICENSE("GPL");
  1690. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  1691. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");