caif_shmcore.c 18 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson AB 2010
  3. * Contact: Sjur Brendeland / sjur.brandeland@stericsson.com
  4. * Authors: Amarnath Revanna / amarnath.bangalore.revanna@stericsson.com,
  5. * Daniel Martensson / daniel.martensson@stericsson.com
  6. * License terms: GNU General Public License (GPL) version 2
  7. */
  8. #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
  9. #include <linux/spinlock.h>
  10. #include <linux/sched.h>
  11. #include <linux/list.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/if_arp.h>
  14. #include <net/caif/caif_device.h>
  15. #include <net/caif/caif_shm.h>
  16. #define NR_TX_BUF 6
  17. #define NR_RX_BUF 6
  18. #define TX_BUF_SZ 0x2000
  19. #define RX_BUF_SZ 0x2000
  20. #define CAIF_NEEDED_HEADROOM 32
  21. #define CAIF_FLOW_ON 1
  22. #define CAIF_FLOW_OFF 0
  23. #define LOW_WATERMARK 3
  24. #define HIGH_WATERMARK 4
  25. /* Maximum number of CAIF buffers per shared memory buffer. */
  26. #define SHM_MAX_FRMS_PER_BUF 10
  27. /*
  28. * Size in bytes of the descriptor area
  29. * (With end of descriptor signalling)
  30. */
  31. #define SHM_CAIF_DESC_SIZE ((SHM_MAX_FRMS_PER_BUF + 1) * \
  32. sizeof(struct shm_pck_desc))
  33. /*
  34. * Offset to the first CAIF frame within a shared memory buffer.
  35. * Aligned on 32 bytes.
  36. */
  37. #define SHM_CAIF_FRM_OFS (SHM_CAIF_DESC_SIZE + (SHM_CAIF_DESC_SIZE % 32))
  38. /* Number of bytes for CAIF shared memory header. */
  39. #define SHM_HDR_LEN 1
  40. /* Number of padding bytes for the complete CAIF frame. */
  41. #define SHM_FRM_PAD_LEN 4
  42. #define CAIF_MAX_MTU 4096
  43. #define SHM_SET_FULL(x) (((x+1) & 0x0F) << 0)
  44. #define SHM_GET_FULL(x) (((x >> 0) & 0x0F) - 1)
  45. #define SHM_SET_EMPTY(x) (((x+1) & 0x0F) << 4)
  46. #define SHM_GET_EMPTY(x) (((x >> 4) & 0x0F) - 1)
  47. #define SHM_FULL_MASK (0x0F << 0)
  48. #define SHM_EMPTY_MASK (0x0F << 4)
  49. struct shm_pck_desc {
  50. /*
  51. * Offset from start of shared memory area to start of
  52. * shared memory CAIF frame.
  53. */
  54. u32 frm_ofs;
  55. u32 frm_len;
  56. };
  57. struct buf_list {
  58. unsigned char *desc_vptr;
  59. u32 phy_addr;
  60. u32 index;
  61. u32 len;
  62. u32 frames;
  63. u32 frm_ofs;
  64. struct list_head list;
  65. };
  66. struct shm_caif_frm {
  67. /* Number of bytes of padding before the CAIF frame. */
  68. u8 hdr_ofs;
  69. };
  70. struct shmdrv_layer {
  71. /* caif_dev_common must always be first in the structure*/
  72. struct caif_dev_common cfdev;
  73. u32 shm_tx_addr;
  74. u32 shm_rx_addr;
  75. u32 shm_base_addr;
  76. u32 tx_empty_available;
  77. spinlock_t lock;
  78. struct list_head tx_empty_list;
  79. struct list_head tx_pend_list;
  80. struct list_head tx_full_list;
  81. struct list_head rx_empty_list;
  82. struct list_head rx_pend_list;
  83. struct list_head rx_full_list;
  84. struct workqueue_struct *pshm_tx_workqueue;
  85. struct workqueue_struct *pshm_rx_workqueue;
  86. struct work_struct shm_tx_work;
  87. struct work_struct shm_rx_work;
  88. struct sk_buff_head sk_qhead;
  89. struct shmdev_layer *pshm_dev;
  90. };
  91. static int shm_netdev_open(struct net_device *shm_netdev)
  92. {
  93. netif_wake_queue(shm_netdev);
  94. return 0;
  95. }
  96. static int shm_netdev_close(struct net_device *shm_netdev)
  97. {
  98. netif_stop_queue(shm_netdev);
  99. return 0;
  100. }
  101. int caif_shmdrv_rx_cb(u32 mbx_msg, void *priv)
  102. {
  103. struct buf_list *pbuf;
  104. struct shmdrv_layer *pshm_drv;
  105. struct list_head *pos;
  106. u32 avail_emptybuff = 0;
  107. unsigned long flags = 0;
  108. pshm_drv = priv;
  109. /* Check for received buffers. */
  110. if (mbx_msg & SHM_FULL_MASK) {
  111. int idx;
  112. spin_lock_irqsave(&pshm_drv->lock, flags);
  113. /* Check whether we have any outstanding buffers. */
  114. if (list_empty(&pshm_drv->rx_empty_list)) {
  115. /* Release spin lock. */
  116. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  117. /* We print even in IRQ context... */
  118. pr_warn("No empty Rx buffers to fill: "
  119. "mbx_msg:%x\n", mbx_msg);
  120. /* Bail out. */
  121. goto err_sync;
  122. }
  123. pbuf =
  124. list_entry(pshm_drv->rx_empty_list.next,
  125. struct buf_list, list);
  126. idx = pbuf->index;
  127. /* Check buffer synchronization. */
  128. if (idx != SHM_GET_FULL(mbx_msg)) {
  129. /* We print even in IRQ context... */
  130. pr_warn(
  131. "phyif_shm_mbx_msg_cb: RX full out of sync:"
  132. " idx:%d, msg:%x SHM_GET_FULL(mbx_msg):%x\n",
  133. idx, mbx_msg, SHM_GET_FULL(mbx_msg));
  134. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  135. /* Bail out. */
  136. goto err_sync;
  137. }
  138. list_del_init(&pbuf->list);
  139. list_add_tail(&pbuf->list, &pshm_drv->rx_full_list);
  140. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  141. /* Schedule RX work queue. */
  142. if (!work_pending(&pshm_drv->shm_rx_work))
  143. queue_work(pshm_drv->pshm_rx_workqueue,
  144. &pshm_drv->shm_rx_work);
  145. }
  146. /* Check for emptied buffers. */
  147. if (mbx_msg & SHM_EMPTY_MASK) {
  148. int idx;
  149. spin_lock_irqsave(&pshm_drv->lock, flags);
  150. /* Check whether we have any outstanding buffers. */
  151. if (list_empty(&pshm_drv->tx_full_list)) {
  152. /* We print even in IRQ context... */
  153. pr_warn("No TX to empty: msg:%x\n", mbx_msg);
  154. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  155. /* Bail out. */
  156. goto err_sync;
  157. }
  158. pbuf =
  159. list_entry(pshm_drv->tx_full_list.next,
  160. struct buf_list, list);
  161. idx = pbuf->index;
  162. /* Check buffer synchronization. */
  163. if (idx != SHM_GET_EMPTY(mbx_msg)) {
  164. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  165. /* We print even in IRQ context... */
  166. pr_warn("TX empty "
  167. "out of sync:idx:%d, msg:%x\n", idx, mbx_msg);
  168. /* Bail out. */
  169. goto err_sync;
  170. }
  171. list_del_init(&pbuf->list);
  172. /* Reset buffer parameters. */
  173. pbuf->frames = 0;
  174. pbuf->frm_ofs = SHM_CAIF_FRM_OFS;
  175. list_add_tail(&pbuf->list, &pshm_drv->tx_empty_list);
  176. /* Check the available no. of buffers in the empty list */
  177. list_for_each(pos, &pshm_drv->tx_empty_list)
  178. avail_emptybuff++;
  179. /* Check whether we have to wake up the transmitter. */
  180. if ((avail_emptybuff > HIGH_WATERMARK) &&
  181. (!pshm_drv->tx_empty_available)) {
  182. pshm_drv->tx_empty_available = 1;
  183. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  184. pshm_drv->cfdev.flowctrl
  185. (pshm_drv->pshm_dev->pshm_netdev,
  186. CAIF_FLOW_ON);
  187. /* Schedule the work queue. if required */
  188. if (!work_pending(&pshm_drv->shm_tx_work))
  189. queue_work(pshm_drv->pshm_tx_workqueue,
  190. &pshm_drv->shm_tx_work);
  191. } else
  192. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  193. }
  194. return 0;
  195. err_sync:
  196. return -EIO;
  197. }
  198. static void shm_rx_work_func(struct work_struct *rx_work)
  199. {
  200. struct shmdrv_layer *pshm_drv;
  201. struct buf_list *pbuf;
  202. unsigned long flags = 0;
  203. struct sk_buff *skb;
  204. char *p;
  205. int ret;
  206. pshm_drv = container_of(rx_work, struct shmdrv_layer, shm_rx_work);
  207. while (1) {
  208. struct shm_pck_desc *pck_desc;
  209. spin_lock_irqsave(&pshm_drv->lock, flags);
  210. /* Check for received buffers. */
  211. if (list_empty(&pshm_drv->rx_full_list)) {
  212. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  213. break;
  214. }
  215. pbuf =
  216. list_entry(pshm_drv->rx_full_list.next, struct buf_list,
  217. list);
  218. list_del_init(&pbuf->list);
  219. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  220. /* Retrieve pointer to start of the packet descriptor area. */
  221. pck_desc = (struct shm_pck_desc *) pbuf->desc_vptr;
  222. /*
  223. * Check whether descriptor contains a CAIF shared memory
  224. * frame.
  225. */
  226. while (pck_desc->frm_ofs) {
  227. unsigned int frm_buf_ofs;
  228. unsigned int frm_pck_ofs;
  229. unsigned int frm_pck_len;
  230. /*
  231. * Check whether offset is within buffer limits
  232. * (lower).
  233. */
  234. if (pck_desc->frm_ofs <
  235. (pbuf->phy_addr - pshm_drv->shm_base_addr))
  236. break;
  237. /*
  238. * Check whether offset is within buffer limits
  239. * (higher).
  240. */
  241. if (pck_desc->frm_ofs >
  242. ((pbuf->phy_addr - pshm_drv->shm_base_addr) +
  243. pbuf->len))
  244. break;
  245. /* Calculate offset from start of buffer. */
  246. frm_buf_ofs =
  247. pck_desc->frm_ofs - (pbuf->phy_addr -
  248. pshm_drv->shm_base_addr);
  249. /*
  250. * Calculate offset and length of CAIF packet while
  251. * taking care of the shared memory header.
  252. */
  253. frm_pck_ofs =
  254. frm_buf_ofs + SHM_HDR_LEN +
  255. (*(pbuf->desc_vptr + frm_buf_ofs));
  256. frm_pck_len =
  257. (pck_desc->frm_len - SHM_HDR_LEN -
  258. (*(pbuf->desc_vptr + frm_buf_ofs)));
  259. /* Check whether CAIF packet is within buffer limits */
  260. if ((frm_pck_ofs + pck_desc->frm_len) > pbuf->len)
  261. break;
  262. /* Get a suitable CAIF packet and copy in data. */
  263. skb = netdev_alloc_skb(pshm_drv->pshm_dev->pshm_netdev,
  264. frm_pck_len + 1);
  265. BUG_ON(skb == NULL);
  266. p = skb_put(skb, frm_pck_len);
  267. memcpy(p, pbuf->desc_vptr + frm_pck_ofs, frm_pck_len);
  268. skb->protocol = htons(ETH_P_CAIF);
  269. skb_reset_mac_header(skb);
  270. skb->dev = pshm_drv->pshm_dev->pshm_netdev;
  271. /* Push received packet up the stack. */
  272. ret = netif_rx_ni(skb);
  273. if (!ret) {
  274. pshm_drv->pshm_dev->pshm_netdev->stats.
  275. rx_packets++;
  276. pshm_drv->pshm_dev->pshm_netdev->stats.
  277. rx_bytes += pck_desc->frm_len;
  278. } else
  279. ++pshm_drv->pshm_dev->pshm_netdev->stats.
  280. rx_dropped;
  281. /* Move to next packet descriptor. */
  282. pck_desc++;
  283. }
  284. spin_lock_irqsave(&pshm_drv->lock, flags);
  285. list_add_tail(&pbuf->list, &pshm_drv->rx_pend_list);
  286. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  287. }
  288. /* Schedule the work queue. if required */
  289. if (!work_pending(&pshm_drv->shm_tx_work))
  290. queue_work(pshm_drv->pshm_tx_workqueue, &pshm_drv->shm_tx_work);
  291. }
  292. static void shm_tx_work_func(struct work_struct *tx_work)
  293. {
  294. u32 mbox_msg;
  295. unsigned int frmlen, avail_emptybuff, append = 0;
  296. unsigned long flags = 0;
  297. struct buf_list *pbuf = NULL;
  298. struct shmdrv_layer *pshm_drv;
  299. struct shm_caif_frm *frm;
  300. struct sk_buff *skb;
  301. struct shm_pck_desc *pck_desc;
  302. struct list_head *pos;
  303. pshm_drv = container_of(tx_work, struct shmdrv_layer, shm_tx_work);
  304. do {
  305. /* Initialize mailbox message. */
  306. mbox_msg = 0x00;
  307. avail_emptybuff = 0;
  308. spin_lock_irqsave(&pshm_drv->lock, flags);
  309. /* Check for pending receive buffers. */
  310. if (!list_empty(&pshm_drv->rx_pend_list)) {
  311. pbuf = list_entry(pshm_drv->rx_pend_list.next,
  312. struct buf_list, list);
  313. list_del_init(&pbuf->list);
  314. list_add_tail(&pbuf->list, &pshm_drv->rx_empty_list);
  315. /*
  316. * Value index is never changed,
  317. * so read access should be safe.
  318. */
  319. mbox_msg |= SHM_SET_EMPTY(pbuf->index);
  320. }
  321. skb = skb_peek(&pshm_drv->sk_qhead);
  322. if (skb == NULL)
  323. goto send_msg;
  324. /* Check the available no. of buffers in the empty list */
  325. list_for_each(pos, &pshm_drv->tx_empty_list)
  326. avail_emptybuff++;
  327. if ((avail_emptybuff < LOW_WATERMARK) &&
  328. pshm_drv->tx_empty_available) {
  329. /* Update blocking condition. */
  330. pshm_drv->tx_empty_available = 0;
  331. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  332. pshm_drv->cfdev.flowctrl
  333. (pshm_drv->pshm_dev->pshm_netdev,
  334. CAIF_FLOW_OFF);
  335. spin_lock_irqsave(&pshm_drv->lock, flags);
  336. }
  337. /*
  338. * We simply return back to the caller if we do not have space
  339. * either in Tx pending list or Tx empty list. In this case,
  340. * we hold the received skb in the skb list, waiting to
  341. * be transmitted once Tx buffers become available
  342. */
  343. if (list_empty(&pshm_drv->tx_empty_list))
  344. goto send_msg;
  345. /* Get the first free Tx buffer. */
  346. pbuf = list_entry(pshm_drv->tx_empty_list.next,
  347. struct buf_list, list);
  348. do {
  349. if (append) {
  350. skb = skb_peek(&pshm_drv->sk_qhead);
  351. if (skb == NULL)
  352. break;
  353. }
  354. frm = (struct shm_caif_frm *)
  355. (pbuf->desc_vptr + pbuf->frm_ofs);
  356. frm->hdr_ofs = 0;
  357. frmlen = 0;
  358. frmlen += SHM_HDR_LEN + frm->hdr_ofs + skb->len;
  359. /* Add tail padding if needed. */
  360. if (frmlen % SHM_FRM_PAD_LEN)
  361. frmlen += SHM_FRM_PAD_LEN -
  362. (frmlen % SHM_FRM_PAD_LEN);
  363. /*
  364. * Verify that packet, header and additional padding
  365. * can fit within the buffer frame area.
  366. */
  367. if (frmlen >= (pbuf->len - pbuf->frm_ofs))
  368. break;
  369. if (!append) {
  370. list_del_init(&pbuf->list);
  371. append = 1;
  372. }
  373. skb = skb_dequeue(&pshm_drv->sk_qhead);
  374. if (skb == NULL)
  375. break;
  376. /* Copy in CAIF frame. */
  377. skb_copy_bits(skb, 0, pbuf->desc_vptr +
  378. pbuf->frm_ofs + SHM_HDR_LEN +
  379. frm->hdr_ofs, skb->len);
  380. pshm_drv->pshm_dev->pshm_netdev->stats.tx_packets++;
  381. pshm_drv->pshm_dev->pshm_netdev->stats.tx_bytes +=
  382. frmlen;
  383. dev_kfree_skb_irq(skb);
  384. /* Fill in the shared memory packet descriptor area. */
  385. pck_desc = (struct shm_pck_desc *) (pbuf->desc_vptr);
  386. /* Forward to current frame. */
  387. pck_desc += pbuf->frames;
  388. pck_desc->frm_ofs = (pbuf->phy_addr -
  389. pshm_drv->shm_base_addr) +
  390. pbuf->frm_ofs;
  391. pck_desc->frm_len = frmlen;
  392. /* Terminate packet descriptor area. */
  393. pck_desc++;
  394. pck_desc->frm_ofs = 0;
  395. /* Update buffer parameters. */
  396. pbuf->frames++;
  397. pbuf->frm_ofs += frmlen + (frmlen % 32);
  398. } while (pbuf->frames < SHM_MAX_FRMS_PER_BUF);
  399. /* Assign buffer as full. */
  400. list_add_tail(&pbuf->list, &pshm_drv->tx_full_list);
  401. append = 0;
  402. mbox_msg |= SHM_SET_FULL(pbuf->index);
  403. send_msg:
  404. spin_unlock_irqrestore(&pshm_drv->lock, flags);
  405. if (mbox_msg)
  406. pshm_drv->pshm_dev->pshmdev_mbxsend
  407. (pshm_drv->pshm_dev->shm_id, mbox_msg);
  408. } while (mbox_msg);
  409. }
  410. static int shm_netdev_tx(struct sk_buff *skb, struct net_device *shm_netdev)
  411. {
  412. struct shmdrv_layer *pshm_drv;
  413. pshm_drv = netdev_priv(shm_netdev);
  414. skb_queue_tail(&pshm_drv->sk_qhead, skb);
  415. /* Schedule Tx work queue. for deferred processing of skbs*/
  416. if (!work_pending(&pshm_drv->shm_tx_work))
  417. queue_work(pshm_drv->pshm_tx_workqueue, &pshm_drv->shm_tx_work);
  418. return 0;
  419. }
  420. static const struct net_device_ops netdev_ops = {
  421. .ndo_open = shm_netdev_open,
  422. .ndo_stop = shm_netdev_close,
  423. .ndo_start_xmit = shm_netdev_tx,
  424. };
  425. static void shm_netdev_setup(struct net_device *pshm_netdev)
  426. {
  427. struct shmdrv_layer *pshm_drv;
  428. pshm_netdev->netdev_ops = &netdev_ops;
  429. pshm_netdev->mtu = CAIF_MAX_MTU;
  430. pshm_netdev->type = ARPHRD_CAIF;
  431. pshm_netdev->hard_header_len = CAIF_NEEDED_HEADROOM;
  432. pshm_netdev->tx_queue_len = 0;
  433. pshm_netdev->destructor = free_netdev;
  434. pshm_drv = netdev_priv(pshm_netdev);
  435. /* Initialize structures in a clean state. */
  436. memset(pshm_drv, 0, sizeof(struct shmdrv_layer));
  437. pshm_drv->cfdev.link_select = CAIF_LINK_LOW_LATENCY;
  438. }
  439. int caif_shmcore_probe(struct shmdev_layer *pshm_dev)
  440. {
  441. int result, j;
  442. struct shmdrv_layer *pshm_drv = NULL;
  443. pshm_dev->pshm_netdev = alloc_netdev(sizeof(struct shmdrv_layer),
  444. "cfshm%d", shm_netdev_setup);
  445. if (!pshm_dev->pshm_netdev)
  446. return -ENOMEM;
  447. pshm_drv = netdev_priv(pshm_dev->pshm_netdev);
  448. pshm_drv->pshm_dev = pshm_dev;
  449. /*
  450. * Initialization starts with the verification of the
  451. * availability of MBX driver by calling its setup function.
  452. * MBX driver must be available by this time for proper
  453. * functioning of SHM driver.
  454. */
  455. if ((pshm_dev->pshmdev_mbxsetup
  456. (caif_shmdrv_rx_cb, pshm_dev, pshm_drv)) != 0) {
  457. pr_warn("Could not config. SHM Mailbox,"
  458. " Bailing out.....\n");
  459. free_netdev(pshm_dev->pshm_netdev);
  460. return -ENODEV;
  461. }
  462. skb_queue_head_init(&pshm_drv->sk_qhead);
  463. pr_info("SHM DEVICE[%d] PROBED BY DRIVER, NEW SHM DRIVER"
  464. " INSTANCE AT pshm_drv =0x%p\n",
  465. pshm_drv->pshm_dev->shm_id, pshm_drv);
  466. if (pshm_dev->shm_total_sz <
  467. (NR_TX_BUF * TX_BUF_SZ + NR_RX_BUF * RX_BUF_SZ)) {
  468. pr_warn("ERROR, Amount of available"
  469. " Phys. SHM cannot accommodate current SHM "
  470. "driver configuration, Bailing out ...\n");
  471. free_netdev(pshm_dev->pshm_netdev);
  472. return -ENOMEM;
  473. }
  474. pshm_drv->shm_base_addr = pshm_dev->shm_base_addr;
  475. pshm_drv->shm_tx_addr = pshm_drv->shm_base_addr;
  476. if (pshm_dev->shm_loopback)
  477. pshm_drv->shm_rx_addr = pshm_drv->shm_tx_addr;
  478. else
  479. pshm_drv->shm_rx_addr = pshm_dev->shm_base_addr +
  480. (NR_TX_BUF * TX_BUF_SZ);
  481. spin_lock_init(&pshm_drv->lock);
  482. INIT_LIST_HEAD(&pshm_drv->tx_empty_list);
  483. INIT_LIST_HEAD(&pshm_drv->tx_pend_list);
  484. INIT_LIST_HEAD(&pshm_drv->tx_full_list);
  485. INIT_LIST_HEAD(&pshm_drv->rx_empty_list);
  486. INIT_LIST_HEAD(&pshm_drv->rx_pend_list);
  487. INIT_LIST_HEAD(&pshm_drv->rx_full_list);
  488. INIT_WORK(&pshm_drv->shm_tx_work, shm_tx_work_func);
  489. INIT_WORK(&pshm_drv->shm_rx_work, shm_rx_work_func);
  490. pshm_drv->pshm_tx_workqueue =
  491. create_singlethread_workqueue("shm_tx_work");
  492. pshm_drv->pshm_rx_workqueue =
  493. create_singlethread_workqueue("shm_rx_work");
  494. for (j = 0; j < NR_TX_BUF; j++) {
  495. struct buf_list *tx_buf =
  496. kmalloc(sizeof(struct buf_list), GFP_KERNEL);
  497. if (tx_buf == NULL) {
  498. pr_warn("ERROR, Could not"
  499. " allocate dynamic mem. for tx_buf,"
  500. " Bailing out ...\n");
  501. free_netdev(pshm_dev->pshm_netdev);
  502. return -ENOMEM;
  503. }
  504. tx_buf->index = j;
  505. tx_buf->phy_addr = pshm_drv->shm_tx_addr + (TX_BUF_SZ * j);
  506. tx_buf->len = TX_BUF_SZ;
  507. tx_buf->frames = 0;
  508. tx_buf->frm_ofs = SHM_CAIF_FRM_OFS;
  509. if (pshm_dev->shm_loopback)
  510. tx_buf->desc_vptr = (unsigned char *)tx_buf->phy_addr;
  511. else
  512. tx_buf->desc_vptr =
  513. ioremap(tx_buf->phy_addr, TX_BUF_SZ);
  514. list_add_tail(&tx_buf->list, &pshm_drv->tx_empty_list);
  515. }
  516. for (j = 0; j < NR_RX_BUF; j++) {
  517. struct buf_list *rx_buf =
  518. kmalloc(sizeof(struct buf_list), GFP_KERNEL);
  519. if (rx_buf == NULL) {
  520. pr_warn("ERROR, Could not"
  521. " allocate dynamic mem.for rx_buf,"
  522. " Bailing out ...\n");
  523. free_netdev(pshm_dev->pshm_netdev);
  524. return -ENOMEM;
  525. }
  526. rx_buf->index = j;
  527. rx_buf->phy_addr = pshm_drv->shm_rx_addr + (RX_BUF_SZ * j);
  528. rx_buf->len = RX_BUF_SZ;
  529. if (pshm_dev->shm_loopback)
  530. rx_buf->desc_vptr = (unsigned char *)rx_buf->phy_addr;
  531. else
  532. rx_buf->desc_vptr =
  533. ioremap(rx_buf->phy_addr, RX_BUF_SZ);
  534. list_add_tail(&rx_buf->list, &pshm_drv->rx_empty_list);
  535. }
  536. pshm_drv->tx_empty_available = 1;
  537. result = register_netdev(pshm_dev->pshm_netdev);
  538. if (result)
  539. pr_warn("ERROR[%d], SHM could not, "
  540. "register with NW FRMWK Bailing out ...\n", result);
  541. return result;
  542. }
  543. void caif_shmcore_remove(struct net_device *pshm_netdev)
  544. {
  545. struct buf_list *pbuf;
  546. struct shmdrv_layer *pshm_drv = NULL;
  547. pshm_drv = netdev_priv(pshm_netdev);
  548. while (!(list_empty(&pshm_drv->tx_pend_list))) {
  549. pbuf =
  550. list_entry(pshm_drv->tx_pend_list.next,
  551. struct buf_list, list);
  552. list_del(&pbuf->list);
  553. kfree(pbuf);
  554. }
  555. while (!(list_empty(&pshm_drv->tx_full_list))) {
  556. pbuf =
  557. list_entry(pshm_drv->tx_full_list.next,
  558. struct buf_list, list);
  559. list_del(&pbuf->list);
  560. kfree(pbuf);
  561. }
  562. while (!(list_empty(&pshm_drv->tx_empty_list))) {
  563. pbuf =
  564. list_entry(pshm_drv->tx_empty_list.next,
  565. struct buf_list, list);
  566. list_del(&pbuf->list);
  567. kfree(pbuf);
  568. }
  569. while (!(list_empty(&pshm_drv->rx_full_list))) {
  570. pbuf =
  571. list_entry(pshm_drv->tx_full_list.next,
  572. struct buf_list, list);
  573. list_del(&pbuf->list);
  574. kfree(pbuf);
  575. }
  576. while (!(list_empty(&pshm_drv->rx_pend_list))) {
  577. pbuf =
  578. list_entry(pshm_drv->tx_pend_list.next,
  579. struct buf_list, list);
  580. list_del(&pbuf->list);
  581. kfree(pbuf);
  582. }
  583. while (!(list_empty(&pshm_drv->rx_empty_list))) {
  584. pbuf =
  585. list_entry(pshm_drv->rx_empty_list.next,
  586. struct buf_list, list);
  587. list_del(&pbuf->list);
  588. kfree(pbuf);
  589. }
  590. /* Destroy work queues. */
  591. destroy_workqueue(pshm_drv->pshm_tx_workqueue);
  592. destroy_workqueue(pshm_drv->pshm_rx_workqueue);
  593. unregister_netdev(pshm_netdev);
  594. }