tw9910.c 23 KB

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  1. /*
  2. * tw9910 Video Driver
  3. *
  4. * Copyright (C) 2008 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ov772x driver,
  8. *
  9. * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  10. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  11. * Copyright (C) 2008 Magnus Damm
  12. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/i2c.h>
  21. #include <linux/slab.h>
  22. #include <linux/kernel.h>
  23. #include <linux/delay.h>
  24. #include <linux/videodev2.h>
  25. #include <media/soc_camera.h>
  26. #include <media/soc_mediabus.h>
  27. #include <media/tw9910.h>
  28. #include <media/v4l2-chip-ident.h>
  29. #include <media/v4l2-subdev.h>
  30. #define GET_ID(val) ((val & 0xF8) >> 3)
  31. #define GET_REV(val) (val & 0x07)
  32. /*
  33. * register offset
  34. */
  35. #define ID 0x00 /* Product ID Code Register */
  36. #define STATUS1 0x01 /* Chip Status Register I */
  37. #define INFORM 0x02 /* Input Format */
  38. #define OPFORM 0x03 /* Output Format Control Register */
  39. #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
  40. #define OUTCTR1 0x05 /* Output Control I */
  41. #define ACNTL1 0x06 /* Analog Control Register 1 */
  42. #define CROP_HI 0x07 /* Cropping Register, High */
  43. #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
  44. #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
  45. #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
  46. #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
  47. #define CNTRL1 0x0C /* Control Register I */
  48. #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
  49. #define SCALE_HI 0x0E /* Scaling Register, High */
  50. #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
  51. #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
  52. #define CONTRAST 0x11 /* CONTRAST Control Register */
  53. #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
  54. #define SAT_U 0x13 /* Chroma (U) Gain Register */
  55. #define SAT_V 0x14 /* Chroma (V) Gain Register */
  56. #define HUE 0x15 /* Hue Control Register */
  57. #define CORING1 0x17
  58. #define CORING2 0x18 /* Coring and IF compensation */
  59. #define VBICNTL 0x19 /* VBI Control Register */
  60. #define ACNTL2 0x1A /* Analog Control 2 */
  61. #define OUTCTR2 0x1B /* Output Control 2 */
  62. #define SDT 0x1C /* Standard Selection */
  63. #define SDTR 0x1D /* Standard Recognition */
  64. #define TEST 0x1F /* Test Control Register */
  65. #define CLMPG 0x20 /* Clamping Gain */
  66. #define IAGC 0x21 /* Individual AGC Gain */
  67. #define AGCGAIN 0x22 /* AGC Gain */
  68. #define PEAKWT 0x23 /* White Peak Threshold */
  69. #define CLMPL 0x24 /* Clamp level */
  70. #define SYNCT 0x25 /* Sync Amplitude */
  71. #define MISSCNT 0x26 /* Sync Miss Count Register */
  72. #define PCLAMP 0x27 /* Clamp Position Register */
  73. #define VCNTL1 0x28 /* Vertical Control I */
  74. #define VCNTL2 0x29 /* Vertical Control II */
  75. #define CKILL 0x2A /* Color Killer Level Control */
  76. #define COMB 0x2B /* Comb Filter Control */
  77. #define LDLY 0x2C /* Luma Delay and H Filter Control */
  78. #define MISC1 0x2D /* Miscellaneous Control I */
  79. #define LOOP 0x2E /* LOOP Control Register */
  80. #define MISC2 0x2F /* Miscellaneous Control II */
  81. #define MVSN 0x30 /* Macrovision Detection */
  82. #define STATUS2 0x31 /* Chip STATUS II */
  83. #define HFREF 0x32 /* H monitor */
  84. #define CLMD 0x33 /* CLAMP MODE */
  85. #define IDCNTL 0x34 /* ID Detection Control */
  86. #define CLCNTL1 0x35 /* Clamp Control I */
  87. #define ANAPLLCTL 0x4C
  88. #define VBIMIN 0x4D
  89. #define HSLOWCTL 0x4E
  90. #define WSS3 0x4F
  91. #define FILLDATA 0x50
  92. #define SDID 0x51
  93. #define DID 0x52
  94. #define WSS1 0x53
  95. #define WSS2 0x54
  96. #define VVBI 0x55
  97. #define LCTL6 0x56
  98. #define LCTL7 0x57
  99. #define LCTL8 0x58
  100. #define LCTL9 0x59
  101. #define LCTL10 0x5A
  102. #define LCTL11 0x5B
  103. #define LCTL12 0x5C
  104. #define LCTL13 0x5D
  105. #define LCTL14 0x5E
  106. #define LCTL15 0x5F
  107. #define LCTL16 0x60
  108. #define LCTL17 0x61
  109. #define LCTL18 0x62
  110. #define LCTL19 0x63
  111. #define LCTL20 0x64
  112. #define LCTL21 0x65
  113. #define LCTL22 0x66
  114. #define LCTL23 0x67
  115. #define LCTL24 0x68
  116. #define LCTL25 0x69
  117. #define LCTL26 0x6A
  118. #define HSBEGIN 0x6B
  119. #define HSEND 0x6C
  120. #define OVSDLY 0x6D
  121. #define OVSEND 0x6E
  122. #define VBIDELAY 0x6F
  123. /*
  124. * register detail
  125. */
  126. /* INFORM */
  127. #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
  128. #define FC27_FF 0x00 /* 0 : Square pixel mode. */
  129. /* Must use 24.54MHz for 60Hz field rate */
  130. /* source or 29.5MHz for 50Hz field rate */
  131. #define IFSEL_S 0x10 /* 01 : S-video decoding */
  132. #define IFSEL_C 0x00 /* 00 : Composite video decoding */
  133. /* Y input video selection */
  134. #define YSEL_M0 0x00 /* 00 : Mux0 selected */
  135. #define YSEL_M1 0x04 /* 01 : Mux1 selected */
  136. #define YSEL_M2 0x08 /* 10 : Mux2 selected */
  137. #define YSEL_M3 0x10 /* 11 : Mux3 selected */
  138. /* OPFORM */
  139. #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
  140. /* 1 : ITU-R-656 compatible data sequence format */
  141. #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
  142. /* 1 : 16-bit YCrCb 4:2:2 output format.*/
  143. #define LLCMODE 0x20 /* 1 : LLC output mode. */
  144. /* 0 : free-run output mode */
  145. #define AINC 0x10 /* Serial interface auto-indexing control */
  146. /* 0 : auto-increment */
  147. /* 1 : non-auto */
  148. #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
  149. /* 0 : Vertical out ctrl by HACTIVE and DVALID */
  150. #define OEN_TRI_SEL_MASK 0x07
  151. #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
  152. #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
  153. #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
  154. /* OUTCTR1 */
  155. #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
  156. #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
  157. /* VS pin output control */
  158. #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
  159. #define VSSL_VACT 0x10 /* 1 : VACT */
  160. #define VSSL_FIELD 0x20 /* 2 : FIELD */
  161. #define VSSL_VVALID 0x30 /* 3 : VVALID */
  162. #define VSSL_ZERO 0x70 /* 7 : 0 */
  163. #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
  164. #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
  165. /* HS pin output control */
  166. #define HSSL_HACT 0x00 /* 0 : HACT */
  167. #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
  168. #define HSSL_DVALID 0x02 /* 2 : DVALID */
  169. #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
  170. #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
  171. #define HSSL_ZERO 0x07 /* 7 : 0 */
  172. /* ACNTL1 */
  173. #define SRESET 0x80 /* resets the device to its default state
  174. * but all register content remain unchanged.
  175. * This bit is self-resetting.
  176. */
  177. #define ACNTL1_PDN_MASK 0x0e
  178. #define CLK_PDN 0x08 /* system clock power down */
  179. #define Y_PDN 0x04 /* Luma ADC power down */
  180. #define C_PDN 0x02 /* Chroma ADC power down */
  181. /* ACNTL2 */
  182. #define ACNTL2_PDN_MASK 0x40
  183. #define PLL_PDN 0x40 /* PLL power down */
  184. /* VBICNTL */
  185. /* RTSEL : control the real time signal output from the MPOUT pin */
  186. #define RTSEL_MASK 0x07
  187. #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
  188. #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
  189. #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
  190. #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
  191. #define RTSEL_MONO 0x04 /* 0100 = MONO */
  192. #define RTSEL_DET50 0x05 /* 0101 = DET50 */
  193. #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
  194. #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
  195. /* HSYNC start and end are constant for now */
  196. #define HSYNC_START 0x0260
  197. #define HSYNC_END 0x0300
  198. /*
  199. * structure
  200. */
  201. struct regval_list {
  202. unsigned char reg_num;
  203. unsigned char value;
  204. };
  205. struct tw9910_scale_ctrl {
  206. char *name;
  207. unsigned short width;
  208. unsigned short height;
  209. u16 hscale;
  210. u16 vscale;
  211. };
  212. struct tw9910_priv {
  213. struct v4l2_subdev subdev;
  214. struct tw9910_video_info *info;
  215. const struct tw9910_scale_ctrl *scale;
  216. u32 revision;
  217. };
  218. static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
  219. {
  220. .name = "NTSC SQ",
  221. .width = 640,
  222. .height = 480,
  223. .hscale = 0x0100,
  224. .vscale = 0x0100,
  225. },
  226. {
  227. .name = "NTSC CCIR601",
  228. .width = 720,
  229. .height = 480,
  230. .hscale = 0x0100,
  231. .vscale = 0x0100,
  232. },
  233. {
  234. .name = "NTSC SQ (CIF)",
  235. .width = 320,
  236. .height = 240,
  237. .hscale = 0x0200,
  238. .vscale = 0x0200,
  239. },
  240. {
  241. .name = "NTSC CCIR601 (CIF)",
  242. .width = 360,
  243. .height = 240,
  244. .hscale = 0x0200,
  245. .vscale = 0x0200,
  246. },
  247. {
  248. .name = "NTSC SQ (QCIF)",
  249. .width = 160,
  250. .height = 120,
  251. .hscale = 0x0400,
  252. .vscale = 0x0400,
  253. },
  254. {
  255. .name = "NTSC CCIR601 (QCIF)",
  256. .width = 180,
  257. .height = 120,
  258. .hscale = 0x0400,
  259. .vscale = 0x0400,
  260. },
  261. };
  262. static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
  263. {
  264. .name = "PAL SQ",
  265. .width = 768,
  266. .height = 576,
  267. .hscale = 0x0100,
  268. .vscale = 0x0100,
  269. },
  270. {
  271. .name = "PAL CCIR601",
  272. .width = 720,
  273. .height = 576,
  274. .hscale = 0x0100,
  275. .vscale = 0x0100,
  276. },
  277. {
  278. .name = "PAL SQ (CIF)",
  279. .width = 384,
  280. .height = 288,
  281. .hscale = 0x0200,
  282. .vscale = 0x0200,
  283. },
  284. {
  285. .name = "PAL CCIR601 (CIF)",
  286. .width = 360,
  287. .height = 288,
  288. .hscale = 0x0200,
  289. .vscale = 0x0200,
  290. },
  291. {
  292. .name = "PAL SQ (QCIF)",
  293. .width = 192,
  294. .height = 144,
  295. .hscale = 0x0400,
  296. .vscale = 0x0400,
  297. },
  298. {
  299. .name = "PAL CCIR601 (QCIF)",
  300. .width = 180,
  301. .height = 144,
  302. .hscale = 0x0400,
  303. .vscale = 0x0400,
  304. },
  305. };
  306. /*
  307. * general function
  308. */
  309. static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
  310. {
  311. return container_of(i2c_get_clientdata(client), struct tw9910_priv,
  312. subdev);
  313. }
  314. static int tw9910_mask_set(struct i2c_client *client, u8 command,
  315. u8 mask, u8 set)
  316. {
  317. s32 val = i2c_smbus_read_byte_data(client, command);
  318. if (val < 0)
  319. return val;
  320. val &= ~mask;
  321. val |= set & mask;
  322. return i2c_smbus_write_byte_data(client, command, val);
  323. }
  324. static int tw9910_set_scale(struct i2c_client *client,
  325. const struct tw9910_scale_ctrl *scale)
  326. {
  327. int ret;
  328. ret = i2c_smbus_write_byte_data(client, SCALE_HI,
  329. (scale->vscale & 0x0F00) >> 4 |
  330. (scale->hscale & 0x0F00) >> 8);
  331. if (ret < 0)
  332. return ret;
  333. ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
  334. scale->hscale & 0x00FF);
  335. if (ret < 0)
  336. return ret;
  337. ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
  338. scale->vscale & 0x00FF);
  339. return ret;
  340. }
  341. static int tw9910_set_hsync(struct i2c_client *client)
  342. {
  343. struct tw9910_priv *priv = to_tw9910(client);
  344. int ret;
  345. /* bit 10 - 3 */
  346. ret = i2c_smbus_write_byte_data(client, HSBEGIN,
  347. (HSYNC_START & 0x07F8) >> 3);
  348. if (ret < 0)
  349. return ret;
  350. /* bit 10 - 3 */
  351. ret = i2c_smbus_write_byte_data(client, HSEND,
  352. (HSYNC_END & 0x07F8) >> 3);
  353. if (ret < 0)
  354. return ret;
  355. /* So far only revisions 0 and 1 have been seen */
  356. /* bit 2 - 0 */
  357. if (1 == priv->revision)
  358. ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
  359. (HSYNC_START & 0x0007) << 4 |
  360. (HSYNC_END & 0x0007));
  361. return ret;
  362. }
  363. static void tw9910_reset(struct i2c_client *client)
  364. {
  365. tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
  366. msleep(1);
  367. }
  368. static int tw9910_power(struct i2c_client *client, int enable)
  369. {
  370. int ret;
  371. u8 acntl1;
  372. u8 acntl2;
  373. if (enable) {
  374. acntl1 = 0;
  375. acntl2 = 0;
  376. } else {
  377. acntl1 = CLK_PDN | Y_PDN | C_PDN;
  378. acntl2 = PLL_PDN;
  379. }
  380. ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
  381. if (ret < 0)
  382. return ret;
  383. return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
  384. }
  385. static const struct tw9910_scale_ctrl *tw9910_select_norm(struct soc_camera_device *icd,
  386. u32 width, u32 height)
  387. {
  388. const struct tw9910_scale_ctrl *scale;
  389. const struct tw9910_scale_ctrl *ret = NULL;
  390. v4l2_std_id norm = icd->vdev->current_norm;
  391. __u32 diff = 0xffffffff, tmp;
  392. int size, i;
  393. if (norm & V4L2_STD_NTSC) {
  394. scale = tw9910_ntsc_scales;
  395. size = ARRAY_SIZE(tw9910_ntsc_scales);
  396. } else if (norm & V4L2_STD_PAL) {
  397. scale = tw9910_pal_scales;
  398. size = ARRAY_SIZE(tw9910_pal_scales);
  399. } else {
  400. return NULL;
  401. }
  402. for (i = 0; i < size; i++) {
  403. tmp = abs(width - scale[i].width) +
  404. abs(height - scale[i].height);
  405. if (tmp < diff) {
  406. diff = tmp;
  407. ret = scale + i;
  408. }
  409. }
  410. return ret;
  411. }
  412. /*
  413. * subdevice operations
  414. */
  415. static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
  416. {
  417. struct i2c_client *client = v4l2_get_subdevdata(sd);
  418. struct tw9910_priv *priv = to_tw9910(client);
  419. u8 val;
  420. int ret;
  421. if (!enable) {
  422. switch (priv->revision) {
  423. case 0:
  424. val = OEN_TRI_SEL_ALL_OFF_r0;
  425. break;
  426. case 1:
  427. val = OEN_TRI_SEL_ALL_OFF_r1;
  428. break;
  429. default:
  430. dev_err(&client->dev, "un-supported revision\n");
  431. return -EINVAL;
  432. }
  433. } else {
  434. val = OEN_TRI_SEL_ALL_ON;
  435. if (!priv->scale) {
  436. dev_err(&client->dev, "norm select error\n");
  437. return -EPERM;
  438. }
  439. dev_dbg(&client->dev, "%s %dx%d\n",
  440. priv->scale->name,
  441. priv->scale->width,
  442. priv->scale->height);
  443. }
  444. ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
  445. if (ret < 0)
  446. return ret;
  447. return tw9910_power(client, enable);
  448. }
  449. static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
  450. {
  451. int ret = -EINVAL;
  452. if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL))
  453. ret = 0;
  454. return ret;
  455. }
  456. static int tw9910_g_chip_ident(struct v4l2_subdev *sd,
  457. struct v4l2_dbg_chip_ident *id)
  458. {
  459. struct i2c_client *client = v4l2_get_subdevdata(sd);
  460. struct tw9910_priv *priv = to_tw9910(client);
  461. id->ident = V4L2_IDENT_TW9910;
  462. id->revision = priv->revision;
  463. return 0;
  464. }
  465. #ifdef CONFIG_VIDEO_ADV_DEBUG
  466. static int tw9910_g_register(struct v4l2_subdev *sd,
  467. struct v4l2_dbg_register *reg)
  468. {
  469. struct i2c_client *client = v4l2_get_subdevdata(sd);
  470. int ret;
  471. if (reg->reg > 0xff)
  472. return -EINVAL;
  473. ret = i2c_smbus_read_byte_data(client, reg->reg);
  474. if (ret < 0)
  475. return ret;
  476. /*
  477. * ret = int
  478. * reg->val = __u64
  479. */
  480. reg->val = (__u64)ret;
  481. return 0;
  482. }
  483. static int tw9910_s_register(struct v4l2_subdev *sd,
  484. struct v4l2_dbg_register *reg)
  485. {
  486. struct i2c_client *client = v4l2_get_subdevdata(sd);
  487. if (reg->reg > 0xff ||
  488. reg->val > 0xff)
  489. return -EINVAL;
  490. return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
  491. }
  492. #endif
  493. static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
  494. {
  495. struct i2c_client *client = v4l2_get_subdevdata(sd);
  496. struct tw9910_priv *priv = to_tw9910(client);
  497. struct soc_camera_device *icd = client->dev.platform_data;
  498. int ret = -EINVAL;
  499. u8 val;
  500. /*
  501. * select suitable norm
  502. */
  503. priv->scale = tw9910_select_norm(icd, *width, *height);
  504. if (!priv->scale)
  505. goto tw9910_set_fmt_error;
  506. /*
  507. * reset hardware
  508. */
  509. tw9910_reset(client);
  510. /*
  511. * set bus width
  512. */
  513. val = 0x00;
  514. if (SOCAM_DATAWIDTH_16 == priv->info->buswidth)
  515. val = LEN;
  516. ret = tw9910_mask_set(client, OPFORM, LEN, val);
  517. if (ret < 0)
  518. goto tw9910_set_fmt_error;
  519. /*
  520. * select MPOUT behavior
  521. */
  522. switch (priv->info->mpout) {
  523. case TW9910_MPO_VLOSS:
  524. val = RTSEL_VLOSS; break;
  525. case TW9910_MPO_HLOCK:
  526. val = RTSEL_HLOCK; break;
  527. case TW9910_MPO_SLOCK:
  528. val = RTSEL_SLOCK; break;
  529. case TW9910_MPO_VLOCK:
  530. val = RTSEL_VLOCK; break;
  531. case TW9910_MPO_MONO:
  532. val = RTSEL_MONO; break;
  533. case TW9910_MPO_DET50:
  534. val = RTSEL_DET50; break;
  535. case TW9910_MPO_FIELD:
  536. val = RTSEL_FIELD; break;
  537. case TW9910_MPO_RTCO:
  538. val = RTSEL_RTCO; break;
  539. default:
  540. val = 0;
  541. }
  542. ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
  543. if (ret < 0)
  544. goto tw9910_set_fmt_error;
  545. /*
  546. * set scale
  547. */
  548. ret = tw9910_set_scale(client, priv->scale);
  549. if (ret < 0)
  550. goto tw9910_set_fmt_error;
  551. /*
  552. * set hsync
  553. */
  554. ret = tw9910_set_hsync(client);
  555. if (ret < 0)
  556. goto tw9910_set_fmt_error;
  557. *width = priv->scale->width;
  558. *height = priv->scale->height;
  559. return ret;
  560. tw9910_set_fmt_error:
  561. tw9910_reset(client);
  562. priv->scale = NULL;
  563. return ret;
  564. }
  565. static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
  566. {
  567. struct i2c_client *client = v4l2_get_subdevdata(sd);
  568. struct soc_camera_device *icd = client->dev.platform_data;
  569. a->c.left = 0;
  570. a->c.top = 0;
  571. if (icd->vdev->current_norm & V4L2_STD_NTSC) {
  572. a->c.width = 640;
  573. a->c.height = 480;
  574. } else {
  575. a->c.width = 768;
  576. a->c.height = 576;
  577. }
  578. a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  579. return 0;
  580. }
  581. static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
  582. {
  583. struct i2c_client *client = v4l2_get_subdevdata(sd);
  584. struct soc_camera_device *icd = client->dev.platform_data;
  585. a->bounds.left = 0;
  586. a->bounds.top = 0;
  587. if (icd->vdev->current_norm & V4L2_STD_NTSC) {
  588. a->bounds.width = 640;
  589. a->bounds.height = 480;
  590. } else {
  591. a->bounds.width = 768;
  592. a->bounds.height = 576;
  593. }
  594. a->defrect = a->bounds;
  595. a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  596. a->pixelaspect.numerator = 1;
  597. a->pixelaspect.denominator = 1;
  598. return 0;
  599. }
  600. static int tw9910_g_fmt(struct v4l2_subdev *sd,
  601. struct v4l2_mbus_framefmt *mf)
  602. {
  603. struct i2c_client *client = v4l2_get_subdevdata(sd);
  604. struct tw9910_priv *priv = to_tw9910(client);
  605. if (!priv->scale) {
  606. int ret;
  607. u32 width = 640, height = 480;
  608. ret = tw9910_set_frame(sd, &width, &height);
  609. if (ret < 0)
  610. return ret;
  611. }
  612. mf->width = priv->scale->width;
  613. mf->height = priv->scale->height;
  614. mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
  615. mf->colorspace = V4L2_COLORSPACE_JPEG;
  616. mf->field = V4L2_FIELD_INTERLACED_BT;
  617. return 0;
  618. }
  619. static int tw9910_s_fmt(struct v4l2_subdev *sd,
  620. struct v4l2_mbus_framefmt *mf)
  621. {
  622. u32 width = mf->width, height = mf->height;
  623. int ret;
  624. WARN_ON(mf->field != V4L2_FIELD_ANY &&
  625. mf->field != V4L2_FIELD_INTERLACED_BT);
  626. /*
  627. * check color format
  628. */
  629. if (mf->code != V4L2_MBUS_FMT_UYVY8_2X8)
  630. return -EINVAL;
  631. mf->colorspace = V4L2_COLORSPACE_JPEG;
  632. ret = tw9910_set_frame(sd, &width, &height);
  633. if (!ret) {
  634. mf->width = width;
  635. mf->height = height;
  636. }
  637. return ret;
  638. }
  639. static int tw9910_try_fmt(struct v4l2_subdev *sd,
  640. struct v4l2_mbus_framefmt *mf)
  641. {
  642. struct i2c_client *client = v4l2_get_subdevdata(sd);
  643. struct soc_camera_device *icd = client->dev.platform_data;
  644. const struct tw9910_scale_ctrl *scale;
  645. if (V4L2_FIELD_ANY == mf->field) {
  646. mf->field = V4L2_FIELD_INTERLACED_BT;
  647. } else if (V4L2_FIELD_INTERLACED_BT != mf->field) {
  648. dev_err(&client->dev, "Field type %d invalid.\n", mf->field);
  649. return -EINVAL;
  650. }
  651. mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
  652. mf->colorspace = V4L2_COLORSPACE_JPEG;
  653. /*
  654. * select suitable norm
  655. */
  656. scale = tw9910_select_norm(icd, mf->width, mf->height);
  657. if (!scale)
  658. return -EINVAL;
  659. mf->width = scale->width;
  660. mf->height = scale->height;
  661. return 0;
  662. }
  663. static int tw9910_video_probe(struct soc_camera_device *icd,
  664. struct i2c_client *client)
  665. {
  666. struct tw9910_priv *priv = to_tw9910(client);
  667. s32 id;
  668. /* We must have a parent by now. And it cannot be a wrong one. */
  669. BUG_ON(!icd->parent ||
  670. to_soc_camera_host(icd->parent)->nr != icd->iface);
  671. /*
  672. * tw9910 only use 8 or 16 bit bus width
  673. */
  674. if (SOCAM_DATAWIDTH_16 != priv->info->buswidth &&
  675. SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
  676. dev_err(&client->dev, "bus width error\n");
  677. return -ENODEV;
  678. }
  679. /*
  680. * check and show Product ID
  681. * So far only revisions 0 and 1 have been seen
  682. */
  683. id = i2c_smbus_read_byte_data(client, ID);
  684. priv->revision = GET_REV(id);
  685. id = GET_ID(id);
  686. if (0x0B != id ||
  687. 0x01 < priv->revision) {
  688. dev_err(&client->dev,
  689. "Product ID error %x:%x\n",
  690. id, priv->revision);
  691. return -ENODEV;
  692. }
  693. dev_info(&client->dev,
  694. "tw9910 Product ID %0x:%0x\n", id, priv->revision);
  695. icd->vdev->tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL;
  696. icd->vdev->current_norm = V4L2_STD_NTSC;
  697. return 0;
  698. }
  699. static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
  700. .g_chip_ident = tw9910_g_chip_ident,
  701. .s_std = tw9910_s_std,
  702. #ifdef CONFIG_VIDEO_ADV_DEBUG
  703. .g_register = tw9910_g_register,
  704. .s_register = tw9910_s_register,
  705. #endif
  706. };
  707. static int tw9910_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
  708. enum v4l2_mbus_pixelcode *code)
  709. {
  710. if (index)
  711. return -EINVAL;
  712. *code = V4L2_MBUS_FMT_UYVY8_2X8;
  713. return 0;
  714. }
  715. static int tw9910_g_mbus_config(struct v4l2_subdev *sd,
  716. struct v4l2_mbus_config *cfg)
  717. {
  718. struct i2c_client *client = v4l2_get_subdevdata(sd);
  719. struct soc_camera_device *icd = client->dev.platform_data;
  720. struct soc_camera_link *icl = to_soc_camera_link(icd);
  721. cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
  722. V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
  723. V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
  724. V4L2_MBUS_DATA_ACTIVE_HIGH;
  725. cfg->type = V4L2_MBUS_PARALLEL;
  726. cfg->flags = soc_camera_apply_board_flags(icl, cfg);
  727. return 0;
  728. }
  729. static int tw9910_s_mbus_config(struct v4l2_subdev *sd,
  730. const struct v4l2_mbus_config *cfg)
  731. {
  732. struct i2c_client *client = v4l2_get_subdevdata(sd);
  733. struct soc_camera_device *icd = client->dev.platform_data;
  734. struct soc_camera_link *icl = to_soc_camera_link(icd);
  735. u8 val = VSSL_VVALID | HSSL_DVALID;
  736. unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
  737. /*
  738. * set OUTCTR1
  739. *
  740. * We use VVALID and DVALID signals to control VSYNC and HSYNC
  741. * outputs, in this mode their polarity is inverted.
  742. */
  743. if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  744. val |= HSP_HI;
  745. if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  746. val |= VSP_HI;
  747. return i2c_smbus_write_byte_data(client, OUTCTR1, val);
  748. }
  749. static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
  750. .s_stream = tw9910_s_stream,
  751. .g_mbus_fmt = tw9910_g_fmt,
  752. .s_mbus_fmt = tw9910_s_fmt,
  753. .try_mbus_fmt = tw9910_try_fmt,
  754. .cropcap = tw9910_cropcap,
  755. .g_crop = tw9910_g_crop,
  756. .enum_mbus_fmt = tw9910_enum_fmt,
  757. .g_mbus_config = tw9910_g_mbus_config,
  758. .s_mbus_config = tw9910_s_mbus_config,
  759. };
  760. static struct v4l2_subdev_ops tw9910_subdev_ops = {
  761. .core = &tw9910_subdev_core_ops,
  762. .video = &tw9910_subdev_video_ops,
  763. };
  764. /*
  765. * i2c_driver function
  766. */
  767. static int tw9910_probe(struct i2c_client *client,
  768. const struct i2c_device_id *did)
  769. {
  770. struct tw9910_priv *priv;
  771. struct tw9910_video_info *info;
  772. struct soc_camera_device *icd = client->dev.platform_data;
  773. struct i2c_adapter *adapter =
  774. to_i2c_adapter(client->dev.parent);
  775. struct soc_camera_link *icl;
  776. int ret;
  777. if (!icd) {
  778. dev_err(&client->dev, "TW9910: missing soc-camera data!\n");
  779. return -EINVAL;
  780. }
  781. icl = to_soc_camera_link(icd);
  782. if (!icl || !icl->priv)
  783. return -EINVAL;
  784. info = icl->priv;
  785. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
  786. dev_err(&client->dev,
  787. "I2C-Adapter doesn't support "
  788. "I2C_FUNC_SMBUS_BYTE_DATA\n");
  789. return -EIO;
  790. }
  791. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  792. if (!priv)
  793. return -ENOMEM;
  794. priv->info = info;
  795. v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
  796. icd->iface = icl->bus_id;
  797. ret = tw9910_video_probe(icd, client);
  798. if (ret)
  799. kfree(priv);
  800. return ret;
  801. }
  802. static int tw9910_remove(struct i2c_client *client)
  803. {
  804. struct tw9910_priv *priv = to_tw9910(client);
  805. kfree(priv);
  806. return 0;
  807. }
  808. static const struct i2c_device_id tw9910_id[] = {
  809. { "tw9910", 0 },
  810. { }
  811. };
  812. MODULE_DEVICE_TABLE(i2c, tw9910_id);
  813. static struct i2c_driver tw9910_i2c_driver = {
  814. .driver = {
  815. .name = "tw9910",
  816. },
  817. .probe = tw9910_probe,
  818. .remove = tw9910_remove,
  819. .id_table = tw9910_id,
  820. };
  821. /*
  822. * module function
  823. */
  824. static int __init tw9910_module_init(void)
  825. {
  826. return i2c_add_driver(&tw9910_i2c_driver);
  827. }
  828. static void __exit tw9910_module_exit(void)
  829. {
  830. i2c_del_driver(&tw9910_i2c_driver);
  831. }
  832. module_init(tw9910_module_init);
  833. module_exit(tw9910_module_exit);
  834. MODULE_DESCRIPTION("SoC Camera driver for tw9910");
  835. MODULE_AUTHOR("Kuninori Morimoto");
  836. MODULE_LICENSE("GPL v2");