qla_init.c 146 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_device_resync(scsi_qla_host_t *);
  29. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  30. uint16_t *);
  31. static int qla2x00_restart_isp(scsi_qla_host_t *);
  32. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  33. static int qla84xx_init_chip(scsi_qla_host_t *);
  34. static int qla25xx_init_queues(struct qla_hw_data *);
  35. /* SRB Extensions ---------------------------------------------------------- */
  36. static void
  37. qla2x00_ctx_sp_timeout(unsigned long __data)
  38. {
  39. srb_t *sp = (srb_t *)__data;
  40. struct srb_ctx *ctx;
  41. struct srb_iocb *iocb;
  42. fc_port_t *fcport = sp->fcport;
  43. struct qla_hw_data *ha = fcport->vha->hw;
  44. struct req_que *req;
  45. unsigned long flags;
  46. spin_lock_irqsave(&ha->hardware_lock, flags);
  47. req = ha->req_q_map[0];
  48. req->outstanding_cmds[sp->handle] = NULL;
  49. ctx = sp->ctx;
  50. iocb = ctx->u.iocb_cmd;
  51. iocb->timeout(sp);
  52. iocb->free(sp);
  53. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  54. }
  55. static void
  56. qla2x00_ctx_sp_free(srb_t *sp)
  57. {
  58. struct srb_ctx *ctx = sp->ctx;
  59. struct srb_iocb *iocb = ctx->u.iocb_cmd;
  60. struct scsi_qla_host *vha = sp->fcport->vha;
  61. del_timer(&iocb->timer);
  62. kfree(iocb);
  63. kfree(ctx);
  64. mempool_free(sp, sp->fcport->vha->hw->srb_mempool);
  65. QLA_VHA_MARK_NOT_BUSY(vha);
  66. }
  67. inline srb_t *
  68. qla2x00_get_ctx_sp(scsi_qla_host_t *vha, fc_port_t *fcport, size_t size,
  69. unsigned long tmo)
  70. {
  71. srb_t *sp = NULL;
  72. struct qla_hw_data *ha = vha->hw;
  73. struct srb_ctx *ctx;
  74. struct srb_iocb *iocb;
  75. uint8_t bail;
  76. QLA_VHA_MARK_BUSY(vha, bail);
  77. if (bail)
  78. return NULL;
  79. sp = mempool_alloc(ha->srb_mempool, GFP_KERNEL);
  80. if (!sp)
  81. goto done;
  82. ctx = kzalloc(size, GFP_KERNEL);
  83. if (!ctx) {
  84. mempool_free(sp, ha->srb_mempool);
  85. sp = NULL;
  86. goto done;
  87. }
  88. iocb = kzalloc(sizeof(struct srb_iocb), GFP_KERNEL);
  89. if (!iocb) {
  90. mempool_free(sp, ha->srb_mempool);
  91. sp = NULL;
  92. kfree(ctx);
  93. goto done;
  94. }
  95. memset(sp, 0, sizeof(*sp));
  96. sp->fcport = fcport;
  97. sp->ctx = ctx;
  98. ctx->u.iocb_cmd = iocb;
  99. iocb->free = qla2x00_ctx_sp_free;
  100. init_timer(&iocb->timer);
  101. if (!tmo)
  102. goto done;
  103. iocb->timer.expires = jiffies + tmo * HZ;
  104. iocb->timer.data = (unsigned long)sp;
  105. iocb->timer.function = qla2x00_ctx_sp_timeout;
  106. add_timer(&iocb->timer);
  107. done:
  108. if (!sp)
  109. QLA_VHA_MARK_NOT_BUSY(vha);
  110. return sp;
  111. }
  112. /* Asynchronous Login/Logout Routines -------------------------------------- */
  113. static inline unsigned long
  114. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  115. {
  116. unsigned long tmo;
  117. struct qla_hw_data *ha = vha->hw;
  118. /* Firmware should use switch negotiated r_a_tov for timeout. */
  119. tmo = ha->r_a_tov / 10 * 2;
  120. if (!IS_FWI2_CAPABLE(ha)) {
  121. /*
  122. * Except for earlier ISPs where the timeout is seeded from the
  123. * initialization control block.
  124. */
  125. tmo = ha->login_timeout;
  126. }
  127. return tmo;
  128. }
  129. static void
  130. qla2x00_async_iocb_timeout(srb_t *sp)
  131. {
  132. fc_port_t *fcport = sp->fcport;
  133. struct srb_ctx *ctx = sp->ctx;
  134. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  135. "Async-%s timeout - portid=%02x%02x%02x.\n",
  136. ctx->name, fcport->d_id.b.domain, fcport->d_id.b.area,
  137. fcport->d_id.b.al_pa);
  138. fcport->flags &= ~FCF_ASYNC_SENT;
  139. if (ctx->type == SRB_LOGIN_CMD) {
  140. struct srb_iocb *lio = ctx->u.iocb_cmd;
  141. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  142. /* Retry as needed. */
  143. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  144. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  145. QLA_LOGIO_LOGIN_RETRIED : 0;
  146. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  147. lio->u.logio.data);
  148. }
  149. }
  150. static void
  151. qla2x00_async_login_ctx_done(srb_t *sp)
  152. {
  153. struct srb_ctx *ctx = sp->ctx;
  154. struct srb_iocb *lio = ctx->u.iocb_cmd;
  155. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  156. lio->u.logio.data);
  157. lio->free(sp);
  158. }
  159. int
  160. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  161. uint16_t *data)
  162. {
  163. srb_t *sp;
  164. struct srb_ctx *ctx;
  165. struct srb_iocb *lio;
  166. int rval;
  167. rval = QLA_FUNCTION_FAILED;
  168. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  169. qla2x00_get_async_timeout(vha) + 2);
  170. if (!sp)
  171. goto done;
  172. ctx = sp->ctx;
  173. ctx->type = SRB_LOGIN_CMD;
  174. ctx->name = "login";
  175. lio = ctx->u.iocb_cmd;
  176. lio->timeout = qla2x00_async_iocb_timeout;
  177. lio->done = qla2x00_async_login_ctx_done;
  178. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  179. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  180. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  181. rval = qla2x00_start_sp(sp);
  182. if (rval != QLA_SUCCESS)
  183. goto done_free_sp;
  184. ql_dbg(ql_dbg_disc, vha, 0x2072,
  185. "Async-login - loopid=%x portid=%02x%02x%02x retries=%d.\n",
  186. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  187. fcport->d_id.b.al_pa, fcport->login_retry);
  188. return rval;
  189. done_free_sp:
  190. lio->free(sp);
  191. done:
  192. return rval;
  193. }
  194. static void
  195. qla2x00_async_logout_ctx_done(srb_t *sp)
  196. {
  197. struct srb_ctx *ctx = sp->ctx;
  198. struct srb_iocb *lio = ctx->u.iocb_cmd;
  199. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  200. lio->u.logio.data);
  201. lio->free(sp);
  202. }
  203. int
  204. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  205. {
  206. srb_t *sp;
  207. struct srb_ctx *ctx;
  208. struct srb_iocb *lio;
  209. int rval;
  210. rval = QLA_FUNCTION_FAILED;
  211. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  212. qla2x00_get_async_timeout(vha) + 2);
  213. if (!sp)
  214. goto done;
  215. ctx = sp->ctx;
  216. ctx->type = SRB_LOGOUT_CMD;
  217. ctx->name = "logout";
  218. lio = ctx->u.iocb_cmd;
  219. lio->timeout = qla2x00_async_iocb_timeout;
  220. lio->done = qla2x00_async_logout_ctx_done;
  221. rval = qla2x00_start_sp(sp);
  222. if (rval != QLA_SUCCESS)
  223. goto done_free_sp;
  224. ql_dbg(ql_dbg_disc, vha, 0x2070,
  225. "Async-logout - loop-id=%x portid=%02x%02x%02x.\n",
  226. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  227. fcport->d_id.b.al_pa);
  228. return rval;
  229. done_free_sp:
  230. lio->free(sp);
  231. done:
  232. return rval;
  233. }
  234. static void
  235. qla2x00_async_adisc_ctx_done(srb_t *sp)
  236. {
  237. struct srb_ctx *ctx = sp->ctx;
  238. struct srb_iocb *lio = ctx->u.iocb_cmd;
  239. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  240. lio->u.logio.data);
  241. lio->free(sp);
  242. }
  243. int
  244. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  245. uint16_t *data)
  246. {
  247. srb_t *sp;
  248. struct srb_ctx *ctx;
  249. struct srb_iocb *lio;
  250. int rval;
  251. rval = QLA_FUNCTION_FAILED;
  252. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  253. qla2x00_get_async_timeout(vha) + 2);
  254. if (!sp)
  255. goto done;
  256. ctx = sp->ctx;
  257. ctx->type = SRB_ADISC_CMD;
  258. ctx->name = "adisc";
  259. lio = ctx->u.iocb_cmd;
  260. lio->timeout = qla2x00_async_iocb_timeout;
  261. lio->done = qla2x00_async_adisc_ctx_done;
  262. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  263. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  264. rval = qla2x00_start_sp(sp);
  265. if (rval != QLA_SUCCESS)
  266. goto done_free_sp;
  267. ql_dbg(ql_dbg_disc, vha, 0x206f,
  268. "Async-adisc - loopid=%x portid=%02x%02x%02x.\n",
  269. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  270. fcport->d_id.b.al_pa);
  271. return rval;
  272. done_free_sp:
  273. lio->free(sp);
  274. done:
  275. return rval;
  276. }
  277. static void
  278. qla2x00_async_tm_cmd_ctx_done(srb_t *sp)
  279. {
  280. struct srb_ctx *ctx = sp->ctx;
  281. struct srb_iocb *iocb = (struct srb_iocb *)ctx->u.iocb_cmd;
  282. qla2x00_async_tm_cmd_done(sp->fcport->vha, sp->fcport, iocb);
  283. iocb->free(sp);
  284. }
  285. int
  286. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
  287. uint32_t tag)
  288. {
  289. struct scsi_qla_host *vha = fcport->vha;
  290. srb_t *sp;
  291. struct srb_ctx *ctx;
  292. struct srb_iocb *tcf;
  293. int rval;
  294. rval = QLA_FUNCTION_FAILED;
  295. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  296. qla2x00_get_async_timeout(vha) + 2);
  297. if (!sp)
  298. goto done;
  299. ctx = sp->ctx;
  300. ctx->type = SRB_TM_CMD;
  301. ctx->name = "tmf";
  302. tcf = ctx->u.iocb_cmd;
  303. tcf->u.tmf.flags = flags;
  304. tcf->u.tmf.lun = lun;
  305. tcf->u.tmf.data = tag;
  306. tcf->timeout = qla2x00_async_iocb_timeout;
  307. tcf->done = qla2x00_async_tm_cmd_ctx_done;
  308. rval = qla2x00_start_sp(sp);
  309. if (rval != QLA_SUCCESS)
  310. goto done_free_sp;
  311. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  312. "Async-tmf loop-id=%x portid=%02x%02x%02x.\n",
  313. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  314. fcport->d_id.b.al_pa);
  315. return rval;
  316. done_free_sp:
  317. tcf->free(sp);
  318. done:
  319. return rval;
  320. }
  321. void
  322. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  323. uint16_t *data)
  324. {
  325. int rval;
  326. switch (data[0]) {
  327. case MBS_COMMAND_COMPLETE:
  328. /*
  329. * Driver must validate login state - If PRLI not complete,
  330. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  331. * requests.
  332. */
  333. rval = qla2x00_get_port_database(vha, fcport, 0);
  334. if (rval != QLA_SUCCESS) {
  335. qla2x00_post_async_logout_work(vha, fcport, NULL);
  336. qla2x00_post_async_login_work(vha, fcport, NULL);
  337. break;
  338. }
  339. if (fcport->flags & FCF_FCP2_DEVICE) {
  340. qla2x00_post_async_adisc_work(vha, fcport, data);
  341. break;
  342. }
  343. qla2x00_update_fcport(vha, fcport);
  344. break;
  345. case MBS_COMMAND_ERROR:
  346. fcport->flags &= ~FCF_ASYNC_SENT;
  347. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  348. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  349. else
  350. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  351. break;
  352. case MBS_PORT_ID_USED:
  353. fcport->loop_id = data[1];
  354. qla2x00_post_async_logout_work(vha, fcport, NULL);
  355. qla2x00_post_async_login_work(vha, fcport, NULL);
  356. break;
  357. case MBS_LOOP_ID_USED:
  358. fcport->loop_id++;
  359. rval = qla2x00_find_new_loop_id(vha, fcport);
  360. if (rval != QLA_SUCCESS) {
  361. fcport->flags &= ~FCF_ASYNC_SENT;
  362. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  363. break;
  364. }
  365. qla2x00_post_async_login_work(vha, fcport, NULL);
  366. break;
  367. }
  368. return;
  369. }
  370. void
  371. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  372. uint16_t *data)
  373. {
  374. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  375. return;
  376. }
  377. void
  378. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  379. uint16_t *data)
  380. {
  381. if (data[0] == MBS_COMMAND_COMPLETE) {
  382. qla2x00_update_fcport(vha, fcport);
  383. return;
  384. }
  385. /* Retry login. */
  386. fcport->flags &= ~FCF_ASYNC_SENT;
  387. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  388. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  389. else
  390. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  391. return;
  392. }
  393. void
  394. qla2x00_async_tm_cmd_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  395. struct srb_iocb *iocb)
  396. {
  397. int rval;
  398. uint32_t flags;
  399. uint16_t lun;
  400. flags = iocb->u.tmf.flags;
  401. lun = (uint16_t)iocb->u.tmf.lun;
  402. /* Issue Marker IOCB */
  403. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  404. vha->hw->rsp_q_map[0], fcport->loop_id, lun,
  405. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  406. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  407. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  408. "TM IOCB failed (%x).\n", rval);
  409. }
  410. return;
  411. }
  412. /****************************************************************************/
  413. /* QLogic ISP2x00 Hardware Support Functions. */
  414. /****************************************************************************/
  415. /*
  416. * qla2x00_initialize_adapter
  417. * Initialize board.
  418. *
  419. * Input:
  420. * ha = adapter block pointer.
  421. *
  422. * Returns:
  423. * 0 = success
  424. */
  425. int
  426. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  427. {
  428. int rval;
  429. struct qla_hw_data *ha = vha->hw;
  430. struct req_que *req = ha->req_q_map[0];
  431. /* Clear adapter flags. */
  432. vha->flags.online = 0;
  433. ha->flags.chip_reset_done = 0;
  434. vha->flags.reset_active = 0;
  435. ha->flags.pci_channel_io_perm_failure = 0;
  436. ha->flags.eeh_busy = 0;
  437. ha->flags.thermal_supported = 1;
  438. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  439. atomic_set(&vha->loop_state, LOOP_DOWN);
  440. vha->device_flags = DFLG_NO_CABLE;
  441. vha->dpc_flags = 0;
  442. vha->flags.management_server_logged_in = 0;
  443. vha->marker_needed = 0;
  444. ha->isp_abort_cnt = 0;
  445. ha->beacon_blink_led = 0;
  446. set_bit(0, ha->req_qid_map);
  447. set_bit(0, ha->rsp_qid_map);
  448. ql_log(ql_log_info, vha, 0x0040,
  449. "Configuring PCI space...\n");
  450. rval = ha->isp_ops->pci_config(vha);
  451. if (rval) {
  452. ql_log(ql_log_warn, vha, 0x0044,
  453. "Unable to configure PCI space.\n");
  454. return (rval);
  455. }
  456. ha->isp_ops->reset_chip(vha);
  457. rval = qla2xxx_get_flash_info(vha);
  458. if (rval) {
  459. ql_log(ql_log_fatal, vha, 0x004f,
  460. "Unable to validate FLASH data.\n");
  461. return (rval);
  462. }
  463. ha->isp_ops->get_flash_version(vha, req->ring);
  464. ql_log(ql_log_info, vha, 0x0061,
  465. "Configure NVRAM parameters...\n");
  466. ha->isp_ops->nvram_config(vha);
  467. if (ha->flags.disable_serdes) {
  468. /* Mask HBA via NVRAM settings? */
  469. ql_log(ql_log_info, vha, 0x0077,
  470. "Masking HBA WWPN "
  471. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  472. vha->port_name[0], vha->port_name[1],
  473. vha->port_name[2], vha->port_name[3],
  474. vha->port_name[4], vha->port_name[5],
  475. vha->port_name[6], vha->port_name[7]);
  476. return QLA_FUNCTION_FAILED;
  477. }
  478. ql_log(ql_log_info, vha, 0x0078,
  479. "Verifying loaded RISC code...\n");
  480. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  481. rval = ha->isp_ops->chip_diag(vha);
  482. if (rval)
  483. return (rval);
  484. rval = qla2x00_setup_chip(vha);
  485. if (rval)
  486. return (rval);
  487. }
  488. if (IS_QLA84XX(ha)) {
  489. ha->cs84xx = qla84xx_get_chip(vha);
  490. if (!ha->cs84xx) {
  491. ql_log(ql_log_warn, vha, 0x00d0,
  492. "Unable to configure ISP84XX.\n");
  493. return QLA_FUNCTION_FAILED;
  494. }
  495. }
  496. rval = qla2x00_init_rings(vha);
  497. ha->flags.chip_reset_done = 1;
  498. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  499. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  500. rval = qla84xx_init_chip(vha);
  501. if (rval != QLA_SUCCESS) {
  502. ql_log(ql_log_warn, vha, 0x00d4,
  503. "Unable to initialize ISP84XX.\n");
  504. qla84xx_put_chip(vha);
  505. }
  506. }
  507. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  508. qla24xx_read_fcp_prio_cfg(vha);
  509. return (rval);
  510. }
  511. /**
  512. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  513. * @ha: HA context
  514. *
  515. * Returns 0 on success.
  516. */
  517. int
  518. qla2100_pci_config(scsi_qla_host_t *vha)
  519. {
  520. uint16_t w;
  521. unsigned long flags;
  522. struct qla_hw_data *ha = vha->hw;
  523. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  524. pci_set_master(ha->pdev);
  525. pci_try_set_mwi(ha->pdev);
  526. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  527. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  528. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  529. pci_disable_rom(ha->pdev);
  530. /* Get PCI bus information. */
  531. spin_lock_irqsave(&ha->hardware_lock, flags);
  532. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  533. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  534. return QLA_SUCCESS;
  535. }
  536. /**
  537. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  538. * @ha: HA context
  539. *
  540. * Returns 0 on success.
  541. */
  542. int
  543. qla2300_pci_config(scsi_qla_host_t *vha)
  544. {
  545. uint16_t w;
  546. unsigned long flags = 0;
  547. uint32_t cnt;
  548. struct qla_hw_data *ha = vha->hw;
  549. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  550. pci_set_master(ha->pdev);
  551. pci_try_set_mwi(ha->pdev);
  552. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  553. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  554. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  555. w &= ~PCI_COMMAND_INTX_DISABLE;
  556. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  557. /*
  558. * If this is a 2300 card and not 2312, reset the
  559. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  560. * the 2310 also reports itself as a 2300 so we need to get the
  561. * fb revision level -- a 6 indicates it really is a 2300 and
  562. * not a 2310.
  563. */
  564. if (IS_QLA2300(ha)) {
  565. spin_lock_irqsave(&ha->hardware_lock, flags);
  566. /* Pause RISC. */
  567. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  568. for (cnt = 0; cnt < 30000; cnt++) {
  569. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  570. break;
  571. udelay(10);
  572. }
  573. /* Select FPM registers. */
  574. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  575. RD_REG_WORD(&reg->ctrl_status);
  576. /* Get the fb rev level */
  577. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  578. if (ha->fb_rev == FPM_2300)
  579. pci_clear_mwi(ha->pdev);
  580. /* Deselect FPM registers. */
  581. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  582. RD_REG_WORD(&reg->ctrl_status);
  583. /* Release RISC module. */
  584. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  585. for (cnt = 0; cnt < 30000; cnt++) {
  586. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  587. break;
  588. udelay(10);
  589. }
  590. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  591. }
  592. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  593. pci_disable_rom(ha->pdev);
  594. /* Get PCI bus information. */
  595. spin_lock_irqsave(&ha->hardware_lock, flags);
  596. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  597. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  598. return QLA_SUCCESS;
  599. }
  600. /**
  601. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  602. * @ha: HA context
  603. *
  604. * Returns 0 on success.
  605. */
  606. int
  607. qla24xx_pci_config(scsi_qla_host_t *vha)
  608. {
  609. uint16_t w;
  610. unsigned long flags = 0;
  611. struct qla_hw_data *ha = vha->hw;
  612. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  613. pci_set_master(ha->pdev);
  614. pci_try_set_mwi(ha->pdev);
  615. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  616. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  617. w &= ~PCI_COMMAND_INTX_DISABLE;
  618. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  619. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  620. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  621. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  622. pcix_set_mmrbc(ha->pdev, 2048);
  623. /* PCIe -- adjust Maximum Read Request Size (2048). */
  624. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  625. pcie_set_readrq(ha->pdev, 2048);
  626. pci_disable_rom(ha->pdev);
  627. ha->chip_revision = ha->pdev->revision;
  628. /* Get PCI bus information. */
  629. spin_lock_irqsave(&ha->hardware_lock, flags);
  630. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  631. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  632. return QLA_SUCCESS;
  633. }
  634. /**
  635. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  636. * @ha: HA context
  637. *
  638. * Returns 0 on success.
  639. */
  640. int
  641. qla25xx_pci_config(scsi_qla_host_t *vha)
  642. {
  643. uint16_t w;
  644. struct qla_hw_data *ha = vha->hw;
  645. pci_set_master(ha->pdev);
  646. pci_try_set_mwi(ha->pdev);
  647. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  648. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  649. w &= ~PCI_COMMAND_INTX_DISABLE;
  650. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  651. /* PCIe -- adjust Maximum Read Request Size (2048). */
  652. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  653. pcie_set_readrq(ha->pdev, 2048);
  654. pci_disable_rom(ha->pdev);
  655. ha->chip_revision = ha->pdev->revision;
  656. return QLA_SUCCESS;
  657. }
  658. /**
  659. * qla2x00_isp_firmware() - Choose firmware image.
  660. * @ha: HA context
  661. *
  662. * Returns 0 on success.
  663. */
  664. static int
  665. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  666. {
  667. int rval;
  668. uint16_t loop_id, topo, sw_cap;
  669. uint8_t domain, area, al_pa;
  670. struct qla_hw_data *ha = vha->hw;
  671. /* Assume loading risc code */
  672. rval = QLA_FUNCTION_FAILED;
  673. if (ha->flags.disable_risc_code_load) {
  674. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  675. /* Verify checksum of loaded RISC code. */
  676. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  677. if (rval == QLA_SUCCESS) {
  678. /* And, verify we are not in ROM code. */
  679. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  680. &area, &domain, &topo, &sw_cap);
  681. }
  682. }
  683. if (rval)
  684. ql_dbg(ql_dbg_init, vha, 0x007a,
  685. "**** Load RISC code ****.\n");
  686. return (rval);
  687. }
  688. /**
  689. * qla2x00_reset_chip() - Reset ISP chip.
  690. * @ha: HA context
  691. *
  692. * Returns 0 on success.
  693. */
  694. void
  695. qla2x00_reset_chip(scsi_qla_host_t *vha)
  696. {
  697. unsigned long flags = 0;
  698. struct qla_hw_data *ha = vha->hw;
  699. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  700. uint32_t cnt;
  701. uint16_t cmd;
  702. if (unlikely(pci_channel_offline(ha->pdev)))
  703. return;
  704. ha->isp_ops->disable_intrs(ha);
  705. spin_lock_irqsave(&ha->hardware_lock, flags);
  706. /* Turn off master enable */
  707. cmd = 0;
  708. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  709. cmd &= ~PCI_COMMAND_MASTER;
  710. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  711. if (!IS_QLA2100(ha)) {
  712. /* Pause RISC. */
  713. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  714. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  715. for (cnt = 0; cnt < 30000; cnt++) {
  716. if ((RD_REG_WORD(&reg->hccr) &
  717. HCCR_RISC_PAUSE) != 0)
  718. break;
  719. udelay(100);
  720. }
  721. } else {
  722. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  723. udelay(10);
  724. }
  725. /* Select FPM registers. */
  726. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  727. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  728. /* FPM Soft Reset. */
  729. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  730. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  731. /* Toggle Fpm Reset. */
  732. if (!IS_QLA2200(ha)) {
  733. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  734. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  735. }
  736. /* Select frame buffer registers. */
  737. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  738. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  739. /* Reset frame buffer FIFOs. */
  740. if (IS_QLA2200(ha)) {
  741. WRT_FB_CMD_REG(ha, reg, 0xa000);
  742. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  743. } else {
  744. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  745. /* Read back fb_cmd until zero or 3 seconds max */
  746. for (cnt = 0; cnt < 3000; cnt++) {
  747. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  748. break;
  749. udelay(100);
  750. }
  751. }
  752. /* Select RISC module registers. */
  753. WRT_REG_WORD(&reg->ctrl_status, 0);
  754. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  755. /* Reset RISC processor. */
  756. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  757. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  758. /* Release RISC processor. */
  759. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  760. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  761. }
  762. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  763. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  764. /* Reset ISP chip. */
  765. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  766. /* Wait for RISC to recover from reset. */
  767. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  768. /*
  769. * It is necessary to for a delay here since the card doesn't
  770. * respond to PCI reads during a reset. On some architectures
  771. * this will result in an MCA.
  772. */
  773. udelay(20);
  774. for (cnt = 30000; cnt; cnt--) {
  775. if ((RD_REG_WORD(&reg->ctrl_status) &
  776. CSR_ISP_SOFT_RESET) == 0)
  777. break;
  778. udelay(100);
  779. }
  780. } else
  781. udelay(10);
  782. /* Reset RISC processor. */
  783. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  784. WRT_REG_WORD(&reg->semaphore, 0);
  785. /* Release RISC processor. */
  786. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  787. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  788. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  789. for (cnt = 0; cnt < 30000; cnt++) {
  790. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  791. break;
  792. udelay(100);
  793. }
  794. } else
  795. udelay(100);
  796. /* Turn on master enable */
  797. cmd |= PCI_COMMAND_MASTER;
  798. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  799. /* Disable RISC pause on FPM parity error. */
  800. if (!IS_QLA2100(ha)) {
  801. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  802. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  803. }
  804. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  805. }
  806. /**
  807. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  808. *
  809. * Returns 0 on success.
  810. */
  811. int
  812. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  813. {
  814. uint16_t mb[4] = {0x1010, 0, 1, 0};
  815. return qla81xx_write_mpi_register(vha, mb);
  816. }
  817. /**
  818. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  819. * @ha: HA context
  820. *
  821. * Returns 0 on success.
  822. */
  823. static inline void
  824. qla24xx_reset_risc(scsi_qla_host_t *vha)
  825. {
  826. unsigned long flags = 0;
  827. struct qla_hw_data *ha = vha->hw;
  828. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  829. uint32_t cnt, d2;
  830. uint16_t wd;
  831. static int abts_cnt; /* ISP abort retry counts */
  832. spin_lock_irqsave(&ha->hardware_lock, flags);
  833. /* Reset RISC. */
  834. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  835. for (cnt = 0; cnt < 30000; cnt++) {
  836. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  837. break;
  838. udelay(10);
  839. }
  840. WRT_REG_DWORD(&reg->ctrl_status,
  841. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  842. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  843. udelay(100);
  844. /* Wait for firmware to complete NVRAM accesses. */
  845. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  846. for (cnt = 10000 ; cnt && d2; cnt--) {
  847. udelay(5);
  848. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  849. barrier();
  850. }
  851. /* Wait for soft-reset to complete. */
  852. d2 = RD_REG_DWORD(&reg->ctrl_status);
  853. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  854. udelay(5);
  855. d2 = RD_REG_DWORD(&reg->ctrl_status);
  856. barrier();
  857. }
  858. /* If required, do an MPI FW reset now */
  859. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  860. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  861. if (++abts_cnt < 5) {
  862. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  863. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  864. } else {
  865. /*
  866. * We exhausted the ISP abort retries. We have to
  867. * set the board offline.
  868. */
  869. abts_cnt = 0;
  870. vha->flags.online = 0;
  871. }
  872. }
  873. }
  874. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  875. RD_REG_DWORD(&reg->hccr);
  876. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  877. RD_REG_DWORD(&reg->hccr);
  878. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  879. RD_REG_DWORD(&reg->hccr);
  880. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  881. for (cnt = 6000000 ; cnt && d2; cnt--) {
  882. udelay(5);
  883. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  884. barrier();
  885. }
  886. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  887. if (IS_NOPOLLING_TYPE(ha))
  888. ha->isp_ops->enable_intrs(ha);
  889. }
  890. /**
  891. * qla24xx_reset_chip() - Reset ISP24xx chip.
  892. * @ha: HA context
  893. *
  894. * Returns 0 on success.
  895. */
  896. void
  897. qla24xx_reset_chip(scsi_qla_host_t *vha)
  898. {
  899. struct qla_hw_data *ha = vha->hw;
  900. if (pci_channel_offline(ha->pdev) &&
  901. ha->flags.pci_channel_io_perm_failure) {
  902. return;
  903. }
  904. ha->isp_ops->disable_intrs(ha);
  905. /* Perform RISC reset. */
  906. qla24xx_reset_risc(vha);
  907. }
  908. /**
  909. * qla2x00_chip_diag() - Test chip for proper operation.
  910. * @ha: HA context
  911. *
  912. * Returns 0 on success.
  913. */
  914. int
  915. qla2x00_chip_diag(scsi_qla_host_t *vha)
  916. {
  917. int rval;
  918. struct qla_hw_data *ha = vha->hw;
  919. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  920. unsigned long flags = 0;
  921. uint16_t data;
  922. uint32_t cnt;
  923. uint16_t mb[5];
  924. struct req_que *req = ha->req_q_map[0];
  925. /* Assume a failed state */
  926. rval = QLA_FUNCTION_FAILED;
  927. ql_dbg(ql_dbg_init, vha, 0x007b,
  928. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  929. spin_lock_irqsave(&ha->hardware_lock, flags);
  930. /* Reset ISP chip. */
  931. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  932. /*
  933. * We need to have a delay here since the card will not respond while
  934. * in reset causing an MCA on some architectures.
  935. */
  936. udelay(20);
  937. data = qla2x00_debounce_register(&reg->ctrl_status);
  938. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  939. udelay(5);
  940. data = RD_REG_WORD(&reg->ctrl_status);
  941. barrier();
  942. }
  943. if (!cnt)
  944. goto chip_diag_failed;
  945. ql_dbg(ql_dbg_init, vha, 0x007c,
  946. "Reset register cleared by chip reset.\n");
  947. /* Reset RISC processor. */
  948. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  949. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  950. /* Workaround for QLA2312 PCI parity error */
  951. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  952. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  953. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  954. udelay(5);
  955. data = RD_MAILBOX_REG(ha, reg, 0);
  956. barrier();
  957. }
  958. } else
  959. udelay(10);
  960. if (!cnt)
  961. goto chip_diag_failed;
  962. /* Check product ID of chip */
  963. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  964. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  965. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  966. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  967. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  968. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  969. mb[3] != PROD_ID_3) {
  970. ql_log(ql_log_warn, vha, 0x0062,
  971. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  972. mb[1], mb[2], mb[3]);
  973. goto chip_diag_failed;
  974. }
  975. ha->product_id[0] = mb[1];
  976. ha->product_id[1] = mb[2];
  977. ha->product_id[2] = mb[3];
  978. ha->product_id[3] = mb[4];
  979. /* Adjust fw RISC transfer size */
  980. if (req->length > 1024)
  981. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  982. else
  983. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  984. req->length;
  985. if (IS_QLA2200(ha) &&
  986. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  987. /* Limit firmware transfer size with a 2200A */
  988. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  989. ha->device_type |= DT_ISP2200A;
  990. ha->fw_transfer_size = 128;
  991. }
  992. /* Wrap Incoming Mailboxes Test. */
  993. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  994. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  995. rval = qla2x00_mbx_reg_test(vha);
  996. if (rval)
  997. ql_log(ql_log_warn, vha, 0x0080,
  998. "Failed mailbox send register test.\n");
  999. else
  1000. /* Flag a successful rval */
  1001. rval = QLA_SUCCESS;
  1002. spin_lock_irqsave(&ha->hardware_lock, flags);
  1003. chip_diag_failed:
  1004. if (rval)
  1005. ql_log(ql_log_info, vha, 0x0081,
  1006. "Chip diagnostics **** FAILED ****.\n");
  1007. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1008. return (rval);
  1009. }
  1010. /**
  1011. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  1012. * @ha: HA context
  1013. *
  1014. * Returns 0 on success.
  1015. */
  1016. int
  1017. qla24xx_chip_diag(scsi_qla_host_t *vha)
  1018. {
  1019. int rval;
  1020. struct qla_hw_data *ha = vha->hw;
  1021. struct req_que *req = ha->req_q_map[0];
  1022. if (IS_QLA82XX(ha))
  1023. return QLA_SUCCESS;
  1024. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  1025. rval = qla2x00_mbx_reg_test(vha);
  1026. if (rval) {
  1027. ql_log(ql_log_warn, vha, 0x0082,
  1028. "Failed mailbox send register test.\n");
  1029. } else {
  1030. /* Flag a successful rval */
  1031. rval = QLA_SUCCESS;
  1032. }
  1033. return rval;
  1034. }
  1035. void
  1036. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  1037. {
  1038. int rval;
  1039. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  1040. eft_size, fce_size, mq_size;
  1041. dma_addr_t tc_dma;
  1042. void *tc;
  1043. struct qla_hw_data *ha = vha->hw;
  1044. struct req_que *req = ha->req_q_map[0];
  1045. struct rsp_que *rsp = ha->rsp_q_map[0];
  1046. if (ha->fw_dump) {
  1047. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1048. "Firmware dump already allocated.\n");
  1049. return;
  1050. }
  1051. ha->fw_dumped = 0;
  1052. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1053. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1054. fixed_size = sizeof(struct qla2100_fw_dump);
  1055. } else if (IS_QLA23XX(ha)) {
  1056. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1057. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1058. sizeof(uint16_t);
  1059. } else if (IS_FWI2_CAPABLE(ha)) {
  1060. if (IS_QLA81XX(ha))
  1061. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1062. else if (IS_QLA25XX(ha))
  1063. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1064. else
  1065. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1066. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1067. sizeof(uint32_t);
  1068. if (ha->mqenable)
  1069. mq_size = sizeof(struct qla2xxx_mq_chain);
  1070. /* Allocate memory for Fibre Channel Event Buffer. */
  1071. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
  1072. goto try_eft;
  1073. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1074. GFP_KERNEL);
  1075. if (!tc) {
  1076. ql_log(ql_log_warn, vha, 0x00be,
  1077. "Unable to allocate (%d KB) for FCE.\n",
  1078. FCE_SIZE / 1024);
  1079. goto try_eft;
  1080. }
  1081. memset(tc, 0, FCE_SIZE);
  1082. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1083. ha->fce_mb, &ha->fce_bufs);
  1084. if (rval) {
  1085. ql_log(ql_log_warn, vha, 0x00bf,
  1086. "Unable to initialize FCE (%d).\n", rval);
  1087. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1088. tc_dma);
  1089. ha->flags.fce_enabled = 0;
  1090. goto try_eft;
  1091. }
  1092. ql_log(ql_log_info, vha, 0x00c0,
  1093. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1094. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1095. ha->flags.fce_enabled = 1;
  1096. ha->fce_dma = tc_dma;
  1097. ha->fce = tc;
  1098. try_eft:
  1099. /* Allocate memory for Extended Trace Buffer. */
  1100. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1101. GFP_KERNEL);
  1102. if (!tc) {
  1103. ql_log(ql_log_warn, vha, 0x00c1,
  1104. "Unable to allocate (%d KB) for EFT.\n",
  1105. EFT_SIZE / 1024);
  1106. goto cont_alloc;
  1107. }
  1108. memset(tc, 0, EFT_SIZE);
  1109. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1110. if (rval) {
  1111. ql_log(ql_log_warn, vha, 0x00c2,
  1112. "Unable to initialize EFT (%d).\n", rval);
  1113. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1114. tc_dma);
  1115. goto cont_alloc;
  1116. }
  1117. ql_log(ql_log_info, vha, 0x00c3,
  1118. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1119. eft_size = EFT_SIZE;
  1120. ha->eft_dma = tc_dma;
  1121. ha->eft = tc;
  1122. }
  1123. cont_alloc:
  1124. req_q_size = req->length * sizeof(request_t);
  1125. rsp_q_size = rsp->length * sizeof(response_t);
  1126. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1127. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1128. ha->chain_offset = dump_size;
  1129. dump_size += mq_size + fce_size;
  1130. ha->fw_dump = vmalloc(dump_size);
  1131. if (!ha->fw_dump) {
  1132. ql_log(ql_log_warn, vha, 0x00c4,
  1133. "Unable to allocate (%d KB) for firmware dump.\n",
  1134. dump_size / 1024);
  1135. if (ha->fce) {
  1136. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1137. ha->fce_dma);
  1138. ha->fce = NULL;
  1139. ha->fce_dma = 0;
  1140. }
  1141. if (ha->eft) {
  1142. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1143. ha->eft_dma);
  1144. ha->eft = NULL;
  1145. ha->eft_dma = 0;
  1146. }
  1147. return;
  1148. }
  1149. ql_log(ql_log_info, vha, 0x00c5,
  1150. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1151. ha->fw_dump_len = dump_size;
  1152. ha->fw_dump->signature[0] = 'Q';
  1153. ha->fw_dump->signature[1] = 'L';
  1154. ha->fw_dump->signature[2] = 'G';
  1155. ha->fw_dump->signature[3] = 'C';
  1156. ha->fw_dump->version = __constant_htonl(1);
  1157. ha->fw_dump->fixed_size = htonl(fixed_size);
  1158. ha->fw_dump->mem_size = htonl(mem_size);
  1159. ha->fw_dump->req_q_size = htonl(req_q_size);
  1160. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1161. ha->fw_dump->eft_size = htonl(eft_size);
  1162. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1163. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1164. ha->fw_dump->header_size =
  1165. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1166. }
  1167. static int
  1168. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1169. {
  1170. #define MPS_MASK 0xe0
  1171. int rval;
  1172. uint16_t dc;
  1173. uint32_t dw;
  1174. if (!IS_QLA81XX(vha->hw))
  1175. return QLA_SUCCESS;
  1176. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1177. if (rval != QLA_SUCCESS) {
  1178. ql_log(ql_log_warn, vha, 0x0105,
  1179. "Unable to acquire semaphore.\n");
  1180. goto done;
  1181. }
  1182. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1183. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1184. if (rval != QLA_SUCCESS) {
  1185. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1186. goto done_release;
  1187. }
  1188. dc &= MPS_MASK;
  1189. if (dc == (dw & MPS_MASK))
  1190. goto done_release;
  1191. dw &= ~MPS_MASK;
  1192. dw |= dc;
  1193. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1194. if (rval != QLA_SUCCESS) {
  1195. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1196. }
  1197. done_release:
  1198. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1199. if (rval != QLA_SUCCESS) {
  1200. ql_log(ql_log_warn, vha, 0x006d,
  1201. "Unable to release semaphore.\n");
  1202. }
  1203. done:
  1204. return rval;
  1205. }
  1206. /**
  1207. * qla2x00_setup_chip() - Load and start RISC firmware.
  1208. * @ha: HA context
  1209. *
  1210. * Returns 0 on success.
  1211. */
  1212. static int
  1213. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1214. {
  1215. int rval;
  1216. uint32_t srisc_address = 0;
  1217. struct qla_hw_data *ha = vha->hw;
  1218. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1219. unsigned long flags;
  1220. uint16_t fw_major_version;
  1221. if (IS_QLA82XX(ha)) {
  1222. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1223. if (rval == QLA_SUCCESS) {
  1224. qla2x00_stop_firmware(vha);
  1225. goto enable_82xx_npiv;
  1226. } else
  1227. goto failed;
  1228. }
  1229. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1230. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1231. spin_lock_irqsave(&ha->hardware_lock, flags);
  1232. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1233. RD_REG_WORD(&reg->hccr);
  1234. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1235. }
  1236. qla81xx_mpi_sync(vha);
  1237. /* Load firmware sequences */
  1238. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1239. if (rval == QLA_SUCCESS) {
  1240. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1241. "Verifying Checksum of loaded RISC code.\n");
  1242. rval = qla2x00_verify_checksum(vha, srisc_address);
  1243. if (rval == QLA_SUCCESS) {
  1244. /* Start firmware execution. */
  1245. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1246. "Starting firmware.\n");
  1247. rval = qla2x00_execute_fw(vha, srisc_address);
  1248. /* Retrieve firmware information. */
  1249. if (rval == QLA_SUCCESS) {
  1250. enable_82xx_npiv:
  1251. fw_major_version = ha->fw_major_version;
  1252. rval = qla2x00_get_fw_version(vha,
  1253. &ha->fw_major_version,
  1254. &ha->fw_minor_version,
  1255. &ha->fw_subminor_version,
  1256. &ha->fw_attributes, &ha->fw_memory_size,
  1257. ha->mpi_version, &ha->mpi_capabilities,
  1258. ha->phy_version);
  1259. if (rval != QLA_SUCCESS)
  1260. goto failed;
  1261. ha->flags.npiv_supported = 0;
  1262. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1263. (ha->fw_attributes & BIT_2)) {
  1264. ha->flags.npiv_supported = 1;
  1265. if ((!ha->max_npiv_vports) ||
  1266. ((ha->max_npiv_vports + 1) %
  1267. MIN_MULTI_ID_FABRIC))
  1268. ha->max_npiv_vports =
  1269. MIN_MULTI_ID_FABRIC - 1;
  1270. }
  1271. qla2x00_get_resource_cnts(vha, NULL,
  1272. &ha->fw_xcb_count, NULL, NULL,
  1273. &ha->max_npiv_vports, NULL);
  1274. if (!fw_major_version && ql2xallocfwdump)
  1275. qla2x00_alloc_fw_dump(vha);
  1276. }
  1277. } else {
  1278. ql_log(ql_log_fatal, vha, 0x00cd,
  1279. "ISP Firmware failed checksum.\n");
  1280. goto failed;
  1281. }
  1282. }
  1283. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1284. /* Enable proper parity. */
  1285. spin_lock_irqsave(&ha->hardware_lock, flags);
  1286. if (IS_QLA2300(ha))
  1287. /* SRAM parity */
  1288. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1289. else
  1290. /* SRAM, Instruction RAM and GP RAM parity */
  1291. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1292. RD_REG_WORD(&reg->hccr);
  1293. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1294. }
  1295. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1296. uint32_t size;
  1297. rval = qla81xx_fac_get_sector_size(vha, &size);
  1298. if (rval == QLA_SUCCESS) {
  1299. ha->flags.fac_supported = 1;
  1300. ha->fdt_block_size = size << 2;
  1301. } else {
  1302. ql_log(ql_log_warn, vha, 0x00ce,
  1303. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1304. ha->fw_major_version, ha->fw_minor_version,
  1305. ha->fw_subminor_version);
  1306. }
  1307. }
  1308. failed:
  1309. if (rval) {
  1310. ql_log(ql_log_fatal, vha, 0x00cf,
  1311. "Setup chip ****FAILED****.\n");
  1312. }
  1313. return (rval);
  1314. }
  1315. /**
  1316. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1317. * @ha: HA context
  1318. *
  1319. * Beginning of request ring has initialization control block already built
  1320. * by nvram config routine.
  1321. *
  1322. * Returns 0 on success.
  1323. */
  1324. void
  1325. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1326. {
  1327. uint16_t cnt;
  1328. response_t *pkt;
  1329. rsp->ring_ptr = rsp->ring;
  1330. rsp->ring_index = 0;
  1331. rsp->status_srb = NULL;
  1332. pkt = rsp->ring_ptr;
  1333. for (cnt = 0; cnt < rsp->length; cnt++) {
  1334. pkt->signature = RESPONSE_PROCESSED;
  1335. pkt++;
  1336. }
  1337. }
  1338. /**
  1339. * qla2x00_update_fw_options() - Read and process firmware options.
  1340. * @ha: HA context
  1341. *
  1342. * Returns 0 on success.
  1343. */
  1344. void
  1345. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1346. {
  1347. uint16_t swing, emphasis, tx_sens, rx_sens;
  1348. struct qla_hw_data *ha = vha->hw;
  1349. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1350. qla2x00_get_fw_options(vha, ha->fw_options);
  1351. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1352. return;
  1353. /* Serial Link options. */
  1354. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1355. "Serial link options.\n");
  1356. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1357. (uint8_t *)&ha->fw_seriallink_options,
  1358. sizeof(ha->fw_seriallink_options));
  1359. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1360. if (ha->fw_seriallink_options[3] & BIT_2) {
  1361. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1362. /* 1G settings */
  1363. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1364. emphasis = (ha->fw_seriallink_options[2] &
  1365. (BIT_4 | BIT_3)) >> 3;
  1366. tx_sens = ha->fw_seriallink_options[0] &
  1367. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1368. rx_sens = (ha->fw_seriallink_options[0] &
  1369. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1370. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1371. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1372. if (rx_sens == 0x0)
  1373. rx_sens = 0x3;
  1374. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1375. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1376. ha->fw_options[10] |= BIT_5 |
  1377. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1378. (tx_sens & (BIT_1 | BIT_0));
  1379. /* 2G settings */
  1380. swing = (ha->fw_seriallink_options[2] &
  1381. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1382. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1383. tx_sens = ha->fw_seriallink_options[1] &
  1384. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1385. rx_sens = (ha->fw_seriallink_options[1] &
  1386. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1387. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1388. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1389. if (rx_sens == 0x0)
  1390. rx_sens = 0x3;
  1391. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1392. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1393. ha->fw_options[11] |= BIT_5 |
  1394. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1395. (tx_sens & (BIT_1 | BIT_0));
  1396. }
  1397. /* FCP2 options. */
  1398. /* Return command IOCBs without waiting for an ABTS to complete. */
  1399. ha->fw_options[3] |= BIT_13;
  1400. /* LED scheme. */
  1401. if (ha->flags.enable_led_scheme)
  1402. ha->fw_options[2] |= BIT_12;
  1403. /* Detect ISP6312. */
  1404. if (IS_QLA6312(ha))
  1405. ha->fw_options[2] |= BIT_13;
  1406. /* Update firmware options. */
  1407. qla2x00_set_fw_options(vha, ha->fw_options);
  1408. }
  1409. void
  1410. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1411. {
  1412. int rval;
  1413. struct qla_hw_data *ha = vha->hw;
  1414. if (IS_QLA82XX(ha))
  1415. return;
  1416. /* Update Serial Link options. */
  1417. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1418. return;
  1419. rval = qla2x00_set_serdes_params(vha,
  1420. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1421. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1422. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1423. if (rval != QLA_SUCCESS) {
  1424. ql_log(ql_log_warn, vha, 0x0104,
  1425. "Unable to update Serial Link options (%x).\n", rval);
  1426. }
  1427. }
  1428. void
  1429. qla2x00_config_rings(struct scsi_qla_host *vha)
  1430. {
  1431. struct qla_hw_data *ha = vha->hw;
  1432. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1433. struct req_que *req = ha->req_q_map[0];
  1434. struct rsp_que *rsp = ha->rsp_q_map[0];
  1435. /* Setup ring parameters in initialization control block. */
  1436. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1437. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1438. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1439. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1440. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1441. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1442. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1443. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1444. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1445. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1446. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1447. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1448. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1449. }
  1450. void
  1451. qla24xx_config_rings(struct scsi_qla_host *vha)
  1452. {
  1453. struct qla_hw_data *ha = vha->hw;
  1454. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1455. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1456. struct qla_msix_entry *msix;
  1457. struct init_cb_24xx *icb;
  1458. uint16_t rid = 0;
  1459. struct req_que *req = ha->req_q_map[0];
  1460. struct rsp_que *rsp = ha->rsp_q_map[0];
  1461. /* Setup ring parameters in initialization control block. */
  1462. icb = (struct init_cb_24xx *)ha->init_cb;
  1463. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1464. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1465. icb->request_q_length = cpu_to_le16(req->length);
  1466. icb->response_q_length = cpu_to_le16(rsp->length);
  1467. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1468. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1469. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1470. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1471. if (ha->mqenable) {
  1472. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1473. icb->rid = __constant_cpu_to_le16(rid);
  1474. if (ha->flags.msix_enabled) {
  1475. msix = &ha->msix_entries[1];
  1476. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1477. "Registering vector 0x%x for base que.\n",
  1478. msix->entry);
  1479. icb->msix = cpu_to_le16(msix->entry);
  1480. }
  1481. /* Use alternate PCI bus number */
  1482. if (MSB(rid))
  1483. icb->firmware_options_2 |=
  1484. __constant_cpu_to_le32(BIT_19);
  1485. /* Use alternate PCI devfn */
  1486. if (LSB(rid))
  1487. icb->firmware_options_2 |=
  1488. __constant_cpu_to_le32(BIT_18);
  1489. /* Use Disable MSIX Handshake mode for capable adapters */
  1490. if (IS_MSIX_NACK_CAPABLE(ha)) {
  1491. icb->firmware_options_2 &=
  1492. __constant_cpu_to_le32(~BIT_22);
  1493. ha->flags.disable_msix_handshake = 1;
  1494. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1495. "MSIX Handshake Disable Mode turned on.\n");
  1496. } else {
  1497. icb->firmware_options_2 |=
  1498. __constant_cpu_to_le32(BIT_22);
  1499. }
  1500. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1501. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1502. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1503. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1504. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1505. } else {
  1506. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1507. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1508. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1509. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1510. }
  1511. /* PCI posting */
  1512. RD_REG_DWORD(&ioreg->hccr);
  1513. }
  1514. /**
  1515. * qla2x00_init_rings() - Initializes firmware.
  1516. * @ha: HA context
  1517. *
  1518. * Beginning of request ring has initialization control block already built
  1519. * by nvram config routine.
  1520. *
  1521. * Returns 0 on success.
  1522. */
  1523. static int
  1524. qla2x00_init_rings(scsi_qla_host_t *vha)
  1525. {
  1526. int rval;
  1527. unsigned long flags = 0;
  1528. int cnt, que;
  1529. struct qla_hw_data *ha = vha->hw;
  1530. struct req_que *req;
  1531. struct rsp_que *rsp;
  1532. struct scsi_qla_host *vp;
  1533. struct mid_init_cb_24xx *mid_init_cb =
  1534. (struct mid_init_cb_24xx *) ha->init_cb;
  1535. spin_lock_irqsave(&ha->hardware_lock, flags);
  1536. /* Clear outstanding commands array. */
  1537. for (que = 0; que < ha->max_req_queues; que++) {
  1538. req = ha->req_q_map[que];
  1539. if (!req)
  1540. continue;
  1541. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1542. req->outstanding_cmds[cnt] = NULL;
  1543. req->current_outstanding_cmd = 1;
  1544. /* Initialize firmware. */
  1545. req->ring_ptr = req->ring;
  1546. req->ring_index = 0;
  1547. req->cnt = req->length;
  1548. }
  1549. for (que = 0; que < ha->max_rsp_queues; que++) {
  1550. rsp = ha->rsp_q_map[que];
  1551. if (!rsp)
  1552. continue;
  1553. /* Initialize response queue entries */
  1554. qla2x00_init_response_q_entries(rsp);
  1555. }
  1556. spin_lock(&ha->vport_slock);
  1557. /* Clear RSCN queue. */
  1558. list_for_each_entry(vp, &ha->vp_list, list) {
  1559. vp->rscn_in_ptr = 0;
  1560. vp->rscn_out_ptr = 0;
  1561. }
  1562. spin_unlock(&ha->vport_slock);
  1563. ha->isp_ops->config_rings(vha);
  1564. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1565. /* Update any ISP specific firmware options before initialization. */
  1566. ha->isp_ops->update_fw_options(vha);
  1567. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1568. if (ha->flags.npiv_supported) {
  1569. if (ha->operating_mode == LOOP)
  1570. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1571. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1572. }
  1573. if (IS_FWI2_CAPABLE(ha)) {
  1574. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1575. mid_init_cb->init_cb.execution_throttle =
  1576. cpu_to_le16(ha->fw_xcb_count);
  1577. }
  1578. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1579. if (rval) {
  1580. ql_log(ql_log_fatal, vha, 0x00d2,
  1581. "Init Firmware **** FAILED ****.\n");
  1582. } else {
  1583. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1584. "Init Firmware -- success.\n");
  1585. }
  1586. return (rval);
  1587. }
  1588. /**
  1589. * qla2x00_fw_ready() - Waits for firmware ready.
  1590. * @ha: HA context
  1591. *
  1592. * Returns 0 on success.
  1593. */
  1594. static int
  1595. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1596. {
  1597. int rval;
  1598. unsigned long wtime, mtime, cs84xx_time;
  1599. uint16_t min_wait; /* Minimum wait time if loop is down */
  1600. uint16_t wait_time; /* Wait time if loop is coming ready */
  1601. uint16_t state[5];
  1602. struct qla_hw_data *ha = vha->hw;
  1603. rval = QLA_SUCCESS;
  1604. /* 20 seconds for loop down. */
  1605. min_wait = 20;
  1606. /*
  1607. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1608. * our own processing.
  1609. */
  1610. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1611. wait_time = min_wait;
  1612. }
  1613. /* Min wait time if loop down */
  1614. mtime = jiffies + (min_wait * HZ);
  1615. /* wait time before firmware ready */
  1616. wtime = jiffies + (wait_time * HZ);
  1617. /* Wait for ISP to finish LIP */
  1618. if (!vha->flags.init_done)
  1619. ql_log(ql_log_info, vha, 0x801e,
  1620. "Waiting for LIP to complete.\n");
  1621. do {
  1622. rval = qla2x00_get_firmware_state(vha, state);
  1623. if (rval == QLA_SUCCESS) {
  1624. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1625. vha->device_flags &= ~DFLG_NO_CABLE;
  1626. }
  1627. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1628. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1629. "fw_state=%x 84xx=%x.\n", state[0],
  1630. state[2]);
  1631. if ((state[2] & FSTATE_LOGGED_IN) &&
  1632. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1633. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1634. "Sending verify iocb.\n");
  1635. cs84xx_time = jiffies;
  1636. rval = qla84xx_init_chip(vha);
  1637. if (rval != QLA_SUCCESS) {
  1638. ql_log(ql_log_warn,
  1639. vha, 0x8026,
  1640. "Init chip failed.\n");
  1641. break;
  1642. }
  1643. /* Add time taken to initialize. */
  1644. cs84xx_time = jiffies - cs84xx_time;
  1645. wtime += cs84xx_time;
  1646. mtime += cs84xx_time;
  1647. ql_dbg(ql_dbg_taskm, vha, 0x8025,
  1648. "Increasing wait time by %ld. "
  1649. "New time %ld.\n", cs84xx_time,
  1650. wtime);
  1651. }
  1652. } else if (state[0] == FSTATE_READY) {
  1653. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1654. "F/W Ready - OK.\n");
  1655. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1656. &ha->login_timeout, &ha->r_a_tov);
  1657. rval = QLA_SUCCESS;
  1658. break;
  1659. }
  1660. rval = QLA_FUNCTION_FAILED;
  1661. if (atomic_read(&vha->loop_down_timer) &&
  1662. state[0] != FSTATE_READY) {
  1663. /* Loop down. Timeout on min_wait for states
  1664. * other than Wait for Login.
  1665. */
  1666. if (time_after_eq(jiffies, mtime)) {
  1667. ql_log(ql_log_info, vha, 0x8038,
  1668. "Cable is unplugged...\n");
  1669. vha->device_flags |= DFLG_NO_CABLE;
  1670. break;
  1671. }
  1672. }
  1673. } else {
  1674. /* Mailbox cmd failed. Timeout on min_wait. */
  1675. if (time_after_eq(jiffies, mtime) ||
  1676. ha->flags.isp82xx_fw_hung)
  1677. break;
  1678. }
  1679. if (time_after_eq(jiffies, wtime))
  1680. break;
  1681. /* Delay for a while */
  1682. msleep(500);
  1683. ql_dbg(ql_dbg_taskm, vha, 0x8039,
  1684. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  1685. } while (1);
  1686. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1687. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1688. state[1], state[2], state[3], state[4], jiffies);
  1689. if (rval) {
  1690. ql_log(ql_log_warn, vha, 0x803b,
  1691. "Firmware ready **** FAILED ****.\n");
  1692. }
  1693. return (rval);
  1694. }
  1695. /*
  1696. * qla2x00_configure_hba
  1697. * Setup adapter context.
  1698. *
  1699. * Input:
  1700. * ha = adapter state pointer.
  1701. *
  1702. * Returns:
  1703. * 0 = success
  1704. *
  1705. * Context:
  1706. * Kernel context.
  1707. */
  1708. static int
  1709. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1710. {
  1711. int rval;
  1712. uint16_t loop_id;
  1713. uint16_t topo;
  1714. uint16_t sw_cap;
  1715. uint8_t al_pa;
  1716. uint8_t area;
  1717. uint8_t domain;
  1718. char connect_type[22];
  1719. struct qla_hw_data *ha = vha->hw;
  1720. /* Get host addresses. */
  1721. rval = qla2x00_get_adapter_id(vha,
  1722. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1723. if (rval != QLA_SUCCESS) {
  1724. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1725. IS_QLA8XXX_TYPE(ha) ||
  1726. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1727. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1728. "Loop is in a transition state.\n");
  1729. } else {
  1730. ql_log(ql_log_warn, vha, 0x2009,
  1731. "Unable to get host loop ID.\n");
  1732. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1733. }
  1734. return (rval);
  1735. }
  1736. if (topo == 4) {
  1737. ql_log(ql_log_info, vha, 0x200a,
  1738. "Cannot get topology - retrying.\n");
  1739. return (QLA_FUNCTION_FAILED);
  1740. }
  1741. vha->loop_id = loop_id;
  1742. /* initialize */
  1743. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1744. ha->operating_mode = LOOP;
  1745. ha->switch_cap = 0;
  1746. switch (topo) {
  1747. case 0:
  1748. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1749. ha->current_topology = ISP_CFG_NL;
  1750. strcpy(connect_type, "(Loop)");
  1751. break;
  1752. case 1:
  1753. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1754. ha->switch_cap = sw_cap;
  1755. ha->current_topology = ISP_CFG_FL;
  1756. strcpy(connect_type, "(FL_Port)");
  1757. break;
  1758. case 2:
  1759. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1760. ha->operating_mode = P2P;
  1761. ha->current_topology = ISP_CFG_N;
  1762. strcpy(connect_type, "(N_Port-to-N_Port)");
  1763. break;
  1764. case 3:
  1765. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1766. ha->switch_cap = sw_cap;
  1767. ha->operating_mode = P2P;
  1768. ha->current_topology = ISP_CFG_F;
  1769. strcpy(connect_type, "(F_Port)");
  1770. break;
  1771. default:
  1772. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1773. "HBA in unknown topology %x, using NL.\n", topo);
  1774. ha->current_topology = ISP_CFG_NL;
  1775. strcpy(connect_type, "(Loop)");
  1776. break;
  1777. }
  1778. /* Save Host port and loop ID. */
  1779. /* byte order - Big Endian */
  1780. vha->d_id.b.domain = domain;
  1781. vha->d_id.b.area = area;
  1782. vha->d_id.b.al_pa = al_pa;
  1783. if (!vha->flags.init_done)
  1784. ql_log(ql_log_info, vha, 0x2010,
  1785. "Topology - %s, Host Loop address 0x%x.\n",
  1786. connect_type, vha->loop_id);
  1787. if (rval) {
  1788. ql_log(ql_log_warn, vha, 0x2011,
  1789. "%s FAILED\n", __func__);
  1790. } else {
  1791. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1792. "%s success\n", __func__);
  1793. }
  1794. return(rval);
  1795. }
  1796. inline void
  1797. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1798. char *def)
  1799. {
  1800. char *st, *en;
  1801. uint16_t index;
  1802. struct qla_hw_data *ha = vha->hw;
  1803. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1804. !IS_QLA8XXX_TYPE(ha);
  1805. if (memcmp(model, BINZERO, len) != 0) {
  1806. strncpy(ha->model_number, model, len);
  1807. st = en = ha->model_number;
  1808. en += len - 1;
  1809. while (en > st) {
  1810. if (*en != 0x20 && *en != 0x00)
  1811. break;
  1812. *en-- = '\0';
  1813. }
  1814. index = (ha->pdev->subsystem_device & 0xff);
  1815. if (use_tbl &&
  1816. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1817. index < QLA_MODEL_NAMES)
  1818. strncpy(ha->model_desc,
  1819. qla2x00_model_name[index * 2 + 1],
  1820. sizeof(ha->model_desc) - 1);
  1821. } else {
  1822. index = (ha->pdev->subsystem_device & 0xff);
  1823. if (use_tbl &&
  1824. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1825. index < QLA_MODEL_NAMES) {
  1826. strcpy(ha->model_number,
  1827. qla2x00_model_name[index * 2]);
  1828. strncpy(ha->model_desc,
  1829. qla2x00_model_name[index * 2 + 1],
  1830. sizeof(ha->model_desc) - 1);
  1831. } else {
  1832. strcpy(ha->model_number, def);
  1833. }
  1834. }
  1835. if (IS_FWI2_CAPABLE(ha))
  1836. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1837. sizeof(ha->model_desc));
  1838. }
  1839. /* On sparc systems, obtain port and node WWN from firmware
  1840. * properties.
  1841. */
  1842. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1843. {
  1844. #ifdef CONFIG_SPARC
  1845. struct qla_hw_data *ha = vha->hw;
  1846. struct pci_dev *pdev = ha->pdev;
  1847. struct device_node *dp = pci_device_to_OF_node(pdev);
  1848. const u8 *val;
  1849. int len;
  1850. val = of_get_property(dp, "port-wwn", &len);
  1851. if (val && len >= WWN_SIZE)
  1852. memcpy(nv->port_name, val, WWN_SIZE);
  1853. val = of_get_property(dp, "node-wwn", &len);
  1854. if (val && len >= WWN_SIZE)
  1855. memcpy(nv->node_name, val, WWN_SIZE);
  1856. #endif
  1857. }
  1858. /*
  1859. * NVRAM configuration for ISP 2xxx
  1860. *
  1861. * Input:
  1862. * ha = adapter block pointer.
  1863. *
  1864. * Output:
  1865. * initialization control block in response_ring
  1866. * host adapters parameters in host adapter block
  1867. *
  1868. * Returns:
  1869. * 0 = success.
  1870. */
  1871. int
  1872. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1873. {
  1874. int rval;
  1875. uint8_t chksum = 0;
  1876. uint16_t cnt;
  1877. uint8_t *dptr1, *dptr2;
  1878. struct qla_hw_data *ha = vha->hw;
  1879. init_cb_t *icb = ha->init_cb;
  1880. nvram_t *nv = ha->nvram;
  1881. uint8_t *ptr = ha->nvram;
  1882. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1883. rval = QLA_SUCCESS;
  1884. /* Determine NVRAM starting address. */
  1885. ha->nvram_size = sizeof(nvram_t);
  1886. ha->nvram_base = 0;
  1887. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1888. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1889. ha->nvram_base = 0x80;
  1890. /* Get NVRAM data and calculate checksum. */
  1891. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1892. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1893. chksum += *ptr++;
  1894. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1895. "Contents of NVRAM.\n");
  1896. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1897. (uint8_t *)nv, ha->nvram_size);
  1898. /* Bad NVRAM data, set defaults parameters. */
  1899. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1900. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1901. /* Reset NVRAM data. */
  1902. ql_log(ql_log_warn, vha, 0x0064,
  1903. "Inconisistent NVRAM "
  1904. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1905. chksum, nv->id[0], nv->nvram_version);
  1906. ql_log(ql_log_warn, vha, 0x0065,
  1907. "Falling back to "
  1908. "functioning (yet invalid -- WWPN) defaults.\n");
  1909. /*
  1910. * Set default initialization control block.
  1911. */
  1912. memset(nv, 0, ha->nvram_size);
  1913. nv->parameter_block_version = ICB_VERSION;
  1914. if (IS_QLA23XX(ha)) {
  1915. nv->firmware_options[0] = BIT_2 | BIT_1;
  1916. nv->firmware_options[1] = BIT_7 | BIT_5;
  1917. nv->add_firmware_options[0] = BIT_5;
  1918. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1919. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1920. nv->special_options[1] = BIT_7;
  1921. } else if (IS_QLA2200(ha)) {
  1922. nv->firmware_options[0] = BIT_2 | BIT_1;
  1923. nv->firmware_options[1] = BIT_7 | BIT_5;
  1924. nv->add_firmware_options[0] = BIT_5;
  1925. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1926. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1927. } else if (IS_QLA2100(ha)) {
  1928. nv->firmware_options[0] = BIT_3 | BIT_1;
  1929. nv->firmware_options[1] = BIT_5;
  1930. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1931. }
  1932. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1933. nv->execution_throttle = __constant_cpu_to_le16(16);
  1934. nv->retry_count = 8;
  1935. nv->retry_delay = 1;
  1936. nv->port_name[0] = 33;
  1937. nv->port_name[3] = 224;
  1938. nv->port_name[4] = 139;
  1939. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1940. nv->login_timeout = 4;
  1941. /*
  1942. * Set default host adapter parameters
  1943. */
  1944. nv->host_p[1] = BIT_2;
  1945. nv->reset_delay = 5;
  1946. nv->port_down_retry_count = 8;
  1947. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1948. nv->link_down_timeout = 60;
  1949. rval = 1;
  1950. }
  1951. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1952. /*
  1953. * The SN2 does not provide BIOS emulation which means you can't change
  1954. * potentially bogus BIOS settings. Force the use of default settings
  1955. * for link rate and frame size. Hope that the rest of the settings
  1956. * are valid.
  1957. */
  1958. if (ia64_platform_is("sn2")) {
  1959. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1960. if (IS_QLA23XX(ha))
  1961. nv->special_options[1] = BIT_7;
  1962. }
  1963. #endif
  1964. /* Reset Initialization control block */
  1965. memset(icb, 0, ha->init_cb_size);
  1966. /*
  1967. * Setup driver NVRAM options.
  1968. */
  1969. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1970. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1971. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1972. nv->firmware_options[1] &= ~BIT_4;
  1973. if (IS_QLA23XX(ha)) {
  1974. nv->firmware_options[0] |= BIT_2;
  1975. nv->firmware_options[0] &= ~BIT_3;
  1976. nv->firmware_options[0] &= ~BIT_6;
  1977. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1978. if (IS_QLA2300(ha)) {
  1979. if (ha->fb_rev == FPM_2310) {
  1980. strcpy(ha->model_number, "QLA2310");
  1981. } else {
  1982. strcpy(ha->model_number, "QLA2300");
  1983. }
  1984. } else {
  1985. qla2x00_set_model_info(vha, nv->model_number,
  1986. sizeof(nv->model_number), "QLA23xx");
  1987. }
  1988. } else if (IS_QLA2200(ha)) {
  1989. nv->firmware_options[0] |= BIT_2;
  1990. /*
  1991. * 'Point-to-point preferred, else loop' is not a safe
  1992. * connection mode setting.
  1993. */
  1994. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  1995. (BIT_5 | BIT_4)) {
  1996. /* Force 'loop preferred, else point-to-point'. */
  1997. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  1998. nv->add_firmware_options[0] |= BIT_5;
  1999. }
  2000. strcpy(ha->model_number, "QLA22xx");
  2001. } else /*if (IS_QLA2100(ha))*/ {
  2002. strcpy(ha->model_number, "QLA2100");
  2003. }
  2004. /*
  2005. * Copy over NVRAM RISC parameter block to initialization control block.
  2006. */
  2007. dptr1 = (uint8_t *)icb;
  2008. dptr2 = (uint8_t *)&nv->parameter_block_version;
  2009. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  2010. while (cnt--)
  2011. *dptr1++ = *dptr2++;
  2012. /* Copy 2nd half. */
  2013. dptr1 = (uint8_t *)icb->add_firmware_options;
  2014. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  2015. while (cnt--)
  2016. *dptr1++ = *dptr2++;
  2017. /* Use alternate WWN? */
  2018. if (nv->host_p[1] & BIT_7) {
  2019. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  2020. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  2021. }
  2022. /* Prepare nodename */
  2023. if ((icb->firmware_options[1] & BIT_6) == 0) {
  2024. /*
  2025. * Firmware will apply the following mask if the nodename was
  2026. * not provided.
  2027. */
  2028. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  2029. icb->node_name[0] &= 0xF0;
  2030. }
  2031. /*
  2032. * Set host adapter parameters.
  2033. */
  2034. /*
  2035. * BIT_7 in the host-parameters section allows for modification to
  2036. * internal driver logging.
  2037. */
  2038. if (nv->host_p[0] & BIT_7)
  2039. ql2xextended_error_logging = 0x7fffffff;
  2040. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2041. /* Always load RISC code on non ISP2[12]00 chips. */
  2042. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2043. ha->flags.disable_risc_code_load = 0;
  2044. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2045. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2046. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2047. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2048. ha->flags.disable_serdes = 0;
  2049. ha->operating_mode =
  2050. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2051. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2052. sizeof(ha->fw_seriallink_options));
  2053. /* save HBA serial number */
  2054. ha->serial0 = icb->port_name[5];
  2055. ha->serial1 = icb->port_name[6];
  2056. ha->serial2 = icb->port_name[7];
  2057. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2058. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2059. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2060. ha->retry_count = nv->retry_count;
  2061. /* Set minimum login_timeout to 4 seconds. */
  2062. if (nv->login_timeout != ql2xlogintimeout)
  2063. nv->login_timeout = ql2xlogintimeout;
  2064. if (nv->login_timeout < 4)
  2065. nv->login_timeout = 4;
  2066. ha->login_timeout = nv->login_timeout;
  2067. icb->login_timeout = nv->login_timeout;
  2068. /* Set minimum RATOV to 100 tenths of a second. */
  2069. ha->r_a_tov = 100;
  2070. ha->loop_reset_delay = nv->reset_delay;
  2071. /* Link Down Timeout = 0:
  2072. *
  2073. * When Port Down timer expires we will start returning
  2074. * I/O's to OS with "DID_NO_CONNECT".
  2075. *
  2076. * Link Down Timeout != 0:
  2077. *
  2078. * The driver waits for the link to come up after link down
  2079. * before returning I/Os to OS with "DID_NO_CONNECT".
  2080. */
  2081. if (nv->link_down_timeout == 0) {
  2082. ha->loop_down_abort_time =
  2083. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2084. } else {
  2085. ha->link_down_timeout = nv->link_down_timeout;
  2086. ha->loop_down_abort_time =
  2087. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2088. }
  2089. /*
  2090. * Need enough time to try and get the port back.
  2091. */
  2092. ha->port_down_retry_count = nv->port_down_retry_count;
  2093. if (qlport_down_retry)
  2094. ha->port_down_retry_count = qlport_down_retry;
  2095. /* Set login_retry_count */
  2096. ha->login_retry_count = nv->retry_count;
  2097. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2098. ha->port_down_retry_count > 3)
  2099. ha->login_retry_count = ha->port_down_retry_count;
  2100. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2101. ha->login_retry_count = ha->port_down_retry_count;
  2102. if (ql2xloginretrycount)
  2103. ha->login_retry_count = ql2xloginretrycount;
  2104. icb->lun_enables = __constant_cpu_to_le16(0);
  2105. icb->command_resource_count = 0;
  2106. icb->immediate_notify_resource_count = 0;
  2107. icb->timeout = __constant_cpu_to_le16(0);
  2108. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2109. /* Enable RIO */
  2110. icb->firmware_options[0] &= ~BIT_3;
  2111. icb->add_firmware_options[0] &=
  2112. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2113. icb->add_firmware_options[0] |= BIT_2;
  2114. icb->response_accumulation_timer = 3;
  2115. icb->interrupt_delay_timer = 5;
  2116. vha->flags.process_response_queue = 1;
  2117. } else {
  2118. /* Enable ZIO. */
  2119. if (!vha->flags.init_done) {
  2120. ha->zio_mode = icb->add_firmware_options[0] &
  2121. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2122. ha->zio_timer = icb->interrupt_delay_timer ?
  2123. icb->interrupt_delay_timer: 2;
  2124. }
  2125. icb->add_firmware_options[0] &=
  2126. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2127. vha->flags.process_response_queue = 0;
  2128. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2129. ha->zio_mode = QLA_ZIO_MODE_6;
  2130. ql_log(ql_log_info, vha, 0x0068,
  2131. "ZIO mode %d enabled; timer delay (%d us).\n",
  2132. ha->zio_mode, ha->zio_timer * 100);
  2133. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2134. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2135. vha->flags.process_response_queue = 1;
  2136. }
  2137. }
  2138. if (rval) {
  2139. ql_log(ql_log_warn, vha, 0x0069,
  2140. "NVRAM configuration failed.\n");
  2141. }
  2142. return (rval);
  2143. }
  2144. static void
  2145. qla2x00_rport_del(void *data)
  2146. {
  2147. fc_port_t *fcport = data;
  2148. struct fc_rport *rport;
  2149. unsigned long flags;
  2150. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2151. rport = fcport->drport ? fcport->drport: fcport->rport;
  2152. fcport->drport = NULL;
  2153. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2154. if (rport)
  2155. fc_remote_port_delete(rport);
  2156. }
  2157. /**
  2158. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2159. * @ha: HA context
  2160. * @flags: allocation flags
  2161. *
  2162. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2163. */
  2164. fc_port_t *
  2165. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2166. {
  2167. fc_port_t *fcport;
  2168. fcport = kzalloc(sizeof(fc_port_t), flags);
  2169. if (!fcport)
  2170. return NULL;
  2171. /* Setup fcport template structure. */
  2172. fcport->vha = vha;
  2173. fcport->vp_idx = vha->vp_idx;
  2174. fcport->port_type = FCT_UNKNOWN;
  2175. fcport->loop_id = FC_NO_LOOP_ID;
  2176. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2177. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2178. return fcport;
  2179. }
  2180. /*
  2181. * qla2x00_configure_loop
  2182. * Updates Fibre Channel Device Database with what is actually on loop.
  2183. *
  2184. * Input:
  2185. * ha = adapter block pointer.
  2186. *
  2187. * Returns:
  2188. * 0 = success.
  2189. * 1 = error.
  2190. * 2 = database was full and device was not configured.
  2191. */
  2192. static int
  2193. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2194. {
  2195. int rval;
  2196. unsigned long flags, save_flags;
  2197. struct qla_hw_data *ha = vha->hw;
  2198. rval = QLA_SUCCESS;
  2199. /* Get Initiator ID */
  2200. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2201. rval = qla2x00_configure_hba(vha);
  2202. if (rval != QLA_SUCCESS) {
  2203. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2204. "Unable to configure HBA.\n");
  2205. return (rval);
  2206. }
  2207. }
  2208. save_flags = flags = vha->dpc_flags;
  2209. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2210. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2211. /*
  2212. * If we have both an RSCN and PORT UPDATE pending then handle them
  2213. * both at the same time.
  2214. */
  2215. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2216. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2217. qla2x00_get_data_rate(vha);
  2218. /* Determine what we need to do */
  2219. if (ha->current_topology == ISP_CFG_FL &&
  2220. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2221. vha->flags.rscn_queue_overflow = 1;
  2222. set_bit(RSCN_UPDATE, &flags);
  2223. } else if (ha->current_topology == ISP_CFG_F &&
  2224. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2225. vha->flags.rscn_queue_overflow = 1;
  2226. set_bit(RSCN_UPDATE, &flags);
  2227. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2228. } else if (ha->current_topology == ISP_CFG_N) {
  2229. clear_bit(RSCN_UPDATE, &flags);
  2230. } else if (!vha->flags.online ||
  2231. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2232. vha->flags.rscn_queue_overflow = 1;
  2233. set_bit(RSCN_UPDATE, &flags);
  2234. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2235. }
  2236. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2237. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2238. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2239. "Loop resync needed, failing.\n");
  2240. rval = QLA_FUNCTION_FAILED;
  2241. }
  2242. else
  2243. rval = qla2x00_configure_local_loop(vha);
  2244. }
  2245. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2246. if (LOOP_TRANSITION(vha)) {
  2247. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2248. "Needs RSCN update and loop transition.\n");
  2249. rval = QLA_FUNCTION_FAILED;
  2250. }
  2251. else
  2252. rval = qla2x00_configure_fabric(vha);
  2253. }
  2254. if (rval == QLA_SUCCESS) {
  2255. if (atomic_read(&vha->loop_down_timer) ||
  2256. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2257. rval = QLA_FUNCTION_FAILED;
  2258. } else {
  2259. atomic_set(&vha->loop_state, LOOP_READY);
  2260. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2261. "LOOP READY.\n");
  2262. }
  2263. }
  2264. if (rval) {
  2265. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2266. "%s *** FAILED ***.\n", __func__);
  2267. } else {
  2268. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2269. "%s: exiting normally.\n", __func__);
  2270. }
  2271. /* Restore state if a resync event occurred during processing */
  2272. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2273. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2274. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2275. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2276. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2277. if (!IS_ALOGIO_CAPABLE(ha))
  2278. vha->flags.rscn_queue_overflow = 1;
  2279. }
  2280. }
  2281. return (rval);
  2282. }
  2283. /*
  2284. * qla2x00_configure_local_loop
  2285. * Updates Fibre Channel Device Database with local loop devices.
  2286. *
  2287. * Input:
  2288. * ha = adapter block pointer.
  2289. *
  2290. * Returns:
  2291. * 0 = success.
  2292. */
  2293. static int
  2294. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2295. {
  2296. int rval, rval2;
  2297. int found_devs;
  2298. int found;
  2299. fc_port_t *fcport, *new_fcport;
  2300. uint16_t index;
  2301. uint16_t entries;
  2302. char *id_iter;
  2303. uint16_t loop_id;
  2304. uint8_t domain, area, al_pa;
  2305. struct qla_hw_data *ha = vha->hw;
  2306. found_devs = 0;
  2307. new_fcport = NULL;
  2308. entries = MAX_FIBRE_DEVICES;
  2309. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2310. "Getting FCAL position map.\n");
  2311. if (ql2xextended_error_logging & ql_dbg_disc)
  2312. qla2x00_get_fcal_position_map(vha, NULL);
  2313. /* Get list of logged in devices. */
  2314. memset(ha->gid_list, 0, GID_LIST_SIZE);
  2315. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2316. &entries);
  2317. if (rval != QLA_SUCCESS)
  2318. goto cleanup_allocation;
  2319. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2320. "Entries in ID list (%d).\n", entries);
  2321. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2322. (uint8_t *)ha->gid_list,
  2323. entries * sizeof(struct gid_list_info));
  2324. /* Allocate temporary fcport for any new fcports discovered. */
  2325. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2326. if (new_fcport == NULL) {
  2327. ql_log(ql_log_warn, vha, 0x2018,
  2328. "Memory allocation failed for fcport.\n");
  2329. rval = QLA_MEMORY_ALLOC_FAILED;
  2330. goto cleanup_allocation;
  2331. }
  2332. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2333. /*
  2334. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2335. */
  2336. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2337. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2338. fcport->port_type != FCT_BROADCAST &&
  2339. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2340. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2341. "Marking port lost loop_id=0x%04x.\n",
  2342. fcport->loop_id);
  2343. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2344. }
  2345. }
  2346. /* Add devices to port list. */
  2347. id_iter = (char *)ha->gid_list;
  2348. for (index = 0; index < entries; index++) {
  2349. domain = ((struct gid_list_info *)id_iter)->domain;
  2350. area = ((struct gid_list_info *)id_iter)->area;
  2351. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2352. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2353. loop_id = (uint16_t)
  2354. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2355. else
  2356. loop_id = le16_to_cpu(
  2357. ((struct gid_list_info *)id_iter)->loop_id);
  2358. id_iter += ha->gid_list_info_size;
  2359. /* Bypass reserved domain fields. */
  2360. if ((domain & 0xf0) == 0xf0)
  2361. continue;
  2362. /* Bypass if not same domain and area of adapter. */
  2363. if (area && domain &&
  2364. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2365. continue;
  2366. /* Bypass invalid local loop ID. */
  2367. if (loop_id > LAST_LOCAL_LOOP_ID)
  2368. continue;
  2369. /* Fill in member data. */
  2370. new_fcport->d_id.b.domain = domain;
  2371. new_fcport->d_id.b.area = area;
  2372. new_fcport->d_id.b.al_pa = al_pa;
  2373. new_fcport->loop_id = loop_id;
  2374. new_fcport->vp_idx = vha->vp_idx;
  2375. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2376. if (rval2 != QLA_SUCCESS) {
  2377. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2378. "Failed to retrieve fcport information "
  2379. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2380. rval2, new_fcport->loop_id);
  2381. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2382. "Scheduling resync.\n");
  2383. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2384. continue;
  2385. }
  2386. /* Check for matching device in port list. */
  2387. found = 0;
  2388. fcport = NULL;
  2389. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2390. if (memcmp(new_fcport->port_name, fcport->port_name,
  2391. WWN_SIZE))
  2392. continue;
  2393. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2394. fcport->loop_id = new_fcport->loop_id;
  2395. fcport->port_type = new_fcport->port_type;
  2396. fcport->d_id.b24 = new_fcport->d_id.b24;
  2397. memcpy(fcport->node_name, new_fcport->node_name,
  2398. WWN_SIZE);
  2399. found++;
  2400. break;
  2401. }
  2402. if (!found) {
  2403. /* New device, add to fcports list. */
  2404. if (vha->vp_idx) {
  2405. new_fcport->vha = vha;
  2406. new_fcport->vp_idx = vha->vp_idx;
  2407. }
  2408. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2409. /* Allocate a new replacement fcport. */
  2410. fcport = new_fcport;
  2411. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2412. if (new_fcport == NULL) {
  2413. ql_log(ql_log_warn, vha, 0x201c,
  2414. "Failed to allocate memory for fcport.\n");
  2415. rval = QLA_MEMORY_ALLOC_FAILED;
  2416. goto cleanup_allocation;
  2417. }
  2418. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2419. }
  2420. /* Base iIDMA settings on HBA port speed. */
  2421. fcport->fp_speed = ha->link_data_rate;
  2422. qla2x00_update_fcport(vha, fcport);
  2423. found_devs++;
  2424. }
  2425. cleanup_allocation:
  2426. kfree(new_fcport);
  2427. if (rval != QLA_SUCCESS) {
  2428. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2429. "Configure local loop error exit: rval=%x.\n", rval);
  2430. }
  2431. return (rval);
  2432. }
  2433. static void
  2434. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2435. {
  2436. #define LS_UNKNOWN 2
  2437. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2438. char *link_speed;
  2439. int rval;
  2440. uint16_t mb[4];
  2441. struct qla_hw_data *ha = vha->hw;
  2442. if (!IS_IIDMA_CAPABLE(ha))
  2443. return;
  2444. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2445. return;
  2446. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2447. fcport->fp_speed > ha->link_data_rate)
  2448. return;
  2449. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2450. mb);
  2451. if (rval != QLA_SUCCESS) {
  2452. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2453. "Unable to adjust iIDMA "
  2454. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2455. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2456. fcport->port_name[2], fcport->port_name[3],
  2457. fcport->port_name[4], fcport->port_name[5],
  2458. fcport->port_name[6], fcport->port_name[7], rval,
  2459. fcport->fp_speed, mb[0], mb[1]);
  2460. } else {
  2461. link_speed = link_speeds[LS_UNKNOWN];
  2462. if (fcport->fp_speed < 5)
  2463. link_speed = link_speeds[fcport->fp_speed];
  2464. else if (fcport->fp_speed == 0x13)
  2465. link_speed = link_speeds[5];
  2466. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2467. "iIDMA adjusted to %s GB/s "
  2468. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2469. fcport->port_name[0], fcport->port_name[1],
  2470. fcport->port_name[2], fcport->port_name[3],
  2471. fcport->port_name[4], fcport->port_name[5],
  2472. fcport->port_name[6], fcport->port_name[7]);
  2473. }
  2474. }
  2475. static void
  2476. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2477. {
  2478. struct fc_rport_identifiers rport_ids;
  2479. struct fc_rport *rport;
  2480. unsigned long flags;
  2481. qla2x00_rport_del(fcport);
  2482. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2483. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2484. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2485. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2486. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2487. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2488. if (!rport) {
  2489. ql_log(ql_log_warn, vha, 0x2006,
  2490. "Unable to allocate fc remote port.\n");
  2491. return;
  2492. }
  2493. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2494. *((fc_port_t **)rport->dd_data) = fcport;
  2495. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2496. rport->supported_classes = fcport->supported_classes;
  2497. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2498. if (fcport->port_type == FCT_INITIATOR)
  2499. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2500. if (fcport->port_type == FCT_TARGET)
  2501. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2502. fc_remote_port_rolechg(rport, rport_ids.roles);
  2503. }
  2504. /*
  2505. * qla2x00_update_fcport
  2506. * Updates device on list.
  2507. *
  2508. * Input:
  2509. * ha = adapter block pointer.
  2510. * fcport = port structure pointer.
  2511. *
  2512. * Return:
  2513. * 0 - Success
  2514. * BIT_0 - error
  2515. *
  2516. * Context:
  2517. * Kernel context.
  2518. */
  2519. void
  2520. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2521. {
  2522. fcport->vha = vha;
  2523. fcport->login_retry = 0;
  2524. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2525. qla2x00_iidma_fcport(vha, fcport);
  2526. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2527. qla2x00_reg_remote_port(vha, fcport);
  2528. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2529. }
  2530. /*
  2531. * qla2x00_configure_fabric
  2532. * Setup SNS devices with loop ID's.
  2533. *
  2534. * Input:
  2535. * ha = adapter block pointer.
  2536. *
  2537. * Returns:
  2538. * 0 = success.
  2539. * BIT_0 = error
  2540. */
  2541. static int
  2542. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2543. {
  2544. int rval, rval2;
  2545. fc_port_t *fcport, *fcptemp;
  2546. uint16_t next_loopid;
  2547. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2548. uint16_t loop_id;
  2549. LIST_HEAD(new_fcports);
  2550. struct qla_hw_data *ha = vha->hw;
  2551. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2552. /* If FL port exists, then SNS is present */
  2553. if (IS_FWI2_CAPABLE(ha))
  2554. loop_id = NPH_F_PORT;
  2555. else
  2556. loop_id = SNS_FL_PORT;
  2557. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2558. if (rval != QLA_SUCCESS) {
  2559. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2560. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2561. vha->device_flags &= ~SWITCH_FOUND;
  2562. return (QLA_SUCCESS);
  2563. }
  2564. vha->device_flags |= SWITCH_FOUND;
  2565. /* Mark devices that need re-synchronization. */
  2566. rval2 = qla2x00_device_resync(vha);
  2567. if (rval2 == QLA_RSCNS_HANDLED) {
  2568. /* No point doing the scan, just continue. */
  2569. return (QLA_SUCCESS);
  2570. }
  2571. do {
  2572. /* FDMI support. */
  2573. if (ql2xfdmienable &&
  2574. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2575. qla2x00_fdmi_register(vha);
  2576. /* Ensure we are logged into the SNS. */
  2577. if (IS_FWI2_CAPABLE(ha))
  2578. loop_id = NPH_SNS;
  2579. else
  2580. loop_id = SIMPLE_NAME_SERVER;
  2581. ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2582. 0xfc, mb, BIT_1 | BIT_0);
  2583. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2584. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2585. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2586. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2587. mb[2], mb[6], mb[7]);
  2588. return (QLA_SUCCESS);
  2589. }
  2590. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2591. if (qla2x00_rft_id(vha)) {
  2592. /* EMPTY */
  2593. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2594. "Register FC-4 TYPE failed.\n");
  2595. }
  2596. if (qla2x00_rff_id(vha)) {
  2597. /* EMPTY */
  2598. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2599. "Register FC-4 Features failed.\n");
  2600. }
  2601. if (qla2x00_rnn_id(vha)) {
  2602. /* EMPTY */
  2603. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2604. "Register Node Name failed.\n");
  2605. } else if (qla2x00_rsnn_nn(vha)) {
  2606. /* EMPTY */
  2607. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2608. "Register Symobilic Node Name failed.\n");
  2609. }
  2610. }
  2611. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2612. if (rval != QLA_SUCCESS)
  2613. break;
  2614. /*
  2615. * Logout all previous fabric devices marked lost, except
  2616. * FCP2 devices.
  2617. */
  2618. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2619. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2620. break;
  2621. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2622. continue;
  2623. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  2624. qla2x00_mark_device_lost(vha, fcport,
  2625. ql2xplogiabsentdevice, 0);
  2626. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2627. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2628. fcport->port_type != FCT_INITIATOR &&
  2629. fcport->port_type != FCT_BROADCAST) {
  2630. ha->isp_ops->fabric_logout(vha,
  2631. fcport->loop_id,
  2632. fcport->d_id.b.domain,
  2633. fcport->d_id.b.area,
  2634. fcport->d_id.b.al_pa);
  2635. fcport->loop_id = FC_NO_LOOP_ID;
  2636. }
  2637. }
  2638. }
  2639. /* Starting free loop ID. */
  2640. next_loopid = ha->min_external_loopid;
  2641. /*
  2642. * Scan through our port list and login entries that need to be
  2643. * logged in.
  2644. */
  2645. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2646. if (atomic_read(&vha->loop_down_timer) ||
  2647. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2648. break;
  2649. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2650. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2651. continue;
  2652. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2653. fcport->loop_id = next_loopid;
  2654. rval = qla2x00_find_new_loop_id(
  2655. base_vha, fcport);
  2656. if (rval != QLA_SUCCESS) {
  2657. /* Ran out of IDs to use */
  2658. break;
  2659. }
  2660. }
  2661. /* Login and update database */
  2662. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2663. }
  2664. /* Exit if out of loop IDs. */
  2665. if (rval != QLA_SUCCESS) {
  2666. break;
  2667. }
  2668. /*
  2669. * Login and add the new devices to our port list.
  2670. */
  2671. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2672. if (atomic_read(&vha->loop_down_timer) ||
  2673. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2674. break;
  2675. /* Find a new loop ID to use. */
  2676. fcport->loop_id = next_loopid;
  2677. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2678. if (rval != QLA_SUCCESS) {
  2679. /* Ran out of IDs to use */
  2680. break;
  2681. }
  2682. /* Login and update database */
  2683. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2684. if (vha->vp_idx) {
  2685. fcport->vha = vha;
  2686. fcport->vp_idx = vha->vp_idx;
  2687. }
  2688. list_move_tail(&fcport->list, &vha->vp_fcports);
  2689. }
  2690. } while (0);
  2691. /* Free all new device structures not processed. */
  2692. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2693. list_del(&fcport->list);
  2694. kfree(fcport);
  2695. }
  2696. if (rval) {
  2697. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2698. "Configure fabric error exit rval=%d.\n", rval);
  2699. }
  2700. return (rval);
  2701. }
  2702. /*
  2703. * qla2x00_find_all_fabric_devs
  2704. *
  2705. * Input:
  2706. * ha = adapter block pointer.
  2707. * dev = database device entry pointer.
  2708. *
  2709. * Returns:
  2710. * 0 = success.
  2711. *
  2712. * Context:
  2713. * Kernel context.
  2714. */
  2715. static int
  2716. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2717. struct list_head *new_fcports)
  2718. {
  2719. int rval;
  2720. uint16_t loop_id;
  2721. fc_port_t *fcport, *new_fcport, *fcptemp;
  2722. int found;
  2723. sw_info_t *swl;
  2724. int swl_idx;
  2725. int first_dev, last_dev;
  2726. port_id_t wrap = {}, nxt_d_id;
  2727. struct qla_hw_data *ha = vha->hw;
  2728. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2729. struct scsi_qla_host *tvp;
  2730. rval = QLA_SUCCESS;
  2731. /* Try GID_PT to get device list, else GAN. */
  2732. swl = kcalloc(MAX_FIBRE_DEVICES, sizeof(sw_info_t), GFP_KERNEL);
  2733. if (!swl) {
  2734. /*EMPTY*/
  2735. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2736. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2737. } else {
  2738. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2739. kfree(swl);
  2740. swl = NULL;
  2741. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2742. kfree(swl);
  2743. swl = NULL;
  2744. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2745. kfree(swl);
  2746. swl = NULL;
  2747. } else if (ql2xiidmaenable &&
  2748. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2749. qla2x00_gpsc(vha, swl);
  2750. }
  2751. /* If other queries succeeded probe for FC-4 type */
  2752. if (swl)
  2753. qla2x00_gff_id(vha, swl);
  2754. }
  2755. swl_idx = 0;
  2756. /* Allocate temporary fcport for any new fcports discovered. */
  2757. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2758. if (new_fcport == NULL) {
  2759. ql_log(ql_log_warn, vha, 0x205e,
  2760. "Failed to allocate memory for fcport.\n");
  2761. kfree(swl);
  2762. return (QLA_MEMORY_ALLOC_FAILED);
  2763. }
  2764. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2765. /* Set start port ID scan at adapter ID. */
  2766. first_dev = 1;
  2767. last_dev = 0;
  2768. /* Starting free loop ID. */
  2769. loop_id = ha->min_external_loopid;
  2770. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2771. if (qla2x00_is_reserved_id(vha, loop_id))
  2772. continue;
  2773. if (ha->current_topology == ISP_CFG_FL &&
  2774. (atomic_read(&vha->loop_down_timer) ||
  2775. LOOP_TRANSITION(vha))) {
  2776. atomic_set(&vha->loop_down_timer, 0);
  2777. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2778. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2779. break;
  2780. }
  2781. if (swl != NULL) {
  2782. if (last_dev) {
  2783. wrap.b24 = new_fcport->d_id.b24;
  2784. } else {
  2785. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2786. memcpy(new_fcport->node_name,
  2787. swl[swl_idx].node_name, WWN_SIZE);
  2788. memcpy(new_fcport->port_name,
  2789. swl[swl_idx].port_name, WWN_SIZE);
  2790. memcpy(new_fcport->fabric_port_name,
  2791. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2792. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2793. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2794. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2795. last_dev = 1;
  2796. }
  2797. swl_idx++;
  2798. }
  2799. } else {
  2800. /* Send GA_NXT to the switch */
  2801. rval = qla2x00_ga_nxt(vha, new_fcport);
  2802. if (rval != QLA_SUCCESS) {
  2803. ql_log(ql_log_warn, vha, 0x2064,
  2804. "SNS scan failed -- assuming "
  2805. "zero-entry result.\n");
  2806. list_for_each_entry_safe(fcport, fcptemp,
  2807. new_fcports, list) {
  2808. list_del(&fcport->list);
  2809. kfree(fcport);
  2810. }
  2811. rval = QLA_SUCCESS;
  2812. break;
  2813. }
  2814. }
  2815. /* If wrap on switch device list, exit. */
  2816. if (first_dev) {
  2817. wrap.b24 = new_fcport->d_id.b24;
  2818. first_dev = 0;
  2819. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2820. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2821. "Device wrap (%02x%02x%02x).\n",
  2822. new_fcport->d_id.b.domain,
  2823. new_fcport->d_id.b.area,
  2824. new_fcport->d_id.b.al_pa);
  2825. break;
  2826. }
  2827. /* Bypass if same physical adapter. */
  2828. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2829. continue;
  2830. /* Bypass virtual ports of the same host. */
  2831. found = 0;
  2832. if (ha->num_vhosts) {
  2833. unsigned long flags;
  2834. spin_lock_irqsave(&ha->vport_slock, flags);
  2835. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2836. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2837. found = 1;
  2838. break;
  2839. }
  2840. }
  2841. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2842. if (found)
  2843. continue;
  2844. }
  2845. /* Bypass if same domain and area of adapter. */
  2846. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2847. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2848. ISP_CFG_FL)
  2849. continue;
  2850. /* Bypass reserved domain fields. */
  2851. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2852. continue;
  2853. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2854. if (ql2xgffidenable &&
  2855. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2856. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2857. continue;
  2858. /* Locate matching device in database. */
  2859. found = 0;
  2860. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2861. if (memcmp(new_fcport->port_name, fcport->port_name,
  2862. WWN_SIZE))
  2863. continue;
  2864. found++;
  2865. /* Update port state. */
  2866. memcpy(fcport->fabric_port_name,
  2867. new_fcport->fabric_port_name, WWN_SIZE);
  2868. fcport->fp_speed = new_fcport->fp_speed;
  2869. /*
  2870. * If address the same and state FCS_ONLINE, nothing
  2871. * changed.
  2872. */
  2873. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2874. atomic_read(&fcport->state) == FCS_ONLINE) {
  2875. break;
  2876. }
  2877. /*
  2878. * If device was not a fabric device before.
  2879. */
  2880. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2881. fcport->d_id.b24 = new_fcport->d_id.b24;
  2882. fcport->loop_id = FC_NO_LOOP_ID;
  2883. fcport->flags |= (FCF_FABRIC_DEVICE |
  2884. FCF_LOGIN_NEEDED);
  2885. break;
  2886. }
  2887. /*
  2888. * Port ID changed or device was marked to be updated;
  2889. * Log it out if still logged in and mark it for
  2890. * relogin later.
  2891. */
  2892. fcport->d_id.b24 = new_fcport->d_id.b24;
  2893. fcport->flags |= FCF_LOGIN_NEEDED;
  2894. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2895. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2896. fcport->port_type != FCT_INITIATOR &&
  2897. fcport->port_type != FCT_BROADCAST) {
  2898. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2899. fcport->d_id.b.domain, fcport->d_id.b.area,
  2900. fcport->d_id.b.al_pa);
  2901. fcport->loop_id = FC_NO_LOOP_ID;
  2902. }
  2903. break;
  2904. }
  2905. if (found)
  2906. continue;
  2907. /* If device was not in our fcports list, then add it. */
  2908. list_add_tail(&new_fcport->list, new_fcports);
  2909. /* Allocate a new replacement fcport. */
  2910. nxt_d_id.b24 = new_fcport->d_id.b24;
  2911. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2912. if (new_fcport == NULL) {
  2913. ql_log(ql_log_warn, vha, 0x2066,
  2914. "Memory allocation failed for fcport.\n");
  2915. kfree(swl);
  2916. return (QLA_MEMORY_ALLOC_FAILED);
  2917. }
  2918. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2919. new_fcport->d_id.b24 = nxt_d_id.b24;
  2920. }
  2921. kfree(swl);
  2922. kfree(new_fcport);
  2923. return (rval);
  2924. }
  2925. /*
  2926. * qla2x00_find_new_loop_id
  2927. * Scan through our port list and find a new usable loop ID.
  2928. *
  2929. * Input:
  2930. * ha: adapter state pointer.
  2931. * dev: port structure pointer.
  2932. *
  2933. * Returns:
  2934. * qla2x00 local function return status code.
  2935. *
  2936. * Context:
  2937. * Kernel context.
  2938. */
  2939. int
  2940. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2941. {
  2942. int rval;
  2943. int found;
  2944. fc_port_t *fcport;
  2945. uint16_t first_loop_id;
  2946. struct qla_hw_data *ha = vha->hw;
  2947. struct scsi_qla_host *vp;
  2948. struct scsi_qla_host *tvp;
  2949. unsigned long flags = 0;
  2950. rval = QLA_SUCCESS;
  2951. /* Save starting loop ID. */
  2952. first_loop_id = dev->loop_id;
  2953. for (;;) {
  2954. /* Skip loop ID if already used by adapter. */
  2955. if (dev->loop_id == vha->loop_id)
  2956. dev->loop_id++;
  2957. /* Skip reserved loop IDs. */
  2958. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2959. dev->loop_id++;
  2960. /* Reset loop ID if passed the end. */
  2961. if (dev->loop_id > ha->max_loop_id) {
  2962. /* first loop ID. */
  2963. dev->loop_id = ha->min_external_loopid;
  2964. }
  2965. /* Check for loop ID being already in use. */
  2966. found = 0;
  2967. fcport = NULL;
  2968. spin_lock_irqsave(&ha->vport_slock, flags);
  2969. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2970. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2971. if (fcport->loop_id == dev->loop_id &&
  2972. fcport != dev) {
  2973. /* ID possibly in use */
  2974. found++;
  2975. break;
  2976. }
  2977. }
  2978. if (found)
  2979. break;
  2980. }
  2981. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2982. /* If not in use then it is free to use. */
  2983. if (!found) {
  2984. break;
  2985. }
  2986. /* ID in use. Try next value. */
  2987. dev->loop_id++;
  2988. /* If wrap around. No free ID to use. */
  2989. if (dev->loop_id == first_loop_id) {
  2990. dev->loop_id = FC_NO_LOOP_ID;
  2991. rval = QLA_FUNCTION_FAILED;
  2992. break;
  2993. }
  2994. }
  2995. return (rval);
  2996. }
  2997. /*
  2998. * qla2x00_device_resync
  2999. * Marks devices in the database that needs resynchronization.
  3000. *
  3001. * Input:
  3002. * ha = adapter block pointer.
  3003. *
  3004. * Context:
  3005. * Kernel context.
  3006. */
  3007. static int
  3008. qla2x00_device_resync(scsi_qla_host_t *vha)
  3009. {
  3010. int rval;
  3011. uint32_t mask;
  3012. fc_port_t *fcport;
  3013. uint32_t rscn_entry;
  3014. uint8_t rscn_out_iter;
  3015. uint8_t format;
  3016. port_id_t d_id = {};
  3017. rval = QLA_RSCNS_HANDLED;
  3018. while (vha->rscn_out_ptr != vha->rscn_in_ptr ||
  3019. vha->flags.rscn_queue_overflow) {
  3020. rscn_entry = vha->rscn_queue[vha->rscn_out_ptr];
  3021. format = MSB(MSW(rscn_entry));
  3022. d_id.b.domain = LSB(MSW(rscn_entry));
  3023. d_id.b.area = MSB(LSW(rscn_entry));
  3024. d_id.b.al_pa = LSB(LSW(rscn_entry));
  3025. ql_dbg(ql_dbg_disc, vha, 0x2020,
  3026. "RSCN queue entry[%d] = [%02x/%02x%02x%02x].\n",
  3027. vha->rscn_out_ptr, format, d_id.b.domain, d_id.b.area,
  3028. d_id.b.al_pa);
  3029. vha->rscn_out_ptr++;
  3030. if (vha->rscn_out_ptr == MAX_RSCN_COUNT)
  3031. vha->rscn_out_ptr = 0;
  3032. /* Skip duplicate entries. */
  3033. for (rscn_out_iter = vha->rscn_out_ptr;
  3034. !vha->flags.rscn_queue_overflow &&
  3035. rscn_out_iter != vha->rscn_in_ptr;
  3036. rscn_out_iter = (rscn_out_iter ==
  3037. (MAX_RSCN_COUNT - 1)) ? 0: rscn_out_iter + 1) {
  3038. if (rscn_entry != vha->rscn_queue[rscn_out_iter])
  3039. break;
  3040. ql_dbg(ql_dbg_disc, vha, 0x2021,
  3041. "Skipping duplicate RSCN queue entry found at "
  3042. "[%d].\n", rscn_out_iter);
  3043. vha->rscn_out_ptr = rscn_out_iter;
  3044. }
  3045. /* Queue overflow, set switch default case. */
  3046. if (vha->flags.rscn_queue_overflow) {
  3047. ql_dbg(ql_dbg_disc, vha, 0x2022,
  3048. "device_resync: rscn overflow.\n");
  3049. format = 3;
  3050. vha->flags.rscn_queue_overflow = 0;
  3051. }
  3052. switch (format) {
  3053. case 0:
  3054. mask = 0xffffff;
  3055. break;
  3056. case 1:
  3057. mask = 0xffff00;
  3058. break;
  3059. case 2:
  3060. mask = 0xff0000;
  3061. break;
  3062. default:
  3063. mask = 0x0;
  3064. d_id.b24 = 0;
  3065. vha->rscn_out_ptr = vha->rscn_in_ptr;
  3066. break;
  3067. }
  3068. rval = QLA_SUCCESS;
  3069. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3070. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  3071. (fcport->d_id.b24 & mask) != d_id.b24 ||
  3072. fcport->port_type == FCT_BROADCAST)
  3073. continue;
  3074. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  3075. if (format != 3 ||
  3076. fcport->port_type != FCT_INITIATOR) {
  3077. qla2x00_mark_device_lost(vha, fcport,
  3078. 0, 0);
  3079. }
  3080. }
  3081. }
  3082. }
  3083. return (rval);
  3084. }
  3085. /*
  3086. * qla2x00_fabric_dev_login
  3087. * Login fabric target device and update FC port database.
  3088. *
  3089. * Input:
  3090. * ha: adapter state pointer.
  3091. * fcport: port structure list pointer.
  3092. * next_loopid: contains value of a new loop ID that can be used
  3093. * by the next login attempt.
  3094. *
  3095. * Returns:
  3096. * qla2x00 local function return status code.
  3097. *
  3098. * Context:
  3099. * Kernel context.
  3100. */
  3101. static int
  3102. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3103. uint16_t *next_loopid)
  3104. {
  3105. int rval;
  3106. int retry;
  3107. uint8_t opts;
  3108. struct qla_hw_data *ha = vha->hw;
  3109. rval = QLA_SUCCESS;
  3110. retry = 0;
  3111. if (IS_ALOGIO_CAPABLE(ha)) {
  3112. if (fcport->flags & FCF_ASYNC_SENT)
  3113. return rval;
  3114. fcport->flags |= FCF_ASYNC_SENT;
  3115. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  3116. if (!rval)
  3117. return rval;
  3118. }
  3119. fcport->flags &= ~FCF_ASYNC_SENT;
  3120. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  3121. if (rval == QLA_SUCCESS) {
  3122. /* Send an ADISC to FCP2 devices.*/
  3123. opts = 0;
  3124. if (fcport->flags & FCF_FCP2_DEVICE)
  3125. opts |= BIT_1;
  3126. rval = qla2x00_get_port_database(vha, fcport, opts);
  3127. if (rval != QLA_SUCCESS) {
  3128. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3129. fcport->d_id.b.domain, fcport->d_id.b.area,
  3130. fcport->d_id.b.al_pa);
  3131. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3132. } else {
  3133. qla2x00_update_fcport(vha, fcport);
  3134. }
  3135. }
  3136. return (rval);
  3137. }
  3138. /*
  3139. * qla2x00_fabric_login
  3140. * Issue fabric login command.
  3141. *
  3142. * Input:
  3143. * ha = adapter block pointer.
  3144. * device = pointer to FC device type structure.
  3145. *
  3146. * Returns:
  3147. * 0 - Login successfully
  3148. * 1 - Login failed
  3149. * 2 - Initiator device
  3150. * 3 - Fatal error
  3151. */
  3152. int
  3153. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3154. uint16_t *next_loopid)
  3155. {
  3156. int rval;
  3157. int retry;
  3158. uint16_t tmp_loopid;
  3159. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3160. struct qla_hw_data *ha = vha->hw;
  3161. retry = 0;
  3162. tmp_loopid = 0;
  3163. for (;;) {
  3164. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3165. "Trying Fabric Login w/loop id 0x%04x for port "
  3166. "%02x%02x%02x.\n",
  3167. fcport->loop_id, fcport->d_id.b.domain,
  3168. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3169. /* Login fcport on switch. */
  3170. ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3171. fcport->d_id.b.domain, fcport->d_id.b.area,
  3172. fcport->d_id.b.al_pa, mb, BIT_0);
  3173. if (mb[0] == MBS_PORT_ID_USED) {
  3174. /*
  3175. * Device has another loop ID. The firmware team
  3176. * recommends the driver perform an implicit login with
  3177. * the specified ID again. The ID we just used is save
  3178. * here so we return with an ID that can be tried by
  3179. * the next login.
  3180. */
  3181. retry++;
  3182. tmp_loopid = fcport->loop_id;
  3183. fcport->loop_id = mb[1];
  3184. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3185. "Fabric Login: port in use - next loop "
  3186. "id=0x%04x, port id= %02x%02x%02x.\n",
  3187. fcport->loop_id, fcport->d_id.b.domain,
  3188. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3189. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3190. /*
  3191. * Login succeeded.
  3192. */
  3193. if (retry) {
  3194. /* A retry occurred before. */
  3195. *next_loopid = tmp_loopid;
  3196. } else {
  3197. /*
  3198. * No retry occurred before. Just increment the
  3199. * ID value for next login.
  3200. */
  3201. *next_loopid = (fcport->loop_id + 1);
  3202. }
  3203. if (mb[1] & BIT_0) {
  3204. fcport->port_type = FCT_INITIATOR;
  3205. } else {
  3206. fcport->port_type = FCT_TARGET;
  3207. if (mb[1] & BIT_1) {
  3208. fcport->flags |= FCF_FCP2_DEVICE;
  3209. }
  3210. }
  3211. if (mb[10] & BIT_0)
  3212. fcport->supported_classes |= FC_COS_CLASS2;
  3213. if (mb[10] & BIT_1)
  3214. fcport->supported_classes |= FC_COS_CLASS3;
  3215. rval = QLA_SUCCESS;
  3216. break;
  3217. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3218. /*
  3219. * Loop ID already used, try next loop ID.
  3220. */
  3221. fcport->loop_id++;
  3222. rval = qla2x00_find_new_loop_id(vha, fcport);
  3223. if (rval != QLA_SUCCESS) {
  3224. /* Ran out of loop IDs to use */
  3225. break;
  3226. }
  3227. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3228. /*
  3229. * Firmware possibly timed out during login. If NO
  3230. * retries are left to do then the device is declared
  3231. * dead.
  3232. */
  3233. *next_loopid = fcport->loop_id;
  3234. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3235. fcport->d_id.b.domain, fcport->d_id.b.area,
  3236. fcport->d_id.b.al_pa);
  3237. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3238. rval = 1;
  3239. break;
  3240. } else {
  3241. /*
  3242. * unrecoverable / not handled error
  3243. */
  3244. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3245. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3246. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3247. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3248. fcport->loop_id, jiffies);
  3249. *next_loopid = fcport->loop_id;
  3250. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3251. fcport->d_id.b.domain, fcport->d_id.b.area,
  3252. fcport->d_id.b.al_pa);
  3253. fcport->loop_id = FC_NO_LOOP_ID;
  3254. fcport->login_retry = 0;
  3255. rval = 3;
  3256. break;
  3257. }
  3258. }
  3259. return (rval);
  3260. }
  3261. /*
  3262. * qla2x00_local_device_login
  3263. * Issue local device login command.
  3264. *
  3265. * Input:
  3266. * ha = adapter block pointer.
  3267. * loop_id = loop id of device to login to.
  3268. *
  3269. * Returns (Where's the #define!!!!):
  3270. * 0 - Login successfully
  3271. * 1 - Login failed
  3272. * 3 - Fatal error
  3273. */
  3274. int
  3275. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3276. {
  3277. int rval;
  3278. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3279. memset(mb, 0, sizeof(mb));
  3280. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3281. if (rval == QLA_SUCCESS) {
  3282. /* Interrogate mailbox registers for any errors */
  3283. if (mb[0] == MBS_COMMAND_ERROR)
  3284. rval = 1;
  3285. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3286. /* device not in PCB table */
  3287. rval = 3;
  3288. }
  3289. return (rval);
  3290. }
  3291. /*
  3292. * qla2x00_loop_resync
  3293. * Resync with fibre channel devices.
  3294. *
  3295. * Input:
  3296. * ha = adapter block pointer.
  3297. *
  3298. * Returns:
  3299. * 0 = success
  3300. */
  3301. int
  3302. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3303. {
  3304. int rval = QLA_SUCCESS;
  3305. uint32_t wait_time;
  3306. struct req_que *req;
  3307. struct rsp_que *rsp;
  3308. if (vha->hw->flags.cpu_affinity_enabled)
  3309. req = vha->hw->req_q_map[0];
  3310. else
  3311. req = vha->req;
  3312. rsp = req->rsp;
  3313. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3314. if (vha->flags.online) {
  3315. if (!(rval = qla2x00_fw_ready(vha))) {
  3316. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3317. wait_time = 256;
  3318. do {
  3319. /* Issue a marker after FW becomes ready. */
  3320. qla2x00_marker(vha, req, rsp, 0, 0,
  3321. MK_SYNC_ALL);
  3322. vha->marker_needed = 0;
  3323. /* Remap devices on Loop. */
  3324. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3325. qla2x00_configure_loop(vha);
  3326. wait_time--;
  3327. } while (!atomic_read(&vha->loop_down_timer) &&
  3328. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3329. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3330. &vha->dpc_flags)));
  3331. }
  3332. }
  3333. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3334. return (QLA_FUNCTION_FAILED);
  3335. if (rval)
  3336. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3337. "%s *** FAILED ***.\n", __func__);
  3338. return (rval);
  3339. }
  3340. /*
  3341. * qla2x00_perform_loop_resync
  3342. * Description: This function will set the appropriate flags and call
  3343. * qla2x00_loop_resync. If successful loop will be resynced
  3344. * Arguments : scsi_qla_host_t pointer
  3345. * returm : Success or Failure
  3346. */
  3347. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3348. {
  3349. int32_t rval = 0;
  3350. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3351. /*Configure the flags so that resync happens properly*/
  3352. atomic_set(&ha->loop_down_timer, 0);
  3353. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3354. atomic_set(&ha->loop_state, LOOP_UP);
  3355. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3356. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3357. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3358. rval = qla2x00_loop_resync(ha);
  3359. } else
  3360. atomic_set(&ha->loop_state, LOOP_DEAD);
  3361. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3362. }
  3363. return rval;
  3364. }
  3365. void
  3366. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3367. {
  3368. fc_port_t *fcport;
  3369. struct scsi_qla_host *vha;
  3370. struct qla_hw_data *ha = base_vha->hw;
  3371. unsigned long flags;
  3372. spin_lock_irqsave(&ha->vport_slock, flags);
  3373. /* Go with deferred removal of rport references. */
  3374. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3375. atomic_inc(&vha->vref_count);
  3376. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3377. if (fcport->drport &&
  3378. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3379. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3380. qla2x00_rport_del(fcport);
  3381. spin_lock_irqsave(&ha->vport_slock, flags);
  3382. }
  3383. }
  3384. atomic_dec(&vha->vref_count);
  3385. }
  3386. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3387. }
  3388. /*
  3389. * qla82xx_quiescent_state_cleanup
  3390. * Description: This function will block the new I/Os
  3391. * Its not aborting any I/Os as context
  3392. * is not destroyed during quiescence
  3393. * Arguments: scsi_qla_host_t
  3394. * return : void
  3395. */
  3396. void
  3397. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3398. {
  3399. struct qla_hw_data *ha = vha->hw;
  3400. struct scsi_qla_host *vp;
  3401. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3402. "Performing ISP error recovery - ha=%p.\n", ha);
  3403. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3404. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3405. atomic_set(&vha->loop_state, LOOP_DOWN);
  3406. qla2x00_mark_all_devices_lost(vha, 0);
  3407. list_for_each_entry(vp, &ha->vp_list, list)
  3408. qla2x00_mark_all_devices_lost(vha, 0);
  3409. } else {
  3410. if (!atomic_read(&vha->loop_down_timer))
  3411. atomic_set(&vha->loop_down_timer,
  3412. LOOP_DOWN_TIME);
  3413. }
  3414. /* Wait for pending cmds to complete */
  3415. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3416. }
  3417. void
  3418. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3419. {
  3420. struct qla_hw_data *ha = vha->hw;
  3421. struct scsi_qla_host *vp;
  3422. unsigned long flags;
  3423. fc_port_t *fcport;
  3424. /* For ISP82XX, driver waits for completion of the commands.
  3425. * online flag should be set.
  3426. */
  3427. if (!IS_QLA82XX(ha))
  3428. vha->flags.online = 0;
  3429. ha->flags.chip_reset_done = 0;
  3430. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3431. ha->qla_stats.total_isp_aborts++;
  3432. ql_log(ql_log_info, vha, 0x00af,
  3433. "Performing ISP error recovery - ha=%p.\n", ha);
  3434. /* For ISP82XX, reset_chip is just disabling interrupts.
  3435. * Driver waits for the completion of the commands.
  3436. * the interrupts need to be enabled.
  3437. */
  3438. if (!IS_QLA82XX(ha))
  3439. ha->isp_ops->reset_chip(vha);
  3440. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3441. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3442. atomic_set(&vha->loop_state, LOOP_DOWN);
  3443. qla2x00_mark_all_devices_lost(vha, 0);
  3444. spin_lock_irqsave(&ha->vport_slock, flags);
  3445. list_for_each_entry(vp, &ha->vp_list, list) {
  3446. atomic_inc(&vp->vref_count);
  3447. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3448. qla2x00_mark_all_devices_lost(vp, 0);
  3449. spin_lock_irqsave(&ha->vport_slock, flags);
  3450. atomic_dec(&vp->vref_count);
  3451. }
  3452. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3453. } else {
  3454. if (!atomic_read(&vha->loop_down_timer))
  3455. atomic_set(&vha->loop_down_timer,
  3456. LOOP_DOWN_TIME);
  3457. }
  3458. /* Clear all async request states across all VPs. */
  3459. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3460. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3461. spin_lock_irqsave(&ha->vport_slock, flags);
  3462. list_for_each_entry(vp, &ha->vp_list, list) {
  3463. atomic_inc(&vp->vref_count);
  3464. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3465. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3466. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3467. spin_lock_irqsave(&ha->vport_slock, flags);
  3468. atomic_dec(&vp->vref_count);
  3469. }
  3470. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3471. if (!ha->flags.eeh_busy) {
  3472. /* Make sure for ISP 82XX IO DMA is complete */
  3473. if (IS_QLA82XX(ha)) {
  3474. qla82xx_chip_reset_cleanup(vha);
  3475. ql_log(ql_log_info, vha, 0x00b4,
  3476. "Done chip reset cleanup.\n");
  3477. /* Done waiting for pending commands.
  3478. * Reset the online flag.
  3479. */
  3480. vha->flags.online = 0;
  3481. }
  3482. /* Requeue all commands in outstanding command list. */
  3483. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3484. }
  3485. }
  3486. /*
  3487. * qla2x00_abort_isp
  3488. * Resets ISP and aborts all outstanding commands.
  3489. *
  3490. * Input:
  3491. * ha = adapter block pointer.
  3492. *
  3493. * Returns:
  3494. * 0 = success
  3495. */
  3496. int
  3497. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3498. {
  3499. int rval;
  3500. uint8_t status = 0;
  3501. struct qla_hw_data *ha = vha->hw;
  3502. struct scsi_qla_host *vp;
  3503. struct req_que *req = ha->req_q_map[0];
  3504. unsigned long flags;
  3505. if (vha->flags.online) {
  3506. qla2x00_abort_isp_cleanup(vha);
  3507. if (unlikely(pci_channel_offline(ha->pdev) &&
  3508. ha->flags.pci_channel_io_perm_failure)) {
  3509. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3510. status = 0;
  3511. return status;
  3512. }
  3513. ha->isp_ops->get_flash_version(vha, req->ring);
  3514. ha->isp_ops->nvram_config(vha);
  3515. if (!qla2x00_restart_isp(vha)) {
  3516. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3517. if (!atomic_read(&vha->loop_down_timer)) {
  3518. /*
  3519. * Issue marker command only when we are going
  3520. * to start the I/O .
  3521. */
  3522. vha->marker_needed = 1;
  3523. }
  3524. vha->flags.online = 1;
  3525. ha->isp_ops->enable_intrs(ha);
  3526. ha->isp_abort_cnt = 0;
  3527. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3528. if (IS_QLA81XX(ha))
  3529. qla2x00_get_fw_version(vha,
  3530. &ha->fw_major_version,
  3531. &ha->fw_minor_version,
  3532. &ha->fw_subminor_version,
  3533. &ha->fw_attributes, &ha->fw_memory_size,
  3534. ha->mpi_version, &ha->mpi_capabilities,
  3535. ha->phy_version);
  3536. if (ha->fce) {
  3537. ha->flags.fce_enabled = 1;
  3538. memset(ha->fce, 0,
  3539. fce_calc_size(ha->fce_bufs));
  3540. rval = qla2x00_enable_fce_trace(vha,
  3541. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3542. &ha->fce_bufs);
  3543. if (rval) {
  3544. ql_log(ql_log_warn, vha, 0x8033,
  3545. "Unable to reinitialize FCE "
  3546. "(%d).\n", rval);
  3547. ha->flags.fce_enabled = 0;
  3548. }
  3549. }
  3550. if (ha->eft) {
  3551. memset(ha->eft, 0, EFT_SIZE);
  3552. rval = qla2x00_enable_eft_trace(vha,
  3553. ha->eft_dma, EFT_NUM_BUFFERS);
  3554. if (rval) {
  3555. ql_log(ql_log_warn, vha, 0x8034,
  3556. "Unable to reinitialize EFT "
  3557. "(%d).\n", rval);
  3558. }
  3559. }
  3560. } else { /* failed the ISP abort */
  3561. vha->flags.online = 1;
  3562. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3563. if (ha->isp_abort_cnt == 0) {
  3564. ql_log(ql_log_fatal, vha, 0x8035,
  3565. "ISP error recover failed - "
  3566. "board disabled.\n");
  3567. /*
  3568. * The next call disables the board
  3569. * completely.
  3570. */
  3571. ha->isp_ops->reset_adapter(vha);
  3572. vha->flags.online = 0;
  3573. clear_bit(ISP_ABORT_RETRY,
  3574. &vha->dpc_flags);
  3575. status = 0;
  3576. } else { /* schedule another ISP abort */
  3577. ha->isp_abort_cnt--;
  3578. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3579. "ISP abort - retry remaining %d.\n",
  3580. ha->isp_abort_cnt);
  3581. status = 1;
  3582. }
  3583. } else {
  3584. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3585. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3586. "ISP error recovery - retrying (%d) "
  3587. "more times.\n", ha->isp_abort_cnt);
  3588. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3589. status = 1;
  3590. }
  3591. }
  3592. }
  3593. if (!status) {
  3594. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3595. spin_lock_irqsave(&ha->vport_slock, flags);
  3596. list_for_each_entry(vp, &ha->vp_list, list) {
  3597. if (vp->vp_idx) {
  3598. atomic_inc(&vp->vref_count);
  3599. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3600. qla2x00_vp_abort_isp(vp);
  3601. spin_lock_irqsave(&ha->vport_slock, flags);
  3602. atomic_dec(&vp->vref_count);
  3603. }
  3604. }
  3605. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3606. } else {
  3607. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n");
  3608. }
  3609. return(status);
  3610. }
  3611. /*
  3612. * qla2x00_restart_isp
  3613. * restarts the ISP after a reset
  3614. *
  3615. * Input:
  3616. * ha = adapter block pointer.
  3617. *
  3618. * Returns:
  3619. * 0 = success
  3620. */
  3621. static int
  3622. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3623. {
  3624. int status = 0;
  3625. uint32_t wait_time;
  3626. struct qla_hw_data *ha = vha->hw;
  3627. struct req_que *req = ha->req_q_map[0];
  3628. struct rsp_que *rsp = ha->rsp_q_map[0];
  3629. /* If firmware needs to be loaded */
  3630. if (qla2x00_isp_firmware(vha)) {
  3631. vha->flags.online = 0;
  3632. status = ha->isp_ops->chip_diag(vha);
  3633. if (!status)
  3634. status = qla2x00_setup_chip(vha);
  3635. }
  3636. if (!status && !(status = qla2x00_init_rings(vha))) {
  3637. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3638. ha->flags.chip_reset_done = 1;
  3639. /* Initialize the queues in use */
  3640. qla25xx_init_queues(ha);
  3641. status = qla2x00_fw_ready(vha);
  3642. if (!status) {
  3643. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3644. "Start configure loop status = %d.\n", status);
  3645. /* Issue a marker after FW becomes ready. */
  3646. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3647. vha->flags.online = 1;
  3648. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3649. wait_time = 256;
  3650. do {
  3651. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3652. qla2x00_configure_loop(vha);
  3653. wait_time--;
  3654. } while (!atomic_read(&vha->loop_down_timer) &&
  3655. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3656. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3657. &vha->dpc_flags)));
  3658. }
  3659. /* if no cable then assume it's good */
  3660. if ((vha->device_flags & DFLG_NO_CABLE))
  3661. status = 0;
  3662. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3663. "Configure loop done, status = 0x%x.\n", status);
  3664. }
  3665. return (status);
  3666. }
  3667. static int
  3668. qla25xx_init_queues(struct qla_hw_data *ha)
  3669. {
  3670. struct rsp_que *rsp = NULL;
  3671. struct req_que *req = NULL;
  3672. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3673. int ret = -1;
  3674. int i;
  3675. for (i = 1; i < ha->max_rsp_queues; i++) {
  3676. rsp = ha->rsp_q_map[i];
  3677. if (rsp) {
  3678. rsp->options &= ~BIT_0;
  3679. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3680. if (ret != QLA_SUCCESS)
  3681. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3682. "%s Rsp que: %d init failed.\n",
  3683. __func__, rsp->id);
  3684. else
  3685. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3686. "%s Rsp que: %d inited.\n",
  3687. __func__, rsp->id);
  3688. }
  3689. }
  3690. for (i = 1; i < ha->max_req_queues; i++) {
  3691. req = ha->req_q_map[i];
  3692. if (req) {
  3693. /* Clear outstanding commands array. */
  3694. req->options &= ~BIT_0;
  3695. ret = qla25xx_init_req_que(base_vha, req);
  3696. if (ret != QLA_SUCCESS)
  3697. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3698. "%s Req que: %d init failed.\n",
  3699. __func__, req->id);
  3700. else
  3701. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3702. "%s Req que: %d inited.\n",
  3703. __func__, req->id);
  3704. }
  3705. }
  3706. return ret;
  3707. }
  3708. /*
  3709. * qla2x00_reset_adapter
  3710. * Reset adapter.
  3711. *
  3712. * Input:
  3713. * ha = adapter block pointer.
  3714. */
  3715. void
  3716. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3717. {
  3718. unsigned long flags = 0;
  3719. struct qla_hw_data *ha = vha->hw;
  3720. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3721. vha->flags.online = 0;
  3722. ha->isp_ops->disable_intrs(ha);
  3723. spin_lock_irqsave(&ha->hardware_lock, flags);
  3724. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3725. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3726. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3727. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3728. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3729. }
  3730. void
  3731. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3732. {
  3733. unsigned long flags = 0;
  3734. struct qla_hw_data *ha = vha->hw;
  3735. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3736. if (IS_QLA82XX(ha))
  3737. return;
  3738. vha->flags.online = 0;
  3739. ha->isp_ops->disable_intrs(ha);
  3740. spin_lock_irqsave(&ha->hardware_lock, flags);
  3741. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3742. RD_REG_DWORD(&reg->hccr);
  3743. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3744. RD_REG_DWORD(&reg->hccr);
  3745. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3746. if (IS_NOPOLLING_TYPE(ha))
  3747. ha->isp_ops->enable_intrs(ha);
  3748. }
  3749. /* On sparc systems, obtain port and node WWN from firmware
  3750. * properties.
  3751. */
  3752. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3753. struct nvram_24xx *nv)
  3754. {
  3755. #ifdef CONFIG_SPARC
  3756. struct qla_hw_data *ha = vha->hw;
  3757. struct pci_dev *pdev = ha->pdev;
  3758. struct device_node *dp = pci_device_to_OF_node(pdev);
  3759. const u8 *val;
  3760. int len;
  3761. val = of_get_property(dp, "port-wwn", &len);
  3762. if (val && len >= WWN_SIZE)
  3763. memcpy(nv->port_name, val, WWN_SIZE);
  3764. val = of_get_property(dp, "node-wwn", &len);
  3765. if (val && len >= WWN_SIZE)
  3766. memcpy(nv->node_name, val, WWN_SIZE);
  3767. #endif
  3768. }
  3769. int
  3770. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3771. {
  3772. int rval;
  3773. struct init_cb_24xx *icb;
  3774. struct nvram_24xx *nv;
  3775. uint32_t *dptr;
  3776. uint8_t *dptr1, *dptr2;
  3777. uint32_t chksum;
  3778. uint16_t cnt;
  3779. struct qla_hw_data *ha = vha->hw;
  3780. rval = QLA_SUCCESS;
  3781. icb = (struct init_cb_24xx *)ha->init_cb;
  3782. nv = ha->nvram;
  3783. /* Determine NVRAM starting address. */
  3784. if (ha->flags.port0) {
  3785. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3786. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3787. } else {
  3788. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3789. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3790. }
  3791. ha->nvram_size = sizeof(struct nvram_24xx);
  3792. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3793. if (IS_QLA82XX(ha))
  3794. ha->vpd_size = FA_VPD_SIZE_82XX;
  3795. /* Get VPD data into cache */
  3796. ha->vpd = ha->nvram + VPD_OFFSET;
  3797. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3798. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3799. /* Get NVRAM data into cache and calculate checksum. */
  3800. dptr = (uint32_t *)nv;
  3801. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3802. ha->nvram_size);
  3803. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3804. chksum += le32_to_cpu(*dptr++);
  3805. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3806. "Contents of NVRAM\n");
  3807. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3808. (uint8_t *)nv, ha->nvram_size);
  3809. /* Bad NVRAM data, set defaults parameters. */
  3810. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3811. || nv->id[3] != ' ' ||
  3812. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3813. /* Reset NVRAM data. */
  3814. ql_log(ql_log_warn, vha, 0x006b,
  3815. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  3816. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3817. ql_log(ql_log_warn, vha, 0x006c,
  3818. "Falling back to functioning (yet invalid -- WWPN) "
  3819. "defaults.\n");
  3820. /*
  3821. * Set default initialization control block.
  3822. */
  3823. memset(nv, 0, ha->nvram_size);
  3824. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3825. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3826. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3827. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3828. nv->exchange_count = __constant_cpu_to_le16(0);
  3829. nv->hard_address = __constant_cpu_to_le16(124);
  3830. nv->port_name[0] = 0x21;
  3831. nv->port_name[1] = 0x00 + ha->port_no;
  3832. nv->port_name[2] = 0x00;
  3833. nv->port_name[3] = 0xe0;
  3834. nv->port_name[4] = 0x8b;
  3835. nv->port_name[5] = 0x1c;
  3836. nv->port_name[6] = 0x55;
  3837. nv->port_name[7] = 0x86;
  3838. nv->node_name[0] = 0x20;
  3839. nv->node_name[1] = 0x00;
  3840. nv->node_name[2] = 0x00;
  3841. nv->node_name[3] = 0xe0;
  3842. nv->node_name[4] = 0x8b;
  3843. nv->node_name[5] = 0x1c;
  3844. nv->node_name[6] = 0x55;
  3845. nv->node_name[7] = 0x86;
  3846. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3847. nv->login_retry_count = __constant_cpu_to_le16(8);
  3848. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3849. nv->login_timeout = __constant_cpu_to_le16(0);
  3850. nv->firmware_options_1 =
  3851. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3852. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3853. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3854. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3855. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3856. nv->efi_parameters = __constant_cpu_to_le32(0);
  3857. nv->reset_delay = 5;
  3858. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3859. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3860. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3861. rval = 1;
  3862. }
  3863. /* Reset Initialization control block */
  3864. memset(icb, 0, ha->init_cb_size);
  3865. /* Copy 1st segment. */
  3866. dptr1 = (uint8_t *)icb;
  3867. dptr2 = (uint8_t *)&nv->version;
  3868. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3869. while (cnt--)
  3870. *dptr1++ = *dptr2++;
  3871. icb->login_retry_count = nv->login_retry_count;
  3872. icb->link_down_on_nos = nv->link_down_on_nos;
  3873. /* Copy 2nd segment. */
  3874. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3875. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3876. cnt = (uint8_t *)&icb->reserved_3 -
  3877. (uint8_t *)&icb->interrupt_delay_timer;
  3878. while (cnt--)
  3879. *dptr1++ = *dptr2++;
  3880. /*
  3881. * Setup driver NVRAM options.
  3882. */
  3883. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3884. "QLA2462");
  3885. /* Use alternate WWN? */
  3886. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3887. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3888. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3889. }
  3890. /* Prepare nodename */
  3891. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3892. /*
  3893. * Firmware will apply the following mask if the nodename was
  3894. * not provided.
  3895. */
  3896. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3897. icb->node_name[0] &= 0xF0;
  3898. }
  3899. /* Set host adapter parameters. */
  3900. ha->flags.disable_risc_code_load = 0;
  3901. ha->flags.enable_lip_reset = 0;
  3902. ha->flags.enable_lip_full_login =
  3903. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3904. ha->flags.enable_target_reset =
  3905. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3906. ha->flags.enable_led_scheme = 0;
  3907. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3908. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3909. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3910. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3911. sizeof(ha->fw_seriallink_options24));
  3912. /* save HBA serial number */
  3913. ha->serial0 = icb->port_name[5];
  3914. ha->serial1 = icb->port_name[6];
  3915. ha->serial2 = icb->port_name[7];
  3916. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3917. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3918. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3919. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3920. /* Set minimum login_timeout to 4 seconds. */
  3921. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3922. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3923. if (le16_to_cpu(nv->login_timeout) < 4)
  3924. nv->login_timeout = __constant_cpu_to_le16(4);
  3925. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3926. icb->login_timeout = nv->login_timeout;
  3927. /* Set minimum RATOV to 100 tenths of a second. */
  3928. ha->r_a_tov = 100;
  3929. ha->loop_reset_delay = nv->reset_delay;
  3930. /* Link Down Timeout = 0:
  3931. *
  3932. * When Port Down timer expires we will start returning
  3933. * I/O's to OS with "DID_NO_CONNECT".
  3934. *
  3935. * Link Down Timeout != 0:
  3936. *
  3937. * The driver waits for the link to come up after link down
  3938. * before returning I/Os to OS with "DID_NO_CONNECT".
  3939. */
  3940. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3941. ha->loop_down_abort_time =
  3942. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3943. } else {
  3944. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3945. ha->loop_down_abort_time =
  3946. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3947. }
  3948. /* Need enough time to try and get the port back. */
  3949. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3950. if (qlport_down_retry)
  3951. ha->port_down_retry_count = qlport_down_retry;
  3952. /* Set login_retry_count */
  3953. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3954. if (ha->port_down_retry_count ==
  3955. le16_to_cpu(nv->port_down_retry_count) &&
  3956. ha->port_down_retry_count > 3)
  3957. ha->login_retry_count = ha->port_down_retry_count;
  3958. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3959. ha->login_retry_count = ha->port_down_retry_count;
  3960. if (ql2xloginretrycount)
  3961. ha->login_retry_count = ql2xloginretrycount;
  3962. /* Enable ZIO. */
  3963. if (!vha->flags.init_done) {
  3964. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3965. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3966. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3967. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3968. }
  3969. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3970. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3971. vha->flags.process_response_queue = 0;
  3972. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3973. ha->zio_mode = QLA_ZIO_MODE_6;
  3974. ql_log(ql_log_info, vha, 0x006f,
  3975. "ZIO mode %d enabled; timer delay (%d us).\n",
  3976. ha->zio_mode, ha->zio_timer * 100);
  3977. icb->firmware_options_2 |= cpu_to_le32(
  3978. (uint32_t)ha->zio_mode);
  3979. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3980. vha->flags.process_response_queue = 1;
  3981. }
  3982. if (rval) {
  3983. ql_log(ql_log_warn, vha, 0x0070,
  3984. "NVRAM configuration failed.\n");
  3985. }
  3986. return (rval);
  3987. }
  3988. static int
  3989. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  3990. uint32_t faddr)
  3991. {
  3992. int rval = QLA_SUCCESS;
  3993. int segments, fragment;
  3994. uint32_t *dcode, dlen;
  3995. uint32_t risc_addr;
  3996. uint32_t risc_size;
  3997. uint32_t i;
  3998. struct qla_hw_data *ha = vha->hw;
  3999. struct req_que *req = ha->req_q_map[0];
  4000. ql_dbg(ql_dbg_init, vha, 0x008b,
  4001. "Loading firmware from flash (%x).\n", faddr);
  4002. rval = QLA_SUCCESS;
  4003. segments = FA_RISC_CODE_SEGMENTS;
  4004. dcode = (uint32_t *)req->ring;
  4005. *srisc_addr = 0;
  4006. /* Validate firmware image by checking version. */
  4007. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  4008. for (i = 0; i < 4; i++)
  4009. dcode[i] = be32_to_cpu(dcode[i]);
  4010. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4011. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4012. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4013. dcode[3] == 0)) {
  4014. ql_log(ql_log_fatal, vha, 0x008c,
  4015. "Unable to verify the integrity of flash firmware "
  4016. "image.\n");
  4017. ql_log(ql_log_fatal, vha, 0x008d,
  4018. "Firmware data: %08x %08x %08x %08x.\n",
  4019. dcode[0], dcode[1], dcode[2], dcode[3]);
  4020. return QLA_FUNCTION_FAILED;
  4021. }
  4022. while (segments && rval == QLA_SUCCESS) {
  4023. /* Read segment's load information. */
  4024. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  4025. risc_addr = be32_to_cpu(dcode[2]);
  4026. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4027. risc_size = be32_to_cpu(dcode[3]);
  4028. fragment = 0;
  4029. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4030. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4031. if (dlen > risc_size)
  4032. dlen = risc_size;
  4033. ql_dbg(ql_dbg_init, vha, 0x008e,
  4034. "Loading risc segment@ risc addr %x "
  4035. "number of dwords 0x%x offset 0x%x.\n",
  4036. risc_addr, dlen, faddr);
  4037. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  4038. for (i = 0; i < dlen; i++)
  4039. dcode[i] = swab32(dcode[i]);
  4040. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4041. dlen);
  4042. if (rval) {
  4043. ql_log(ql_log_fatal, vha, 0x008f,
  4044. "Failed to load segment %d of firmware.\n",
  4045. fragment);
  4046. break;
  4047. }
  4048. faddr += dlen;
  4049. risc_addr += dlen;
  4050. risc_size -= dlen;
  4051. fragment++;
  4052. }
  4053. /* Next segment. */
  4054. segments--;
  4055. }
  4056. return rval;
  4057. }
  4058. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  4059. int
  4060. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4061. {
  4062. int rval;
  4063. int i, fragment;
  4064. uint16_t *wcode, *fwcode;
  4065. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  4066. struct fw_blob *blob;
  4067. struct qla_hw_data *ha = vha->hw;
  4068. struct req_que *req = ha->req_q_map[0];
  4069. /* Load firmware blob. */
  4070. blob = qla2x00_request_firmware(vha);
  4071. if (!blob) {
  4072. ql_log(ql_log_info, vha, 0x0083,
  4073. "Fimware image unavailable.\n");
  4074. ql_log(ql_log_info, vha, 0x0084,
  4075. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  4076. return QLA_FUNCTION_FAILED;
  4077. }
  4078. rval = QLA_SUCCESS;
  4079. wcode = (uint16_t *)req->ring;
  4080. *srisc_addr = 0;
  4081. fwcode = (uint16_t *)blob->fw->data;
  4082. fwclen = 0;
  4083. /* Validate firmware image by checking version. */
  4084. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  4085. ql_log(ql_log_fatal, vha, 0x0085,
  4086. "Unable to verify integrity of firmware image (%Zd).\n",
  4087. blob->fw->size);
  4088. goto fail_fw_integrity;
  4089. }
  4090. for (i = 0; i < 4; i++)
  4091. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  4092. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  4093. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  4094. wcode[2] == 0 && wcode[3] == 0)) {
  4095. ql_log(ql_log_fatal, vha, 0x0086,
  4096. "Unable to verify integrity of firmware image.\n");
  4097. ql_log(ql_log_fatal, vha, 0x0087,
  4098. "Firmware data: %04x %04x %04x %04x.\n",
  4099. wcode[0], wcode[1], wcode[2], wcode[3]);
  4100. goto fail_fw_integrity;
  4101. }
  4102. seg = blob->segs;
  4103. while (*seg && rval == QLA_SUCCESS) {
  4104. risc_addr = *seg;
  4105. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  4106. risc_size = be16_to_cpu(fwcode[3]);
  4107. /* Validate firmware image size. */
  4108. fwclen += risc_size * sizeof(uint16_t);
  4109. if (blob->fw->size < fwclen) {
  4110. ql_log(ql_log_fatal, vha, 0x0088,
  4111. "Unable to verify integrity of firmware image "
  4112. "(%Zd).\n", blob->fw->size);
  4113. goto fail_fw_integrity;
  4114. }
  4115. fragment = 0;
  4116. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4117. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  4118. if (wlen > risc_size)
  4119. wlen = risc_size;
  4120. ql_dbg(ql_dbg_init, vha, 0x0089,
  4121. "Loading risc segment@ risc addr %x number of "
  4122. "words 0x%x.\n", risc_addr, wlen);
  4123. for (i = 0; i < wlen; i++)
  4124. wcode[i] = swab16(fwcode[i]);
  4125. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4126. wlen);
  4127. if (rval) {
  4128. ql_log(ql_log_fatal, vha, 0x008a,
  4129. "Failed to load segment %d of firmware.\n",
  4130. fragment);
  4131. break;
  4132. }
  4133. fwcode += wlen;
  4134. risc_addr += wlen;
  4135. risc_size -= wlen;
  4136. fragment++;
  4137. }
  4138. /* Next segment. */
  4139. seg++;
  4140. }
  4141. return rval;
  4142. fail_fw_integrity:
  4143. return QLA_FUNCTION_FAILED;
  4144. }
  4145. static int
  4146. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4147. {
  4148. int rval;
  4149. int segments, fragment;
  4150. uint32_t *dcode, dlen;
  4151. uint32_t risc_addr;
  4152. uint32_t risc_size;
  4153. uint32_t i;
  4154. struct fw_blob *blob;
  4155. uint32_t *fwcode, fwclen;
  4156. struct qla_hw_data *ha = vha->hw;
  4157. struct req_que *req = ha->req_q_map[0];
  4158. /* Load firmware blob. */
  4159. blob = qla2x00_request_firmware(vha);
  4160. if (!blob) {
  4161. ql_log(ql_log_warn, vha, 0x0090,
  4162. "Fimware image unavailable.\n");
  4163. ql_log(ql_log_warn, vha, 0x0091,
  4164. "Firmware images can be retrieved from: "
  4165. QLA_FW_URL ".\n");
  4166. return QLA_FUNCTION_FAILED;
  4167. }
  4168. ql_log(ql_log_info, vha, 0x0092,
  4169. "Loading via request-firmware.\n");
  4170. rval = QLA_SUCCESS;
  4171. segments = FA_RISC_CODE_SEGMENTS;
  4172. dcode = (uint32_t *)req->ring;
  4173. *srisc_addr = 0;
  4174. fwcode = (uint32_t *)blob->fw->data;
  4175. fwclen = 0;
  4176. /* Validate firmware image by checking version. */
  4177. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4178. ql_log(ql_log_fatal, vha, 0x0093,
  4179. "Unable to verify integrity of firmware image (%Zd).\n",
  4180. blob->fw->size);
  4181. goto fail_fw_integrity;
  4182. }
  4183. for (i = 0; i < 4; i++)
  4184. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4185. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4186. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4187. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4188. dcode[3] == 0)) {
  4189. ql_log(ql_log_fatal, vha, 0x0094,
  4190. "Unable to verify integrity of firmware image (%Zd).\n",
  4191. blob->fw->size);
  4192. ql_log(ql_log_fatal, vha, 0x0095,
  4193. "Firmware data: %08x %08x %08x %08x.\n",
  4194. dcode[0], dcode[1], dcode[2], dcode[3]);
  4195. goto fail_fw_integrity;
  4196. }
  4197. while (segments && rval == QLA_SUCCESS) {
  4198. risc_addr = be32_to_cpu(fwcode[2]);
  4199. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4200. risc_size = be32_to_cpu(fwcode[3]);
  4201. /* Validate firmware image size. */
  4202. fwclen += risc_size * sizeof(uint32_t);
  4203. if (blob->fw->size < fwclen) {
  4204. ql_log(ql_log_fatal, vha, 0x0096,
  4205. "Unable to verify integrity of firmware image "
  4206. "(%Zd).\n", blob->fw->size);
  4207. goto fail_fw_integrity;
  4208. }
  4209. fragment = 0;
  4210. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4211. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4212. if (dlen > risc_size)
  4213. dlen = risc_size;
  4214. ql_dbg(ql_dbg_init, vha, 0x0097,
  4215. "Loading risc segment@ risc addr %x "
  4216. "number of dwords 0x%x.\n", risc_addr, dlen);
  4217. for (i = 0; i < dlen; i++)
  4218. dcode[i] = swab32(fwcode[i]);
  4219. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4220. dlen);
  4221. if (rval) {
  4222. ql_log(ql_log_fatal, vha, 0x0098,
  4223. "Failed to load segment %d of firmware.\n",
  4224. fragment);
  4225. break;
  4226. }
  4227. fwcode += dlen;
  4228. risc_addr += dlen;
  4229. risc_size -= dlen;
  4230. fragment++;
  4231. }
  4232. /* Next segment. */
  4233. segments--;
  4234. }
  4235. return rval;
  4236. fail_fw_integrity:
  4237. return QLA_FUNCTION_FAILED;
  4238. }
  4239. int
  4240. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4241. {
  4242. int rval;
  4243. if (ql2xfwloadbin == 1)
  4244. return qla81xx_load_risc(vha, srisc_addr);
  4245. /*
  4246. * FW Load priority:
  4247. * 1) Firmware via request-firmware interface (.bin file).
  4248. * 2) Firmware residing in flash.
  4249. */
  4250. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4251. if (rval == QLA_SUCCESS)
  4252. return rval;
  4253. return qla24xx_load_risc_flash(vha, srisc_addr,
  4254. vha->hw->flt_region_fw);
  4255. }
  4256. int
  4257. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4258. {
  4259. int rval;
  4260. struct qla_hw_data *ha = vha->hw;
  4261. if (ql2xfwloadbin == 2)
  4262. goto try_blob_fw;
  4263. /*
  4264. * FW Load priority:
  4265. * 1) Firmware residing in flash.
  4266. * 2) Firmware via request-firmware interface (.bin file).
  4267. * 3) Golden-Firmware residing in flash -- limited operation.
  4268. */
  4269. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4270. if (rval == QLA_SUCCESS)
  4271. return rval;
  4272. try_blob_fw:
  4273. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4274. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4275. return rval;
  4276. ql_log(ql_log_info, vha, 0x0099,
  4277. "Attempting to fallback to golden firmware.\n");
  4278. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4279. if (rval != QLA_SUCCESS)
  4280. return rval;
  4281. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4282. ha->flags.running_gold_fw = 1;
  4283. return rval;
  4284. }
  4285. void
  4286. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4287. {
  4288. int ret, retries;
  4289. struct qla_hw_data *ha = vha->hw;
  4290. if (ha->flags.pci_channel_io_perm_failure)
  4291. return;
  4292. if (!IS_FWI2_CAPABLE(ha))
  4293. return;
  4294. if (!ha->fw_major_version)
  4295. return;
  4296. ret = qla2x00_stop_firmware(vha);
  4297. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4298. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4299. ha->isp_ops->reset_chip(vha);
  4300. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4301. continue;
  4302. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4303. continue;
  4304. ql_log(ql_log_info, vha, 0x8015,
  4305. "Attempting retry of stop-firmware command.\n");
  4306. ret = qla2x00_stop_firmware(vha);
  4307. }
  4308. }
  4309. int
  4310. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4311. {
  4312. int rval = QLA_SUCCESS;
  4313. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4314. struct qla_hw_data *ha = vha->hw;
  4315. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4316. struct req_que *req;
  4317. struct rsp_que *rsp;
  4318. if (!vha->vp_idx)
  4319. return -EINVAL;
  4320. rval = qla2x00_fw_ready(base_vha);
  4321. if (ha->flags.cpu_affinity_enabled)
  4322. req = ha->req_q_map[0];
  4323. else
  4324. req = vha->req;
  4325. rsp = req->rsp;
  4326. if (rval == QLA_SUCCESS) {
  4327. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4328. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4329. }
  4330. vha->flags.management_server_logged_in = 0;
  4331. /* Login to SNS first */
  4332. ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, BIT_1);
  4333. if (mb[0] != MBS_COMMAND_COMPLETE) {
  4334. ql_dbg(ql_dbg_init, vha, 0x0103,
  4335. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  4336. "mb[6]=%x mb[7]=%x.\n",
  4337. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4338. return (QLA_FUNCTION_FAILED);
  4339. }
  4340. atomic_set(&vha->loop_down_timer, 0);
  4341. atomic_set(&vha->loop_state, LOOP_UP);
  4342. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4343. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4344. rval = qla2x00_loop_resync(base_vha);
  4345. return rval;
  4346. }
  4347. /* 84XX Support **************************************************************/
  4348. static LIST_HEAD(qla_cs84xx_list);
  4349. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4350. static struct qla_chip_state_84xx *
  4351. qla84xx_get_chip(struct scsi_qla_host *vha)
  4352. {
  4353. struct qla_chip_state_84xx *cs84xx;
  4354. struct qla_hw_data *ha = vha->hw;
  4355. mutex_lock(&qla_cs84xx_mutex);
  4356. /* Find any shared 84xx chip. */
  4357. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4358. if (cs84xx->bus == ha->pdev->bus) {
  4359. kref_get(&cs84xx->kref);
  4360. goto done;
  4361. }
  4362. }
  4363. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4364. if (!cs84xx)
  4365. goto done;
  4366. kref_init(&cs84xx->kref);
  4367. spin_lock_init(&cs84xx->access_lock);
  4368. mutex_init(&cs84xx->fw_update_mutex);
  4369. cs84xx->bus = ha->pdev->bus;
  4370. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4371. done:
  4372. mutex_unlock(&qla_cs84xx_mutex);
  4373. return cs84xx;
  4374. }
  4375. static void
  4376. __qla84xx_chip_release(struct kref *kref)
  4377. {
  4378. struct qla_chip_state_84xx *cs84xx =
  4379. container_of(kref, struct qla_chip_state_84xx, kref);
  4380. mutex_lock(&qla_cs84xx_mutex);
  4381. list_del(&cs84xx->list);
  4382. mutex_unlock(&qla_cs84xx_mutex);
  4383. kfree(cs84xx);
  4384. }
  4385. void
  4386. qla84xx_put_chip(struct scsi_qla_host *vha)
  4387. {
  4388. struct qla_hw_data *ha = vha->hw;
  4389. if (ha->cs84xx)
  4390. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4391. }
  4392. static int
  4393. qla84xx_init_chip(scsi_qla_host_t *vha)
  4394. {
  4395. int rval;
  4396. uint16_t status[2];
  4397. struct qla_hw_data *ha = vha->hw;
  4398. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4399. rval = qla84xx_verify_chip(vha, status);
  4400. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4401. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4402. QLA_SUCCESS;
  4403. }
  4404. /* 81XX Support **************************************************************/
  4405. int
  4406. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4407. {
  4408. int rval;
  4409. struct init_cb_81xx *icb;
  4410. struct nvram_81xx *nv;
  4411. uint32_t *dptr;
  4412. uint8_t *dptr1, *dptr2;
  4413. uint32_t chksum;
  4414. uint16_t cnt;
  4415. struct qla_hw_data *ha = vha->hw;
  4416. rval = QLA_SUCCESS;
  4417. icb = (struct init_cb_81xx *)ha->init_cb;
  4418. nv = ha->nvram;
  4419. /* Determine NVRAM starting address. */
  4420. ha->nvram_size = sizeof(struct nvram_81xx);
  4421. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4422. /* Get VPD data into cache */
  4423. ha->vpd = ha->nvram + VPD_OFFSET;
  4424. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4425. ha->vpd_size);
  4426. /* Get NVRAM data into cache and calculate checksum. */
  4427. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4428. ha->nvram_size);
  4429. dptr = (uint32_t *)nv;
  4430. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4431. chksum += le32_to_cpu(*dptr++);
  4432. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4433. "Contents of NVRAM:\n");
  4434. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4435. (uint8_t *)nv, ha->nvram_size);
  4436. /* Bad NVRAM data, set defaults parameters. */
  4437. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4438. || nv->id[3] != ' ' ||
  4439. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4440. /* Reset NVRAM data. */
  4441. ql_log(ql_log_info, vha, 0x0073,
  4442. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  4443. "version=0x%x.\n", chksum, nv->id[0],
  4444. le16_to_cpu(nv->nvram_version));
  4445. ql_log(ql_log_info, vha, 0x0074,
  4446. "Falling back to functioning (yet invalid -- WWPN) "
  4447. "defaults.\n");
  4448. /*
  4449. * Set default initialization control block.
  4450. */
  4451. memset(nv, 0, ha->nvram_size);
  4452. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4453. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4454. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4455. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4456. nv->exchange_count = __constant_cpu_to_le16(0);
  4457. nv->port_name[0] = 0x21;
  4458. nv->port_name[1] = 0x00 + ha->port_no;
  4459. nv->port_name[2] = 0x00;
  4460. nv->port_name[3] = 0xe0;
  4461. nv->port_name[4] = 0x8b;
  4462. nv->port_name[5] = 0x1c;
  4463. nv->port_name[6] = 0x55;
  4464. nv->port_name[7] = 0x86;
  4465. nv->node_name[0] = 0x20;
  4466. nv->node_name[1] = 0x00;
  4467. nv->node_name[2] = 0x00;
  4468. nv->node_name[3] = 0xe0;
  4469. nv->node_name[4] = 0x8b;
  4470. nv->node_name[5] = 0x1c;
  4471. nv->node_name[6] = 0x55;
  4472. nv->node_name[7] = 0x86;
  4473. nv->login_retry_count = __constant_cpu_to_le16(8);
  4474. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4475. nv->login_timeout = __constant_cpu_to_le16(0);
  4476. nv->firmware_options_1 =
  4477. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4478. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4479. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4480. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4481. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4482. nv->efi_parameters = __constant_cpu_to_le32(0);
  4483. nv->reset_delay = 5;
  4484. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4485. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4486. nv->link_down_timeout = __constant_cpu_to_le16(30);
  4487. nv->enode_mac[0] = 0x00;
  4488. nv->enode_mac[1] = 0x02;
  4489. nv->enode_mac[2] = 0x03;
  4490. nv->enode_mac[3] = 0x04;
  4491. nv->enode_mac[4] = 0x05;
  4492. nv->enode_mac[5] = 0x06 + ha->port_no;
  4493. rval = 1;
  4494. }
  4495. /* Reset Initialization control block */
  4496. memset(icb, 0, ha->init_cb_size);
  4497. /* Copy 1st segment. */
  4498. dptr1 = (uint8_t *)icb;
  4499. dptr2 = (uint8_t *)&nv->version;
  4500. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4501. while (cnt--)
  4502. *dptr1++ = *dptr2++;
  4503. icb->login_retry_count = nv->login_retry_count;
  4504. /* Copy 2nd segment. */
  4505. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4506. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4507. cnt = (uint8_t *)&icb->reserved_5 -
  4508. (uint8_t *)&icb->interrupt_delay_timer;
  4509. while (cnt--)
  4510. *dptr1++ = *dptr2++;
  4511. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4512. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4513. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4514. icb->enode_mac[0] = 0x01;
  4515. icb->enode_mac[1] = 0x02;
  4516. icb->enode_mac[2] = 0x03;
  4517. icb->enode_mac[3] = 0x04;
  4518. icb->enode_mac[4] = 0x05;
  4519. icb->enode_mac[5] = 0x06 + ha->port_no;
  4520. }
  4521. /* Use extended-initialization control block. */
  4522. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4523. /*
  4524. * Setup driver NVRAM options.
  4525. */
  4526. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4527. "QLE8XXX");
  4528. /* Use alternate WWN? */
  4529. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4530. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4531. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4532. }
  4533. /* Prepare nodename */
  4534. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4535. /*
  4536. * Firmware will apply the following mask if the nodename was
  4537. * not provided.
  4538. */
  4539. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4540. icb->node_name[0] &= 0xF0;
  4541. }
  4542. /* Set host adapter parameters. */
  4543. ha->flags.disable_risc_code_load = 0;
  4544. ha->flags.enable_lip_reset = 0;
  4545. ha->flags.enable_lip_full_login =
  4546. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4547. ha->flags.enable_target_reset =
  4548. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4549. ha->flags.enable_led_scheme = 0;
  4550. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4551. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4552. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4553. /* save HBA serial number */
  4554. ha->serial0 = icb->port_name[5];
  4555. ha->serial1 = icb->port_name[6];
  4556. ha->serial2 = icb->port_name[7];
  4557. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4558. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4559. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4560. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4561. /* Set minimum login_timeout to 4 seconds. */
  4562. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4563. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4564. if (le16_to_cpu(nv->login_timeout) < 4)
  4565. nv->login_timeout = __constant_cpu_to_le16(4);
  4566. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4567. icb->login_timeout = nv->login_timeout;
  4568. /* Set minimum RATOV to 100 tenths of a second. */
  4569. ha->r_a_tov = 100;
  4570. ha->loop_reset_delay = nv->reset_delay;
  4571. /* Link Down Timeout = 0:
  4572. *
  4573. * When Port Down timer expires we will start returning
  4574. * I/O's to OS with "DID_NO_CONNECT".
  4575. *
  4576. * Link Down Timeout != 0:
  4577. *
  4578. * The driver waits for the link to come up after link down
  4579. * before returning I/Os to OS with "DID_NO_CONNECT".
  4580. */
  4581. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4582. ha->loop_down_abort_time =
  4583. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4584. } else {
  4585. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4586. ha->loop_down_abort_time =
  4587. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4588. }
  4589. /* Need enough time to try and get the port back. */
  4590. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4591. if (qlport_down_retry)
  4592. ha->port_down_retry_count = qlport_down_retry;
  4593. /* Set login_retry_count */
  4594. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4595. if (ha->port_down_retry_count ==
  4596. le16_to_cpu(nv->port_down_retry_count) &&
  4597. ha->port_down_retry_count > 3)
  4598. ha->login_retry_count = ha->port_down_retry_count;
  4599. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4600. ha->login_retry_count = ha->port_down_retry_count;
  4601. if (ql2xloginretrycount)
  4602. ha->login_retry_count = ql2xloginretrycount;
  4603. /* Enable ZIO. */
  4604. if (!vha->flags.init_done) {
  4605. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4606. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4607. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4608. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4609. }
  4610. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4611. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4612. vha->flags.process_response_queue = 0;
  4613. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4614. ha->zio_mode = QLA_ZIO_MODE_6;
  4615. ql_log(ql_log_info, vha, 0x0075,
  4616. "ZIO mode %d enabled; timer delay (%d us).\n",
  4617. ha->zio_mode,
  4618. ha->zio_timer * 100);
  4619. icb->firmware_options_2 |= cpu_to_le32(
  4620. (uint32_t)ha->zio_mode);
  4621. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4622. vha->flags.process_response_queue = 1;
  4623. }
  4624. if (rval) {
  4625. ql_log(ql_log_warn, vha, 0x0076,
  4626. "NVRAM configuration failed.\n");
  4627. }
  4628. return (rval);
  4629. }
  4630. int
  4631. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4632. {
  4633. int status, rval;
  4634. uint32_t wait_time;
  4635. struct qla_hw_data *ha = vha->hw;
  4636. struct req_que *req = ha->req_q_map[0];
  4637. struct rsp_que *rsp = ha->rsp_q_map[0];
  4638. struct scsi_qla_host *vp;
  4639. unsigned long flags;
  4640. status = qla2x00_init_rings(vha);
  4641. if (!status) {
  4642. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4643. ha->flags.chip_reset_done = 1;
  4644. status = qla2x00_fw_ready(vha);
  4645. if (!status) {
  4646. ql_log(ql_log_info, vha, 0x803c,
  4647. "Start configure loop, status =%d.\n", status);
  4648. /* Issue a marker after FW becomes ready. */
  4649. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4650. vha->flags.online = 1;
  4651. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4652. wait_time = 256;
  4653. do {
  4654. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4655. qla2x00_configure_loop(vha);
  4656. wait_time--;
  4657. } while (!atomic_read(&vha->loop_down_timer) &&
  4658. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4659. wait_time &&
  4660. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4661. }
  4662. /* if no cable then assume it's good */
  4663. if ((vha->device_flags & DFLG_NO_CABLE))
  4664. status = 0;
  4665. ql_log(ql_log_info, vha, 0x803d,
  4666. "Configure loop done, status = 0x%x.\n", status);
  4667. }
  4668. if (!status) {
  4669. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4670. if (!atomic_read(&vha->loop_down_timer)) {
  4671. /*
  4672. * Issue marker command only when we are going
  4673. * to start the I/O .
  4674. */
  4675. vha->marker_needed = 1;
  4676. }
  4677. vha->flags.online = 1;
  4678. ha->isp_ops->enable_intrs(ha);
  4679. ha->isp_abort_cnt = 0;
  4680. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4681. /* Update the firmware version */
  4682. qla2x00_get_fw_version(vha, &ha->fw_major_version,
  4683. &ha->fw_minor_version, &ha->fw_subminor_version,
  4684. &ha->fw_attributes, &ha->fw_memory_size,
  4685. ha->mpi_version, &ha->mpi_capabilities,
  4686. ha->phy_version);
  4687. if (ha->fce) {
  4688. ha->flags.fce_enabled = 1;
  4689. memset(ha->fce, 0,
  4690. fce_calc_size(ha->fce_bufs));
  4691. rval = qla2x00_enable_fce_trace(vha,
  4692. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4693. &ha->fce_bufs);
  4694. if (rval) {
  4695. ql_log(ql_log_warn, vha, 0x803e,
  4696. "Unable to reinitialize FCE (%d).\n",
  4697. rval);
  4698. ha->flags.fce_enabled = 0;
  4699. }
  4700. }
  4701. if (ha->eft) {
  4702. memset(ha->eft, 0, EFT_SIZE);
  4703. rval = qla2x00_enable_eft_trace(vha,
  4704. ha->eft_dma, EFT_NUM_BUFFERS);
  4705. if (rval) {
  4706. ql_log(ql_log_warn, vha, 0x803f,
  4707. "Unable to reinitialize EFT (%d).\n",
  4708. rval);
  4709. }
  4710. }
  4711. }
  4712. if (!status) {
  4713. ql_dbg(ql_dbg_taskm, vha, 0x8040,
  4714. "qla82xx_restart_isp succeeded.\n");
  4715. spin_lock_irqsave(&ha->vport_slock, flags);
  4716. list_for_each_entry(vp, &ha->vp_list, list) {
  4717. if (vp->vp_idx) {
  4718. atomic_inc(&vp->vref_count);
  4719. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4720. qla2x00_vp_abort_isp(vp);
  4721. spin_lock_irqsave(&ha->vport_slock, flags);
  4722. atomic_dec(&vp->vref_count);
  4723. }
  4724. }
  4725. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4726. } else {
  4727. ql_log(ql_log_warn, vha, 0x8041,
  4728. "qla82xx_restart_isp **** FAILED ****.\n");
  4729. }
  4730. return status;
  4731. }
  4732. void
  4733. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4734. {
  4735. struct qla_hw_data *ha = vha->hw;
  4736. if (!ql2xetsenable)
  4737. return;
  4738. /* Enable ETS Burst. */
  4739. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4740. ha->fw_options[2] |= BIT_9;
  4741. qla2x00_set_fw_options(vha, ha->fw_options);
  4742. }
  4743. /*
  4744. * qla24xx_get_fcp_prio
  4745. * Gets the fcp cmd priority value for the logged in port.
  4746. * Looks for a match of the port descriptors within
  4747. * each of the fcp prio config entries. If a match is found,
  4748. * the tag (priority) value is returned.
  4749. *
  4750. * Input:
  4751. * vha = scsi host structure pointer.
  4752. * fcport = port structure pointer.
  4753. *
  4754. * Return:
  4755. * non-zero (if found)
  4756. * -1 (if not found)
  4757. *
  4758. * Context:
  4759. * Kernel context
  4760. */
  4761. static int
  4762. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4763. {
  4764. int i, entries;
  4765. uint8_t pid_match, wwn_match;
  4766. int priority;
  4767. uint32_t pid1, pid2;
  4768. uint64_t wwn1, wwn2;
  4769. struct qla_fcp_prio_entry *pri_entry;
  4770. struct qla_hw_data *ha = vha->hw;
  4771. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4772. return -1;
  4773. priority = -1;
  4774. entries = ha->fcp_prio_cfg->num_entries;
  4775. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4776. for (i = 0; i < entries; i++) {
  4777. pid_match = wwn_match = 0;
  4778. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4779. pri_entry++;
  4780. continue;
  4781. }
  4782. /* check source pid for a match */
  4783. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4784. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4785. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4786. if (pid1 == INVALID_PORT_ID)
  4787. pid_match++;
  4788. else if (pid1 == pid2)
  4789. pid_match++;
  4790. }
  4791. /* check destination pid for a match */
  4792. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4793. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4794. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4795. if (pid1 == INVALID_PORT_ID)
  4796. pid_match++;
  4797. else if (pid1 == pid2)
  4798. pid_match++;
  4799. }
  4800. /* check source WWN for a match */
  4801. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4802. wwn1 = wwn_to_u64(vha->port_name);
  4803. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4804. if (wwn2 == (uint64_t)-1)
  4805. wwn_match++;
  4806. else if (wwn1 == wwn2)
  4807. wwn_match++;
  4808. }
  4809. /* check destination WWN for a match */
  4810. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4811. wwn1 = wwn_to_u64(fcport->port_name);
  4812. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4813. if (wwn2 == (uint64_t)-1)
  4814. wwn_match++;
  4815. else if (wwn1 == wwn2)
  4816. wwn_match++;
  4817. }
  4818. if (pid_match == 2 || wwn_match == 2) {
  4819. /* Found a matching entry */
  4820. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4821. priority = pri_entry->tag;
  4822. break;
  4823. }
  4824. pri_entry++;
  4825. }
  4826. return priority;
  4827. }
  4828. /*
  4829. * qla24xx_update_fcport_fcp_prio
  4830. * Activates fcp priority for the logged in fc port
  4831. *
  4832. * Input:
  4833. * vha = scsi host structure pointer.
  4834. * fcp = port structure pointer.
  4835. *
  4836. * Return:
  4837. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4838. *
  4839. * Context:
  4840. * Kernel context.
  4841. */
  4842. int
  4843. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4844. {
  4845. int ret;
  4846. int priority;
  4847. uint16_t mb[5];
  4848. if (fcport->port_type != FCT_TARGET ||
  4849. fcport->loop_id == FC_NO_LOOP_ID)
  4850. return QLA_FUNCTION_FAILED;
  4851. priority = qla24xx_get_fcp_prio(vha, fcport);
  4852. if (priority < 0)
  4853. return QLA_FUNCTION_FAILED;
  4854. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4855. if (ret == QLA_SUCCESS)
  4856. fcport->fcp_prio = priority;
  4857. else
  4858. ql_dbg(ql_dbg_user, vha, 0x704f,
  4859. "Unable to activate fcp priority, ret=0x%x.\n", ret);
  4860. return ret;
  4861. }
  4862. /*
  4863. * qla24xx_update_all_fcp_prio
  4864. * Activates fcp priority for all the logged in ports
  4865. *
  4866. * Input:
  4867. * ha = adapter block pointer.
  4868. *
  4869. * Return:
  4870. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4871. *
  4872. * Context:
  4873. * Kernel context.
  4874. */
  4875. int
  4876. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4877. {
  4878. int ret;
  4879. fc_port_t *fcport;
  4880. ret = QLA_FUNCTION_FAILED;
  4881. /* We need to set priority for all logged in ports */
  4882. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4883. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4884. return ret;
  4885. }