intr_remapping.c 9.6 KB

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  1. #include <linux/dmar.h>
  2. #include <linux/spinlock.h>
  3. #include <linux/jiffies.h>
  4. #include <linux/pci.h>
  5. #include <linux/irq.h>
  6. #include <asm/io_apic.h>
  7. #include <linux/intel-iommu.h>
  8. #include "intr_remapping.h"
  9. static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  10. static int ir_ioapic_num;
  11. int intr_remapping_enabled;
  12. static struct {
  13. struct intel_iommu *iommu;
  14. u16 irte_index;
  15. u16 sub_handle;
  16. u8 irte_mask;
  17. } irq_2_iommu[NR_IRQS];
  18. static DEFINE_SPINLOCK(irq_2_ir_lock);
  19. int irq_remapped(int irq)
  20. {
  21. if (irq > NR_IRQS)
  22. return 0;
  23. if (!irq_2_iommu[irq].iommu)
  24. return 0;
  25. return 1;
  26. }
  27. int get_irte(int irq, struct irte *entry)
  28. {
  29. int index;
  30. if (!entry || irq > NR_IRQS)
  31. return -1;
  32. spin_lock(&irq_2_ir_lock);
  33. if (!irq_2_iommu[irq].iommu) {
  34. spin_unlock(&irq_2_ir_lock);
  35. return -1;
  36. }
  37. index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
  38. *entry = *(irq_2_iommu[irq].iommu->ir_table->base + index);
  39. spin_unlock(&irq_2_ir_lock);
  40. return 0;
  41. }
  42. int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
  43. {
  44. struct ir_table *table = iommu->ir_table;
  45. u16 index, start_index;
  46. unsigned int mask = 0;
  47. int i;
  48. if (!count)
  49. return -1;
  50. /*
  51. * start the IRTE search from index 0.
  52. */
  53. index = start_index = 0;
  54. if (count > 1) {
  55. count = __roundup_pow_of_two(count);
  56. mask = ilog2(count);
  57. }
  58. if (mask > ecap_max_handle_mask(iommu->ecap)) {
  59. printk(KERN_ERR
  60. "Requested mask %x exceeds the max invalidation handle"
  61. " mask value %Lx\n", mask,
  62. ecap_max_handle_mask(iommu->ecap));
  63. return -1;
  64. }
  65. spin_lock(&irq_2_ir_lock);
  66. do {
  67. for (i = index; i < index + count; i++)
  68. if (table->base[i].present)
  69. break;
  70. /* empty index found */
  71. if (i == index + count)
  72. break;
  73. index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
  74. if (index == start_index) {
  75. spin_unlock(&irq_2_ir_lock);
  76. printk(KERN_ERR "can't allocate an IRTE\n");
  77. return -1;
  78. }
  79. } while (1);
  80. for (i = index; i < index + count; i++)
  81. table->base[i].present = 1;
  82. irq_2_iommu[irq].iommu = iommu;
  83. irq_2_iommu[irq].irte_index = index;
  84. irq_2_iommu[irq].sub_handle = 0;
  85. irq_2_iommu[irq].irte_mask = mask;
  86. spin_unlock(&irq_2_ir_lock);
  87. return index;
  88. }
  89. static void qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
  90. {
  91. struct qi_desc desc;
  92. desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
  93. | QI_IEC_SELECTIVE;
  94. desc.high = 0;
  95. qi_submit_sync(&desc, iommu);
  96. }
  97. int map_irq_to_irte_handle(int irq, u16 *sub_handle)
  98. {
  99. int index;
  100. spin_lock(&irq_2_ir_lock);
  101. if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
  102. spin_unlock(&irq_2_ir_lock);
  103. return -1;
  104. }
  105. *sub_handle = irq_2_iommu[irq].sub_handle;
  106. index = irq_2_iommu[irq].irte_index;
  107. spin_unlock(&irq_2_ir_lock);
  108. return index;
  109. }
  110. int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
  111. {
  112. spin_lock(&irq_2_ir_lock);
  113. if (irq >= NR_IRQS || irq_2_iommu[irq].iommu) {
  114. spin_unlock(&irq_2_ir_lock);
  115. return -1;
  116. }
  117. irq_2_iommu[irq].iommu = iommu;
  118. irq_2_iommu[irq].irte_index = index;
  119. irq_2_iommu[irq].sub_handle = subhandle;
  120. irq_2_iommu[irq].irte_mask = 0;
  121. spin_unlock(&irq_2_ir_lock);
  122. return 0;
  123. }
  124. int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
  125. {
  126. spin_lock(&irq_2_ir_lock);
  127. if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
  128. spin_unlock(&irq_2_ir_lock);
  129. return -1;
  130. }
  131. irq_2_iommu[irq].iommu = NULL;
  132. irq_2_iommu[irq].irte_index = 0;
  133. irq_2_iommu[irq].sub_handle = 0;
  134. irq_2_iommu[irq].irte_mask = 0;
  135. spin_unlock(&irq_2_ir_lock);
  136. return 0;
  137. }
  138. int modify_irte(int irq, struct irte *irte_modified)
  139. {
  140. int index;
  141. struct irte *irte;
  142. struct intel_iommu *iommu;
  143. spin_lock(&irq_2_ir_lock);
  144. if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
  145. spin_unlock(&irq_2_ir_lock);
  146. return -1;
  147. }
  148. iommu = irq_2_iommu[irq].iommu;
  149. index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
  150. irte = &iommu->ir_table->base[index];
  151. set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1));
  152. __iommu_flush_cache(iommu, irte, sizeof(*irte));
  153. qi_flush_iec(iommu, index, 0);
  154. spin_unlock(&irq_2_ir_lock);
  155. return 0;
  156. }
  157. int flush_irte(int irq)
  158. {
  159. int index;
  160. struct intel_iommu *iommu;
  161. spin_lock(&irq_2_ir_lock);
  162. if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
  163. spin_unlock(&irq_2_ir_lock);
  164. return -1;
  165. }
  166. iommu = irq_2_iommu[irq].iommu;
  167. index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
  168. qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask);
  169. spin_unlock(&irq_2_ir_lock);
  170. return 0;
  171. }
  172. struct intel_iommu *map_ioapic_to_ir(int apic)
  173. {
  174. int i;
  175. for (i = 0; i < MAX_IO_APICS; i++)
  176. if (ir_ioapic[i].id == apic)
  177. return ir_ioapic[i].iommu;
  178. return NULL;
  179. }
  180. struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
  181. {
  182. struct dmar_drhd_unit *drhd;
  183. drhd = dmar_find_matched_drhd_unit(dev);
  184. if (!drhd)
  185. return NULL;
  186. return drhd->iommu;
  187. }
  188. int free_irte(int irq)
  189. {
  190. int index, i;
  191. struct irte *irte;
  192. struct intel_iommu *iommu;
  193. spin_lock(&irq_2_ir_lock);
  194. if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
  195. spin_unlock(&irq_2_ir_lock);
  196. return -1;
  197. }
  198. iommu = irq_2_iommu[irq].iommu;
  199. index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
  200. irte = &iommu->ir_table->base[index];
  201. if (!irq_2_iommu[irq].sub_handle) {
  202. for (i = 0; i < (1 << irq_2_iommu[irq].irte_mask); i++)
  203. set_64bit((unsigned long *)irte, 0);
  204. qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask);
  205. }
  206. irq_2_iommu[irq].iommu = NULL;
  207. irq_2_iommu[irq].irte_index = 0;
  208. irq_2_iommu[irq].sub_handle = 0;
  209. irq_2_iommu[irq].irte_mask = 0;
  210. spin_unlock(&irq_2_ir_lock);
  211. return 0;
  212. }
  213. static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
  214. {
  215. u64 addr;
  216. u32 cmd, sts;
  217. unsigned long flags;
  218. addr = virt_to_phys((void *)iommu->ir_table->base);
  219. spin_lock_irqsave(&iommu->register_lock, flags);
  220. dmar_writeq(iommu->reg + DMAR_IRTA_REG,
  221. (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
  222. /* Set interrupt-remapping table pointer */
  223. cmd = iommu->gcmd | DMA_GCMD_SIRTP;
  224. writel(cmd, iommu->reg + DMAR_GCMD_REG);
  225. IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
  226. readl, (sts & DMA_GSTS_IRTPS), sts);
  227. spin_unlock_irqrestore(&iommu->register_lock, flags);
  228. /*
  229. * global invalidation of interrupt entry cache before enabling
  230. * interrupt-remapping.
  231. */
  232. qi_global_iec(iommu);
  233. spin_lock_irqsave(&iommu->register_lock, flags);
  234. /* Enable interrupt-remapping */
  235. cmd = iommu->gcmd | DMA_GCMD_IRE;
  236. iommu->gcmd |= DMA_GCMD_IRE;
  237. writel(cmd, iommu->reg + DMAR_GCMD_REG);
  238. IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
  239. readl, (sts & DMA_GSTS_IRES), sts);
  240. spin_unlock_irqrestore(&iommu->register_lock, flags);
  241. }
  242. static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
  243. {
  244. struct ir_table *ir_table;
  245. struct page *pages;
  246. ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
  247. GFP_KERNEL);
  248. if (!iommu->ir_table)
  249. return -ENOMEM;
  250. pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
  251. if (!pages) {
  252. printk(KERN_ERR "failed to allocate pages of order %d\n",
  253. INTR_REMAP_PAGE_ORDER);
  254. kfree(iommu->ir_table);
  255. return -ENOMEM;
  256. }
  257. ir_table->base = page_address(pages);
  258. iommu_set_intr_remapping(iommu, mode);
  259. return 0;
  260. }
  261. int __init enable_intr_remapping(int eim)
  262. {
  263. struct dmar_drhd_unit *drhd;
  264. int setup = 0;
  265. /*
  266. * check for the Interrupt-remapping support
  267. */
  268. for_each_drhd_unit(drhd) {
  269. struct intel_iommu *iommu = drhd->iommu;
  270. if (!ecap_ir_support(iommu->ecap))
  271. continue;
  272. if (eim && !ecap_eim_support(iommu->ecap)) {
  273. printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
  274. " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
  275. return -1;
  276. }
  277. }
  278. /*
  279. * Enable queued invalidation for all the DRHD's.
  280. */
  281. for_each_drhd_unit(drhd) {
  282. int ret;
  283. struct intel_iommu *iommu = drhd->iommu;
  284. ret = dmar_enable_qi(iommu);
  285. if (ret) {
  286. printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
  287. " invalidation, ecap %Lx, ret %d\n",
  288. drhd->reg_base_addr, iommu->ecap, ret);
  289. return -1;
  290. }
  291. }
  292. /*
  293. * Setup Interrupt-remapping for all the DRHD's now.
  294. */
  295. for_each_drhd_unit(drhd) {
  296. struct intel_iommu *iommu = drhd->iommu;
  297. if (!ecap_ir_support(iommu->ecap))
  298. continue;
  299. if (setup_intr_remapping(iommu, eim))
  300. goto error;
  301. setup = 1;
  302. }
  303. if (!setup)
  304. goto error;
  305. intr_remapping_enabled = 1;
  306. return 0;
  307. error:
  308. /*
  309. * handle error condition gracefully here!
  310. */
  311. return -1;
  312. }
  313. static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
  314. struct intel_iommu *iommu)
  315. {
  316. struct acpi_dmar_hardware_unit *drhd;
  317. struct acpi_dmar_device_scope *scope;
  318. void *start, *end;
  319. drhd = (struct acpi_dmar_hardware_unit *)header;
  320. start = (void *)(drhd + 1);
  321. end = ((void *)drhd) + header->length;
  322. while (start < end) {
  323. scope = start;
  324. if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
  325. if (ir_ioapic_num == MAX_IO_APICS) {
  326. printk(KERN_WARNING "Exceeded Max IO APICS\n");
  327. return -1;
  328. }
  329. printk(KERN_INFO "IOAPIC id %d under DRHD base"
  330. " 0x%Lx\n", scope->enumeration_id,
  331. drhd->address);
  332. ir_ioapic[ir_ioapic_num].iommu = iommu;
  333. ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
  334. ir_ioapic_num++;
  335. }
  336. start += scope->length;
  337. }
  338. return 0;
  339. }
  340. /*
  341. * Finds the assocaition between IOAPIC's and its Interrupt-remapping
  342. * hardware unit.
  343. */
  344. int __init parse_ioapics_under_ir(void)
  345. {
  346. struct dmar_drhd_unit *drhd;
  347. int ir_supported = 0;
  348. for_each_drhd_unit(drhd) {
  349. struct intel_iommu *iommu = drhd->iommu;
  350. if (ecap_ir_support(iommu->ecap)) {
  351. if (ir_parse_ioapic_scope(drhd->hdr, iommu))
  352. return -1;
  353. ir_supported = 1;
  354. }
  355. }
  356. if (ir_supported && ir_ioapic_num != nr_ioapics) {
  357. printk(KERN_WARNING
  358. "Not all IO-APIC's listed under remapping hardware\n");
  359. return -1;
  360. }
  361. return ir_supported;
  362. }