mthca_dev.h 14 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
  33. */
  34. #ifndef MTHCA_DEV_H
  35. #define MTHCA_DEV_H
  36. #include <linux/spinlock.h>
  37. #include <linux/kernel.h>
  38. #include <linux/pci.h>
  39. #include <linux/dma-mapping.h>
  40. #include <asm/semaphore.h>
  41. #include "mthca_provider.h"
  42. #include "mthca_doorbell.h"
  43. #define DRV_NAME "ib_mthca"
  44. #define PFX DRV_NAME ": "
  45. #define DRV_VERSION "0.06-pre"
  46. #define DRV_RELDATE "November 8, 2004"
  47. /* Types of supported HCA */
  48. enum {
  49. TAVOR, /* MT23108 */
  50. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  51. ARBEL_NATIVE /* MT25208 with extended features */
  52. };
  53. enum {
  54. MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
  55. MTHCA_FLAG_SRQ = 1 << 2,
  56. MTHCA_FLAG_MSI = 1 << 3,
  57. MTHCA_FLAG_MSI_X = 1 << 4,
  58. MTHCA_FLAG_NO_LAM = 1 << 5,
  59. MTHCA_FLAG_FMR = 1 << 6
  60. };
  61. enum {
  62. MTHCA_MAX_PORTS = 2
  63. };
  64. enum {
  65. MTHCA_EQ_CONTEXT_SIZE = 0x40,
  66. MTHCA_CQ_CONTEXT_SIZE = 0x40,
  67. MTHCA_QP_CONTEXT_SIZE = 0x200,
  68. MTHCA_RDB_ENTRY_SIZE = 0x20,
  69. MTHCA_AV_SIZE = 0x20,
  70. MTHCA_MGM_ENTRY_SIZE = 0x40,
  71. /* Arbel FW gives us these, but we need them for Tavor */
  72. MTHCA_MPT_ENTRY_SIZE = 0x40,
  73. MTHCA_MTT_SEG_SIZE = 0x40,
  74. };
  75. enum {
  76. MTHCA_EQ_CMD,
  77. MTHCA_EQ_ASYNC,
  78. MTHCA_EQ_COMP,
  79. MTHCA_NUM_EQ
  80. };
  81. enum {
  82. MTHCA_OPCODE_NOP = 0x00,
  83. MTHCA_OPCODE_RDMA_WRITE = 0x08,
  84. MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
  85. MTHCA_OPCODE_SEND = 0x0a,
  86. MTHCA_OPCODE_SEND_IMM = 0x0b,
  87. MTHCA_OPCODE_RDMA_READ = 0x10,
  88. MTHCA_OPCODE_ATOMIC_CS = 0x11,
  89. MTHCA_OPCODE_ATOMIC_FA = 0x12,
  90. MTHCA_OPCODE_BIND_MW = 0x18,
  91. MTHCA_OPCODE_INVALID = 0xff
  92. };
  93. struct mthca_cmd {
  94. int use_events;
  95. struct semaphore hcr_sem;
  96. struct semaphore poll_sem;
  97. struct semaphore event_sem;
  98. int max_cmds;
  99. spinlock_t context_lock;
  100. int free_head;
  101. struct mthca_cmd_context *context;
  102. u16 token_mask;
  103. };
  104. struct mthca_limits {
  105. int num_ports;
  106. int vl_cap;
  107. int mtu_cap;
  108. int gid_table_len;
  109. int pkey_table_len;
  110. int local_ca_ack_delay;
  111. int num_uars;
  112. int max_sg;
  113. int num_qps;
  114. int reserved_qps;
  115. int num_srqs;
  116. int reserved_srqs;
  117. int num_eecs;
  118. int reserved_eecs;
  119. int num_cqs;
  120. int reserved_cqs;
  121. int num_eqs;
  122. int reserved_eqs;
  123. int num_mpts;
  124. int num_mtt_segs;
  125. int fmr_reserved_mtts;
  126. int reserved_mtts;
  127. int reserved_mrws;
  128. int reserved_uars;
  129. int num_mgms;
  130. int num_amgms;
  131. int reserved_mcgs;
  132. int num_pds;
  133. int reserved_pds;
  134. };
  135. struct mthca_alloc {
  136. u32 last;
  137. u32 top;
  138. u32 max;
  139. u32 mask;
  140. spinlock_t lock;
  141. unsigned long *table;
  142. };
  143. struct mthca_array {
  144. struct {
  145. void **page;
  146. int used;
  147. } *page_list;
  148. };
  149. struct mthca_uar_table {
  150. struct mthca_alloc alloc;
  151. u64 uarc_base;
  152. int uarc_size;
  153. };
  154. struct mthca_pd_table {
  155. struct mthca_alloc alloc;
  156. };
  157. struct mthca_buddy {
  158. unsigned long **bits;
  159. int max_order;
  160. spinlock_t lock;
  161. };
  162. struct mthca_mr_table {
  163. struct mthca_alloc mpt_alloc;
  164. struct mthca_buddy mtt_buddy;
  165. struct mthca_buddy *fmr_mtt_buddy;
  166. u64 mtt_base;
  167. u64 mpt_base;
  168. struct mthca_icm_table *mtt_table;
  169. struct mthca_icm_table *mpt_table;
  170. struct {
  171. void __iomem *mpt_base;
  172. void __iomem *mtt_base;
  173. struct mthca_buddy mtt_buddy;
  174. } tavor_fmr;
  175. };
  176. struct mthca_eq_table {
  177. struct mthca_alloc alloc;
  178. void __iomem *clr_int;
  179. u32 clr_mask;
  180. u32 arm_mask;
  181. struct mthca_eq eq[MTHCA_NUM_EQ];
  182. u64 icm_virt;
  183. struct page *icm_page;
  184. dma_addr_t icm_dma;
  185. int have_irq;
  186. u8 inta_pin;
  187. };
  188. struct mthca_cq_table {
  189. struct mthca_alloc alloc;
  190. spinlock_t lock;
  191. struct mthca_array cq;
  192. struct mthca_icm_table *table;
  193. };
  194. struct mthca_qp_table {
  195. struct mthca_alloc alloc;
  196. u32 rdb_base;
  197. int rdb_shift;
  198. int sqp_start;
  199. spinlock_t lock;
  200. struct mthca_array qp;
  201. struct mthca_icm_table *qp_table;
  202. struct mthca_icm_table *eqp_table;
  203. struct mthca_icm_table *rdb_table;
  204. };
  205. struct mthca_av_table {
  206. struct pci_pool *pool;
  207. int num_ddr_avs;
  208. u64 ddr_av_base;
  209. void __iomem *av_map;
  210. struct mthca_alloc alloc;
  211. };
  212. struct mthca_mcg_table {
  213. struct semaphore sem;
  214. struct mthca_alloc alloc;
  215. struct mthca_icm_table *table;
  216. };
  217. struct mthca_dev {
  218. struct ib_device ib_dev;
  219. struct pci_dev *pdev;
  220. int hca_type;
  221. unsigned long mthca_flags;
  222. unsigned long device_cap_flags;
  223. u32 rev_id;
  224. /* firmware info */
  225. u64 fw_ver;
  226. union {
  227. struct {
  228. u64 fw_start;
  229. u64 fw_end;
  230. } tavor;
  231. struct {
  232. u64 clr_int_base;
  233. u64 eq_arm_base;
  234. u64 eq_set_ci_base;
  235. struct mthca_icm *fw_icm;
  236. struct mthca_icm *aux_icm;
  237. u16 fw_pages;
  238. } arbel;
  239. } fw;
  240. u64 ddr_start;
  241. u64 ddr_end;
  242. MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
  243. struct semaphore cap_mask_mutex;
  244. void __iomem *hcr;
  245. void __iomem *kar;
  246. void __iomem *clr_base;
  247. union {
  248. struct {
  249. void __iomem *ecr_base;
  250. } tavor;
  251. struct {
  252. void __iomem *eq_arm;
  253. void __iomem *eq_set_ci_base;
  254. } arbel;
  255. } eq_regs;
  256. struct mthca_cmd cmd;
  257. struct mthca_limits limits;
  258. struct mthca_uar_table uar_table;
  259. struct mthca_pd_table pd_table;
  260. struct mthca_mr_table mr_table;
  261. struct mthca_eq_table eq_table;
  262. struct mthca_cq_table cq_table;
  263. struct mthca_qp_table qp_table;
  264. struct mthca_av_table av_table;
  265. struct mthca_mcg_table mcg_table;
  266. struct mthca_uar driver_uar;
  267. struct mthca_db_table *db_tab;
  268. struct mthca_pd driver_pd;
  269. struct mthca_mr driver_mr;
  270. struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
  271. struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
  272. spinlock_t sm_lock;
  273. };
  274. #define mthca_dbg(mdev, format, arg...) \
  275. dev_dbg(&mdev->pdev->dev, format, ## arg)
  276. #define mthca_err(mdev, format, arg...) \
  277. dev_err(&mdev->pdev->dev, format, ## arg)
  278. #define mthca_info(mdev, format, arg...) \
  279. dev_info(&mdev->pdev->dev, format, ## arg)
  280. #define mthca_warn(mdev, format, arg...) \
  281. dev_warn(&mdev->pdev->dev, format, ## arg)
  282. extern void __buggy_use_of_MTHCA_GET(void);
  283. extern void __buggy_use_of_MTHCA_PUT(void);
  284. #define MTHCA_GET(dest, source, offset) \
  285. do { \
  286. void *__p = (char *) (source) + (offset); \
  287. switch (sizeof (dest)) { \
  288. case 1: (dest) = *(u8 *) __p; break; \
  289. case 2: (dest) = be16_to_cpup(__p); break; \
  290. case 4: (dest) = be32_to_cpup(__p); break; \
  291. case 8: (dest) = be64_to_cpup(__p); break; \
  292. default: __buggy_use_of_MTHCA_GET(); \
  293. } \
  294. } while (0)
  295. #define MTHCA_PUT(dest, source, offset) \
  296. do { \
  297. __typeof__(source) *__p = \
  298. (__typeof__(source) *) ((char *) (dest) + (offset)); \
  299. switch (sizeof(source)) { \
  300. case 1: *__p = (source); break; \
  301. case 2: *__p = cpu_to_be16(source); break; \
  302. case 4: *__p = cpu_to_be32(source); break; \
  303. case 8: *__p = cpu_to_be64(source); break; \
  304. default: __buggy_use_of_MTHCA_PUT(); \
  305. } \
  306. } while (0)
  307. int mthca_reset(struct mthca_dev *mdev);
  308. u32 mthca_alloc(struct mthca_alloc *alloc);
  309. void mthca_free(struct mthca_alloc *alloc, u32 obj);
  310. int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
  311. u32 reserved);
  312. void mthca_alloc_cleanup(struct mthca_alloc *alloc);
  313. void *mthca_array_get(struct mthca_array *array, int index);
  314. int mthca_array_set(struct mthca_array *array, int index, void *value);
  315. void mthca_array_clear(struct mthca_array *array, int index);
  316. int mthca_array_init(struct mthca_array *array, int nent);
  317. void mthca_array_cleanup(struct mthca_array *array, int nent);
  318. int mthca_init_uar_table(struct mthca_dev *dev);
  319. int mthca_init_pd_table(struct mthca_dev *dev);
  320. int mthca_init_mr_table(struct mthca_dev *dev);
  321. int mthca_init_eq_table(struct mthca_dev *dev);
  322. int mthca_init_cq_table(struct mthca_dev *dev);
  323. int mthca_init_qp_table(struct mthca_dev *dev);
  324. int mthca_init_av_table(struct mthca_dev *dev);
  325. int mthca_init_mcg_table(struct mthca_dev *dev);
  326. void mthca_cleanup_uar_table(struct mthca_dev *dev);
  327. void mthca_cleanup_pd_table(struct mthca_dev *dev);
  328. void mthca_cleanup_mr_table(struct mthca_dev *dev);
  329. void mthca_cleanup_eq_table(struct mthca_dev *dev);
  330. void mthca_cleanup_cq_table(struct mthca_dev *dev);
  331. void mthca_cleanup_qp_table(struct mthca_dev *dev);
  332. void mthca_cleanup_av_table(struct mthca_dev *dev);
  333. void mthca_cleanup_mcg_table(struct mthca_dev *dev);
  334. int mthca_register_device(struct mthca_dev *dev);
  335. void mthca_unregister_device(struct mthca_dev *dev);
  336. int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
  337. void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
  338. int mthca_pd_alloc(struct mthca_dev *dev, struct mthca_pd *pd);
  339. void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
  340. int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
  341. u32 access, struct mthca_mr *mr);
  342. int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
  343. u64 *buffer_list, int buffer_size_shift,
  344. int list_len, u64 iova, u64 total_size,
  345. u32 access, struct mthca_mr *mr);
  346. void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
  347. int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
  348. u32 access, struct mthca_fmr *fmr);
  349. int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  350. int list_len, u64 iova);
  351. void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
  352. int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  353. int list_len, u64 iova);
  354. void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
  355. int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
  356. int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
  357. void mthca_unmap_eq_icm(struct mthca_dev *dev);
  358. int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
  359. struct ib_wc *entry);
  360. int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
  361. int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
  362. int mthca_init_cq(struct mthca_dev *dev, int nent,
  363. struct mthca_cq *cq);
  364. void mthca_free_cq(struct mthca_dev *dev,
  365. struct mthca_cq *cq);
  366. void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
  367. void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);
  368. void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
  369. enum ib_event_type event_type);
  370. int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
  371. int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  372. struct ib_send_wr **bad_wr);
  373. int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  374. struct ib_recv_wr **bad_wr);
  375. int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  376. struct ib_send_wr **bad_wr);
  377. int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  378. struct ib_recv_wr **bad_wr);
  379. int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
  380. int index, int *dbd, u32 *new_wqe);
  381. int mthca_alloc_qp(struct mthca_dev *dev,
  382. struct mthca_pd *pd,
  383. struct mthca_cq *send_cq,
  384. struct mthca_cq *recv_cq,
  385. enum ib_qp_type type,
  386. enum ib_sig_type send_policy,
  387. struct mthca_qp *qp);
  388. int mthca_alloc_sqp(struct mthca_dev *dev,
  389. struct mthca_pd *pd,
  390. struct mthca_cq *send_cq,
  391. struct mthca_cq *recv_cq,
  392. enum ib_sig_type send_policy,
  393. int qpn,
  394. int port,
  395. struct mthca_sqp *sqp);
  396. void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
  397. int mthca_create_ah(struct mthca_dev *dev,
  398. struct mthca_pd *pd,
  399. struct ib_ah_attr *ah_attr,
  400. struct mthca_ah *ah);
  401. int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
  402. int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
  403. struct ib_ud_header *header);
  404. int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
  405. int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
  406. int mthca_process_mad(struct ib_device *ibdev,
  407. int mad_flags,
  408. u8 port_num,
  409. struct ib_wc *in_wc,
  410. struct ib_grh *in_grh,
  411. struct ib_mad *in_mad,
  412. struct ib_mad *out_mad);
  413. int mthca_create_agents(struct mthca_dev *dev);
  414. void mthca_free_agents(struct mthca_dev *dev);
  415. static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
  416. {
  417. return container_of(ibdev, struct mthca_dev, ib_dev);
  418. }
  419. static inline int mthca_is_memfree(struct mthca_dev *dev)
  420. {
  421. return dev->hca_type == ARBEL_NATIVE;
  422. }
  423. #endif /* MTHCA_DEV_H */