events.c 39 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. static LIST_HEAD(xen_irq_list_head);
  55. /* IRQ <-> VIRQ mapping. */
  56. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  57. /* IRQ <-> IPI mapping */
  58. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  59. /* Interrupt types. */
  60. enum xen_irq_type {
  61. IRQT_UNBOUND = 0,
  62. IRQT_PIRQ,
  63. IRQT_VIRQ,
  64. IRQT_IPI,
  65. IRQT_EVTCHN
  66. };
  67. /*
  68. * Packed IRQ information:
  69. * type - enum xen_irq_type
  70. * event channel - irq->event channel mapping
  71. * cpu - cpu this event channel is bound to
  72. * index - type-specific information:
  73. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  74. * guest, or GSI (real passthrough IRQ) of the device.
  75. * VIRQ - virq number
  76. * IPI - IPI vector
  77. * EVTCHN -
  78. */
  79. struct irq_info {
  80. struct list_head list;
  81. enum xen_irq_type type; /* type */
  82. unsigned irq;
  83. unsigned short evtchn; /* event channel */
  84. unsigned short cpu; /* cpu bound */
  85. union {
  86. unsigned short virq;
  87. enum ipi_vector ipi;
  88. struct {
  89. unsigned short pirq;
  90. unsigned short gsi;
  91. unsigned char vector;
  92. unsigned char flags;
  93. uint16_t domid;
  94. } pirq;
  95. } u;
  96. };
  97. #define PIRQ_NEEDS_EOI (1 << 0)
  98. #define PIRQ_SHAREABLE (1 << 1)
  99. static int *evtchn_to_irq;
  100. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  101. cpu_evtchn_mask);
  102. /* Xen will never allocate port zero for any purpose. */
  103. #define VALID_EVTCHN(chn) ((chn) != 0)
  104. static struct irq_chip xen_dynamic_chip;
  105. static struct irq_chip xen_percpu_chip;
  106. static struct irq_chip xen_pirq_chip;
  107. static void enable_dynirq(struct irq_data *data);
  108. static void disable_dynirq(struct irq_data *data);
  109. /* Get info for IRQ */
  110. static struct irq_info *info_for_irq(unsigned irq)
  111. {
  112. return irq_get_handler_data(irq);
  113. }
  114. /* Constructors for packed IRQ information. */
  115. static void xen_irq_info_common_init(struct irq_info *info,
  116. unsigned irq,
  117. enum xen_irq_type type,
  118. unsigned short evtchn,
  119. unsigned short cpu)
  120. {
  121. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  122. info->type = type;
  123. info->irq = irq;
  124. info->evtchn = evtchn;
  125. info->cpu = cpu;
  126. evtchn_to_irq[evtchn] = irq;
  127. }
  128. static void xen_irq_info_evtchn_init(unsigned irq,
  129. unsigned short evtchn)
  130. {
  131. struct irq_info *info = info_for_irq(irq);
  132. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  133. }
  134. static void xen_irq_info_ipi_init(unsigned cpu,
  135. unsigned irq,
  136. unsigned short evtchn,
  137. enum ipi_vector ipi)
  138. {
  139. struct irq_info *info = info_for_irq(irq);
  140. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  141. info->u.ipi = ipi;
  142. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  143. }
  144. static void xen_irq_info_virq_init(unsigned cpu,
  145. unsigned irq,
  146. unsigned short evtchn,
  147. unsigned short virq)
  148. {
  149. struct irq_info *info = info_for_irq(irq);
  150. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  151. info->u.virq = virq;
  152. per_cpu(virq_to_irq, cpu)[virq] = irq;
  153. }
  154. static void xen_irq_info_pirq_init(unsigned irq,
  155. unsigned short evtchn,
  156. unsigned short pirq,
  157. unsigned short gsi,
  158. unsigned short vector,
  159. uint16_t domid,
  160. unsigned char flags)
  161. {
  162. struct irq_info *info = info_for_irq(irq);
  163. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  164. info->u.pirq.pirq = pirq;
  165. info->u.pirq.gsi = gsi;
  166. info->u.pirq.vector = vector;
  167. info->u.pirq.domid = domid;
  168. info->u.pirq.flags = flags;
  169. }
  170. /*
  171. * Accessors for packed IRQ information.
  172. */
  173. static unsigned int evtchn_from_irq(unsigned irq)
  174. {
  175. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  176. return 0;
  177. return info_for_irq(irq)->evtchn;
  178. }
  179. unsigned irq_from_evtchn(unsigned int evtchn)
  180. {
  181. return evtchn_to_irq[evtchn];
  182. }
  183. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  184. static enum ipi_vector ipi_from_irq(unsigned irq)
  185. {
  186. struct irq_info *info = info_for_irq(irq);
  187. BUG_ON(info == NULL);
  188. BUG_ON(info->type != IRQT_IPI);
  189. return info->u.ipi;
  190. }
  191. static unsigned virq_from_irq(unsigned irq)
  192. {
  193. struct irq_info *info = info_for_irq(irq);
  194. BUG_ON(info == NULL);
  195. BUG_ON(info->type != IRQT_VIRQ);
  196. return info->u.virq;
  197. }
  198. static unsigned pirq_from_irq(unsigned irq)
  199. {
  200. struct irq_info *info = info_for_irq(irq);
  201. BUG_ON(info == NULL);
  202. BUG_ON(info->type != IRQT_PIRQ);
  203. return info->u.pirq.pirq;
  204. }
  205. static enum xen_irq_type type_from_irq(unsigned irq)
  206. {
  207. return info_for_irq(irq)->type;
  208. }
  209. static unsigned cpu_from_irq(unsigned irq)
  210. {
  211. return info_for_irq(irq)->cpu;
  212. }
  213. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  214. {
  215. int irq = evtchn_to_irq[evtchn];
  216. unsigned ret = 0;
  217. if (irq != -1)
  218. ret = cpu_from_irq(irq);
  219. return ret;
  220. }
  221. static bool pirq_needs_eoi(unsigned irq)
  222. {
  223. struct irq_info *info = info_for_irq(irq);
  224. BUG_ON(info->type != IRQT_PIRQ);
  225. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  226. }
  227. static inline unsigned long active_evtchns(unsigned int cpu,
  228. struct shared_info *sh,
  229. unsigned int idx)
  230. {
  231. return sh->evtchn_pending[idx] &
  232. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  233. ~sh->evtchn_mask[idx];
  234. }
  235. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  236. {
  237. int irq = evtchn_to_irq[chn];
  238. BUG_ON(irq == -1);
  239. #ifdef CONFIG_SMP
  240. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  241. #endif
  242. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  243. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  244. info_for_irq(irq)->cpu = cpu;
  245. }
  246. static void init_evtchn_cpu_bindings(void)
  247. {
  248. int i;
  249. #ifdef CONFIG_SMP
  250. struct irq_info *info;
  251. /* By default all event channels notify CPU#0. */
  252. list_for_each_entry(info, &xen_irq_list_head, list) {
  253. struct irq_desc *desc = irq_to_desc(info->irq);
  254. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  255. }
  256. #endif
  257. for_each_possible_cpu(i)
  258. memset(per_cpu(cpu_evtchn_mask, i),
  259. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  260. }
  261. static inline void clear_evtchn(int port)
  262. {
  263. struct shared_info *s = HYPERVISOR_shared_info;
  264. sync_clear_bit(port, &s->evtchn_pending[0]);
  265. }
  266. static inline void set_evtchn(int port)
  267. {
  268. struct shared_info *s = HYPERVISOR_shared_info;
  269. sync_set_bit(port, &s->evtchn_pending[0]);
  270. }
  271. static inline int test_evtchn(int port)
  272. {
  273. struct shared_info *s = HYPERVISOR_shared_info;
  274. return sync_test_bit(port, &s->evtchn_pending[0]);
  275. }
  276. /**
  277. * notify_remote_via_irq - send event to remote end of event channel via irq
  278. * @irq: irq of event channel to send event to
  279. *
  280. * Unlike notify_remote_via_evtchn(), this is safe to use across
  281. * save/restore. Notifications on a broken connection are silently
  282. * dropped.
  283. */
  284. void notify_remote_via_irq(int irq)
  285. {
  286. int evtchn = evtchn_from_irq(irq);
  287. if (VALID_EVTCHN(evtchn))
  288. notify_remote_via_evtchn(evtchn);
  289. }
  290. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  291. static void mask_evtchn(int port)
  292. {
  293. struct shared_info *s = HYPERVISOR_shared_info;
  294. sync_set_bit(port, &s->evtchn_mask[0]);
  295. }
  296. static void unmask_evtchn(int port)
  297. {
  298. struct shared_info *s = HYPERVISOR_shared_info;
  299. unsigned int cpu = get_cpu();
  300. BUG_ON(!irqs_disabled());
  301. /* Slow path (hypercall) if this is a non-local port. */
  302. if (unlikely(cpu != cpu_from_evtchn(port))) {
  303. struct evtchn_unmask unmask = { .port = port };
  304. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  305. } else {
  306. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  307. sync_clear_bit(port, &s->evtchn_mask[0]);
  308. /*
  309. * The following is basically the equivalent of
  310. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  311. * the interrupt edge' if the channel is masked.
  312. */
  313. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  314. !sync_test_and_set_bit(port / BITS_PER_LONG,
  315. &vcpu_info->evtchn_pending_sel))
  316. vcpu_info->evtchn_upcall_pending = 1;
  317. }
  318. put_cpu();
  319. }
  320. static void xen_irq_init(unsigned irq)
  321. {
  322. struct irq_info *info;
  323. #ifdef CONFIG_SMP
  324. struct irq_desc *desc = irq_to_desc(irq);
  325. /* By default all event channels notify CPU#0. */
  326. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  327. #endif
  328. info = kzalloc(sizeof(*info), GFP_KERNEL);
  329. if (info == NULL)
  330. panic("Unable to allocate metadata for IRQ%d\n", irq);
  331. info->type = IRQT_UNBOUND;
  332. irq_set_handler_data(irq, info);
  333. list_add_tail(&info->list, &xen_irq_list_head);
  334. }
  335. static int __must_check xen_allocate_irq_dynamic(void)
  336. {
  337. int first = 0;
  338. int irq;
  339. #ifdef CONFIG_X86_IO_APIC
  340. /*
  341. * For an HVM guest or domain 0 which see "real" (emulated or
  342. * actual respectively) GSIs we allocate dynamic IRQs
  343. * e.g. those corresponding to event channels or MSIs
  344. * etc. from the range above those "real" GSIs to avoid
  345. * collisions.
  346. */
  347. if (xen_initial_domain() || xen_hvm_domain())
  348. first = get_nr_irqs_gsi();
  349. #endif
  350. irq = irq_alloc_desc_from(first, -1);
  351. xen_irq_init(irq);
  352. return irq;
  353. }
  354. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  355. {
  356. int irq;
  357. /*
  358. * A PV guest has no concept of a GSI (since it has no ACPI
  359. * nor access to/knowledge of the physical APICs). Therefore
  360. * all IRQs are dynamically allocated from the entire IRQ
  361. * space.
  362. */
  363. if (xen_pv_domain() && !xen_initial_domain())
  364. return xen_allocate_irq_dynamic();
  365. /* Legacy IRQ descriptors are already allocated by the arch. */
  366. if (gsi < NR_IRQS_LEGACY)
  367. irq = gsi;
  368. else
  369. irq = irq_alloc_desc_at(gsi, -1);
  370. xen_irq_init(irq);
  371. return irq;
  372. }
  373. static void xen_free_irq(unsigned irq)
  374. {
  375. struct irq_info *info = irq_get_handler_data(irq);
  376. list_del(&info->list);
  377. irq_set_handler_data(irq, NULL);
  378. kfree(info);
  379. /* Legacy IRQ descriptors are managed by the arch. */
  380. if (irq < NR_IRQS_LEGACY)
  381. return;
  382. irq_free_desc(irq);
  383. }
  384. static void pirq_query_unmask(int irq)
  385. {
  386. struct physdev_irq_status_query irq_status;
  387. struct irq_info *info = info_for_irq(irq);
  388. BUG_ON(info->type != IRQT_PIRQ);
  389. irq_status.irq = pirq_from_irq(irq);
  390. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  391. irq_status.flags = 0;
  392. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  393. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  394. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  395. }
  396. static bool probing_irq(int irq)
  397. {
  398. struct irq_desc *desc = irq_to_desc(irq);
  399. return desc && desc->action == NULL;
  400. }
  401. static void eoi_pirq(struct irq_data *data)
  402. {
  403. int evtchn = evtchn_from_irq(data->irq);
  404. struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
  405. int rc = 0;
  406. irq_move_irq(data);
  407. if (VALID_EVTCHN(evtchn))
  408. clear_evtchn(evtchn);
  409. if (pirq_needs_eoi(data->irq)) {
  410. rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  411. WARN_ON(rc);
  412. }
  413. }
  414. static void mask_ack_pirq(struct irq_data *data)
  415. {
  416. disable_dynirq(data);
  417. eoi_pirq(data);
  418. }
  419. static unsigned int __startup_pirq(unsigned int irq)
  420. {
  421. struct evtchn_bind_pirq bind_pirq;
  422. struct irq_info *info = info_for_irq(irq);
  423. int evtchn = evtchn_from_irq(irq);
  424. int rc;
  425. BUG_ON(info->type != IRQT_PIRQ);
  426. if (VALID_EVTCHN(evtchn))
  427. goto out;
  428. bind_pirq.pirq = pirq_from_irq(irq);
  429. /* NB. We are happy to share unless we are probing. */
  430. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  431. BIND_PIRQ__WILL_SHARE : 0;
  432. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  433. if (rc != 0) {
  434. if (!probing_irq(irq))
  435. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  436. irq);
  437. return 0;
  438. }
  439. evtchn = bind_pirq.port;
  440. pirq_query_unmask(irq);
  441. evtchn_to_irq[evtchn] = irq;
  442. bind_evtchn_to_cpu(evtchn, 0);
  443. info->evtchn = evtchn;
  444. out:
  445. unmask_evtchn(evtchn);
  446. eoi_pirq(irq_get_irq_data(irq));
  447. return 0;
  448. }
  449. static unsigned int startup_pirq(struct irq_data *data)
  450. {
  451. return __startup_pirq(data->irq);
  452. }
  453. static void shutdown_pirq(struct irq_data *data)
  454. {
  455. struct evtchn_close close;
  456. unsigned int irq = data->irq;
  457. struct irq_info *info = info_for_irq(irq);
  458. int evtchn = evtchn_from_irq(irq);
  459. BUG_ON(info->type != IRQT_PIRQ);
  460. if (!VALID_EVTCHN(evtchn))
  461. return;
  462. mask_evtchn(evtchn);
  463. close.port = evtchn;
  464. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  465. BUG();
  466. bind_evtchn_to_cpu(evtchn, 0);
  467. evtchn_to_irq[evtchn] = -1;
  468. info->evtchn = 0;
  469. }
  470. static void enable_pirq(struct irq_data *data)
  471. {
  472. startup_pirq(data);
  473. }
  474. static void disable_pirq(struct irq_data *data)
  475. {
  476. disable_dynirq(data);
  477. }
  478. static int find_irq_by_gsi(unsigned gsi)
  479. {
  480. struct irq_info *info;
  481. list_for_each_entry(info, &xen_irq_list_head, list) {
  482. if (info->type != IRQT_PIRQ)
  483. continue;
  484. if (info->u.pirq.gsi == gsi)
  485. return info->irq;
  486. }
  487. return -1;
  488. }
  489. /*
  490. * Do not make any assumptions regarding the relationship between the
  491. * IRQ number returned here and the Xen pirq argument.
  492. *
  493. * Note: We don't assign an event channel until the irq actually started
  494. * up. Return an existing irq if we've already got one for the gsi.
  495. *
  496. * Shareable implies level triggered, not shareable implies edge
  497. * triggered here.
  498. */
  499. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  500. unsigned pirq, int shareable, char *name)
  501. {
  502. int irq = -1;
  503. struct physdev_irq irq_op;
  504. spin_lock(&irq_mapping_update_lock);
  505. irq = find_irq_by_gsi(gsi);
  506. if (irq != -1) {
  507. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  508. irq, gsi);
  509. goto out; /* XXX need refcount? */
  510. }
  511. irq = xen_allocate_irq_gsi(gsi);
  512. if (irq < 0)
  513. goto out;
  514. irq_op.irq = irq;
  515. irq_op.vector = 0;
  516. /* Only the privileged domain can do this. For non-priv, the pcifront
  517. * driver provides a PCI bus that does the call to do exactly
  518. * this in the priv domain. */
  519. if (xen_initial_domain() &&
  520. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  521. xen_free_irq(irq);
  522. irq = -ENOSPC;
  523. goto out;
  524. }
  525. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
  526. shareable ? PIRQ_SHAREABLE : 0);
  527. pirq_query_unmask(irq);
  528. /* We try to use the handler with the appropriate semantic for the
  529. * type of interrupt: if the interrupt is an edge triggered
  530. * interrupt we use handle_edge_irq.
  531. *
  532. * On the other hand if the interrupt is level triggered we use
  533. * handle_fasteoi_irq like the native code does for this kind of
  534. * interrupts.
  535. *
  536. * Depending on the Xen version, pirq_needs_eoi might return true
  537. * not only for level triggered interrupts but for edge triggered
  538. * interrupts too. In any case Xen always honors the eoi mechanism,
  539. * not injecting any more pirqs of the same kind if the first one
  540. * hasn't received an eoi yet. Therefore using the fasteoi handler
  541. * is the right choice either way.
  542. */
  543. if (shareable)
  544. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  545. handle_fasteoi_irq, name);
  546. else
  547. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  548. handle_edge_irq, name);
  549. out:
  550. spin_unlock(&irq_mapping_update_lock);
  551. return irq;
  552. }
  553. #ifdef CONFIG_PCI_MSI
  554. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  555. {
  556. int rc;
  557. struct physdev_get_free_pirq op_get_free_pirq;
  558. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  559. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  560. WARN_ONCE(rc == -ENOSYS,
  561. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  562. return rc ? -1 : op_get_free_pirq.pirq;
  563. }
  564. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  565. int pirq, int vector, const char *name,
  566. domid_t domid)
  567. {
  568. int irq, ret;
  569. spin_lock(&irq_mapping_update_lock);
  570. irq = xen_allocate_irq_dynamic();
  571. if (irq == -1)
  572. goto out;
  573. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
  574. name);
  575. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
  576. ret = irq_set_msi_desc(irq, msidesc);
  577. if (ret < 0)
  578. goto error_irq;
  579. out:
  580. spin_unlock(&irq_mapping_update_lock);
  581. return irq;
  582. error_irq:
  583. spin_unlock(&irq_mapping_update_lock);
  584. xen_free_irq(irq);
  585. return -1;
  586. }
  587. #endif
  588. int xen_destroy_irq(int irq)
  589. {
  590. struct irq_desc *desc;
  591. struct physdev_unmap_pirq unmap_irq;
  592. struct irq_info *info = info_for_irq(irq);
  593. int rc = -ENOENT;
  594. spin_lock(&irq_mapping_update_lock);
  595. desc = irq_to_desc(irq);
  596. if (!desc)
  597. goto out;
  598. if (xen_initial_domain()) {
  599. unmap_irq.pirq = info->u.pirq.pirq;
  600. unmap_irq.domid = info->u.pirq.domid;
  601. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  602. /* If another domain quits without making the pci_disable_msix
  603. * call, the Xen hypervisor takes care of freeing the PIRQs
  604. * (free_domain_pirqs).
  605. */
  606. if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
  607. printk(KERN_INFO "domain %d does not have %d anymore\n",
  608. info->u.pirq.domid, info->u.pirq.pirq);
  609. else if (rc) {
  610. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  611. goto out;
  612. }
  613. }
  614. xen_free_irq(irq);
  615. out:
  616. spin_unlock(&irq_mapping_update_lock);
  617. return rc;
  618. }
  619. int xen_irq_from_pirq(unsigned pirq)
  620. {
  621. int irq;
  622. struct irq_info *info;
  623. spin_lock(&irq_mapping_update_lock);
  624. list_for_each_entry(info, &xen_irq_list_head, list) {
  625. if (info == NULL || info->type != IRQT_PIRQ)
  626. continue;
  627. irq = info->irq;
  628. if (info->u.pirq.pirq == pirq)
  629. goto out;
  630. }
  631. irq = -1;
  632. out:
  633. spin_unlock(&irq_mapping_update_lock);
  634. return irq;
  635. }
  636. int xen_pirq_from_irq(unsigned irq)
  637. {
  638. return pirq_from_irq(irq);
  639. }
  640. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  641. int bind_evtchn_to_irq(unsigned int evtchn)
  642. {
  643. int irq;
  644. spin_lock(&irq_mapping_update_lock);
  645. irq = evtchn_to_irq[evtchn];
  646. if (irq == -1) {
  647. irq = xen_allocate_irq_dynamic();
  648. if (irq == -1)
  649. goto out;
  650. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  651. handle_edge_irq, "event");
  652. xen_irq_info_evtchn_init(irq, evtchn);
  653. }
  654. out:
  655. spin_unlock(&irq_mapping_update_lock);
  656. return irq;
  657. }
  658. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  659. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  660. {
  661. struct evtchn_bind_ipi bind_ipi;
  662. int evtchn, irq;
  663. spin_lock(&irq_mapping_update_lock);
  664. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  665. if (irq == -1) {
  666. irq = xen_allocate_irq_dynamic();
  667. if (irq < 0)
  668. goto out;
  669. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  670. handle_percpu_irq, "ipi");
  671. bind_ipi.vcpu = cpu;
  672. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  673. &bind_ipi) != 0)
  674. BUG();
  675. evtchn = bind_ipi.port;
  676. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  677. bind_evtchn_to_cpu(evtchn, cpu);
  678. }
  679. out:
  680. spin_unlock(&irq_mapping_update_lock);
  681. return irq;
  682. }
  683. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  684. unsigned int remote_port)
  685. {
  686. struct evtchn_bind_interdomain bind_interdomain;
  687. int err;
  688. bind_interdomain.remote_dom = remote_domain;
  689. bind_interdomain.remote_port = remote_port;
  690. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  691. &bind_interdomain);
  692. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  693. }
  694. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  695. {
  696. struct evtchn_bind_virq bind_virq;
  697. int evtchn, irq;
  698. spin_lock(&irq_mapping_update_lock);
  699. irq = per_cpu(virq_to_irq, cpu)[virq];
  700. if (irq == -1) {
  701. irq = xen_allocate_irq_dynamic();
  702. if (irq == -1)
  703. goto out;
  704. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  705. handle_percpu_irq, "virq");
  706. bind_virq.virq = virq;
  707. bind_virq.vcpu = cpu;
  708. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  709. &bind_virq) != 0)
  710. BUG();
  711. evtchn = bind_virq.port;
  712. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  713. bind_evtchn_to_cpu(evtchn, cpu);
  714. }
  715. out:
  716. spin_unlock(&irq_mapping_update_lock);
  717. return irq;
  718. }
  719. static void unbind_from_irq(unsigned int irq)
  720. {
  721. struct evtchn_close close;
  722. int evtchn = evtchn_from_irq(irq);
  723. spin_lock(&irq_mapping_update_lock);
  724. if (VALID_EVTCHN(evtchn)) {
  725. close.port = evtchn;
  726. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  727. BUG();
  728. switch (type_from_irq(irq)) {
  729. case IRQT_VIRQ:
  730. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  731. [virq_from_irq(irq)] = -1;
  732. break;
  733. case IRQT_IPI:
  734. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  735. [ipi_from_irq(irq)] = -1;
  736. break;
  737. default:
  738. break;
  739. }
  740. /* Closed ports are implicitly re-bound to VCPU0. */
  741. bind_evtchn_to_cpu(evtchn, 0);
  742. evtchn_to_irq[evtchn] = -1;
  743. }
  744. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  745. xen_free_irq(irq);
  746. spin_unlock(&irq_mapping_update_lock);
  747. }
  748. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  749. irq_handler_t handler,
  750. unsigned long irqflags,
  751. const char *devname, void *dev_id)
  752. {
  753. int irq, retval;
  754. irq = bind_evtchn_to_irq(evtchn);
  755. if (irq < 0)
  756. return irq;
  757. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  758. if (retval != 0) {
  759. unbind_from_irq(irq);
  760. return retval;
  761. }
  762. return irq;
  763. }
  764. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  765. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  766. unsigned int remote_port,
  767. irq_handler_t handler,
  768. unsigned long irqflags,
  769. const char *devname,
  770. void *dev_id)
  771. {
  772. int irq, retval;
  773. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  774. if (irq < 0)
  775. return irq;
  776. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  777. if (retval != 0) {
  778. unbind_from_irq(irq);
  779. return retval;
  780. }
  781. return irq;
  782. }
  783. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  784. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  785. irq_handler_t handler,
  786. unsigned long irqflags, const char *devname, void *dev_id)
  787. {
  788. int irq, retval;
  789. irq = bind_virq_to_irq(virq, cpu);
  790. if (irq < 0)
  791. return irq;
  792. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  793. if (retval != 0) {
  794. unbind_from_irq(irq);
  795. return retval;
  796. }
  797. return irq;
  798. }
  799. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  800. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  801. unsigned int cpu,
  802. irq_handler_t handler,
  803. unsigned long irqflags,
  804. const char *devname,
  805. void *dev_id)
  806. {
  807. int irq, retval;
  808. irq = bind_ipi_to_irq(ipi, cpu);
  809. if (irq < 0)
  810. return irq;
  811. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
  812. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  813. if (retval != 0) {
  814. unbind_from_irq(irq);
  815. return retval;
  816. }
  817. return irq;
  818. }
  819. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  820. {
  821. free_irq(irq, dev_id);
  822. unbind_from_irq(irq);
  823. }
  824. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  825. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  826. {
  827. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  828. BUG_ON(irq < 0);
  829. notify_remote_via_irq(irq);
  830. }
  831. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  832. {
  833. struct shared_info *sh = HYPERVISOR_shared_info;
  834. int cpu = smp_processor_id();
  835. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  836. int i;
  837. unsigned long flags;
  838. static DEFINE_SPINLOCK(debug_lock);
  839. struct vcpu_info *v;
  840. spin_lock_irqsave(&debug_lock, flags);
  841. printk("\nvcpu %d\n ", cpu);
  842. for_each_online_cpu(i) {
  843. int pending;
  844. v = per_cpu(xen_vcpu, i);
  845. pending = (get_irq_regs() && i == cpu)
  846. ? xen_irqs_disabled(get_irq_regs())
  847. : v->evtchn_upcall_mask;
  848. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  849. pending, v->evtchn_upcall_pending,
  850. (int)(sizeof(v->evtchn_pending_sel)*2),
  851. v->evtchn_pending_sel);
  852. }
  853. v = per_cpu(xen_vcpu, cpu);
  854. printk("\npending:\n ");
  855. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  856. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  857. sh->evtchn_pending[i],
  858. i % 8 == 0 ? "\n " : " ");
  859. printk("\nglobal mask:\n ");
  860. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  861. printk("%0*lx%s",
  862. (int)(sizeof(sh->evtchn_mask[0])*2),
  863. sh->evtchn_mask[i],
  864. i % 8 == 0 ? "\n " : " ");
  865. printk("\nglobally unmasked:\n ");
  866. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  867. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  868. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  869. i % 8 == 0 ? "\n " : " ");
  870. printk("\nlocal cpu%d mask:\n ", cpu);
  871. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  872. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  873. cpu_evtchn[i],
  874. i % 8 == 0 ? "\n " : " ");
  875. printk("\nlocally unmasked:\n ");
  876. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  877. unsigned long pending = sh->evtchn_pending[i]
  878. & ~sh->evtchn_mask[i]
  879. & cpu_evtchn[i];
  880. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  881. pending, i % 8 == 0 ? "\n " : " ");
  882. }
  883. printk("\npending list:\n");
  884. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  885. if (sync_test_bit(i, sh->evtchn_pending)) {
  886. int word_idx = i / BITS_PER_LONG;
  887. printk(" %d: event %d -> irq %d%s%s%s\n",
  888. cpu_from_evtchn(i), i,
  889. evtchn_to_irq[i],
  890. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  891. ? "" : " l2-clear",
  892. !sync_test_bit(i, sh->evtchn_mask)
  893. ? "" : " globally-masked",
  894. sync_test_bit(i, cpu_evtchn)
  895. ? "" : " locally-masked");
  896. }
  897. }
  898. spin_unlock_irqrestore(&debug_lock, flags);
  899. return IRQ_HANDLED;
  900. }
  901. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  902. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  903. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  904. /*
  905. * Mask out the i least significant bits of w
  906. */
  907. #define MASK_LSBS(w, i) (w & ((~0UL) << i))
  908. /*
  909. * Search the CPUs pending events bitmasks. For each one found, map
  910. * the event number to an irq, and feed it into do_IRQ() for
  911. * handling.
  912. *
  913. * Xen uses a two-level bitmap to speed searching. The first level is
  914. * a bitset of words which contain pending event bits. The second
  915. * level is a bitset of pending events themselves.
  916. */
  917. static void __xen_evtchn_do_upcall(void)
  918. {
  919. int start_word_idx, start_bit_idx;
  920. int word_idx, bit_idx;
  921. int i;
  922. int cpu = get_cpu();
  923. struct shared_info *s = HYPERVISOR_shared_info;
  924. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  925. unsigned count;
  926. do {
  927. unsigned long pending_words;
  928. vcpu_info->evtchn_upcall_pending = 0;
  929. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  930. goto out;
  931. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  932. /* Clear master flag /before/ clearing selector flag. */
  933. wmb();
  934. #endif
  935. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  936. start_word_idx = __this_cpu_read(current_word_idx);
  937. start_bit_idx = __this_cpu_read(current_bit_idx);
  938. word_idx = start_word_idx;
  939. for (i = 0; pending_words != 0; i++) {
  940. unsigned long pending_bits;
  941. unsigned long words;
  942. words = MASK_LSBS(pending_words, word_idx);
  943. /*
  944. * If we masked out all events, wrap to beginning.
  945. */
  946. if (words == 0) {
  947. word_idx = 0;
  948. bit_idx = 0;
  949. continue;
  950. }
  951. word_idx = __ffs(words);
  952. pending_bits = active_evtchns(cpu, s, word_idx);
  953. bit_idx = 0; /* usually scan entire word from start */
  954. if (word_idx == start_word_idx) {
  955. /* We scan the starting word in two parts */
  956. if (i == 0)
  957. /* 1st time: start in the middle */
  958. bit_idx = start_bit_idx;
  959. else
  960. /* 2nd time: mask bits done already */
  961. bit_idx &= (1UL << start_bit_idx) - 1;
  962. }
  963. do {
  964. unsigned long bits;
  965. int port, irq;
  966. struct irq_desc *desc;
  967. bits = MASK_LSBS(pending_bits, bit_idx);
  968. /* If we masked out all events, move on. */
  969. if (bits == 0)
  970. break;
  971. bit_idx = __ffs(bits);
  972. /* Process port. */
  973. port = (word_idx * BITS_PER_LONG) + bit_idx;
  974. irq = evtchn_to_irq[port];
  975. if (irq != -1) {
  976. desc = irq_to_desc(irq);
  977. if (desc)
  978. generic_handle_irq_desc(irq, desc);
  979. }
  980. bit_idx = (bit_idx + 1) % BITS_PER_LONG;
  981. /* Next caller starts at last processed + 1 */
  982. __this_cpu_write(current_word_idx,
  983. bit_idx ? word_idx :
  984. (word_idx+1) % BITS_PER_LONG);
  985. __this_cpu_write(current_bit_idx, bit_idx);
  986. } while (bit_idx != 0);
  987. /* Scan start_l1i twice; all others once. */
  988. if ((word_idx != start_word_idx) || (i != 0))
  989. pending_words &= ~(1UL << word_idx);
  990. word_idx = (word_idx + 1) % BITS_PER_LONG;
  991. }
  992. BUG_ON(!irqs_disabled());
  993. count = __this_cpu_read(xed_nesting_count);
  994. __this_cpu_write(xed_nesting_count, 0);
  995. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  996. out:
  997. put_cpu();
  998. }
  999. void xen_evtchn_do_upcall(struct pt_regs *regs)
  1000. {
  1001. struct pt_regs *old_regs = set_irq_regs(regs);
  1002. exit_idle();
  1003. irq_enter();
  1004. __xen_evtchn_do_upcall();
  1005. irq_exit();
  1006. set_irq_regs(old_regs);
  1007. }
  1008. void xen_hvm_evtchn_do_upcall(void)
  1009. {
  1010. __xen_evtchn_do_upcall();
  1011. }
  1012. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  1013. /* Rebind a new event channel to an existing irq. */
  1014. void rebind_evtchn_irq(int evtchn, int irq)
  1015. {
  1016. struct irq_info *info = info_for_irq(irq);
  1017. /* Make sure the irq is masked, since the new event channel
  1018. will also be masked. */
  1019. disable_irq(irq);
  1020. spin_lock(&irq_mapping_update_lock);
  1021. /* After resume the irq<->evtchn mappings are all cleared out */
  1022. BUG_ON(evtchn_to_irq[evtchn] != -1);
  1023. /* Expect irq to have been bound before,
  1024. so there should be a proper type */
  1025. BUG_ON(info->type == IRQT_UNBOUND);
  1026. xen_irq_info_evtchn_init(irq, evtchn);
  1027. spin_unlock(&irq_mapping_update_lock);
  1028. /* new event channels are always bound to cpu 0 */
  1029. irq_set_affinity(irq, cpumask_of(0));
  1030. /* Unmask the event channel. */
  1031. enable_irq(irq);
  1032. }
  1033. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1034. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1035. {
  1036. struct evtchn_bind_vcpu bind_vcpu;
  1037. int evtchn = evtchn_from_irq(irq);
  1038. if (!VALID_EVTCHN(evtchn))
  1039. return -1;
  1040. /*
  1041. * Events delivered via platform PCI interrupts are always
  1042. * routed to vcpu 0 and hence cannot be rebound.
  1043. */
  1044. if (xen_hvm_domain() && !xen_have_vector_callback)
  1045. return -1;
  1046. /* Send future instances of this interrupt to other vcpu. */
  1047. bind_vcpu.port = evtchn;
  1048. bind_vcpu.vcpu = tcpu;
  1049. /*
  1050. * If this fails, it usually just indicates that we're dealing with a
  1051. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1052. * it, but don't do the xenlinux-level rebind in that case.
  1053. */
  1054. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1055. bind_evtchn_to_cpu(evtchn, tcpu);
  1056. return 0;
  1057. }
  1058. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1059. bool force)
  1060. {
  1061. unsigned tcpu = cpumask_first(dest);
  1062. return rebind_irq_to_cpu(data->irq, tcpu);
  1063. }
  1064. int resend_irq_on_evtchn(unsigned int irq)
  1065. {
  1066. int masked, evtchn = evtchn_from_irq(irq);
  1067. struct shared_info *s = HYPERVISOR_shared_info;
  1068. if (!VALID_EVTCHN(evtchn))
  1069. return 1;
  1070. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1071. sync_set_bit(evtchn, s->evtchn_pending);
  1072. if (!masked)
  1073. unmask_evtchn(evtchn);
  1074. return 1;
  1075. }
  1076. static void enable_dynirq(struct irq_data *data)
  1077. {
  1078. int evtchn = evtchn_from_irq(data->irq);
  1079. if (VALID_EVTCHN(evtchn))
  1080. unmask_evtchn(evtchn);
  1081. }
  1082. static void disable_dynirq(struct irq_data *data)
  1083. {
  1084. int evtchn = evtchn_from_irq(data->irq);
  1085. if (VALID_EVTCHN(evtchn))
  1086. mask_evtchn(evtchn);
  1087. }
  1088. static void ack_dynirq(struct irq_data *data)
  1089. {
  1090. int evtchn = evtchn_from_irq(data->irq);
  1091. irq_move_irq(data);
  1092. if (VALID_EVTCHN(evtchn))
  1093. clear_evtchn(evtchn);
  1094. }
  1095. static void mask_ack_dynirq(struct irq_data *data)
  1096. {
  1097. disable_dynirq(data);
  1098. ack_dynirq(data);
  1099. }
  1100. static int retrigger_dynirq(struct irq_data *data)
  1101. {
  1102. int evtchn = evtchn_from_irq(data->irq);
  1103. struct shared_info *sh = HYPERVISOR_shared_info;
  1104. int ret = 0;
  1105. if (VALID_EVTCHN(evtchn)) {
  1106. int masked;
  1107. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1108. sync_set_bit(evtchn, sh->evtchn_pending);
  1109. if (!masked)
  1110. unmask_evtchn(evtchn);
  1111. ret = 1;
  1112. }
  1113. return ret;
  1114. }
  1115. static void restore_pirqs(void)
  1116. {
  1117. int pirq, rc, irq, gsi;
  1118. struct physdev_map_pirq map_irq;
  1119. struct irq_info *info;
  1120. list_for_each_entry(info, &xen_irq_list_head, list) {
  1121. if (info->type != IRQT_PIRQ)
  1122. continue;
  1123. pirq = info->u.pirq.pirq;
  1124. gsi = info->u.pirq.gsi;
  1125. irq = info->irq;
  1126. /* save/restore of PT devices doesn't work, so at this point the
  1127. * only devices present are GSI based emulated devices */
  1128. if (!gsi)
  1129. continue;
  1130. map_irq.domid = DOMID_SELF;
  1131. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1132. map_irq.index = gsi;
  1133. map_irq.pirq = pirq;
  1134. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1135. if (rc) {
  1136. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1137. gsi, irq, pirq, rc);
  1138. xen_free_irq(irq);
  1139. continue;
  1140. }
  1141. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1142. __startup_pirq(irq);
  1143. }
  1144. }
  1145. static void restore_cpu_virqs(unsigned int cpu)
  1146. {
  1147. struct evtchn_bind_virq bind_virq;
  1148. int virq, irq, evtchn;
  1149. for (virq = 0; virq < NR_VIRQS; virq++) {
  1150. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1151. continue;
  1152. BUG_ON(virq_from_irq(irq) != virq);
  1153. /* Get a new binding from Xen. */
  1154. bind_virq.virq = virq;
  1155. bind_virq.vcpu = cpu;
  1156. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1157. &bind_virq) != 0)
  1158. BUG();
  1159. evtchn = bind_virq.port;
  1160. /* Record the new mapping. */
  1161. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1162. bind_evtchn_to_cpu(evtchn, cpu);
  1163. }
  1164. }
  1165. static void restore_cpu_ipis(unsigned int cpu)
  1166. {
  1167. struct evtchn_bind_ipi bind_ipi;
  1168. int ipi, irq, evtchn;
  1169. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1170. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1171. continue;
  1172. BUG_ON(ipi_from_irq(irq) != ipi);
  1173. /* Get a new binding from Xen. */
  1174. bind_ipi.vcpu = cpu;
  1175. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1176. &bind_ipi) != 0)
  1177. BUG();
  1178. evtchn = bind_ipi.port;
  1179. /* Record the new mapping. */
  1180. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1181. bind_evtchn_to_cpu(evtchn, cpu);
  1182. }
  1183. }
  1184. /* Clear an irq's pending state, in preparation for polling on it */
  1185. void xen_clear_irq_pending(int irq)
  1186. {
  1187. int evtchn = evtchn_from_irq(irq);
  1188. if (VALID_EVTCHN(evtchn))
  1189. clear_evtchn(evtchn);
  1190. }
  1191. EXPORT_SYMBOL(xen_clear_irq_pending);
  1192. void xen_set_irq_pending(int irq)
  1193. {
  1194. int evtchn = evtchn_from_irq(irq);
  1195. if (VALID_EVTCHN(evtchn))
  1196. set_evtchn(evtchn);
  1197. }
  1198. bool xen_test_irq_pending(int irq)
  1199. {
  1200. int evtchn = evtchn_from_irq(irq);
  1201. bool ret = false;
  1202. if (VALID_EVTCHN(evtchn))
  1203. ret = test_evtchn(evtchn);
  1204. return ret;
  1205. }
  1206. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1207. * the irq will be disabled so it won't deliver an interrupt. */
  1208. void xen_poll_irq_timeout(int irq, u64 timeout)
  1209. {
  1210. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1211. if (VALID_EVTCHN(evtchn)) {
  1212. struct sched_poll poll;
  1213. poll.nr_ports = 1;
  1214. poll.timeout = timeout;
  1215. set_xen_guest_handle(poll.ports, &evtchn);
  1216. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1217. BUG();
  1218. }
  1219. }
  1220. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1221. /* Poll waiting for an irq to become pending. In the usual case, the
  1222. * irq will be disabled so it won't deliver an interrupt. */
  1223. void xen_poll_irq(int irq)
  1224. {
  1225. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1226. }
  1227. /* Check whether the IRQ line is shared with other guests. */
  1228. int xen_test_irq_shared(int irq)
  1229. {
  1230. struct irq_info *info = info_for_irq(irq);
  1231. struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
  1232. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1233. return 0;
  1234. return !(irq_status.flags & XENIRQSTAT_shared);
  1235. }
  1236. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1237. void xen_irq_resume(void)
  1238. {
  1239. unsigned int cpu, evtchn;
  1240. struct irq_info *info;
  1241. init_evtchn_cpu_bindings();
  1242. /* New event-channel space is not 'live' yet. */
  1243. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1244. mask_evtchn(evtchn);
  1245. /* No IRQ <-> event-channel mappings. */
  1246. list_for_each_entry(info, &xen_irq_list_head, list)
  1247. info->evtchn = 0; /* zap event-channel binding */
  1248. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1249. evtchn_to_irq[evtchn] = -1;
  1250. for_each_possible_cpu(cpu) {
  1251. restore_cpu_virqs(cpu);
  1252. restore_cpu_ipis(cpu);
  1253. }
  1254. restore_pirqs();
  1255. }
  1256. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1257. .name = "xen-dyn",
  1258. .irq_disable = disable_dynirq,
  1259. .irq_mask = disable_dynirq,
  1260. .irq_unmask = enable_dynirq,
  1261. .irq_ack = ack_dynirq,
  1262. .irq_mask_ack = mask_ack_dynirq,
  1263. .irq_set_affinity = set_affinity_irq,
  1264. .irq_retrigger = retrigger_dynirq,
  1265. };
  1266. static struct irq_chip xen_pirq_chip __read_mostly = {
  1267. .name = "xen-pirq",
  1268. .irq_startup = startup_pirq,
  1269. .irq_shutdown = shutdown_pirq,
  1270. .irq_enable = enable_pirq,
  1271. .irq_disable = disable_pirq,
  1272. .irq_mask = disable_dynirq,
  1273. .irq_unmask = enable_dynirq,
  1274. .irq_ack = eoi_pirq,
  1275. .irq_eoi = eoi_pirq,
  1276. .irq_mask_ack = mask_ack_pirq,
  1277. .irq_set_affinity = set_affinity_irq,
  1278. .irq_retrigger = retrigger_dynirq,
  1279. };
  1280. static struct irq_chip xen_percpu_chip __read_mostly = {
  1281. .name = "xen-percpu",
  1282. .irq_disable = disable_dynirq,
  1283. .irq_mask = disable_dynirq,
  1284. .irq_unmask = enable_dynirq,
  1285. .irq_ack = ack_dynirq,
  1286. };
  1287. int xen_set_callback_via(uint64_t via)
  1288. {
  1289. struct xen_hvm_param a;
  1290. a.domid = DOMID_SELF;
  1291. a.index = HVM_PARAM_CALLBACK_IRQ;
  1292. a.value = via;
  1293. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1294. }
  1295. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1296. #ifdef CONFIG_XEN_PVHVM
  1297. /* Vector callbacks are better than PCI interrupts to receive event
  1298. * channel notifications because we can receive vector callbacks on any
  1299. * vcpu and we don't need PCI support or APIC interactions. */
  1300. void xen_callback_vector(void)
  1301. {
  1302. int rc;
  1303. uint64_t callback_via;
  1304. if (xen_have_vector_callback) {
  1305. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1306. rc = xen_set_callback_via(callback_via);
  1307. if (rc) {
  1308. printk(KERN_ERR "Request for Xen HVM callback vector"
  1309. " failed.\n");
  1310. xen_have_vector_callback = 0;
  1311. return;
  1312. }
  1313. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1314. "enabled\n");
  1315. /* in the restore case the vector has already been allocated */
  1316. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1317. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1318. }
  1319. }
  1320. #else
  1321. void xen_callback_vector(void) {}
  1322. #endif
  1323. void __init xen_init_IRQ(void)
  1324. {
  1325. int i;
  1326. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1327. GFP_KERNEL);
  1328. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1329. evtchn_to_irq[i] = -1;
  1330. init_evtchn_cpu_bindings();
  1331. /* No event channels are 'live' right now. */
  1332. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1333. mask_evtchn(i);
  1334. if (xen_hvm_domain()) {
  1335. xen_callback_vector();
  1336. native_init_IRQ();
  1337. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1338. * __acpi_register_gsi can point at the right function */
  1339. pci_xen_hvm_init();
  1340. } else {
  1341. irq_ctx_init(smp_processor_id());
  1342. if (xen_initial_domain())
  1343. pci_xen_initial_domain();
  1344. }
  1345. }