mwl8k.c 89 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817
  1. /*
  2. * drivers/net/wireless/mwl8k.c
  3. * Driver for Marvell TOPDOG 802.11 Wireless cards
  4. *
  5. * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/list.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <linux/etherdevice.h>
  21. #include <net/mac80211.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/firmware.h>
  24. #include <linux/workqueue.h>
  25. #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
  26. #define MWL8K_NAME KBUILD_MODNAME
  27. #define MWL8K_VERSION "0.11"
  28. /* Register definitions */
  29. #define MWL8K_HIU_GEN_PTR 0x00000c10
  30. #define MWL8K_MODE_STA 0x0000005a
  31. #define MWL8K_MODE_AP 0x000000a5
  32. #define MWL8K_HIU_INT_CODE 0x00000c14
  33. #define MWL8K_FWSTA_READY 0xf0f1f2f4
  34. #define MWL8K_FWAP_READY 0xf1f2f4a5
  35. #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
  36. #define MWL8K_HIU_SCRATCH 0x00000c40
  37. /* Host->device communications */
  38. #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
  39. #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
  40. #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
  41. #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
  42. #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
  43. #define MWL8K_H2A_INT_DUMMY (1 << 20)
  44. #define MWL8K_H2A_INT_RESET (1 << 15)
  45. #define MWL8K_H2A_INT_DOORBELL (1 << 1)
  46. #define MWL8K_H2A_INT_PPA_READY (1 << 0)
  47. /* Device->host communications */
  48. #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
  49. #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
  50. #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
  51. #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
  52. #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
  53. #define MWL8K_A2H_INT_DUMMY (1 << 20)
  54. #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
  55. #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
  56. #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
  57. #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
  58. #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
  59. #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
  60. #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
  61. #define MWL8K_A2H_INT_RX_READY (1 << 1)
  62. #define MWL8K_A2H_INT_TX_DONE (1 << 0)
  63. #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
  64. MWL8K_A2H_INT_CHNL_SWITCHED | \
  65. MWL8K_A2H_INT_QUEUE_EMPTY | \
  66. MWL8K_A2H_INT_RADAR_DETECT | \
  67. MWL8K_A2H_INT_RADIO_ON | \
  68. MWL8K_A2H_INT_RADIO_OFF | \
  69. MWL8K_A2H_INT_MAC_EVENT | \
  70. MWL8K_A2H_INT_OPC_DONE | \
  71. MWL8K_A2H_INT_RX_READY | \
  72. MWL8K_A2H_INT_TX_DONE)
  73. #define MWL8K_RX_QUEUES 1
  74. #define MWL8K_TX_QUEUES 4
  75. struct rxd_ops {
  76. int rxd_size;
  77. void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
  78. void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
  79. int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
  80. __le16 *qos);
  81. };
  82. struct mwl8k_device_info {
  83. char *part_name;
  84. char *helper_image;
  85. char *fw_image;
  86. struct rxd_ops *ap_rxd_ops;
  87. };
  88. struct mwl8k_rx_queue {
  89. int rxd_count;
  90. /* hw receives here */
  91. int head;
  92. /* refill descs here */
  93. int tail;
  94. void *rxd;
  95. dma_addr_t rxd_dma;
  96. struct {
  97. struct sk_buff *skb;
  98. DECLARE_PCI_UNMAP_ADDR(dma)
  99. } *buf;
  100. };
  101. struct mwl8k_tx_queue {
  102. /* hw transmits here */
  103. int head;
  104. /* sw appends here */
  105. int tail;
  106. struct ieee80211_tx_queue_stats stats;
  107. struct mwl8k_tx_desc *txd;
  108. dma_addr_t txd_dma;
  109. struct sk_buff **skb;
  110. };
  111. struct mwl8k_priv {
  112. struct ieee80211_hw *hw;
  113. struct pci_dev *pdev;
  114. struct mwl8k_device_info *device_info;
  115. void __iomem *sram;
  116. void __iomem *regs;
  117. /* firmware */
  118. struct firmware *fw_helper;
  119. struct firmware *fw_ucode;
  120. /* hardware/firmware parameters */
  121. bool ap_fw;
  122. struct rxd_ops *rxd_ops;
  123. /* firmware access */
  124. struct mutex fw_mutex;
  125. struct task_struct *fw_mutex_owner;
  126. int fw_mutex_depth;
  127. struct completion *hostcmd_wait;
  128. /* lock held over TX and TX reap */
  129. spinlock_t tx_lock;
  130. /* TX quiesce completion, protected by fw_mutex and tx_lock */
  131. struct completion *tx_wait;
  132. struct ieee80211_vif *vif;
  133. struct ieee80211_channel *current_channel;
  134. /* power management status cookie from firmware */
  135. u32 *cookie;
  136. dma_addr_t cookie_dma;
  137. u16 num_mcaddrs;
  138. u8 hw_rev;
  139. u32 fw_rev;
  140. /*
  141. * Running count of TX packets in flight, to avoid
  142. * iterating over the transmit rings each time.
  143. */
  144. int pending_tx_pkts;
  145. struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
  146. struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
  147. /* PHY parameters */
  148. struct ieee80211_supported_band band;
  149. struct ieee80211_channel channels[14];
  150. struct ieee80211_rate rates[14];
  151. bool radio_on;
  152. bool radio_short_preamble;
  153. bool sniffer_enabled;
  154. bool wmm_enabled;
  155. struct work_struct sta_notify_worker;
  156. spinlock_t sta_notify_list_lock;
  157. struct list_head sta_notify_list;
  158. /* XXX need to convert this to handle multiple interfaces */
  159. bool capture_beacon;
  160. u8 capture_bssid[ETH_ALEN];
  161. struct sk_buff *beacon_skb;
  162. /*
  163. * This FJ worker has to be global as it is scheduled from the
  164. * RX handler. At this point we don't know which interface it
  165. * belongs to until the list of bssids waiting to complete join
  166. * is checked.
  167. */
  168. struct work_struct finalize_join_worker;
  169. /* Tasklet to reclaim TX descriptors and buffers after tx */
  170. struct tasklet_struct tx_reclaim_task;
  171. };
  172. /* Per interface specific private data */
  173. struct mwl8k_vif {
  174. /* Non AMPDU sequence number assigned by driver. */
  175. u16 seqno;
  176. };
  177. #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
  178. struct mwl8k_sta {
  179. /* Index into station database. Returned by UPDATE_STADB. */
  180. u8 peer_id;
  181. };
  182. #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
  183. static const struct ieee80211_channel mwl8k_channels[] = {
  184. { .center_freq = 2412, .hw_value = 1, },
  185. { .center_freq = 2417, .hw_value = 2, },
  186. { .center_freq = 2422, .hw_value = 3, },
  187. { .center_freq = 2427, .hw_value = 4, },
  188. { .center_freq = 2432, .hw_value = 5, },
  189. { .center_freq = 2437, .hw_value = 6, },
  190. { .center_freq = 2442, .hw_value = 7, },
  191. { .center_freq = 2447, .hw_value = 8, },
  192. { .center_freq = 2452, .hw_value = 9, },
  193. { .center_freq = 2457, .hw_value = 10, },
  194. { .center_freq = 2462, .hw_value = 11, },
  195. { .center_freq = 2467, .hw_value = 12, },
  196. { .center_freq = 2472, .hw_value = 13, },
  197. { .center_freq = 2484, .hw_value = 14, },
  198. };
  199. static const struct ieee80211_rate mwl8k_rates[] = {
  200. { .bitrate = 10, .hw_value = 2, },
  201. { .bitrate = 20, .hw_value = 4, },
  202. { .bitrate = 55, .hw_value = 11, },
  203. { .bitrate = 110, .hw_value = 22, },
  204. { .bitrate = 220, .hw_value = 44, },
  205. { .bitrate = 60, .hw_value = 12, },
  206. { .bitrate = 90, .hw_value = 18, },
  207. { .bitrate = 120, .hw_value = 24, },
  208. { .bitrate = 180, .hw_value = 36, },
  209. { .bitrate = 240, .hw_value = 48, },
  210. { .bitrate = 360, .hw_value = 72, },
  211. { .bitrate = 480, .hw_value = 96, },
  212. { .bitrate = 540, .hw_value = 108, },
  213. { .bitrate = 720, .hw_value = 144, },
  214. };
  215. /* Set or get info from Firmware */
  216. #define MWL8K_CMD_SET 0x0001
  217. #define MWL8K_CMD_GET 0x0000
  218. /* Firmware command codes */
  219. #define MWL8K_CMD_CODE_DNLD 0x0001
  220. #define MWL8K_CMD_GET_HW_SPEC 0x0003
  221. #define MWL8K_CMD_SET_HW_SPEC 0x0004
  222. #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
  223. #define MWL8K_CMD_GET_STAT 0x0014
  224. #define MWL8K_CMD_RADIO_CONTROL 0x001c
  225. #define MWL8K_CMD_RF_TX_POWER 0x001e
  226. #define MWL8K_CMD_RF_ANTENNA 0x0020
  227. #define MWL8K_CMD_SET_PRE_SCAN 0x0107
  228. #define MWL8K_CMD_SET_POST_SCAN 0x0108
  229. #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
  230. #define MWL8K_CMD_SET_AID 0x010d
  231. #define MWL8K_CMD_SET_RATE 0x0110
  232. #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
  233. #define MWL8K_CMD_RTS_THRESHOLD 0x0113
  234. #define MWL8K_CMD_SET_SLOT 0x0114
  235. #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
  236. #define MWL8K_CMD_SET_WMM_MODE 0x0123
  237. #define MWL8K_CMD_MIMO_CONFIG 0x0125
  238. #define MWL8K_CMD_USE_FIXED_RATE 0x0126
  239. #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
  240. #define MWL8K_CMD_SET_MAC_ADDR 0x0202
  241. #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
  242. #define MWL8K_CMD_UPDATE_STADB 0x1123
  243. static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
  244. {
  245. #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
  246. snprintf(buf, bufsize, "%s", #x);\
  247. return buf;\
  248. } while (0)
  249. switch (cmd & ~0x8000) {
  250. MWL8K_CMDNAME(CODE_DNLD);
  251. MWL8K_CMDNAME(GET_HW_SPEC);
  252. MWL8K_CMDNAME(SET_HW_SPEC);
  253. MWL8K_CMDNAME(MAC_MULTICAST_ADR);
  254. MWL8K_CMDNAME(GET_STAT);
  255. MWL8K_CMDNAME(RADIO_CONTROL);
  256. MWL8K_CMDNAME(RF_TX_POWER);
  257. MWL8K_CMDNAME(RF_ANTENNA);
  258. MWL8K_CMDNAME(SET_PRE_SCAN);
  259. MWL8K_CMDNAME(SET_POST_SCAN);
  260. MWL8K_CMDNAME(SET_RF_CHANNEL);
  261. MWL8K_CMDNAME(SET_AID);
  262. MWL8K_CMDNAME(SET_RATE);
  263. MWL8K_CMDNAME(SET_FINALIZE_JOIN);
  264. MWL8K_CMDNAME(RTS_THRESHOLD);
  265. MWL8K_CMDNAME(SET_SLOT);
  266. MWL8K_CMDNAME(SET_EDCA_PARAMS);
  267. MWL8K_CMDNAME(SET_WMM_MODE);
  268. MWL8K_CMDNAME(MIMO_CONFIG);
  269. MWL8K_CMDNAME(USE_FIXED_RATE);
  270. MWL8K_CMDNAME(ENABLE_SNIFFER);
  271. MWL8K_CMDNAME(SET_MAC_ADDR);
  272. MWL8K_CMDNAME(SET_RATEADAPT_MODE);
  273. MWL8K_CMDNAME(UPDATE_STADB);
  274. default:
  275. snprintf(buf, bufsize, "0x%x", cmd);
  276. }
  277. #undef MWL8K_CMDNAME
  278. return buf;
  279. }
  280. /* Hardware and firmware reset */
  281. static void mwl8k_hw_reset(struct mwl8k_priv *priv)
  282. {
  283. iowrite32(MWL8K_H2A_INT_RESET,
  284. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  285. iowrite32(MWL8K_H2A_INT_RESET,
  286. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  287. msleep(20);
  288. }
  289. /* Release fw image */
  290. static void mwl8k_release_fw(struct firmware **fw)
  291. {
  292. if (*fw == NULL)
  293. return;
  294. release_firmware(*fw);
  295. *fw = NULL;
  296. }
  297. static void mwl8k_release_firmware(struct mwl8k_priv *priv)
  298. {
  299. mwl8k_release_fw(&priv->fw_ucode);
  300. mwl8k_release_fw(&priv->fw_helper);
  301. }
  302. /* Request fw image */
  303. static int mwl8k_request_fw(struct mwl8k_priv *priv,
  304. const char *fname, struct firmware **fw)
  305. {
  306. /* release current image */
  307. if (*fw != NULL)
  308. mwl8k_release_fw(fw);
  309. return request_firmware((const struct firmware **)fw,
  310. fname, &priv->pdev->dev);
  311. }
  312. static int mwl8k_request_firmware(struct mwl8k_priv *priv)
  313. {
  314. struct mwl8k_device_info *di = priv->device_info;
  315. int rc;
  316. if (di->helper_image != NULL) {
  317. rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
  318. if (rc) {
  319. printk(KERN_ERR "%s: Error requesting helper "
  320. "firmware file %s\n", pci_name(priv->pdev),
  321. di->helper_image);
  322. return rc;
  323. }
  324. }
  325. rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
  326. if (rc) {
  327. printk(KERN_ERR "%s: Error requesting firmware file %s\n",
  328. pci_name(priv->pdev), di->fw_image);
  329. mwl8k_release_fw(&priv->fw_helper);
  330. return rc;
  331. }
  332. return 0;
  333. }
  334. MODULE_FIRMWARE("mwl8k/helper_8687.fw");
  335. MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
  336. struct mwl8k_cmd_pkt {
  337. __le16 code;
  338. __le16 length;
  339. __le16 seq_num;
  340. __le16 result;
  341. char payload[0];
  342. } __attribute__((packed));
  343. /*
  344. * Firmware loading.
  345. */
  346. static int
  347. mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
  348. {
  349. void __iomem *regs = priv->regs;
  350. dma_addr_t dma_addr;
  351. int loops;
  352. dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
  353. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  354. return -ENOMEM;
  355. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  356. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  357. iowrite32(MWL8K_H2A_INT_DOORBELL,
  358. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  359. iowrite32(MWL8K_H2A_INT_DUMMY,
  360. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  361. loops = 1000;
  362. do {
  363. u32 int_code;
  364. int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
  365. if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
  366. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  367. break;
  368. }
  369. cond_resched();
  370. udelay(1);
  371. } while (--loops);
  372. pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
  373. return loops ? 0 : -ETIMEDOUT;
  374. }
  375. static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
  376. const u8 *data, size_t length)
  377. {
  378. struct mwl8k_cmd_pkt *cmd;
  379. int done;
  380. int rc = 0;
  381. cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
  382. if (cmd == NULL)
  383. return -ENOMEM;
  384. cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
  385. cmd->seq_num = 0;
  386. cmd->result = 0;
  387. done = 0;
  388. while (length) {
  389. int block_size = length > 256 ? 256 : length;
  390. memcpy(cmd->payload, data + done, block_size);
  391. cmd->length = cpu_to_le16(block_size);
  392. rc = mwl8k_send_fw_load_cmd(priv, cmd,
  393. sizeof(*cmd) + block_size);
  394. if (rc)
  395. break;
  396. done += block_size;
  397. length -= block_size;
  398. }
  399. if (!rc) {
  400. cmd->length = 0;
  401. rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
  402. }
  403. kfree(cmd);
  404. return rc;
  405. }
  406. static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
  407. const u8 *data, size_t length)
  408. {
  409. unsigned char *buffer;
  410. int may_continue, rc = 0;
  411. u32 done, prev_block_size;
  412. buffer = kmalloc(1024, GFP_KERNEL);
  413. if (buffer == NULL)
  414. return -ENOMEM;
  415. done = 0;
  416. prev_block_size = 0;
  417. may_continue = 1000;
  418. while (may_continue > 0) {
  419. u32 block_size;
  420. block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
  421. if (block_size & 1) {
  422. block_size &= ~1;
  423. may_continue--;
  424. } else {
  425. done += prev_block_size;
  426. length -= prev_block_size;
  427. }
  428. if (block_size > 1024 || block_size > length) {
  429. rc = -EOVERFLOW;
  430. break;
  431. }
  432. if (length == 0) {
  433. rc = 0;
  434. break;
  435. }
  436. if (block_size == 0) {
  437. rc = -EPROTO;
  438. may_continue--;
  439. udelay(1);
  440. continue;
  441. }
  442. prev_block_size = block_size;
  443. memcpy(buffer, data + done, block_size);
  444. rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
  445. if (rc)
  446. break;
  447. }
  448. if (!rc && length != 0)
  449. rc = -EREMOTEIO;
  450. kfree(buffer);
  451. return rc;
  452. }
  453. static int mwl8k_load_firmware(struct ieee80211_hw *hw)
  454. {
  455. struct mwl8k_priv *priv = hw->priv;
  456. struct firmware *fw = priv->fw_ucode;
  457. int rc;
  458. int loops;
  459. if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
  460. struct firmware *helper = priv->fw_helper;
  461. if (helper == NULL) {
  462. printk(KERN_ERR "%s: helper image needed but none "
  463. "given\n", pci_name(priv->pdev));
  464. return -EINVAL;
  465. }
  466. rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
  467. if (rc) {
  468. printk(KERN_ERR "%s: unable to load firmware "
  469. "helper image\n", pci_name(priv->pdev));
  470. return rc;
  471. }
  472. msleep(5);
  473. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  474. } else {
  475. rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
  476. }
  477. if (rc) {
  478. printk(KERN_ERR "%s: unable to load firmware image\n",
  479. pci_name(priv->pdev));
  480. return rc;
  481. }
  482. iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
  483. loops = 500000;
  484. do {
  485. u32 ready_code;
  486. ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  487. if (ready_code == MWL8K_FWAP_READY) {
  488. priv->ap_fw = 1;
  489. break;
  490. } else if (ready_code == MWL8K_FWSTA_READY) {
  491. priv->ap_fw = 0;
  492. break;
  493. }
  494. cond_resched();
  495. udelay(1);
  496. } while (--loops);
  497. return loops ? 0 : -ETIMEDOUT;
  498. }
  499. /* DMA header used by firmware and hardware. */
  500. struct mwl8k_dma_data {
  501. __le16 fwlen;
  502. struct ieee80211_hdr wh;
  503. char data[0];
  504. } __attribute__((packed));
  505. /* Routines to add/remove DMA header from skb. */
  506. static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
  507. {
  508. struct mwl8k_dma_data *tr;
  509. int hdrlen;
  510. tr = (struct mwl8k_dma_data *)skb->data;
  511. hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
  512. if (hdrlen != sizeof(tr->wh)) {
  513. if (ieee80211_is_data_qos(tr->wh.frame_control)) {
  514. memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
  515. *((__le16 *)(tr->data - 2)) = qos;
  516. } else {
  517. memmove(tr->data - hdrlen, &tr->wh, hdrlen);
  518. }
  519. }
  520. if (hdrlen != sizeof(*tr))
  521. skb_pull(skb, sizeof(*tr) - hdrlen);
  522. }
  523. static inline void mwl8k_add_dma_header(struct sk_buff *skb)
  524. {
  525. struct ieee80211_hdr *wh;
  526. int hdrlen;
  527. struct mwl8k_dma_data *tr;
  528. /*
  529. * Add a firmware DMA header; the firmware requires that we
  530. * present a 2-byte payload length followed by a 4-address
  531. * header (without QoS field), followed (optionally) by any
  532. * WEP/ExtIV header (but only filled in for CCMP).
  533. */
  534. wh = (struct ieee80211_hdr *)skb->data;
  535. hdrlen = ieee80211_hdrlen(wh->frame_control);
  536. if (hdrlen != sizeof(*tr))
  537. skb_push(skb, sizeof(*tr) - hdrlen);
  538. if (ieee80211_is_data_qos(wh->frame_control))
  539. hdrlen -= 2;
  540. tr = (struct mwl8k_dma_data *)skb->data;
  541. if (wh != &tr->wh)
  542. memmove(&tr->wh, wh, hdrlen);
  543. if (hdrlen != sizeof(tr->wh))
  544. memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
  545. /*
  546. * Firmware length is the length of the fully formed "802.11
  547. * payload". That is, everything except for the 802.11 header.
  548. * This includes all crypto material including the MIC.
  549. */
  550. tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
  551. }
  552. /*
  553. * Packet reception for 88w8366 AP firmware.
  554. */
  555. struct mwl8k_rxd_8366_ap {
  556. __le16 pkt_len;
  557. __u8 sq2;
  558. __u8 rate;
  559. __le32 pkt_phys_addr;
  560. __le32 next_rxd_phys_addr;
  561. __le16 qos_control;
  562. __le16 htsig2;
  563. __le32 hw_rssi_info;
  564. __le32 hw_noise_floor_info;
  565. __u8 noise_floor;
  566. __u8 pad0[3];
  567. __u8 rssi;
  568. __u8 rx_status;
  569. __u8 channel;
  570. __u8 rx_ctrl;
  571. } __attribute__((packed));
  572. #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
  573. #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
  574. #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
  575. #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
  576. static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
  577. {
  578. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  579. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  580. rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
  581. }
  582. static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
  583. {
  584. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  585. rxd->pkt_len = cpu_to_le16(len);
  586. rxd->pkt_phys_addr = cpu_to_le32(addr);
  587. wmb();
  588. rxd->rx_ctrl = 0;
  589. }
  590. static int
  591. mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
  592. __le16 *qos)
  593. {
  594. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  595. if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
  596. return -1;
  597. rmb();
  598. memset(status, 0, sizeof(*status));
  599. status->signal = -rxd->rssi;
  600. status->noise = -rxd->noise_floor;
  601. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
  602. status->flag |= RX_FLAG_HT;
  603. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
  604. status->flag |= RX_FLAG_40MHZ;
  605. status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
  606. } else {
  607. int i;
  608. for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
  609. if (mwl8k_rates[i].hw_value == rxd->rate) {
  610. status->rate_idx = i;
  611. break;
  612. }
  613. }
  614. }
  615. status->band = IEEE80211_BAND_2GHZ;
  616. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  617. *qos = rxd->qos_control;
  618. return le16_to_cpu(rxd->pkt_len);
  619. }
  620. static struct rxd_ops rxd_8366_ap_ops = {
  621. .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
  622. .rxd_init = mwl8k_rxd_8366_ap_init,
  623. .rxd_refill = mwl8k_rxd_8366_ap_refill,
  624. .rxd_process = mwl8k_rxd_8366_ap_process,
  625. };
  626. /*
  627. * Packet reception for STA firmware.
  628. */
  629. struct mwl8k_rxd_sta {
  630. __le16 pkt_len;
  631. __u8 link_quality;
  632. __u8 noise_level;
  633. __le32 pkt_phys_addr;
  634. __le32 next_rxd_phys_addr;
  635. __le16 qos_control;
  636. __le16 rate_info;
  637. __le32 pad0[4];
  638. __u8 rssi;
  639. __u8 channel;
  640. __le16 pad1;
  641. __u8 rx_ctrl;
  642. __u8 rx_status;
  643. __u8 pad2[2];
  644. } __attribute__((packed));
  645. #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
  646. #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
  647. #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
  648. #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
  649. #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
  650. #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
  651. #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
  652. static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
  653. {
  654. struct mwl8k_rxd_sta *rxd = _rxd;
  655. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  656. rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
  657. }
  658. static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
  659. {
  660. struct mwl8k_rxd_sta *rxd = _rxd;
  661. rxd->pkt_len = cpu_to_le16(len);
  662. rxd->pkt_phys_addr = cpu_to_le32(addr);
  663. wmb();
  664. rxd->rx_ctrl = 0;
  665. }
  666. static int
  667. mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
  668. __le16 *qos)
  669. {
  670. struct mwl8k_rxd_sta *rxd = _rxd;
  671. u16 rate_info;
  672. if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
  673. return -1;
  674. rmb();
  675. rate_info = le16_to_cpu(rxd->rate_info);
  676. memset(status, 0, sizeof(*status));
  677. status->signal = -rxd->rssi;
  678. status->noise = -rxd->noise_level;
  679. status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
  680. status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
  681. if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
  682. status->flag |= RX_FLAG_SHORTPRE;
  683. if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
  684. status->flag |= RX_FLAG_40MHZ;
  685. if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
  686. status->flag |= RX_FLAG_SHORT_GI;
  687. if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
  688. status->flag |= RX_FLAG_HT;
  689. status->band = IEEE80211_BAND_2GHZ;
  690. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  691. *qos = rxd->qos_control;
  692. return le16_to_cpu(rxd->pkt_len);
  693. }
  694. static struct rxd_ops rxd_sta_ops = {
  695. .rxd_size = sizeof(struct mwl8k_rxd_sta),
  696. .rxd_init = mwl8k_rxd_sta_init,
  697. .rxd_refill = mwl8k_rxd_sta_refill,
  698. .rxd_process = mwl8k_rxd_sta_process,
  699. };
  700. #define MWL8K_RX_DESCS 256
  701. #define MWL8K_RX_MAXSZ 3800
  702. static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
  703. {
  704. struct mwl8k_priv *priv = hw->priv;
  705. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  706. int size;
  707. int i;
  708. rxq->rxd_count = 0;
  709. rxq->head = 0;
  710. rxq->tail = 0;
  711. size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
  712. rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
  713. if (rxq->rxd == NULL) {
  714. printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
  715. wiphy_name(hw->wiphy));
  716. return -ENOMEM;
  717. }
  718. memset(rxq->rxd, 0, size);
  719. rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
  720. if (rxq->buf == NULL) {
  721. printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
  722. wiphy_name(hw->wiphy));
  723. pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
  724. return -ENOMEM;
  725. }
  726. memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
  727. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  728. int desc_size;
  729. void *rxd;
  730. int nexti;
  731. dma_addr_t next_dma_addr;
  732. desc_size = priv->rxd_ops->rxd_size;
  733. rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
  734. nexti = i + 1;
  735. if (nexti == MWL8K_RX_DESCS)
  736. nexti = 0;
  737. next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
  738. priv->rxd_ops->rxd_init(rxd, next_dma_addr);
  739. }
  740. return 0;
  741. }
  742. static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
  743. {
  744. struct mwl8k_priv *priv = hw->priv;
  745. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  746. int refilled;
  747. refilled = 0;
  748. while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
  749. struct sk_buff *skb;
  750. dma_addr_t addr;
  751. int rx;
  752. void *rxd;
  753. skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
  754. if (skb == NULL)
  755. break;
  756. addr = pci_map_single(priv->pdev, skb->data,
  757. MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
  758. rxq->rxd_count++;
  759. rx = rxq->tail++;
  760. if (rxq->tail == MWL8K_RX_DESCS)
  761. rxq->tail = 0;
  762. rxq->buf[rx].skb = skb;
  763. pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
  764. rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
  765. priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
  766. refilled++;
  767. }
  768. return refilled;
  769. }
  770. /* Must be called only when the card's reception is completely halted */
  771. static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
  772. {
  773. struct mwl8k_priv *priv = hw->priv;
  774. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  775. int i;
  776. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  777. if (rxq->buf[i].skb != NULL) {
  778. pci_unmap_single(priv->pdev,
  779. pci_unmap_addr(&rxq->buf[i], dma),
  780. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  781. pci_unmap_addr_set(&rxq->buf[i], dma, 0);
  782. kfree_skb(rxq->buf[i].skb);
  783. rxq->buf[i].skb = NULL;
  784. }
  785. }
  786. kfree(rxq->buf);
  787. rxq->buf = NULL;
  788. pci_free_consistent(priv->pdev,
  789. MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
  790. rxq->rxd, rxq->rxd_dma);
  791. rxq->rxd = NULL;
  792. }
  793. /*
  794. * Scan a list of BSSIDs to process for finalize join.
  795. * Allows for extension to process multiple BSSIDs.
  796. */
  797. static inline int
  798. mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
  799. {
  800. return priv->capture_beacon &&
  801. ieee80211_is_beacon(wh->frame_control) &&
  802. !compare_ether_addr(wh->addr3, priv->capture_bssid);
  803. }
  804. static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
  805. struct sk_buff *skb)
  806. {
  807. struct mwl8k_priv *priv = hw->priv;
  808. priv->capture_beacon = false;
  809. memset(priv->capture_bssid, 0, ETH_ALEN);
  810. /*
  811. * Use GFP_ATOMIC as rxq_process is called from
  812. * the primary interrupt handler, memory allocation call
  813. * must not sleep.
  814. */
  815. priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
  816. if (priv->beacon_skb != NULL)
  817. ieee80211_queue_work(hw, &priv->finalize_join_worker);
  818. }
  819. static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
  820. {
  821. struct mwl8k_priv *priv = hw->priv;
  822. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  823. int processed;
  824. processed = 0;
  825. while (rxq->rxd_count && limit--) {
  826. struct sk_buff *skb;
  827. void *rxd;
  828. int pkt_len;
  829. struct ieee80211_rx_status status;
  830. __le16 qos;
  831. skb = rxq->buf[rxq->head].skb;
  832. if (skb == NULL)
  833. break;
  834. rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
  835. pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
  836. if (pkt_len < 0)
  837. break;
  838. rxq->buf[rxq->head].skb = NULL;
  839. pci_unmap_single(priv->pdev,
  840. pci_unmap_addr(&rxq->buf[rxq->head], dma),
  841. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  842. pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
  843. rxq->head++;
  844. if (rxq->head == MWL8K_RX_DESCS)
  845. rxq->head = 0;
  846. rxq->rxd_count--;
  847. skb_put(skb, pkt_len);
  848. mwl8k_remove_dma_header(skb, qos);
  849. /*
  850. * Check for a pending join operation. Save a
  851. * copy of the beacon and schedule a tasklet to
  852. * send a FINALIZE_JOIN command to the firmware.
  853. */
  854. if (mwl8k_capture_bssid(priv, (void *)skb->data))
  855. mwl8k_save_beacon(hw, skb);
  856. memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
  857. ieee80211_rx_irqsafe(hw, skb);
  858. processed++;
  859. }
  860. return processed;
  861. }
  862. /*
  863. * Packet transmission.
  864. */
  865. #define MWL8K_TXD_STATUS_OK 0x00000001
  866. #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
  867. #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
  868. #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
  869. #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
  870. #define MWL8K_QOS_QLEN_UNSPEC 0xff00
  871. #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
  872. #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
  873. #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
  874. #define MWL8K_QOS_EOSP 0x0010
  875. struct mwl8k_tx_desc {
  876. __le32 status;
  877. __u8 data_rate;
  878. __u8 tx_priority;
  879. __le16 qos_control;
  880. __le32 pkt_phys_addr;
  881. __le16 pkt_len;
  882. __u8 dest_MAC_addr[ETH_ALEN];
  883. __le32 next_txd_phys_addr;
  884. __le32 reserved;
  885. __le16 rate_info;
  886. __u8 peer_id;
  887. __u8 tx_frag_cnt;
  888. } __attribute__((packed));
  889. #define MWL8K_TX_DESCS 128
  890. static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
  891. {
  892. struct mwl8k_priv *priv = hw->priv;
  893. struct mwl8k_tx_queue *txq = priv->txq + index;
  894. int size;
  895. int i;
  896. memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
  897. txq->stats.limit = MWL8K_TX_DESCS;
  898. txq->head = 0;
  899. txq->tail = 0;
  900. size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
  901. txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
  902. if (txq->txd == NULL) {
  903. printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
  904. wiphy_name(hw->wiphy));
  905. return -ENOMEM;
  906. }
  907. memset(txq->txd, 0, size);
  908. txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
  909. if (txq->skb == NULL) {
  910. printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
  911. wiphy_name(hw->wiphy));
  912. pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
  913. return -ENOMEM;
  914. }
  915. memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
  916. for (i = 0; i < MWL8K_TX_DESCS; i++) {
  917. struct mwl8k_tx_desc *tx_desc;
  918. int nexti;
  919. tx_desc = txq->txd + i;
  920. nexti = (i + 1) % MWL8K_TX_DESCS;
  921. tx_desc->status = 0;
  922. tx_desc->next_txd_phys_addr =
  923. cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
  924. }
  925. return 0;
  926. }
  927. static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
  928. {
  929. iowrite32(MWL8K_H2A_INT_PPA_READY,
  930. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  931. iowrite32(MWL8K_H2A_INT_DUMMY,
  932. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  933. ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  934. }
  935. static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
  936. {
  937. struct mwl8k_priv *priv = hw->priv;
  938. int i;
  939. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  940. struct mwl8k_tx_queue *txq = priv->txq + i;
  941. int fw_owned = 0;
  942. int drv_owned = 0;
  943. int unused = 0;
  944. int desc;
  945. for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
  946. struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
  947. u32 status;
  948. status = le32_to_cpu(tx_desc->status);
  949. if (status & MWL8K_TXD_STATUS_FW_OWNED)
  950. fw_owned++;
  951. else
  952. drv_owned++;
  953. if (tx_desc->pkt_len == 0)
  954. unused++;
  955. }
  956. printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
  957. "fw_owned=%d drv_owned=%d unused=%d\n",
  958. wiphy_name(hw->wiphy), i,
  959. txq->stats.len, txq->head, txq->tail,
  960. fw_owned, drv_owned, unused);
  961. }
  962. }
  963. /*
  964. * Must be called with priv->fw_mutex held and tx queues stopped.
  965. */
  966. #define MWL8K_TX_WAIT_TIMEOUT_MS 5000
  967. static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
  968. {
  969. struct mwl8k_priv *priv = hw->priv;
  970. DECLARE_COMPLETION_ONSTACK(tx_wait);
  971. int retry;
  972. int rc;
  973. might_sleep();
  974. /*
  975. * The TX queues are stopped at this point, so this test
  976. * doesn't need to take ->tx_lock.
  977. */
  978. if (!priv->pending_tx_pkts)
  979. return 0;
  980. retry = 0;
  981. rc = 0;
  982. spin_lock_bh(&priv->tx_lock);
  983. priv->tx_wait = &tx_wait;
  984. while (!rc) {
  985. int oldcount;
  986. unsigned long timeout;
  987. oldcount = priv->pending_tx_pkts;
  988. spin_unlock_bh(&priv->tx_lock);
  989. timeout = wait_for_completion_timeout(&tx_wait,
  990. msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
  991. spin_lock_bh(&priv->tx_lock);
  992. if (timeout) {
  993. WARN_ON(priv->pending_tx_pkts);
  994. if (retry) {
  995. printk(KERN_NOTICE "%s: tx rings drained\n",
  996. wiphy_name(hw->wiphy));
  997. }
  998. break;
  999. }
  1000. if (priv->pending_tx_pkts < oldcount) {
  1001. printk(KERN_NOTICE "%s: waiting for tx rings "
  1002. "to drain (%d -> %d pkts)\n",
  1003. wiphy_name(hw->wiphy), oldcount,
  1004. priv->pending_tx_pkts);
  1005. retry = 1;
  1006. continue;
  1007. }
  1008. priv->tx_wait = NULL;
  1009. printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
  1010. wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
  1011. mwl8k_dump_tx_rings(hw);
  1012. rc = -ETIMEDOUT;
  1013. }
  1014. spin_unlock_bh(&priv->tx_lock);
  1015. return rc;
  1016. }
  1017. #define MWL8K_TXD_SUCCESS(status) \
  1018. ((status) & (MWL8K_TXD_STATUS_OK | \
  1019. MWL8K_TXD_STATUS_OK_RETRY | \
  1020. MWL8K_TXD_STATUS_OK_MORE_RETRY))
  1021. static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
  1022. {
  1023. struct mwl8k_priv *priv = hw->priv;
  1024. struct mwl8k_tx_queue *txq = priv->txq + index;
  1025. int wake = 0;
  1026. while (txq->stats.len > 0) {
  1027. int tx;
  1028. struct mwl8k_tx_desc *tx_desc;
  1029. unsigned long addr;
  1030. int size;
  1031. struct sk_buff *skb;
  1032. struct ieee80211_tx_info *info;
  1033. u32 status;
  1034. tx = txq->head;
  1035. tx_desc = txq->txd + tx;
  1036. status = le32_to_cpu(tx_desc->status);
  1037. if (status & MWL8K_TXD_STATUS_FW_OWNED) {
  1038. if (!force)
  1039. break;
  1040. tx_desc->status &=
  1041. ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
  1042. }
  1043. txq->head = (tx + 1) % MWL8K_TX_DESCS;
  1044. BUG_ON(txq->stats.len == 0);
  1045. txq->stats.len--;
  1046. priv->pending_tx_pkts--;
  1047. addr = le32_to_cpu(tx_desc->pkt_phys_addr);
  1048. size = le16_to_cpu(tx_desc->pkt_len);
  1049. skb = txq->skb[tx];
  1050. txq->skb[tx] = NULL;
  1051. BUG_ON(skb == NULL);
  1052. pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
  1053. mwl8k_remove_dma_header(skb, tx_desc->qos_control);
  1054. /* Mark descriptor as unused */
  1055. tx_desc->pkt_phys_addr = 0;
  1056. tx_desc->pkt_len = 0;
  1057. info = IEEE80211_SKB_CB(skb);
  1058. ieee80211_tx_info_clear_status(info);
  1059. if (MWL8K_TXD_SUCCESS(status))
  1060. info->flags |= IEEE80211_TX_STAT_ACK;
  1061. ieee80211_tx_status_irqsafe(hw, skb);
  1062. wake = 1;
  1063. }
  1064. if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
  1065. ieee80211_wake_queue(hw, index);
  1066. }
  1067. /* must be called only when the card's transmit is completely halted */
  1068. static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
  1069. {
  1070. struct mwl8k_priv *priv = hw->priv;
  1071. struct mwl8k_tx_queue *txq = priv->txq + index;
  1072. mwl8k_txq_reclaim(hw, index, 1);
  1073. kfree(txq->skb);
  1074. txq->skb = NULL;
  1075. pci_free_consistent(priv->pdev,
  1076. MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
  1077. txq->txd, txq->txd_dma);
  1078. txq->txd = NULL;
  1079. }
  1080. static int
  1081. mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
  1082. {
  1083. struct mwl8k_priv *priv = hw->priv;
  1084. struct ieee80211_tx_info *tx_info;
  1085. struct mwl8k_vif *mwl8k_vif;
  1086. struct ieee80211_hdr *wh;
  1087. struct mwl8k_tx_queue *txq;
  1088. struct mwl8k_tx_desc *tx;
  1089. dma_addr_t dma;
  1090. u32 txstatus;
  1091. u8 txdatarate;
  1092. u16 qos;
  1093. wh = (struct ieee80211_hdr *)skb->data;
  1094. if (ieee80211_is_data_qos(wh->frame_control))
  1095. qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
  1096. else
  1097. qos = 0;
  1098. mwl8k_add_dma_header(skb);
  1099. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1100. tx_info = IEEE80211_SKB_CB(skb);
  1101. mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
  1102. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1103. u16 seqno = mwl8k_vif->seqno;
  1104. wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1105. wh->seq_ctrl |= cpu_to_le16(seqno << 4);
  1106. mwl8k_vif->seqno = seqno++ % 4096;
  1107. }
  1108. /* Setup firmware control bit fields for each frame type. */
  1109. txstatus = 0;
  1110. txdatarate = 0;
  1111. if (ieee80211_is_mgmt(wh->frame_control) ||
  1112. ieee80211_is_ctl(wh->frame_control)) {
  1113. txdatarate = 0;
  1114. qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
  1115. } else if (ieee80211_is_data(wh->frame_control)) {
  1116. txdatarate = 1;
  1117. if (is_multicast_ether_addr(wh->addr1))
  1118. txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
  1119. qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
  1120. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1121. qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
  1122. else
  1123. qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
  1124. }
  1125. dma = pci_map_single(priv->pdev, skb->data,
  1126. skb->len, PCI_DMA_TODEVICE);
  1127. if (pci_dma_mapping_error(priv->pdev, dma)) {
  1128. printk(KERN_DEBUG "%s: failed to dma map skb, "
  1129. "dropping TX frame.\n", wiphy_name(hw->wiphy));
  1130. dev_kfree_skb(skb);
  1131. return NETDEV_TX_OK;
  1132. }
  1133. spin_lock_bh(&priv->tx_lock);
  1134. txq = priv->txq + index;
  1135. BUG_ON(txq->skb[txq->tail] != NULL);
  1136. txq->skb[txq->tail] = skb;
  1137. tx = txq->txd + txq->tail;
  1138. tx->data_rate = txdatarate;
  1139. tx->tx_priority = index;
  1140. tx->qos_control = cpu_to_le16(qos);
  1141. tx->pkt_phys_addr = cpu_to_le32(dma);
  1142. tx->pkt_len = cpu_to_le16(skb->len);
  1143. tx->rate_info = 0;
  1144. if (!priv->ap_fw && tx_info->control.sta != NULL)
  1145. tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
  1146. else
  1147. tx->peer_id = 0;
  1148. wmb();
  1149. tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
  1150. txq->stats.count++;
  1151. txq->stats.len++;
  1152. priv->pending_tx_pkts++;
  1153. txq->tail++;
  1154. if (txq->tail == MWL8K_TX_DESCS)
  1155. txq->tail = 0;
  1156. if (txq->head == txq->tail)
  1157. ieee80211_stop_queue(hw, index);
  1158. mwl8k_tx_start(priv);
  1159. spin_unlock_bh(&priv->tx_lock);
  1160. return NETDEV_TX_OK;
  1161. }
  1162. /*
  1163. * Firmware access.
  1164. *
  1165. * We have the following requirements for issuing firmware commands:
  1166. * - Some commands require that the packet transmit path is idle when
  1167. * the command is issued. (For simplicity, we'll just quiesce the
  1168. * transmit path for every command.)
  1169. * - There are certain sequences of commands that need to be issued to
  1170. * the hardware sequentially, with no other intervening commands.
  1171. *
  1172. * This leads to an implementation of a "firmware lock" as a mutex that
  1173. * can be taken recursively, and which is taken by both the low-level
  1174. * command submission function (mwl8k_post_cmd) as well as any users of
  1175. * that function that require issuing of an atomic sequence of commands,
  1176. * and quiesces the transmit path whenever it's taken.
  1177. */
  1178. static int mwl8k_fw_lock(struct ieee80211_hw *hw)
  1179. {
  1180. struct mwl8k_priv *priv = hw->priv;
  1181. if (priv->fw_mutex_owner != current) {
  1182. int rc;
  1183. mutex_lock(&priv->fw_mutex);
  1184. ieee80211_stop_queues(hw);
  1185. rc = mwl8k_tx_wait_empty(hw);
  1186. if (rc) {
  1187. ieee80211_wake_queues(hw);
  1188. mutex_unlock(&priv->fw_mutex);
  1189. return rc;
  1190. }
  1191. priv->fw_mutex_owner = current;
  1192. }
  1193. priv->fw_mutex_depth++;
  1194. return 0;
  1195. }
  1196. static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
  1197. {
  1198. struct mwl8k_priv *priv = hw->priv;
  1199. if (!--priv->fw_mutex_depth) {
  1200. ieee80211_wake_queues(hw);
  1201. priv->fw_mutex_owner = NULL;
  1202. mutex_unlock(&priv->fw_mutex);
  1203. }
  1204. }
  1205. /*
  1206. * Command processing.
  1207. */
  1208. /* Timeout firmware commands after 10s */
  1209. #define MWL8K_CMD_TIMEOUT_MS 10000
  1210. static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
  1211. {
  1212. DECLARE_COMPLETION_ONSTACK(cmd_wait);
  1213. struct mwl8k_priv *priv = hw->priv;
  1214. void __iomem *regs = priv->regs;
  1215. dma_addr_t dma_addr;
  1216. unsigned int dma_size;
  1217. int rc;
  1218. unsigned long timeout = 0;
  1219. u8 buf[32];
  1220. cmd->result = 0xffff;
  1221. dma_size = le16_to_cpu(cmd->length);
  1222. dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
  1223. PCI_DMA_BIDIRECTIONAL);
  1224. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  1225. return -ENOMEM;
  1226. rc = mwl8k_fw_lock(hw);
  1227. if (rc) {
  1228. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1229. PCI_DMA_BIDIRECTIONAL);
  1230. return rc;
  1231. }
  1232. priv->hostcmd_wait = &cmd_wait;
  1233. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  1234. iowrite32(MWL8K_H2A_INT_DOORBELL,
  1235. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1236. iowrite32(MWL8K_H2A_INT_DUMMY,
  1237. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1238. timeout = wait_for_completion_timeout(&cmd_wait,
  1239. msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
  1240. priv->hostcmd_wait = NULL;
  1241. mwl8k_fw_unlock(hw);
  1242. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1243. PCI_DMA_BIDIRECTIONAL);
  1244. if (!timeout) {
  1245. printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
  1246. wiphy_name(hw->wiphy),
  1247. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1248. MWL8K_CMD_TIMEOUT_MS);
  1249. rc = -ETIMEDOUT;
  1250. } else {
  1251. int ms;
  1252. ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
  1253. rc = cmd->result ? -EINVAL : 0;
  1254. if (rc)
  1255. printk(KERN_ERR "%s: Command %s error 0x%x\n",
  1256. wiphy_name(hw->wiphy),
  1257. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1258. le16_to_cpu(cmd->result));
  1259. else if (ms > 2000)
  1260. printk(KERN_NOTICE "%s: Command %s took %d ms\n",
  1261. wiphy_name(hw->wiphy),
  1262. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1263. ms);
  1264. }
  1265. return rc;
  1266. }
  1267. /*
  1268. * CMD_GET_HW_SPEC (STA version).
  1269. */
  1270. struct mwl8k_cmd_get_hw_spec_sta {
  1271. struct mwl8k_cmd_pkt header;
  1272. __u8 hw_rev;
  1273. __u8 host_interface;
  1274. __le16 num_mcaddrs;
  1275. __u8 perm_addr[ETH_ALEN];
  1276. __le16 region_code;
  1277. __le32 fw_rev;
  1278. __le32 ps_cookie;
  1279. __le32 caps;
  1280. __u8 mcs_bitmap[16];
  1281. __le32 rx_queue_ptr;
  1282. __le32 num_tx_queues;
  1283. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1284. __le32 caps2;
  1285. __le32 num_tx_desc_per_queue;
  1286. __le32 total_rxd;
  1287. } __attribute__((packed));
  1288. #define MWL8K_CAP_MAX_AMSDU 0x20000000
  1289. #define MWL8K_CAP_GREENFIELD 0x08000000
  1290. #define MWL8K_CAP_AMPDU 0x04000000
  1291. #define MWL8K_CAP_RX_STBC 0x01000000
  1292. #define MWL8K_CAP_TX_STBC 0x00800000
  1293. #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
  1294. #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
  1295. #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
  1296. #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
  1297. #define MWL8K_CAP_DELAY_BA 0x00003000
  1298. #define MWL8K_CAP_MIMO 0x00000200
  1299. #define MWL8K_CAP_40MHZ 0x00000100
  1300. static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
  1301. {
  1302. struct mwl8k_priv *priv = hw->priv;
  1303. int rx_streams;
  1304. int tx_streams;
  1305. priv->band.ht_cap.ht_supported = 1;
  1306. if (cap & MWL8K_CAP_MAX_AMSDU)
  1307. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  1308. if (cap & MWL8K_CAP_GREENFIELD)
  1309. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
  1310. if (cap & MWL8K_CAP_AMPDU) {
  1311. hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
  1312. priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1313. priv->band.ht_cap.ampdu_density =
  1314. IEEE80211_HT_MPDU_DENSITY_NONE;
  1315. }
  1316. if (cap & MWL8K_CAP_RX_STBC)
  1317. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
  1318. if (cap & MWL8K_CAP_TX_STBC)
  1319. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
  1320. if (cap & MWL8K_CAP_SHORTGI_40MHZ)
  1321. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
  1322. if (cap & MWL8K_CAP_SHORTGI_20MHZ)
  1323. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
  1324. if (cap & MWL8K_CAP_DELAY_BA)
  1325. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
  1326. if (cap & MWL8K_CAP_40MHZ)
  1327. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  1328. rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
  1329. tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
  1330. priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
  1331. if (rx_streams >= 2)
  1332. priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
  1333. if (rx_streams >= 3)
  1334. priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
  1335. priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
  1336. priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1337. if (rx_streams != tx_streams) {
  1338. priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  1339. priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
  1340. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1341. }
  1342. }
  1343. static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
  1344. {
  1345. struct mwl8k_priv *priv = hw->priv;
  1346. struct mwl8k_cmd_get_hw_spec_sta *cmd;
  1347. int rc;
  1348. int i;
  1349. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1350. if (cmd == NULL)
  1351. return -ENOMEM;
  1352. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1353. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1354. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1355. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1356. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1357. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1358. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1359. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1360. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1361. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1362. rc = mwl8k_post_cmd(hw, &cmd->header);
  1363. if (!rc) {
  1364. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1365. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1366. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1367. priv->hw_rev = cmd->hw_rev;
  1368. if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
  1369. mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
  1370. }
  1371. kfree(cmd);
  1372. return rc;
  1373. }
  1374. /*
  1375. * CMD_GET_HW_SPEC (AP version).
  1376. */
  1377. struct mwl8k_cmd_get_hw_spec_ap {
  1378. struct mwl8k_cmd_pkt header;
  1379. __u8 hw_rev;
  1380. __u8 host_interface;
  1381. __le16 num_wcb;
  1382. __le16 num_mcaddrs;
  1383. __u8 perm_addr[ETH_ALEN];
  1384. __le16 region_code;
  1385. __le16 num_antenna;
  1386. __le32 fw_rev;
  1387. __le32 wcbbase0;
  1388. __le32 rxwrptr;
  1389. __le32 rxrdptr;
  1390. __le32 ps_cookie;
  1391. __le32 wcbbase1;
  1392. __le32 wcbbase2;
  1393. __le32 wcbbase3;
  1394. } __attribute__((packed));
  1395. static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
  1396. {
  1397. struct mwl8k_priv *priv = hw->priv;
  1398. struct mwl8k_cmd_get_hw_spec_ap *cmd;
  1399. int rc;
  1400. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1401. if (cmd == NULL)
  1402. return -ENOMEM;
  1403. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1404. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1405. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1406. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1407. rc = mwl8k_post_cmd(hw, &cmd->header);
  1408. if (!rc) {
  1409. int off;
  1410. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1411. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1412. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1413. priv->hw_rev = cmd->hw_rev;
  1414. off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
  1415. iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
  1416. off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
  1417. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1418. off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
  1419. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1420. off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
  1421. iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
  1422. off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
  1423. iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
  1424. off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
  1425. iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
  1426. }
  1427. kfree(cmd);
  1428. return rc;
  1429. }
  1430. /*
  1431. * CMD_SET_HW_SPEC.
  1432. */
  1433. struct mwl8k_cmd_set_hw_spec {
  1434. struct mwl8k_cmd_pkt header;
  1435. __u8 hw_rev;
  1436. __u8 host_interface;
  1437. __le16 num_mcaddrs;
  1438. __u8 perm_addr[ETH_ALEN];
  1439. __le16 region_code;
  1440. __le32 fw_rev;
  1441. __le32 ps_cookie;
  1442. __le32 caps;
  1443. __le32 rx_queue_ptr;
  1444. __le32 num_tx_queues;
  1445. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1446. __le32 flags;
  1447. __le32 num_tx_desc_per_queue;
  1448. __le32 total_rxd;
  1449. } __attribute__((packed));
  1450. #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
  1451. static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
  1452. {
  1453. struct mwl8k_priv *priv = hw->priv;
  1454. struct mwl8k_cmd_set_hw_spec *cmd;
  1455. int rc;
  1456. int i;
  1457. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1458. if (cmd == NULL)
  1459. return -ENOMEM;
  1460. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
  1461. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1462. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1463. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1464. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1465. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1466. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1467. cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
  1468. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1469. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1470. rc = mwl8k_post_cmd(hw, &cmd->header);
  1471. kfree(cmd);
  1472. return rc;
  1473. }
  1474. /*
  1475. * CMD_MAC_MULTICAST_ADR.
  1476. */
  1477. struct mwl8k_cmd_mac_multicast_adr {
  1478. struct mwl8k_cmd_pkt header;
  1479. __le16 action;
  1480. __le16 numaddr;
  1481. __u8 addr[0][ETH_ALEN];
  1482. };
  1483. #define MWL8K_ENABLE_RX_DIRECTED 0x0001
  1484. #define MWL8K_ENABLE_RX_MULTICAST 0x0002
  1485. #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
  1486. #define MWL8K_ENABLE_RX_BROADCAST 0x0008
  1487. static struct mwl8k_cmd_pkt *
  1488. __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
  1489. int mc_count, struct dev_addr_list *mclist)
  1490. {
  1491. struct mwl8k_priv *priv = hw->priv;
  1492. struct mwl8k_cmd_mac_multicast_adr *cmd;
  1493. int size;
  1494. if (allmulti || mc_count > priv->num_mcaddrs) {
  1495. allmulti = 1;
  1496. mc_count = 0;
  1497. }
  1498. size = sizeof(*cmd) + mc_count * ETH_ALEN;
  1499. cmd = kzalloc(size, GFP_ATOMIC);
  1500. if (cmd == NULL)
  1501. return NULL;
  1502. cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
  1503. cmd->header.length = cpu_to_le16(size);
  1504. cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
  1505. MWL8K_ENABLE_RX_BROADCAST);
  1506. if (allmulti) {
  1507. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
  1508. } else if (mc_count) {
  1509. int i;
  1510. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
  1511. cmd->numaddr = cpu_to_le16(mc_count);
  1512. for (i = 0; i < mc_count && mclist; i++) {
  1513. if (mclist->da_addrlen != ETH_ALEN) {
  1514. kfree(cmd);
  1515. return NULL;
  1516. }
  1517. memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
  1518. mclist = mclist->next;
  1519. }
  1520. }
  1521. return &cmd->header;
  1522. }
  1523. /*
  1524. * CMD_GET_STAT.
  1525. */
  1526. struct mwl8k_cmd_get_stat {
  1527. struct mwl8k_cmd_pkt header;
  1528. __le32 stats[64];
  1529. } __attribute__((packed));
  1530. #define MWL8K_STAT_ACK_FAILURE 9
  1531. #define MWL8K_STAT_RTS_FAILURE 12
  1532. #define MWL8K_STAT_FCS_ERROR 24
  1533. #define MWL8K_STAT_RTS_SUCCESS 11
  1534. static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
  1535. struct ieee80211_low_level_stats *stats)
  1536. {
  1537. struct mwl8k_cmd_get_stat *cmd;
  1538. int rc;
  1539. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1540. if (cmd == NULL)
  1541. return -ENOMEM;
  1542. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
  1543. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1544. rc = mwl8k_post_cmd(hw, &cmd->header);
  1545. if (!rc) {
  1546. stats->dot11ACKFailureCount =
  1547. le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
  1548. stats->dot11RTSFailureCount =
  1549. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
  1550. stats->dot11FCSErrorCount =
  1551. le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
  1552. stats->dot11RTSSuccessCount =
  1553. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
  1554. }
  1555. kfree(cmd);
  1556. return rc;
  1557. }
  1558. /*
  1559. * CMD_RADIO_CONTROL.
  1560. */
  1561. struct mwl8k_cmd_radio_control {
  1562. struct mwl8k_cmd_pkt header;
  1563. __le16 action;
  1564. __le16 control;
  1565. __le16 radio_on;
  1566. } __attribute__((packed));
  1567. static int
  1568. mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
  1569. {
  1570. struct mwl8k_priv *priv = hw->priv;
  1571. struct mwl8k_cmd_radio_control *cmd;
  1572. int rc;
  1573. if (enable == priv->radio_on && !force)
  1574. return 0;
  1575. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1576. if (cmd == NULL)
  1577. return -ENOMEM;
  1578. cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
  1579. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1580. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1581. cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
  1582. cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
  1583. rc = mwl8k_post_cmd(hw, &cmd->header);
  1584. kfree(cmd);
  1585. if (!rc)
  1586. priv->radio_on = enable;
  1587. return rc;
  1588. }
  1589. static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
  1590. {
  1591. return mwl8k_cmd_radio_control(hw, 0, 0);
  1592. }
  1593. static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
  1594. {
  1595. return mwl8k_cmd_radio_control(hw, 1, 0);
  1596. }
  1597. static int
  1598. mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
  1599. {
  1600. struct mwl8k_priv *priv = hw->priv;
  1601. priv->radio_short_preamble = short_preamble;
  1602. return mwl8k_cmd_radio_control(hw, 1, 1);
  1603. }
  1604. /*
  1605. * CMD_RF_TX_POWER.
  1606. */
  1607. #define MWL8K_TX_POWER_LEVEL_TOTAL 8
  1608. struct mwl8k_cmd_rf_tx_power {
  1609. struct mwl8k_cmd_pkt header;
  1610. __le16 action;
  1611. __le16 support_level;
  1612. __le16 current_level;
  1613. __le16 reserved;
  1614. __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
  1615. } __attribute__((packed));
  1616. static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
  1617. {
  1618. struct mwl8k_cmd_rf_tx_power *cmd;
  1619. int rc;
  1620. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1621. if (cmd == NULL)
  1622. return -ENOMEM;
  1623. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
  1624. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1625. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1626. cmd->support_level = cpu_to_le16(dBm);
  1627. rc = mwl8k_post_cmd(hw, &cmd->header);
  1628. kfree(cmd);
  1629. return rc;
  1630. }
  1631. /*
  1632. * CMD_RF_ANTENNA.
  1633. */
  1634. struct mwl8k_cmd_rf_antenna {
  1635. struct mwl8k_cmd_pkt header;
  1636. __le16 antenna;
  1637. __le16 mode;
  1638. } __attribute__((packed));
  1639. #define MWL8K_RF_ANTENNA_RX 1
  1640. #define MWL8K_RF_ANTENNA_TX 2
  1641. static int
  1642. mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
  1643. {
  1644. struct mwl8k_cmd_rf_antenna *cmd;
  1645. int rc;
  1646. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1647. if (cmd == NULL)
  1648. return -ENOMEM;
  1649. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
  1650. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1651. cmd->antenna = cpu_to_le16(antenna);
  1652. cmd->mode = cpu_to_le16(mask);
  1653. rc = mwl8k_post_cmd(hw, &cmd->header);
  1654. kfree(cmd);
  1655. return rc;
  1656. }
  1657. /*
  1658. * CMD_SET_PRE_SCAN.
  1659. */
  1660. struct mwl8k_cmd_set_pre_scan {
  1661. struct mwl8k_cmd_pkt header;
  1662. } __attribute__((packed));
  1663. static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
  1664. {
  1665. struct mwl8k_cmd_set_pre_scan *cmd;
  1666. int rc;
  1667. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1668. if (cmd == NULL)
  1669. return -ENOMEM;
  1670. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
  1671. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1672. rc = mwl8k_post_cmd(hw, &cmd->header);
  1673. kfree(cmd);
  1674. return rc;
  1675. }
  1676. /*
  1677. * CMD_SET_POST_SCAN.
  1678. */
  1679. struct mwl8k_cmd_set_post_scan {
  1680. struct mwl8k_cmd_pkt header;
  1681. __le32 isibss;
  1682. __u8 bssid[ETH_ALEN];
  1683. } __attribute__((packed));
  1684. static int
  1685. mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
  1686. {
  1687. struct mwl8k_cmd_set_post_scan *cmd;
  1688. int rc;
  1689. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1690. if (cmd == NULL)
  1691. return -ENOMEM;
  1692. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
  1693. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1694. cmd->isibss = 0;
  1695. memcpy(cmd->bssid, mac, ETH_ALEN);
  1696. rc = mwl8k_post_cmd(hw, &cmd->header);
  1697. kfree(cmd);
  1698. return rc;
  1699. }
  1700. /*
  1701. * CMD_SET_RF_CHANNEL.
  1702. */
  1703. struct mwl8k_cmd_set_rf_channel {
  1704. struct mwl8k_cmd_pkt header;
  1705. __le16 action;
  1706. __u8 current_channel;
  1707. __le32 channel_flags;
  1708. } __attribute__((packed));
  1709. static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
  1710. struct ieee80211_conf *conf)
  1711. {
  1712. struct ieee80211_channel *channel = conf->channel;
  1713. struct mwl8k_cmd_set_rf_channel *cmd;
  1714. int rc;
  1715. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1716. if (cmd == NULL)
  1717. return -ENOMEM;
  1718. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
  1719. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1720. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1721. cmd->current_channel = channel->hw_value;
  1722. if (channel->band == IEEE80211_BAND_2GHZ)
  1723. cmd->channel_flags |= cpu_to_le32(0x00000001);
  1724. if (conf->channel_type == NL80211_CHAN_NO_HT ||
  1725. conf->channel_type == NL80211_CHAN_HT20)
  1726. cmd->channel_flags |= cpu_to_le32(0x00000080);
  1727. else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
  1728. cmd->channel_flags |= cpu_to_le32(0x000001900);
  1729. else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
  1730. cmd->channel_flags |= cpu_to_le32(0x000000900);
  1731. rc = mwl8k_post_cmd(hw, &cmd->header);
  1732. kfree(cmd);
  1733. return rc;
  1734. }
  1735. /*
  1736. * CMD_SET_AID.
  1737. */
  1738. #define MWL8K_FRAME_PROT_DISABLED 0x00
  1739. #define MWL8K_FRAME_PROT_11G 0x07
  1740. #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
  1741. #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
  1742. struct mwl8k_cmd_update_set_aid {
  1743. struct mwl8k_cmd_pkt header;
  1744. __le16 aid;
  1745. /* AP's MAC address (BSSID) */
  1746. __u8 bssid[ETH_ALEN];
  1747. __le16 protection_mode;
  1748. __u8 supp_rates[14];
  1749. } __attribute__((packed));
  1750. static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
  1751. {
  1752. int i;
  1753. int j;
  1754. /*
  1755. * Clear nonstandard rates 4 and 13.
  1756. */
  1757. mask &= 0x1fef;
  1758. for (i = 0, j = 0; i < 14; i++) {
  1759. if (mask & (1 << i))
  1760. rates[j++] = mwl8k_rates[i].hw_value;
  1761. }
  1762. }
  1763. static int
  1764. mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
  1765. struct ieee80211_vif *vif, u32 legacy_rate_mask)
  1766. {
  1767. struct mwl8k_cmd_update_set_aid *cmd;
  1768. u16 prot_mode;
  1769. int rc;
  1770. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1771. if (cmd == NULL)
  1772. return -ENOMEM;
  1773. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
  1774. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1775. cmd->aid = cpu_to_le16(vif->bss_conf.aid);
  1776. memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
  1777. if (vif->bss_conf.use_cts_prot) {
  1778. prot_mode = MWL8K_FRAME_PROT_11G;
  1779. } else {
  1780. switch (vif->bss_conf.ht_operation_mode &
  1781. IEEE80211_HT_OP_MODE_PROTECTION) {
  1782. case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
  1783. prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
  1784. break;
  1785. case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
  1786. prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
  1787. break;
  1788. default:
  1789. prot_mode = MWL8K_FRAME_PROT_DISABLED;
  1790. break;
  1791. }
  1792. }
  1793. cmd->protection_mode = cpu_to_le16(prot_mode);
  1794. legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
  1795. rc = mwl8k_post_cmd(hw, &cmd->header);
  1796. kfree(cmd);
  1797. return rc;
  1798. }
  1799. /*
  1800. * CMD_SET_RATE.
  1801. */
  1802. struct mwl8k_cmd_set_rate {
  1803. struct mwl8k_cmd_pkt header;
  1804. __u8 legacy_rates[14];
  1805. /* Bitmap for supported MCS codes. */
  1806. __u8 mcs_set[16];
  1807. __u8 reserved[16];
  1808. } __attribute__((packed));
  1809. static int
  1810. mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1811. u32 legacy_rate_mask, u8 *mcs_rates)
  1812. {
  1813. struct mwl8k_cmd_set_rate *cmd;
  1814. int rc;
  1815. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1816. if (cmd == NULL)
  1817. return -ENOMEM;
  1818. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
  1819. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1820. legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
  1821. memcpy(cmd->mcs_set, mcs_rates, 16);
  1822. rc = mwl8k_post_cmd(hw, &cmd->header);
  1823. kfree(cmd);
  1824. return rc;
  1825. }
  1826. /*
  1827. * CMD_FINALIZE_JOIN.
  1828. */
  1829. #define MWL8K_FJ_BEACON_MAXLEN 128
  1830. struct mwl8k_cmd_finalize_join {
  1831. struct mwl8k_cmd_pkt header;
  1832. __le32 sleep_interval; /* Number of beacon periods to sleep */
  1833. __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
  1834. } __attribute__((packed));
  1835. static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
  1836. int framelen, int dtim)
  1837. {
  1838. struct mwl8k_cmd_finalize_join *cmd;
  1839. struct ieee80211_mgmt *payload = frame;
  1840. int payload_len;
  1841. int rc;
  1842. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1843. if (cmd == NULL)
  1844. return -ENOMEM;
  1845. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
  1846. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1847. cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
  1848. payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
  1849. if (payload_len < 0)
  1850. payload_len = 0;
  1851. else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
  1852. payload_len = MWL8K_FJ_BEACON_MAXLEN;
  1853. memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
  1854. rc = mwl8k_post_cmd(hw, &cmd->header);
  1855. kfree(cmd);
  1856. return rc;
  1857. }
  1858. /*
  1859. * CMD_SET_RTS_THRESHOLD.
  1860. */
  1861. struct mwl8k_cmd_set_rts_threshold {
  1862. struct mwl8k_cmd_pkt header;
  1863. __le16 action;
  1864. __le16 threshold;
  1865. } __attribute__((packed));
  1866. static int
  1867. mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
  1868. {
  1869. struct mwl8k_cmd_set_rts_threshold *cmd;
  1870. int rc;
  1871. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1872. if (cmd == NULL)
  1873. return -ENOMEM;
  1874. cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
  1875. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1876. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1877. cmd->threshold = cpu_to_le16(rts_thresh);
  1878. rc = mwl8k_post_cmd(hw, &cmd->header);
  1879. kfree(cmd);
  1880. return rc;
  1881. }
  1882. /*
  1883. * CMD_SET_SLOT.
  1884. */
  1885. struct mwl8k_cmd_set_slot {
  1886. struct mwl8k_cmd_pkt header;
  1887. __le16 action;
  1888. __u8 short_slot;
  1889. } __attribute__((packed));
  1890. static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
  1891. {
  1892. struct mwl8k_cmd_set_slot *cmd;
  1893. int rc;
  1894. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1895. if (cmd == NULL)
  1896. return -ENOMEM;
  1897. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
  1898. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1899. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1900. cmd->short_slot = short_slot_time;
  1901. rc = mwl8k_post_cmd(hw, &cmd->header);
  1902. kfree(cmd);
  1903. return rc;
  1904. }
  1905. /*
  1906. * CMD_SET_EDCA_PARAMS.
  1907. */
  1908. struct mwl8k_cmd_set_edca_params {
  1909. struct mwl8k_cmd_pkt header;
  1910. /* See MWL8K_SET_EDCA_XXX below */
  1911. __le16 action;
  1912. /* TX opportunity in units of 32 us */
  1913. __le16 txop;
  1914. union {
  1915. struct {
  1916. /* Log exponent of max contention period: 0...15 */
  1917. __le32 log_cw_max;
  1918. /* Log exponent of min contention period: 0...15 */
  1919. __le32 log_cw_min;
  1920. /* Adaptive interframe spacing in units of 32us */
  1921. __u8 aifs;
  1922. /* TX queue to configure */
  1923. __u8 txq;
  1924. } ap;
  1925. struct {
  1926. /* Log exponent of max contention period: 0...15 */
  1927. __u8 log_cw_max;
  1928. /* Log exponent of min contention period: 0...15 */
  1929. __u8 log_cw_min;
  1930. /* Adaptive interframe spacing in units of 32us */
  1931. __u8 aifs;
  1932. /* TX queue to configure */
  1933. __u8 txq;
  1934. } sta;
  1935. };
  1936. } __attribute__((packed));
  1937. #define MWL8K_SET_EDCA_CW 0x01
  1938. #define MWL8K_SET_EDCA_TXOP 0x02
  1939. #define MWL8K_SET_EDCA_AIFS 0x04
  1940. #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
  1941. MWL8K_SET_EDCA_TXOP | \
  1942. MWL8K_SET_EDCA_AIFS)
  1943. static int
  1944. mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
  1945. __u16 cw_min, __u16 cw_max,
  1946. __u8 aifs, __u16 txop)
  1947. {
  1948. struct mwl8k_priv *priv = hw->priv;
  1949. struct mwl8k_cmd_set_edca_params *cmd;
  1950. int rc;
  1951. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1952. if (cmd == NULL)
  1953. return -ENOMEM;
  1954. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
  1955. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1956. cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
  1957. cmd->txop = cpu_to_le16(txop);
  1958. if (priv->ap_fw) {
  1959. cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
  1960. cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
  1961. cmd->ap.aifs = aifs;
  1962. cmd->ap.txq = qnum;
  1963. } else {
  1964. cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
  1965. cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
  1966. cmd->sta.aifs = aifs;
  1967. cmd->sta.txq = qnum;
  1968. }
  1969. rc = mwl8k_post_cmd(hw, &cmd->header);
  1970. kfree(cmd);
  1971. return rc;
  1972. }
  1973. /*
  1974. * CMD_SET_WMM_MODE.
  1975. */
  1976. struct mwl8k_cmd_set_wmm_mode {
  1977. struct mwl8k_cmd_pkt header;
  1978. __le16 action;
  1979. } __attribute__((packed));
  1980. static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
  1981. {
  1982. struct mwl8k_priv *priv = hw->priv;
  1983. struct mwl8k_cmd_set_wmm_mode *cmd;
  1984. int rc;
  1985. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1986. if (cmd == NULL)
  1987. return -ENOMEM;
  1988. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
  1989. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1990. cmd->action = cpu_to_le16(!!enable);
  1991. rc = mwl8k_post_cmd(hw, &cmd->header);
  1992. kfree(cmd);
  1993. if (!rc)
  1994. priv->wmm_enabled = enable;
  1995. return rc;
  1996. }
  1997. /*
  1998. * CMD_MIMO_CONFIG.
  1999. */
  2000. struct mwl8k_cmd_mimo_config {
  2001. struct mwl8k_cmd_pkt header;
  2002. __le32 action;
  2003. __u8 rx_antenna_map;
  2004. __u8 tx_antenna_map;
  2005. } __attribute__((packed));
  2006. static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
  2007. {
  2008. struct mwl8k_cmd_mimo_config *cmd;
  2009. int rc;
  2010. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2011. if (cmd == NULL)
  2012. return -ENOMEM;
  2013. cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
  2014. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2015. cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
  2016. cmd->rx_antenna_map = rx;
  2017. cmd->tx_antenna_map = tx;
  2018. rc = mwl8k_post_cmd(hw, &cmd->header);
  2019. kfree(cmd);
  2020. return rc;
  2021. }
  2022. /*
  2023. * CMD_USE_FIXED_RATE (STA version).
  2024. */
  2025. struct mwl8k_cmd_use_fixed_rate_sta {
  2026. struct mwl8k_cmd_pkt header;
  2027. __le32 action;
  2028. __le32 allow_rate_drop;
  2029. __le32 num_rates;
  2030. struct {
  2031. __le32 is_ht_rate;
  2032. __le32 enable_retry;
  2033. __le32 rate;
  2034. __le32 retry_count;
  2035. } rate_entry[8];
  2036. __le32 rate_type;
  2037. __le32 reserved1;
  2038. __le32 reserved2;
  2039. } __attribute__((packed));
  2040. #define MWL8K_USE_AUTO_RATE 0x0002
  2041. #define MWL8K_UCAST_RATE 0
  2042. static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
  2043. {
  2044. struct mwl8k_cmd_use_fixed_rate_sta *cmd;
  2045. int rc;
  2046. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2047. if (cmd == NULL)
  2048. return -ENOMEM;
  2049. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2050. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2051. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2052. cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
  2053. rc = mwl8k_post_cmd(hw, &cmd->header);
  2054. kfree(cmd);
  2055. return rc;
  2056. }
  2057. /*
  2058. * CMD_USE_FIXED_RATE (AP version).
  2059. */
  2060. struct mwl8k_cmd_use_fixed_rate_ap {
  2061. struct mwl8k_cmd_pkt header;
  2062. __le32 action;
  2063. __le32 allow_rate_drop;
  2064. __le32 num_rates;
  2065. struct mwl8k_rate_entry_ap {
  2066. __le32 is_ht_rate;
  2067. __le32 enable_retry;
  2068. __le32 rate;
  2069. __le32 retry_count;
  2070. } rate_entry[4];
  2071. u8 multicast_rate;
  2072. u8 multicast_rate_type;
  2073. u8 management_rate;
  2074. } __attribute__((packed));
  2075. static int
  2076. mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
  2077. {
  2078. struct mwl8k_cmd_use_fixed_rate_ap *cmd;
  2079. int rc;
  2080. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2081. if (cmd == NULL)
  2082. return -ENOMEM;
  2083. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2084. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2085. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2086. cmd->multicast_rate = mcast;
  2087. cmd->management_rate = mgmt;
  2088. rc = mwl8k_post_cmd(hw, &cmd->header);
  2089. kfree(cmd);
  2090. return rc;
  2091. }
  2092. /*
  2093. * CMD_ENABLE_SNIFFER.
  2094. */
  2095. struct mwl8k_cmd_enable_sniffer {
  2096. struct mwl8k_cmd_pkt header;
  2097. __le32 action;
  2098. } __attribute__((packed));
  2099. static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
  2100. {
  2101. struct mwl8k_cmd_enable_sniffer *cmd;
  2102. int rc;
  2103. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2104. if (cmd == NULL)
  2105. return -ENOMEM;
  2106. cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
  2107. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2108. cmd->action = cpu_to_le32(!!enable);
  2109. rc = mwl8k_post_cmd(hw, &cmd->header);
  2110. kfree(cmd);
  2111. return rc;
  2112. }
  2113. /*
  2114. * CMD_SET_MAC_ADDR.
  2115. */
  2116. struct mwl8k_cmd_set_mac_addr {
  2117. struct mwl8k_cmd_pkt header;
  2118. union {
  2119. struct {
  2120. __le16 mac_type;
  2121. __u8 mac_addr[ETH_ALEN];
  2122. } mbss;
  2123. __u8 mac_addr[ETH_ALEN];
  2124. };
  2125. } __attribute__((packed));
  2126. static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
  2127. {
  2128. struct mwl8k_priv *priv = hw->priv;
  2129. struct mwl8k_cmd_set_mac_addr *cmd;
  2130. int rc;
  2131. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2132. if (cmd == NULL)
  2133. return -ENOMEM;
  2134. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
  2135. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2136. if (priv->ap_fw) {
  2137. cmd->mbss.mac_type = 0;
  2138. memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
  2139. } else {
  2140. memcpy(cmd->mac_addr, mac, ETH_ALEN);
  2141. }
  2142. rc = mwl8k_post_cmd(hw, &cmd->header);
  2143. kfree(cmd);
  2144. return rc;
  2145. }
  2146. /*
  2147. * CMD_SET_RATEADAPT_MODE.
  2148. */
  2149. struct mwl8k_cmd_set_rate_adapt_mode {
  2150. struct mwl8k_cmd_pkt header;
  2151. __le16 action;
  2152. __le16 mode;
  2153. } __attribute__((packed));
  2154. static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
  2155. {
  2156. struct mwl8k_cmd_set_rate_adapt_mode *cmd;
  2157. int rc;
  2158. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2159. if (cmd == NULL)
  2160. return -ENOMEM;
  2161. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
  2162. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2163. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  2164. cmd->mode = cpu_to_le16(mode);
  2165. rc = mwl8k_post_cmd(hw, &cmd->header);
  2166. kfree(cmd);
  2167. return rc;
  2168. }
  2169. /*
  2170. * CMD_UPDATE_STADB.
  2171. */
  2172. struct ewc_ht_info {
  2173. __le16 control1;
  2174. __le16 control2;
  2175. __le16 control3;
  2176. } __attribute__((packed));
  2177. struct peer_capability_info {
  2178. /* Peer type - AP vs. STA. */
  2179. __u8 peer_type;
  2180. /* Basic 802.11 capabilities from assoc resp. */
  2181. __le16 basic_caps;
  2182. /* Set if peer supports 802.11n high throughput (HT). */
  2183. __u8 ht_support;
  2184. /* Valid if HT is supported. */
  2185. __le16 ht_caps;
  2186. __u8 extended_ht_caps;
  2187. struct ewc_ht_info ewc_info;
  2188. /* Legacy rate table. Intersection of our rates and peer rates. */
  2189. __u8 legacy_rates[12];
  2190. /* HT rate table. Intersection of our rates and peer rates. */
  2191. __u8 ht_rates[16];
  2192. __u8 pad[16];
  2193. /* If set, interoperability mode, no proprietary extensions. */
  2194. __u8 interop;
  2195. __u8 pad2;
  2196. __u8 station_id;
  2197. __le16 amsdu_enabled;
  2198. } __attribute__((packed));
  2199. struct mwl8k_cmd_update_stadb {
  2200. struct mwl8k_cmd_pkt header;
  2201. /* See STADB_ACTION_TYPE */
  2202. __le32 action;
  2203. /* Peer MAC address */
  2204. __u8 peer_addr[ETH_ALEN];
  2205. __le32 reserved;
  2206. /* Peer info - valid during add/update. */
  2207. struct peer_capability_info peer_info;
  2208. } __attribute__((packed));
  2209. #define MWL8K_STA_DB_MODIFY_ENTRY 1
  2210. #define MWL8K_STA_DB_DEL_ENTRY 2
  2211. /* Peer Entry flags - used to define the type of the peer node */
  2212. #define MWL8K_PEER_TYPE_ACCESSPOINT 2
  2213. static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
  2214. struct ieee80211_vif *vif,
  2215. struct ieee80211_sta *sta)
  2216. {
  2217. struct mwl8k_cmd_update_stadb *cmd;
  2218. struct peer_capability_info *p;
  2219. int rc;
  2220. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2221. if (cmd == NULL)
  2222. return -ENOMEM;
  2223. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2224. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2225. cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
  2226. memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
  2227. p = &cmd->peer_info;
  2228. p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
  2229. p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
  2230. p->ht_support = sta->ht_cap.ht_supported;
  2231. p->ht_caps = sta->ht_cap.cap;
  2232. p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
  2233. ((sta->ht_cap.ampdu_density & 7) << 2);
  2234. legacy_rate_mask_to_array(p->legacy_rates,
  2235. sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2236. memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
  2237. p->interop = 1;
  2238. p->amsdu_enabled = 0;
  2239. rc = mwl8k_post_cmd(hw, &cmd->header);
  2240. kfree(cmd);
  2241. return rc ? rc : p->station_id;
  2242. }
  2243. static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
  2244. struct ieee80211_vif *vif, u8 *addr)
  2245. {
  2246. struct mwl8k_cmd_update_stadb *cmd;
  2247. int rc;
  2248. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2249. if (cmd == NULL)
  2250. return -ENOMEM;
  2251. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2252. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2253. cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
  2254. memcpy(cmd->peer_addr, addr, ETH_ALEN);
  2255. rc = mwl8k_post_cmd(hw, &cmd->header);
  2256. kfree(cmd);
  2257. return rc;
  2258. }
  2259. /*
  2260. * Interrupt handling.
  2261. */
  2262. static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
  2263. {
  2264. struct ieee80211_hw *hw = dev_id;
  2265. struct mwl8k_priv *priv = hw->priv;
  2266. u32 status;
  2267. status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2268. iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2269. if (!status)
  2270. return IRQ_NONE;
  2271. if (status & MWL8K_A2H_INT_TX_DONE)
  2272. tasklet_schedule(&priv->tx_reclaim_task);
  2273. if (status & MWL8K_A2H_INT_RX_READY) {
  2274. while (rxq_process(hw, 0, 1))
  2275. rxq_refill(hw, 0, 1);
  2276. }
  2277. if (status & MWL8K_A2H_INT_OPC_DONE) {
  2278. if (priv->hostcmd_wait != NULL)
  2279. complete(priv->hostcmd_wait);
  2280. }
  2281. if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
  2282. if (!mutex_is_locked(&priv->fw_mutex) &&
  2283. priv->radio_on && priv->pending_tx_pkts)
  2284. mwl8k_tx_start(priv);
  2285. }
  2286. return IRQ_HANDLED;
  2287. }
  2288. /*
  2289. * Core driver operations.
  2290. */
  2291. static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2292. {
  2293. struct mwl8k_priv *priv = hw->priv;
  2294. int index = skb_get_queue_mapping(skb);
  2295. int rc;
  2296. if (priv->current_channel == NULL) {
  2297. printk(KERN_DEBUG "%s: dropped TX frame since radio "
  2298. "disabled\n", wiphy_name(hw->wiphy));
  2299. dev_kfree_skb(skb);
  2300. return NETDEV_TX_OK;
  2301. }
  2302. rc = mwl8k_txq_xmit(hw, index, skb);
  2303. return rc;
  2304. }
  2305. static int mwl8k_start(struct ieee80211_hw *hw)
  2306. {
  2307. struct mwl8k_priv *priv = hw->priv;
  2308. int rc;
  2309. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2310. IRQF_SHARED, MWL8K_NAME, hw);
  2311. if (rc) {
  2312. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2313. wiphy_name(hw->wiphy));
  2314. return -EIO;
  2315. }
  2316. /* Enable tx reclaim tasklet */
  2317. tasklet_enable(&priv->tx_reclaim_task);
  2318. /* Enable interrupts */
  2319. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2320. rc = mwl8k_fw_lock(hw);
  2321. if (!rc) {
  2322. rc = mwl8k_cmd_radio_enable(hw);
  2323. if (!priv->ap_fw) {
  2324. if (!rc)
  2325. rc = mwl8k_cmd_enable_sniffer(hw, 0);
  2326. if (!rc)
  2327. rc = mwl8k_cmd_set_pre_scan(hw);
  2328. if (!rc)
  2329. rc = mwl8k_cmd_set_post_scan(hw,
  2330. "\x00\x00\x00\x00\x00\x00");
  2331. }
  2332. if (!rc)
  2333. rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
  2334. if (!rc)
  2335. rc = mwl8k_cmd_set_wmm_mode(hw, 0);
  2336. mwl8k_fw_unlock(hw);
  2337. }
  2338. if (rc) {
  2339. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2340. free_irq(priv->pdev->irq, hw);
  2341. tasklet_disable(&priv->tx_reclaim_task);
  2342. }
  2343. return rc;
  2344. }
  2345. static void mwl8k_stop(struct ieee80211_hw *hw)
  2346. {
  2347. struct mwl8k_priv *priv = hw->priv;
  2348. int i;
  2349. mwl8k_cmd_radio_disable(hw);
  2350. ieee80211_stop_queues(hw);
  2351. /* Disable interrupts */
  2352. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2353. free_irq(priv->pdev->irq, hw);
  2354. /* Stop finalize join worker */
  2355. cancel_work_sync(&priv->finalize_join_worker);
  2356. if (priv->beacon_skb != NULL)
  2357. dev_kfree_skb(priv->beacon_skb);
  2358. /* Stop tx reclaim tasklet */
  2359. tasklet_disable(&priv->tx_reclaim_task);
  2360. /* Return all skbs to mac80211 */
  2361. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2362. mwl8k_txq_reclaim(hw, i, 1);
  2363. }
  2364. static int mwl8k_add_interface(struct ieee80211_hw *hw,
  2365. struct ieee80211_vif *vif)
  2366. {
  2367. struct mwl8k_priv *priv = hw->priv;
  2368. struct mwl8k_vif *mwl8k_vif;
  2369. /*
  2370. * We only support one active interface at a time.
  2371. */
  2372. if (priv->vif != NULL)
  2373. return -EBUSY;
  2374. /*
  2375. * We only support managed interfaces for now.
  2376. */
  2377. if (vif->type != NL80211_IFTYPE_STATION)
  2378. return -EINVAL;
  2379. /*
  2380. * Reject interface creation if sniffer mode is active, as
  2381. * STA operation is mutually exclusive with hardware sniffer
  2382. * mode.
  2383. */
  2384. if (priv->sniffer_enabled) {
  2385. printk(KERN_INFO "%s: unable to create STA "
  2386. "interface due to sniffer mode being enabled\n",
  2387. wiphy_name(hw->wiphy));
  2388. return -EINVAL;
  2389. }
  2390. /* Set the mac address. */
  2391. mwl8k_cmd_set_mac_addr(hw, vif->addr);
  2392. /* Clean out driver private area */
  2393. mwl8k_vif = MWL8K_VIF(vif);
  2394. memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
  2395. /* Set Initial sequence number to zero */
  2396. mwl8k_vif->seqno = 0;
  2397. priv->vif = vif;
  2398. priv->current_channel = NULL;
  2399. return 0;
  2400. }
  2401. static void mwl8k_remove_interface(struct ieee80211_hw *hw,
  2402. struct ieee80211_vif *vif)
  2403. {
  2404. struct mwl8k_priv *priv = hw->priv;
  2405. mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  2406. priv->vif = NULL;
  2407. }
  2408. static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
  2409. {
  2410. struct ieee80211_conf *conf = &hw->conf;
  2411. struct mwl8k_priv *priv = hw->priv;
  2412. int rc;
  2413. if (conf->flags & IEEE80211_CONF_IDLE) {
  2414. mwl8k_cmd_radio_disable(hw);
  2415. priv->current_channel = NULL;
  2416. return 0;
  2417. }
  2418. rc = mwl8k_fw_lock(hw);
  2419. if (rc)
  2420. return rc;
  2421. rc = mwl8k_cmd_radio_enable(hw);
  2422. if (rc)
  2423. goto out;
  2424. rc = mwl8k_cmd_set_rf_channel(hw, conf);
  2425. if (rc)
  2426. goto out;
  2427. priv->current_channel = conf->channel;
  2428. if (conf->power_level > 18)
  2429. conf->power_level = 18;
  2430. rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
  2431. if (rc)
  2432. goto out;
  2433. if (priv->ap_fw) {
  2434. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
  2435. if (!rc)
  2436. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
  2437. } else {
  2438. rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
  2439. }
  2440. out:
  2441. mwl8k_fw_unlock(hw);
  2442. return rc;
  2443. }
  2444. static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
  2445. struct ieee80211_vif *vif,
  2446. struct ieee80211_bss_conf *info,
  2447. u32 changed)
  2448. {
  2449. struct mwl8k_priv *priv = hw->priv;
  2450. u32 ap_legacy_rates;
  2451. u8 ap_mcs_rates[16];
  2452. int rc;
  2453. if (mwl8k_fw_lock(hw))
  2454. return;
  2455. /*
  2456. * No need to capture a beacon if we're no longer associated.
  2457. */
  2458. if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
  2459. priv->capture_beacon = false;
  2460. /*
  2461. * Get the AP's legacy and MCS rates.
  2462. */
  2463. ap_legacy_rates = 0;
  2464. if (vif->bss_conf.assoc) {
  2465. struct ieee80211_sta *ap;
  2466. rcu_read_lock();
  2467. ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
  2468. if (ap == NULL) {
  2469. rcu_read_unlock();
  2470. goto out;
  2471. }
  2472. ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
  2473. memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
  2474. rcu_read_unlock();
  2475. }
  2476. if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
  2477. rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
  2478. if (rc)
  2479. goto out;
  2480. rc = mwl8k_cmd_use_fixed_rate_sta(hw);
  2481. if (rc)
  2482. goto out;
  2483. }
  2484. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2485. rc = mwl8k_set_radio_preamble(hw,
  2486. vif->bss_conf.use_short_preamble);
  2487. if (rc)
  2488. goto out;
  2489. }
  2490. if (changed & BSS_CHANGED_ERP_SLOT) {
  2491. rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
  2492. if (rc)
  2493. goto out;
  2494. }
  2495. if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) ||
  2496. (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) {
  2497. rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
  2498. if (rc)
  2499. goto out;
  2500. }
  2501. if (vif->bss_conf.assoc &&
  2502. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
  2503. /*
  2504. * Finalize the join. Tell rx handler to process
  2505. * next beacon from our BSSID.
  2506. */
  2507. memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
  2508. priv->capture_beacon = true;
  2509. }
  2510. out:
  2511. mwl8k_fw_unlock(hw);
  2512. }
  2513. static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
  2514. int mc_count, struct dev_addr_list *mclist)
  2515. {
  2516. struct mwl8k_cmd_pkt *cmd;
  2517. /*
  2518. * Synthesize and return a command packet that programs the
  2519. * hardware multicast address filter. At this point we don't
  2520. * know whether FIF_ALLMULTI is being requested, but if it is,
  2521. * we'll end up throwing this packet away and creating a new
  2522. * one in mwl8k_configure_filter().
  2523. */
  2524. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
  2525. return (unsigned long)cmd;
  2526. }
  2527. static int
  2528. mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
  2529. unsigned int changed_flags,
  2530. unsigned int *total_flags)
  2531. {
  2532. struct mwl8k_priv *priv = hw->priv;
  2533. /*
  2534. * Hardware sniffer mode is mutually exclusive with STA
  2535. * operation, so refuse to enable sniffer mode if a STA
  2536. * interface is active.
  2537. */
  2538. if (priv->vif != NULL) {
  2539. if (net_ratelimit())
  2540. printk(KERN_INFO "%s: not enabling sniffer "
  2541. "mode because STA interface is active\n",
  2542. wiphy_name(hw->wiphy));
  2543. return 0;
  2544. }
  2545. if (!priv->sniffer_enabled) {
  2546. if (mwl8k_cmd_enable_sniffer(hw, 1))
  2547. return 0;
  2548. priv->sniffer_enabled = true;
  2549. }
  2550. *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
  2551. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
  2552. FIF_OTHER_BSS;
  2553. return 1;
  2554. }
  2555. static void mwl8k_configure_filter(struct ieee80211_hw *hw,
  2556. unsigned int changed_flags,
  2557. unsigned int *total_flags,
  2558. u64 multicast)
  2559. {
  2560. struct mwl8k_priv *priv = hw->priv;
  2561. struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
  2562. /*
  2563. * AP firmware doesn't allow fine-grained control over
  2564. * the receive filter.
  2565. */
  2566. if (priv->ap_fw) {
  2567. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2568. kfree(cmd);
  2569. return;
  2570. }
  2571. /*
  2572. * Enable hardware sniffer mode if FIF_CONTROL or
  2573. * FIF_OTHER_BSS is requested.
  2574. */
  2575. if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
  2576. mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
  2577. kfree(cmd);
  2578. return;
  2579. }
  2580. /* Clear unsupported feature flags */
  2581. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2582. if (mwl8k_fw_lock(hw)) {
  2583. kfree(cmd);
  2584. return;
  2585. }
  2586. if (priv->sniffer_enabled) {
  2587. mwl8k_cmd_enable_sniffer(hw, 0);
  2588. priv->sniffer_enabled = false;
  2589. }
  2590. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  2591. if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
  2592. /*
  2593. * Disable the BSS filter.
  2594. */
  2595. mwl8k_cmd_set_pre_scan(hw);
  2596. } else {
  2597. const u8 *bssid;
  2598. /*
  2599. * Enable the BSS filter.
  2600. *
  2601. * If there is an active STA interface, use that
  2602. * interface's BSSID, otherwise use a dummy one
  2603. * (where the OUI part needs to be nonzero for
  2604. * the BSSID to be accepted by POST_SCAN).
  2605. */
  2606. bssid = "\x01\x00\x00\x00\x00\x00";
  2607. if (priv->vif != NULL)
  2608. bssid = priv->vif->bss_conf.bssid;
  2609. mwl8k_cmd_set_post_scan(hw, bssid);
  2610. }
  2611. }
  2612. /*
  2613. * If FIF_ALLMULTI is being requested, throw away the command
  2614. * packet that ->prepare_multicast() built and replace it with
  2615. * a command packet that enables reception of all multicast
  2616. * packets.
  2617. */
  2618. if (*total_flags & FIF_ALLMULTI) {
  2619. kfree(cmd);
  2620. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
  2621. }
  2622. if (cmd != NULL) {
  2623. mwl8k_post_cmd(hw, cmd);
  2624. kfree(cmd);
  2625. }
  2626. mwl8k_fw_unlock(hw);
  2627. }
  2628. static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2629. {
  2630. return mwl8k_cmd_set_rts_threshold(hw, value);
  2631. }
  2632. struct mwl8k_sta_notify_item
  2633. {
  2634. struct list_head list;
  2635. struct ieee80211_vif *vif;
  2636. enum sta_notify_cmd cmd;
  2637. struct ieee80211_sta sta;
  2638. };
  2639. static void mwl8k_sta_notify_worker(struct work_struct *work)
  2640. {
  2641. struct mwl8k_priv *priv =
  2642. container_of(work, struct mwl8k_priv, sta_notify_worker);
  2643. struct ieee80211_hw *hw = priv->hw;
  2644. spin_lock_bh(&priv->sta_notify_list_lock);
  2645. while (!list_empty(&priv->sta_notify_list)) {
  2646. struct mwl8k_sta_notify_item *s;
  2647. s = list_entry(priv->sta_notify_list.next,
  2648. struct mwl8k_sta_notify_item, list);
  2649. list_del(&s->list);
  2650. spin_unlock_bh(&priv->sta_notify_list_lock);
  2651. if (s->cmd == STA_NOTIFY_ADD) {
  2652. int rc;
  2653. rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
  2654. if (rc >= 0) {
  2655. struct ieee80211_sta *sta;
  2656. rcu_read_lock();
  2657. sta = ieee80211_find_sta(s->vif, s->sta.addr);
  2658. if (sta != NULL)
  2659. MWL8K_STA(sta)->peer_id = rc;
  2660. rcu_read_unlock();
  2661. }
  2662. } else {
  2663. mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
  2664. }
  2665. kfree(s);
  2666. spin_lock_bh(&priv->sta_notify_list_lock);
  2667. }
  2668. spin_unlock_bh(&priv->sta_notify_list_lock);
  2669. }
  2670. static void
  2671. mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2672. enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
  2673. {
  2674. struct mwl8k_priv *priv = hw->priv;
  2675. struct mwl8k_sta_notify_item *s;
  2676. if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
  2677. return;
  2678. s = kmalloc(sizeof(*s), GFP_ATOMIC);
  2679. if (s != NULL) {
  2680. s->vif = vif;
  2681. s->cmd = cmd;
  2682. s->sta = *sta;
  2683. spin_lock(&priv->sta_notify_list_lock);
  2684. list_add_tail(&s->list, &priv->sta_notify_list);
  2685. spin_unlock(&priv->sta_notify_list_lock);
  2686. ieee80211_queue_work(hw, &priv->sta_notify_worker);
  2687. }
  2688. }
  2689. static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2690. const struct ieee80211_tx_queue_params *params)
  2691. {
  2692. struct mwl8k_priv *priv = hw->priv;
  2693. int rc;
  2694. rc = mwl8k_fw_lock(hw);
  2695. if (!rc) {
  2696. if (!priv->wmm_enabled)
  2697. rc = mwl8k_cmd_set_wmm_mode(hw, 1);
  2698. if (!rc)
  2699. rc = mwl8k_cmd_set_edca_params(hw, queue,
  2700. params->cw_min,
  2701. params->cw_max,
  2702. params->aifs,
  2703. params->txop);
  2704. mwl8k_fw_unlock(hw);
  2705. }
  2706. return rc;
  2707. }
  2708. static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
  2709. struct ieee80211_tx_queue_stats *stats)
  2710. {
  2711. struct mwl8k_priv *priv = hw->priv;
  2712. struct mwl8k_tx_queue *txq;
  2713. int index;
  2714. spin_lock_bh(&priv->tx_lock);
  2715. for (index = 0; index < MWL8K_TX_QUEUES; index++) {
  2716. txq = priv->txq + index;
  2717. memcpy(&stats[index], &txq->stats,
  2718. sizeof(struct ieee80211_tx_queue_stats));
  2719. }
  2720. spin_unlock_bh(&priv->tx_lock);
  2721. return 0;
  2722. }
  2723. static int mwl8k_get_stats(struct ieee80211_hw *hw,
  2724. struct ieee80211_low_level_stats *stats)
  2725. {
  2726. return mwl8k_cmd_get_stat(hw, stats);
  2727. }
  2728. static int
  2729. mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2730. enum ieee80211_ampdu_mlme_action action,
  2731. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2732. {
  2733. switch (action) {
  2734. case IEEE80211_AMPDU_RX_START:
  2735. case IEEE80211_AMPDU_RX_STOP:
  2736. if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
  2737. return -ENOTSUPP;
  2738. return 0;
  2739. default:
  2740. return -ENOTSUPP;
  2741. }
  2742. }
  2743. static const struct ieee80211_ops mwl8k_ops = {
  2744. .tx = mwl8k_tx,
  2745. .start = mwl8k_start,
  2746. .stop = mwl8k_stop,
  2747. .add_interface = mwl8k_add_interface,
  2748. .remove_interface = mwl8k_remove_interface,
  2749. .config = mwl8k_config,
  2750. .bss_info_changed = mwl8k_bss_info_changed,
  2751. .prepare_multicast = mwl8k_prepare_multicast,
  2752. .configure_filter = mwl8k_configure_filter,
  2753. .set_rts_threshold = mwl8k_set_rts_threshold,
  2754. .sta_notify = mwl8k_sta_notify,
  2755. .conf_tx = mwl8k_conf_tx,
  2756. .get_tx_stats = mwl8k_get_tx_stats,
  2757. .get_stats = mwl8k_get_stats,
  2758. .ampdu_action = mwl8k_ampdu_action,
  2759. };
  2760. static void mwl8k_tx_reclaim_handler(unsigned long data)
  2761. {
  2762. int i;
  2763. struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
  2764. struct mwl8k_priv *priv = hw->priv;
  2765. spin_lock_bh(&priv->tx_lock);
  2766. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2767. mwl8k_txq_reclaim(hw, i, 0);
  2768. if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
  2769. complete(priv->tx_wait);
  2770. priv->tx_wait = NULL;
  2771. }
  2772. spin_unlock_bh(&priv->tx_lock);
  2773. }
  2774. static void mwl8k_finalize_join_worker(struct work_struct *work)
  2775. {
  2776. struct mwl8k_priv *priv =
  2777. container_of(work, struct mwl8k_priv, finalize_join_worker);
  2778. struct sk_buff *skb = priv->beacon_skb;
  2779. mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
  2780. priv->vif->bss_conf.dtim_period);
  2781. dev_kfree_skb(skb);
  2782. priv->beacon_skb = NULL;
  2783. }
  2784. enum {
  2785. MWL8363 = 0,
  2786. MWL8687,
  2787. MWL8366,
  2788. };
  2789. static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
  2790. [MWL8363] = {
  2791. .part_name = "88w8363",
  2792. .helper_image = "mwl8k/helper_8363.fw",
  2793. .fw_image = "mwl8k/fmimage_8363.fw",
  2794. },
  2795. [MWL8687] = {
  2796. .part_name = "88w8687",
  2797. .helper_image = "mwl8k/helper_8687.fw",
  2798. .fw_image = "mwl8k/fmimage_8687.fw",
  2799. },
  2800. [MWL8366] = {
  2801. .part_name = "88w8366",
  2802. .helper_image = "mwl8k/helper_8366.fw",
  2803. .fw_image = "mwl8k/fmimage_8366.fw",
  2804. .ap_rxd_ops = &rxd_8366_ap_ops,
  2805. },
  2806. };
  2807. static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
  2808. { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
  2809. { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
  2810. { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
  2811. { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
  2812. { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
  2813. { },
  2814. };
  2815. MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
  2816. static int __devinit mwl8k_probe(struct pci_dev *pdev,
  2817. const struct pci_device_id *id)
  2818. {
  2819. static int printed_version = 0;
  2820. struct ieee80211_hw *hw;
  2821. struct mwl8k_priv *priv;
  2822. int rc;
  2823. int i;
  2824. if (!printed_version) {
  2825. printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
  2826. printed_version = 1;
  2827. }
  2828. rc = pci_enable_device(pdev);
  2829. if (rc) {
  2830. printk(KERN_ERR "%s: Cannot enable new PCI device\n",
  2831. MWL8K_NAME);
  2832. return rc;
  2833. }
  2834. rc = pci_request_regions(pdev, MWL8K_NAME);
  2835. if (rc) {
  2836. printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
  2837. MWL8K_NAME);
  2838. goto err_disable_device;
  2839. }
  2840. pci_set_master(pdev);
  2841. hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
  2842. if (hw == NULL) {
  2843. printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
  2844. rc = -ENOMEM;
  2845. goto err_free_reg;
  2846. }
  2847. SET_IEEE80211_DEV(hw, &pdev->dev);
  2848. pci_set_drvdata(pdev, hw);
  2849. priv = hw->priv;
  2850. priv->hw = hw;
  2851. priv->pdev = pdev;
  2852. priv->device_info = &mwl8k_info_tbl[id->driver_data];
  2853. priv->sram = pci_iomap(pdev, 0, 0x10000);
  2854. if (priv->sram == NULL) {
  2855. printk(KERN_ERR "%s: Cannot map device SRAM\n",
  2856. wiphy_name(hw->wiphy));
  2857. goto err_iounmap;
  2858. }
  2859. /*
  2860. * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
  2861. * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
  2862. */
  2863. priv->regs = pci_iomap(pdev, 1, 0x10000);
  2864. if (priv->regs == NULL) {
  2865. priv->regs = pci_iomap(pdev, 2, 0x10000);
  2866. if (priv->regs == NULL) {
  2867. printk(KERN_ERR "%s: Cannot map device registers\n",
  2868. wiphy_name(hw->wiphy));
  2869. goto err_iounmap;
  2870. }
  2871. }
  2872. /* Reset firmware and hardware */
  2873. mwl8k_hw_reset(priv);
  2874. /* Ask userland hotplug daemon for the device firmware */
  2875. rc = mwl8k_request_firmware(priv);
  2876. if (rc) {
  2877. printk(KERN_ERR "%s: Firmware files not found\n",
  2878. wiphy_name(hw->wiphy));
  2879. goto err_stop_firmware;
  2880. }
  2881. /* Load firmware into hardware */
  2882. rc = mwl8k_load_firmware(hw);
  2883. if (rc) {
  2884. printk(KERN_ERR "%s: Cannot start firmware\n",
  2885. wiphy_name(hw->wiphy));
  2886. goto err_stop_firmware;
  2887. }
  2888. /* Reclaim memory once firmware is successfully loaded */
  2889. mwl8k_release_firmware(priv);
  2890. if (priv->ap_fw) {
  2891. priv->rxd_ops = priv->device_info->ap_rxd_ops;
  2892. if (priv->rxd_ops == NULL) {
  2893. printk(KERN_ERR "%s: Driver does not have AP "
  2894. "firmware image support for this hardware\n",
  2895. wiphy_name(hw->wiphy));
  2896. goto err_stop_firmware;
  2897. }
  2898. } else {
  2899. priv->rxd_ops = &rxd_sta_ops;
  2900. }
  2901. priv->sniffer_enabled = false;
  2902. priv->wmm_enabled = false;
  2903. priv->pending_tx_pkts = 0;
  2904. memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
  2905. priv->band.band = IEEE80211_BAND_2GHZ;
  2906. priv->band.channels = priv->channels;
  2907. priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
  2908. priv->band.bitrates = priv->rates;
  2909. priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
  2910. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
  2911. BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
  2912. memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
  2913. /*
  2914. * Extra headroom is the size of the required DMA header
  2915. * minus the size of the smallest 802.11 frame (CTS frame).
  2916. */
  2917. hw->extra_tx_headroom =
  2918. sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
  2919. hw->channel_change_time = 10;
  2920. hw->queues = MWL8K_TX_QUEUES;
  2921. /* Set rssi and noise values to dBm */
  2922. hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
  2923. hw->vif_data_size = sizeof(struct mwl8k_vif);
  2924. hw->sta_data_size = sizeof(struct mwl8k_sta);
  2925. priv->vif = NULL;
  2926. /* Set default radio state and preamble */
  2927. priv->radio_on = 0;
  2928. priv->radio_short_preamble = 0;
  2929. /* Station database handling */
  2930. INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
  2931. spin_lock_init(&priv->sta_notify_list_lock);
  2932. INIT_LIST_HEAD(&priv->sta_notify_list);
  2933. /* Finalize join worker */
  2934. INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
  2935. /* TX reclaim tasklet */
  2936. tasklet_init(&priv->tx_reclaim_task,
  2937. mwl8k_tx_reclaim_handler, (unsigned long)hw);
  2938. tasklet_disable(&priv->tx_reclaim_task);
  2939. /* Power management cookie */
  2940. priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
  2941. if (priv->cookie == NULL)
  2942. goto err_stop_firmware;
  2943. rc = mwl8k_rxq_init(hw, 0);
  2944. if (rc)
  2945. goto err_free_cookie;
  2946. rxq_refill(hw, 0, INT_MAX);
  2947. mutex_init(&priv->fw_mutex);
  2948. priv->fw_mutex_owner = NULL;
  2949. priv->fw_mutex_depth = 0;
  2950. priv->hostcmd_wait = NULL;
  2951. spin_lock_init(&priv->tx_lock);
  2952. priv->tx_wait = NULL;
  2953. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  2954. rc = mwl8k_txq_init(hw, i);
  2955. if (rc)
  2956. goto err_free_queues;
  2957. }
  2958. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2959. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2960. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
  2961. iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
  2962. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2963. IRQF_SHARED, MWL8K_NAME, hw);
  2964. if (rc) {
  2965. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2966. wiphy_name(hw->wiphy));
  2967. goto err_free_queues;
  2968. }
  2969. /*
  2970. * Temporarily enable interrupts. Initial firmware host
  2971. * commands use interrupts and avoid polling. Disable
  2972. * interrupts when done.
  2973. */
  2974. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2975. /* Get config data, mac addrs etc */
  2976. if (priv->ap_fw) {
  2977. rc = mwl8k_cmd_get_hw_spec_ap(hw);
  2978. if (!rc)
  2979. rc = mwl8k_cmd_set_hw_spec(hw);
  2980. } else {
  2981. rc = mwl8k_cmd_get_hw_spec_sta(hw);
  2982. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
  2983. }
  2984. if (rc) {
  2985. printk(KERN_ERR "%s: Cannot initialise firmware\n",
  2986. wiphy_name(hw->wiphy));
  2987. goto err_free_irq;
  2988. }
  2989. /* Turn radio off */
  2990. rc = mwl8k_cmd_radio_disable(hw);
  2991. if (rc) {
  2992. printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
  2993. goto err_free_irq;
  2994. }
  2995. /* Clear MAC address */
  2996. rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  2997. if (rc) {
  2998. printk(KERN_ERR "%s: Cannot clear MAC address\n",
  2999. wiphy_name(hw->wiphy));
  3000. goto err_free_irq;
  3001. }
  3002. /* Disable interrupts */
  3003. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3004. free_irq(priv->pdev->irq, hw);
  3005. rc = ieee80211_register_hw(hw);
  3006. if (rc) {
  3007. printk(KERN_ERR "%s: Cannot register device\n",
  3008. wiphy_name(hw->wiphy));
  3009. goto err_free_queues;
  3010. }
  3011. printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
  3012. wiphy_name(hw->wiphy), priv->device_info->part_name,
  3013. priv->hw_rev, hw->wiphy->perm_addr,
  3014. priv->ap_fw ? "AP" : "STA",
  3015. (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
  3016. (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
  3017. return 0;
  3018. err_free_irq:
  3019. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3020. free_irq(priv->pdev->irq, hw);
  3021. err_free_queues:
  3022. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3023. mwl8k_txq_deinit(hw, i);
  3024. mwl8k_rxq_deinit(hw, 0);
  3025. err_free_cookie:
  3026. if (priv->cookie != NULL)
  3027. pci_free_consistent(priv->pdev, 4,
  3028. priv->cookie, priv->cookie_dma);
  3029. err_stop_firmware:
  3030. mwl8k_hw_reset(priv);
  3031. mwl8k_release_firmware(priv);
  3032. err_iounmap:
  3033. if (priv->regs != NULL)
  3034. pci_iounmap(pdev, priv->regs);
  3035. if (priv->sram != NULL)
  3036. pci_iounmap(pdev, priv->sram);
  3037. pci_set_drvdata(pdev, NULL);
  3038. ieee80211_free_hw(hw);
  3039. err_free_reg:
  3040. pci_release_regions(pdev);
  3041. err_disable_device:
  3042. pci_disable_device(pdev);
  3043. return rc;
  3044. }
  3045. static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
  3046. {
  3047. printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
  3048. }
  3049. static void __devexit mwl8k_remove(struct pci_dev *pdev)
  3050. {
  3051. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  3052. struct mwl8k_priv *priv;
  3053. int i;
  3054. if (hw == NULL)
  3055. return;
  3056. priv = hw->priv;
  3057. ieee80211_stop_queues(hw);
  3058. ieee80211_unregister_hw(hw);
  3059. /* Remove tx reclaim tasklet */
  3060. tasklet_kill(&priv->tx_reclaim_task);
  3061. /* Stop hardware */
  3062. mwl8k_hw_reset(priv);
  3063. /* Return all skbs to mac80211 */
  3064. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3065. mwl8k_txq_reclaim(hw, i, 1);
  3066. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3067. mwl8k_txq_deinit(hw, i);
  3068. mwl8k_rxq_deinit(hw, 0);
  3069. pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
  3070. pci_iounmap(pdev, priv->regs);
  3071. pci_iounmap(pdev, priv->sram);
  3072. pci_set_drvdata(pdev, NULL);
  3073. ieee80211_free_hw(hw);
  3074. pci_release_regions(pdev);
  3075. pci_disable_device(pdev);
  3076. }
  3077. static struct pci_driver mwl8k_driver = {
  3078. .name = MWL8K_NAME,
  3079. .id_table = mwl8k_pci_id_table,
  3080. .probe = mwl8k_probe,
  3081. .remove = __devexit_p(mwl8k_remove),
  3082. .shutdown = __devexit_p(mwl8k_shutdown),
  3083. };
  3084. static int __init mwl8k_init(void)
  3085. {
  3086. return pci_register_driver(&mwl8k_driver);
  3087. }
  3088. static void __exit mwl8k_exit(void)
  3089. {
  3090. pci_unregister_driver(&mwl8k_driver);
  3091. }
  3092. module_init(mwl8k_init);
  3093. module_exit(mwl8k_exit);
  3094. MODULE_DESCRIPTION(MWL8K_DESC);
  3095. MODULE_VERSION(MWL8K_VERSION);
  3096. MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
  3097. MODULE_LICENSE("GPL");