iwl-agn.c 89 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. priv->cfg->ops->smgmt->clear_station_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->cmd[index]->meta, mapping),
  366. pci_unmap_len(&txq->cmd[index]->meta, len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Misc. internal state and helper functions
  424. *
  425. ******************************************************************************/
  426. #define MAX_UCODE_BEACON_INTERVAL 4096
  427. static u16 iwl_adjust_beacon_interval(u16 beacon_val)
  428. {
  429. u16 new_val = 0;
  430. u16 beacon_factor = 0;
  431. beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  432. / MAX_UCODE_BEACON_INTERVAL;
  433. new_val = beacon_val / beacon_factor;
  434. if (!new_val)
  435. new_val = MAX_UCODE_BEACON_INTERVAL;
  436. return new_val;
  437. }
  438. static void iwl_setup_rxon_timing(struct iwl_priv *priv)
  439. {
  440. u64 tsf;
  441. s32 interval_tm, rem;
  442. unsigned long flags;
  443. struct ieee80211_conf *conf = NULL;
  444. u16 beacon_int = 0;
  445. conf = ieee80211_get_hw_conf(priv->hw);
  446. spin_lock_irqsave(&priv->lock, flags);
  447. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  448. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  449. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  450. beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
  451. priv->rxon_timing.atim_window = 0;
  452. } else {
  453. beacon_int = iwl_adjust_beacon_interval(
  454. priv->vif->bss_conf.beacon_int);
  455. /* TODO: we need to get atim_window from upper stack
  456. * for now we set to 0 */
  457. priv->rxon_timing.atim_window = 0;
  458. }
  459. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  460. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  461. interval_tm = beacon_int * 1024;
  462. rem = do_div(tsf, interval_tm);
  463. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  464. spin_unlock_irqrestore(&priv->lock, flags);
  465. IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
  466. le16_to_cpu(priv->rxon_timing.beacon_interval),
  467. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  468. le16_to_cpu(priv->rxon_timing.atim_window));
  469. }
  470. /******************************************************************************
  471. *
  472. * Generic RX handler implementations
  473. *
  474. ******************************************************************************/
  475. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  476. struct iwl_rx_mem_buffer *rxb)
  477. {
  478. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  479. struct iwl_alive_resp *palive;
  480. struct delayed_work *pwork;
  481. palive = &pkt->u.alive_frame;
  482. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  483. "0x%01X 0x%01X\n",
  484. palive->is_valid, palive->ver_type,
  485. palive->ver_subtype);
  486. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  487. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  488. memcpy(&priv->card_alive_init,
  489. &pkt->u.alive_frame,
  490. sizeof(struct iwl_init_alive_resp));
  491. pwork = &priv->init_alive_start;
  492. } else {
  493. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  494. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  495. sizeof(struct iwl_alive_resp));
  496. pwork = &priv->alive_start;
  497. }
  498. /* We delay the ALIVE response by 5ms to
  499. * give the HW RF Kill time to activate... */
  500. if (palive->is_valid == UCODE_VALID_OK)
  501. queue_delayed_work(priv->workqueue, pwork,
  502. msecs_to_jiffies(5));
  503. else
  504. IWL_WARN(priv, "uCode did not respond OK.\n");
  505. }
  506. static void iwl_bg_beacon_update(struct work_struct *work)
  507. {
  508. struct iwl_priv *priv =
  509. container_of(work, struct iwl_priv, beacon_update);
  510. struct sk_buff *beacon;
  511. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  512. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  513. if (!beacon) {
  514. IWL_ERR(priv, "update beacon failed\n");
  515. return;
  516. }
  517. mutex_lock(&priv->mutex);
  518. /* new beacon skb is allocated every time; dispose previous.*/
  519. if (priv->ibss_beacon)
  520. dev_kfree_skb(priv->ibss_beacon);
  521. priv->ibss_beacon = beacon;
  522. mutex_unlock(&priv->mutex);
  523. iwl_send_beacon_cmd(priv);
  524. }
  525. /**
  526. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  527. *
  528. * This callback is provided in order to send a statistics request.
  529. *
  530. * This timer function is continually reset to execute within
  531. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  532. * was received. We need to ensure we receive the statistics in order
  533. * to update the temperature used for calibrating the TXPOWER.
  534. */
  535. static void iwl_bg_statistics_periodic(unsigned long data)
  536. {
  537. struct iwl_priv *priv = (struct iwl_priv *)data;
  538. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  539. return;
  540. /* dont send host command if rf-kill is on */
  541. if (!iwl_is_ready_rf(priv))
  542. return;
  543. iwl_send_statistics_request(priv, CMD_ASYNC);
  544. }
  545. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  546. struct iwl_rx_mem_buffer *rxb)
  547. {
  548. #ifdef CONFIG_IWLWIFI_DEBUG
  549. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  550. struct iwl4965_beacon_notif *beacon =
  551. (struct iwl4965_beacon_notif *)pkt->u.raw;
  552. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  553. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  554. "tsf %d %d rate %d\n",
  555. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  556. beacon->beacon_notify_hdr.failure_frame,
  557. le32_to_cpu(beacon->ibss_mgr_status),
  558. le32_to_cpu(beacon->high_tsf),
  559. le32_to_cpu(beacon->low_tsf), rate);
  560. #endif
  561. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  562. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  563. queue_work(priv->workqueue, &priv->beacon_update);
  564. }
  565. /* Handle notification from uCode that card's power state is changing
  566. * due to software, hardware, or critical temperature RFKILL */
  567. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  568. struct iwl_rx_mem_buffer *rxb)
  569. {
  570. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  571. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  572. unsigned long status = priv->status;
  573. unsigned long reg_flags;
  574. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  575. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  576. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  577. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  578. RF_CARD_DISABLED)) {
  579. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  580. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  581. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  582. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  583. if (!(flags & RXON_CARD_DISABLED)) {
  584. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  585. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  586. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  587. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  588. }
  589. if (flags & RF_CARD_DISABLED) {
  590. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  591. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  592. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  593. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  594. if (!iwl_grab_nic_access(priv))
  595. iwl_release_nic_access(priv);
  596. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  597. }
  598. }
  599. if (flags & HW_CARD_DISABLED)
  600. set_bit(STATUS_RF_KILL_HW, &priv->status);
  601. else
  602. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  603. if (flags & SW_CARD_DISABLED)
  604. set_bit(STATUS_RF_KILL_SW, &priv->status);
  605. else
  606. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  607. if (!(flags & RXON_CARD_DISABLED))
  608. iwl_scan_cancel(priv);
  609. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  610. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  611. (test_bit(STATUS_RF_KILL_SW, &status) !=
  612. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  613. queue_work(priv->workqueue, &priv->rf_kill);
  614. else
  615. wake_up_interruptible(&priv->wait_command_queue);
  616. }
  617. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  618. {
  619. if (src == IWL_PWR_SRC_VAUX) {
  620. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  621. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  622. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  623. ~APMG_PS_CTRL_MSK_PWR_SRC);
  624. } else {
  625. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  626. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  627. ~APMG_PS_CTRL_MSK_PWR_SRC);
  628. }
  629. return 0;
  630. }
  631. /**
  632. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  633. *
  634. * Setup the RX handlers for each of the reply types sent from the uCode
  635. * to the host.
  636. *
  637. * This function chains into the hardware specific files for them to setup
  638. * any hardware specific handlers as well.
  639. */
  640. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  641. {
  642. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  643. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  644. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  645. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  646. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  647. iwl_rx_pm_debug_statistics_notif;
  648. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  649. /*
  650. * The same handler is used for both the REPLY to a discrete
  651. * statistics request from the host as well as for the periodic
  652. * statistics notifications (after received beacons) from the uCode.
  653. */
  654. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  655. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  656. iwl_setup_spectrum_handlers(priv);
  657. iwl_setup_rx_scan_handlers(priv);
  658. /* status change handler */
  659. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  660. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  661. iwl_rx_missed_beacon_notif;
  662. /* Rx handlers */
  663. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  664. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  665. /* block ack */
  666. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  667. /* Set up hardware specific Rx handlers */
  668. priv->cfg->ops->lib->rx_handler_setup(priv);
  669. }
  670. /**
  671. * iwl_rx_handle - Main entry function for receiving responses from uCode
  672. *
  673. * Uses the priv->rx_handlers callback function array to invoke
  674. * the appropriate handlers, including command responses,
  675. * frame-received notifications, and other notifications.
  676. */
  677. void iwl_rx_handle(struct iwl_priv *priv)
  678. {
  679. struct iwl_rx_mem_buffer *rxb;
  680. struct iwl_rx_packet *pkt;
  681. struct iwl_rx_queue *rxq = &priv->rxq;
  682. u32 r, i;
  683. int reclaim;
  684. unsigned long flags;
  685. u8 fill_rx = 0;
  686. u32 count = 8;
  687. int total_empty;
  688. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  689. * buffer that the driver may process (last buffer filled by ucode). */
  690. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  691. i = rxq->read;
  692. /* Rx interrupt, but nothing sent from uCode */
  693. if (i == r)
  694. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  695. /* calculate total frames need to be restock after handling RX */
  696. total_empty = r - priv->rxq.write_actual;
  697. if (total_empty < 0)
  698. total_empty += RX_QUEUE_SIZE;
  699. if (total_empty > (RX_QUEUE_SIZE / 2))
  700. fill_rx = 1;
  701. while (i != r) {
  702. rxb = rxq->queue[i];
  703. /* If an RXB doesn't have a Rx queue slot associated with it,
  704. * then a bug has been introduced in the queue refilling
  705. * routines -- catch it here */
  706. BUG_ON(rxb == NULL);
  707. rxq->queue[i] = NULL;
  708. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  709. priv->hw_params.rx_buf_size + 256,
  710. PCI_DMA_FROMDEVICE);
  711. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  712. /* Reclaim a command buffer only if this packet is a response
  713. * to a (driver-originated) command.
  714. * If the packet (e.g. Rx frame) originated from uCode,
  715. * there is no command buffer to reclaim.
  716. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  717. * but apparently a few don't get set; catch them here. */
  718. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  719. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  720. (pkt->hdr.cmd != REPLY_RX) &&
  721. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  722. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  723. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  724. (pkt->hdr.cmd != REPLY_TX);
  725. /* Based on type of command response or notification,
  726. * handle those that need handling via function in
  727. * rx_handlers table. See iwl_setup_rx_handlers() */
  728. if (priv->rx_handlers[pkt->hdr.cmd]) {
  729. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  730. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  731. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  732. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  733. } else {
  734. /* No handling needed */
  735. IWL_DEBUG_RX(priv,
  736. "r %d i %d No handler needed for %s, 0x%02x\n",
  737. r, i, get_cmd_string(pkt->hdr.cmd),
  738. pkt->hdr.cmd);
  739. }
  740. if (reclaim) {
  741. /* Invoke any callbacks, transfer the skb to caller, and
  742. * fire off the (possibly) blocking iwl_send_cmd()
  743. * as we reclaim the driver command queue */
  744. if (rxb && rxb->skb)
  745. iwl_tx_cmd_complete(priv, rxb);
  746. else
  747. IWL_WARN(priv, "Claim null rxb?\n");
  748. }
  749. /* For now we just don't re-use anything. We can tweak this
  750. * later to try and re-use notification packets and SKBs that
  751. * fail to Rx correctly */
  752. if (rxb->skb != NULL) {
  753. priv->alloc_rxb_skb--;
  754. dev_kfree_skb_any(rxb->skb);
  755. rxb->skb = NULL;
  756. }
  757. spin_lock_irqsave(&rxq->lock, flags);
  758. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  759. spin_unlock_irqrestore(&rxq->lock, flags);
  760. i = (i + 1) & RX_QUEUE_MASK;
  761. /* If there are a lot of unused frames,
  762. * restock the Rx queue so ucode wont assert. */
  763. if (fill_rx) {
  764. count++;
  765. if (count >= 8) {
  766. priv->rxq.read = i;
  767. iwl_rx_replenish_now(priv);
  768. count = 0;
  769. }
  770. }
  771. }
  772. /* Backtrack one entry */
  773. priv->rxq.read = i;
  774. if (fill_rx)
  775. iwl_rx_replenish_now(priv);
  776. else
  777. iwl_rx_queue_restock(priv);
  778. }
  779. /* call this function to flush any scheduled tasklet */
  780. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  781. {
  782. /* wait to make sure we flush pending tasklet*/
  783. synchronize_irq(priv->pci_dev->irq);
  784. tasklet_kill(&priv->irq_tasklet);
  785. }
  786. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  787. {
  788. u32 inta, handled = 0;
  789. u32 inta_fh;
  790. unsigned long flags;
  791. #ifdef CONFIG_IWLWIFI_DEBUG
  792. u32 inta_mask;
  793. #endif
  794. spin_lock_irqsave(&priv->lock, flags);
  795. /* Ack/clear/reset pending uCode interrupts.
  796. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  797. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  798. inta = iwl_read32(priv, CSR_INT);
  799. iwl_write32(priv, CSR_INT, inta);
  800. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  801. * Any new interrupts that happen after this, either while we're
  802. * in this tasklet, or later, will show up in next ISR/tasklet. */
  803. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  804. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  805. #ifdef CONFIG_IWLWIFI_DEBUG
  806. if (priv->debug_level & IWL_DL_ISR) {
  807. /* just for debug */
  808. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  809. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  810. inta, inta_mask, inta_fh);
  811. }
  812. #endif
  813. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  814. * atomic, make sure that inta covers all the interrupts that
  815. * we've discovered, even if FH interrupt came in just after
  816. * reading CSR_INT. */
  817. if (inta_fh & CSR49_FH_INT_RX_MASK)
  818. inta |= CSR_INT_BIT_FH_RX;
  819. if (inta_fh & CSR49_FH_INT_TX_MASK)
  820. inta |= CSR_INT_BIT_FH_TX;
  821. /* Now service all interrupt bits discovered above. */
  822. if (inta & CSR_INT_BIT_HW_ERR) {
  823. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  824. /* Tell the device to stop sending interrupts */
  825. iwl_disable_interrupts(priv);
  826. priv->isr_stats.hw++;
  827. iwl_irq_handle_error(priv);
  828. handled |= CSR_INT_BIT_HW_ERR;
  829. spin_unlock_irqrestore(&priv->lock, flags);
  830. return;
  831. }
  832. #ifdef CONFIG_IWLWIFI_DEBUG
  833. if (priv->debug_level & (IWL_DL_ISR)) {
  834. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  835. if (inta & CSR_INT_BIT_SCD) {
  836. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  837. "the frame/frames.\n");
  838. priv->isr_stats.sch++;
  839. }
  840. /* Alive notification via Rx interrupt will do the real work */
  841. if (inta & CSR_INT_BIT_ALIVE) {
  842. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  843. priv->isr_stats.alive++;
  844. }
  845. }
  846. #endif
  847. /* Safely ignore these bits for debug checks below */
  848. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  849. /* HW RF KILL switch toggled */
  850. if (inta & CSR_INT_BIT_RF_KILL) {
  851. int hw_rf_kill = 0;
  852. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  853. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  854. hw_rf_kill = 1;
  855. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  856. hw_rf_kill ? "disable radio" : "enable radio");
  857. priv->isr_stats.rfkill++;
  858. /* driver only loads ucode once setting the interface up.
  859. * the driver allows loading the ucode even if the radio
  860. * is killed. Hence update the killswitch state here. The
  861. * rfkill handler will care about restarting if needed.
  862. */
  863. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  864. if (hw_rf_kill)
  865. set_bit(STATUS_RF_KILL_HW, &priv->status);
  866. else
  867. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  868. queue_work(priv->workqueue, &priv->rf_kill);
  869. }
  870. handled |= CSR_INT_BIT_RF_KILL;
  871. }
  872. /* Chip got too hot and stopped itself */
  873. if (inta & CSR_INT_BIT_CT_KILL) {
  874. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  875. priv->isr_stats.ctkill++;
  876. handled |= CSR_INT_BIT_CT_KILL;
  877. }
  878. /* Error detected by uCode */
  879. if (inta & CSR_INT_BIT_SW_ERR) {
  880. IWL_ERR(priv, "Microcode SW error detected. "
  881. " Restarting 0x%X.\n", inta);
  882. priv->isr_stats.sw++;
  883. priv->isr_stats.sw_err = inta;
  884. iwl_irq_handle_error(priv);
  885. handled |= CSR_INT_BIT_SW_ERR;
  886. }
  887. /* uCode wakes up after power-down sleep */
  888. if (inta & CSR_INT_BIT_WAKEUP) {
  889. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  890. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  891. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  892. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  893. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  894. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  895. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  896. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  897. priv->isr_stats.wakeup++;
  898. handled |= CSR_INT_BIT_WAKEUP;
  899. }
  900. /* All uCode command responses, including Tx command responses,
  901. * Rx "responses" (frame-received notification), and other
  902. * notifications from uCode come through here*/
  903. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  904. iwl_rx_handle(priv);
  905. priv->isr_stats.rx++;
  906. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  907. }
  908. if (inta & CSR_INT_BIT_FH_TX) {
  909. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  910. priv->isr_stats.tx++;
  911. handled |= CSR_INT_BIT_FH_TX;
  912. /* FH finished to write, send event */
  913. priv->ucode_write_complete = 1;
  914. wake_up_interruptible(&priv->wait_command_queue);
  915. }
  916. if (inta & ~handled) {
  917. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  918. priv->isr_stats.unhandled++;
  919. }
  920. if (inta & ~(priv->inta_mask)) {
  921. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  922. inta & ~priv->inta_mask);
  923. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  924. }
  925. /* Re-enable all interrupts */
  926. /* only Re-enable if diabled by irq */
  927. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  928. iwl_enable_interrupts(priv);
  929. #ifdef CONFIG_IWLWIFI_DEBUG
  930. if (priv->debug_level & (IWL_DL_ISR)) {
  931. inta = iwl_read32(priv, CSR_INT);
  932. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  933. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  934. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  935. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  936. }
  937. #endif
  938. spin_unlock_irqrestore(&priv->lock, flags);
  939. }
  940. /* tasklet for iwlagn interrupt */
  941. static void iwl_irq_tasklet(struct iwl_priv *priv)
  942. {
  943. u32 inta = 0;
  944. u32 handled = 0;
  945. unsigned long flags;
  946. #ifdef CONFIG_IWLWIFI_DEBUG
  947. u32 inta_mask;
  948. #endif
  949. spin_lock_irqsave(&priv->lock, flags);
  950. /* Ack/clear/reset pending uCode interrupts.
  951. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  952. */
  953. iwl_write32(priv, CSR_INT, priv->inta);
  954. inta = priv->inta;
  955. #ifdef CONFIG_IWLWIFI_DEBUG
  956. if (priv->debug_level & IWL_DL_ISR) {
  957. /* just for debug */
  958. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  959. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  960. inta, inta_mask);
  961. }
  962. #endif
  963. /* saved interrupt in inta variable now we can reset priv->inta */
  964. priv->inta = 0;
  965. /* Now service all interrupt bits discovered above. */
  966. if (inta & CSR_INT_BIT_HW_ERR) {
  967. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  968. /* Tell the device to stop sending interrupts */
  969. iwl_disable_interrupts(priv);
  970. priv->isr_stats.hw++;
  971. iwl_irq_handle_error(priv);
  972. handled |= CSR_INT_BIT_HW_ERR;
  973. spin_unlock_irqrestore(&priv->lock, flags);
  974. return;
  975. }
  976. #ifdef CONFIG_IWLWIFI_DEBUG
  977. if (priv->debug_level & (IWL_DL_ISR)) {
  978. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  979. if (inta & CSR_INT_BIT_SCD) {
  980. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  981. "the frame/frames.\n");
  982. priv->isr_stats.sch++;
  983. }
  984. /* Alive notification via Rx interrupt will do the real work */
  985. if (inta & CSR_INT_BIT_ALIVE) {
  986. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  987. priv->isr_stats.alive++;
  988. }
  989. }
  990. #endif
  991. /* Safely ignore these bits for debug checks below */
  992. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  993. /* HW RF KILL switch toggled */
  994. if (inta & CSR_INT_BIT_RF_KILL) {
  995. int hw_rf_kill = 0;
  996. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  997. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  998. hw_rf_kill = 1;
  999. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  1000. hw_rf_kill ? "disable radio" : "enable radio");
  1001. priv->isr_stats.rfkill++;
  1002. /* driver only loads ucode once setting the interface up.
  1003. * the driver allows loading the ucode even if the radio
  1004. * is killed. Hence update the killswitch state here. The
  1005. * rfkill handler will care about restarting if needed.
  1006. */
  1007. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1008. if (hw_rf_kill)
  1009. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1010. else
  1011. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1012. queue_work(priv->workqueue, &priv->rf_kill);
  1013. }
  1014. handled |= CSR_INT_BIT_RF_KILL;
  1015. }
  1016. /* Chip got too hot and stopped itself */
  1017. if (inta & CSR_INT_BIT_CT_KILL) {
  1018. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1019. priv->isr_stats.ctkill++;
  1020. handled |= CSR_INT_BIT_CT_KILL;
  1021. }
  1022. /* Error detected by uCode */
  1023. if (inta & CSR_INT_BIT_SW_ERR) {
  1024. IWL_ERR(priv, "Microcode SW error detected. "
  1025. " Restarting 0x%X.\n", inta);
  1026. priv->isr_stats.sw++;
  1027. priv->isr_stats.sw_err = inta;
  1028. iwl_irq_handle_error(priv);
  1029. handled |= CSR_INT_BIT_SW_ERR;
  1030. }
  1031. /* uCode wakes up after power-down sleep */
  1032. if (inta & CSR_INT_BIT_WAKEUP) {
  1033. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1034. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1035. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  1036. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1037. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1038. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1039. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1040. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1041. priv->isr_stats.wakeup++;
  1042. handled |= CSR_INT_BIT_WAKEUP;
  1043. }
  1044. /* All uCode command responses, including Tx command responses,
  1045. * Rx "responses" (frame-received notification), and other
  1046. * notifications from uCode come through here*/
  1047. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1048. CSR_INT_BIT_RX_PERIODIC)) {
  1049. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1050. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1051. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1052. iwl_write32(priv, CSR_FH_INT_STATUS,
  1053. CSR49_FH_INT_RX_MASK);
  1054. }
  1055. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1056. handled |= CSR_INT_BIT_RX_PERIODIC;
  1057. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1058. }
  1059. /* Sending RX interrupt require many steps to be done in the
  1060. * the device:
  1061. * 1- write interrupt to current index in ICT table.
  1062. * 2- dma RX frame.
  1063. * 3- update RX shared data to indicate last write index.
  1064. * 4- send interrupt.
  1065. * This could lead to RX race, driver could receive RX interrupt
  1066. * but the shared data changes does not reflect this.
  1067. * this could lead to RX race, RX periodic will solve this race
  1068. */
  1069. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1070. CSR_INT_PERIODIC_DIS);
  1071. iwl_rx_handle(priv);
  1072. /* Only set RX periodic if real RX is received. */
  1073. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1074. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1075. CSR_INT_PERIODIC_ENA);
  1076. priv->isr_stats.rx++;
  1077. }
  1078. if (inta & CSR_INT_BIT_FH_TX) {
  1079. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1080. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1081. priv->isr_stats.tx++;
  1082. handled |= CSR_INT_BIT_FH_TX;
  1083. /* FH finished to write, send event */
  1084. priv->ucode_write_complete = 1;
  1085. wake_up_interruptible(&priv->wait_command_queue);
  1086. }
  1087. if (inta & ~handled) {
  1088. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1089. priv->isr_stats.unhandled++;
  1090. }
  1091. if (inta & ~(priv->inta_mask)) {
  1092. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1093. inta & ~priv->inta_mask);
  1094. }
  1095. /* Re-enable all interrupts */
  1096. /* only Re-enable if diabled by irq */
  1097. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1098. iwl_enable_interrupts(priv);
  1099. spin_unlock_irqrestore(&priv->lock, flags);
  1100. }
  1101. /******************************************************************************
  1102. *
  1103. * uCode download functions
  1104. *
  1105. ******************************************************************************/
  1106. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1107. {
  1108. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1109. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1110. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1111. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1112. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1113. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1114. }
  1115. static void iwl_nic_start(struct iwl_priv *priv)
  1116. {
  1117. /* Remove all resets to allow NIC to operate */
  1118. iwl_write32(priv, CSR_RESET, 0);
  1119. }
  1120. /**
  1121. * iwl_read_ucode - Read uCode images from disk file.
  1122. *
  1123. * Copy into buffers for card to fetch via bus-mastering
  1124. */
  1125. static int iwl_read_ucode(struct iwl_priv *priv)
  1126. {
  1127. struct iwl_ucode *ucode;
  1128. int ret = -EINVAL, index;
  1129. const struct firmware *ucode_raw;
  1130. const char *name_pre = priv->cfg->fw_name_pre;
  1131. const unsigned int api_max = priv->cfg->ucode_api_max;
  1132. const unsigned int api_min = priv->cfg->ucode_api_min;
  1133. char buf[25];
  1134. u8 *src;
  1135. size_t len;
  1136. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1137. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1138. * request_firmware() is synchronous, file is in memory on return. */
  1139. for (index = api_max; index >= api_min; index--) {
  1140. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1141. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1142. if (ret < 0) {
  1143. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1144. buf, ret);
  1145. if (ret == -ENOENT)
  1146. continue;
  1147. else
  1148. goto error;
  1149. } else {
  1150. if (index < api_max)
  1151. IWL_ERR(priv, "Loaded firmware %s, "
  1152. "which is deprecated. "
  1153. "Please use API v%u instead.\n",
  1154. buf, api_max);
  1155. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1156. buf, ucode_raw->size);
  1157. break;
  1158. }
  1159. }
  1160. if (ret < 0)
  1161. goto error;
  1162. /* Make sure that we got at least our header! */
  1163. if (ucode_raw->size < sizeof(*ucode)) {
  1164. IWL_ERR(priv, "File size way too small!\n");
  1165. ret = -EINVAL;
  1166. goto err_release;
  1167. }
  1168. /* Data from ucode file: header followed by uCode images */
  1169. ucode = (void *)ucode_raw->data;
  1170. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1171. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1172. inst_size = le32_to_cpu(ucode->inst_size);
  1173. data_size = le32_to_cpu(ucode->data_size);
  1174. init_size = le32_to_cpu(ucode->init_size);
  1175. init_data_size = le32_to_cpu(ucode->init_data_size);
  1176. boot_size = le32_to_cpu(ucode->boot_size);
  1177. /* api_ver should match the api version forming part of the
  1178. * firmware filename ... but we don't check for that and only rely
  1179. * on the API version read from firmware header from here on forward */
  1180. if (api_ver < api_min || api_ver > api_max) {
  1181. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1182. "Driver supports v%u, firmware is v%u.\n",
  1183. api_max, api_ver);
  1184. priv->ucode_ver = 0;
  1185. ret = -EINVAL;
  1186. goto err_release;
  1187. }
  1188. if (api_ver != api_max)
  1189. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1190. "got v%u. New firmware can be obtained "
  1191. "from http://www.intellinuxwireless.org.\n",
  1192. api_max, api_ver);
  1193. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1194. IWL_UCODE_MAJOR(priv->ucode_ver),
  1195. IWL_UCODE_MINOR(priv->ucode_ver),
  1196. IWL_UCODE_API(priv->ucode_ver),
  1197. IWL_UCODE_SERIAL(priv->ucode_ver));
  1198. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1199. priv->ucode_ver);
  1200. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1201. inst_size);
  1202. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1203. data_size);
  1204. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1205. init_size);
  1206. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1207. init_data_size);
  1208. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1209. boot_size);
  1210. /* Verify size of file vs. image size info in file's header */
  1211. if (ucode_raw->size < sizeof(*ucode) +
  1212. inst_size + data_size + init_size +
  1213. init_data_size + boot_size) {
  1214. IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
  1215. (int)ucode_raw->size);
  1216. ret = -EINVAL;
  1217. goto err_release;
  1218. }
  1219. /* Verify that uCode images will fit in card's SRAM */
  1220. if (inst_size > priv->hw_params.max_inst_size) {
  1221. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1222. inst_size);
  1223. ret = -EINVAL;
  1224. goto err_release;
  1225. }
  1226. if (data_size > priv->hw_params.max_data_size) {
  1227. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1228. data_size);
  1229. ret = -EINVAL;
  1230. goto err_release;
  1231. }
  1232. if (init_size > priv->hw_params.max_inst_size) {
  1233. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1234. init_size);
  1235. ret = -EINVAL;
  1236. goto err_release;
  1237. }
  1238. if (init_data_size > priv->hw_params.max_data_size) {
  1239. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1240. init_data_size);
  1241. ret = -EINVAL;
  1242. goto err_release;
  1243. }
  1244. if (boot_size > priv->hw_params.max_bsm_size) {
  1245. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1246. boot_size);
  1247. ret = -EINVAL;
  1248. goto err_release;
  1249. }
  1250. /* Allocate ucode buffers for card's bus-master loading ... */
  1251. /* Runtime instructions and 2 copies of data:
  1252. * 1) unmodified from disk
  1253. * 2) backup cache for save/restore during power-downs */
  1254. priv->ucode_code.len = inst_size;
  1255. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1256. priv->ucode_data.len = data_size;
  1257. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1258. priv->ucode_data_backup.len = data_size;
  1259. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1260. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1261. !priv->ucode_data_backup.v_addr)
  1262. goto err_pci_alloc;
  1263. /* Initialization instructions and data */
  1264. if (init_size && init_data_size) {
  1265. priv->ucode_init.len = init_size;
  1266. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1267. priv->ucode_init_data.len = init_data_size;
  1268. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1269. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1270. goto err_pci_alloc;
  1271. }
  1272. /* Bootstrap (instructions only, no data) */
  1273. if (boot_size) {
  1274. priv->ucode_boot.len = boot_size;
  1275. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1276. if (!priv->ucode_boot.v_addr)
  1277. goto err_pci_alloc;
  1278. }
  1279. /* Copy images into buffers for card's bus-master reads ... */
  1280. /* Runtime instructions (first block of data in file) */
  1281. src = &ucode->data[0];
  1282. len = priv->ucode_code.len;
  1283. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1284. memcpy(priv->ucode_code.v_addr, src, len);
  1285. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1286. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1287. /* Runtime data (2nd block)
  1288. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1289. src = &ucode->data[inst_size];
  1290. len = priv->ucode_data.len;
  1291. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1292. memcpy(priv->ucode_data.v_addr, src, len);
  1293. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1294. /* Initialization instructions (3rd block) */
  1295. if (init_size) {
  1296. src = &ucode->data[inst_size + data_size];
  1297. len = priv->ucode_init.len;
  1298. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1299. len);
  1300. memcpy(priv->ucode_init.v_addr, src, len);
  1301. }
  1302. /* Initialization data (4th block) */
  1303. if (init_data_size) {
  1304. src = &ucode->data[inst_size + data_size + init_size];
  1305. len = priv->ucode_init_data.len;
  1306. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1307. len);
  1308. memcpy(priv->ucode_init_data.v_addr, src, len);
  1309. }
  1310. /* Bootstrap instructions (5th block) */
  1311. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  1312. len = priv->ucode_boot.len;
  1313. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1314. memcpy(priv->ucode_boot.v_addr, src, len);
  1315. /* We have our copies now, allow OS release its copies */
  1316. release_firmware(ucode_raw);
  1317. return 0;
  1318. err_pci_alloc:
  1319. IWL_ERR(priv, "failed to allocate pci memory\n");
  1320. ret = -ENOMEM;
  1321. iwl_dealloc_ucode_pci(priv);
  1322. err_release:
  1323. release_firmware(ucode_raw);
  1324. error:
  1325. return ret;
  1326. }
  1327. /**
  1328. * iwl_alive_start - called after REPLY_ALIVE notification received
  1329. * from protocol/runtime uCode (initialization uCode's
  1330. * Alive gets handled by iwl_init_alive_start()).
  1331. */
  1332. static void iwl_alive_start(struct iwl_priv *priv)
  1333. {
  1334. int ret = 0;
  1335. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1336. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1337. /* We had an error bringing up the hardware, so take it
  1338. * all the way back down so we can try again */
  1339. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1340. goto restart;
  1341. }
  1342. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1343. * This is a paranoid check, because we would not have gotten the
  1344. * "runtime" alive if code weren't properly loaded. */
  1345. if (iwl_verify_ucode(priv)) {
  1346. /* Runtime instruction load was bad;
  1347. * take it all the way back down so we can try again */
  1348. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1349. goto restart;
  1350. }
  1351. priv->cfg->ops->smgmt->clear_station_table(priv);
  1352. ret = priv->cfg->ops->lib->alive_notify(priv);
  1353. if (ret) {
  1354. IWL_WARN(priv,
  1355. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1356. goto restart;
  1357. }
  1358. /* After the ALIVE response, we can send host commands to the uCode */
  1359. set_bit(STATUS_ALIVE, &priv->status);
  1360. if (iwl_is_rfkill(priv))
  1361. return;
  1362. ieee80211_wake_queues(priv->hw);
  1363. priv->active_rate = priv->rates_mask;
  1364. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1365. if (iwl_is_associated(priv)) {
  1366. struct iwl_rxon_cmd *active_rxon =
  1367. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1368. /* apply any changes in staging */
  1369. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1370. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1371. } else {
  1372. /* Initialize our rx_config data */
  1373. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1374. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1375. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1376. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1377. }
  1378. /* Configure Bluetooth device coexistence support */
  1379. iwl_send_bt_config(priv);
  1380. iwl_reset_run_time_calib(priv);
  1381. /* Configure the adapter for unassociated operation */
  1382. iwlcore_commit_rxon(priv);
  1383. /* At this point, the NIC is initialized and operational */
  1384. iwl_rf_kill_ct_config(priv);
  1385. iwl_leds_register(priv);
  1386. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1387. set_bit(STATUS_READY, &priv->status);
  1388. wake_up_interruptible(&priv->wait_command_queue);
  1389. iwl_power_update_mode(priv, 1);
  1390. /* reassociate for ADHOC mode */
  1391. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1392. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1393. priv->vif);
  1394. if (beacon)
  1395. iwl_mac_beacon_update(priv->hw, beacon);
  1396. }
  1397. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1398. iwl_set_mode(priv, priv->iw_mode);
  1399. return;
  1400. restart:
  1401. queue_work(priv->workqueue, &priv->restart);
  1402. }
  1403. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1404. static void __iwl_down(struct iwl_priv *priv)
  1405. {
  1406. unsigned long flags;
  1407. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1408. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1409. if (!exit_pending)
  1410. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1411. iwl_leds_unregister(priv);
  1412. priv->cfg->ops->smgmt->clear_station_table(priv);
  1413. /* Unblock any waiting calls */
  1414. wake_up_interruptible_all(&priv->wait_command_queue);
  1415. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1416. * exiting the module */
  1417. if (!exit_pending)
  1418. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1419. /* stop and reset the on-board processor */
  1420. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1421. /* tell the device to stop sending interrupts */
  1422. spin_lock_irqsave(&priv->lock, flags);
  1423. iwl_disable_interrupts(priv);
  1424. spin_unlock_irqrestore(&priv->lock, flags);
  1425. iwl_synchronize_irq(priv);
  1426. if (priv->mac80211_registered)
  1427. ieee80211_stop_queues(priv->hw);
  1428. /* If we have not previously called iwl_init() then
  1429. * clear all bits but the RF Kill bits and return */
  1430. if (!iwl_is_init(priv)) {
  1431. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1432. STATUS_RF_KILL_HW |
  1433. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1434. STATUS_RF_KILL_SW |
  1435. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1436. STATUS_GEO_CONFIGURED |
  1437. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1438. STATUS_EXIT_PENDING;
  1439. goto exit;
  1440. }
  1441. /* ...otherwise clear out all the status bits but the RF Kill
  1442. * bits and continue taking the NIC down. */
  1443. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1444. STATUS_RF_KILL_HW |
  1445. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1446. STATUS_RF_KILL_SW |
  1447. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1448. STATUS_GEO_CONFIGURED |
  1449. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1450. STATUS_FW_ERROR |
  1451. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1452. STATUS_EXIT_PENDING;
  1453. /* device going down, Stop using ICT table */
  1454. iwl_disable_ict(priv);
  1455. spin_lock_irqsave(&priv->lock, flags);
  1456. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1457. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1458. spin_unlock_irqrestore(&priv->lock, flags);
  1459. iwl_txq_ctx_stop(priv);
  1460. iwl_rxq_stop(priv);
  1461. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1462. APMG_CLK_VAL_DMA_CLK_RQT);
  1463. udelay(5);
  1464. /* FIXME: apm_ops.suspend(priv) */
  1465. if (exit_pending)
  1466. priv->cfg->ops->lib->apm_ops.stop(priv);
  1467. else
  1468. priv->cfg->ops->lib->apm_ops.reset(priv);
  1469. exit:
  1470. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1471. if (priv->ibss_beacon)
  1472. dev_kfree_skb(priv->ibss_beacon);
  1473. priv->ibss_beacon = NULL;
  1474. /* clear out any free frames */
  1475. iwl_clear_free_frames(priv);
  1476. }
  1477. static void iwl_down(struct iwl_priv *priv)
  1478. {
  1479. mutex_lock(&priv->mutex);
  1480. __iwl_down(priv);
  1481. mutex_unlock(&priv->mutex);
  1482. iwl_cancel_deferred_work(priv);
  1483. }
  1484. #define HW_READY_TIMEOUT (50)
  1485. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1486. {
  1487. int ret = 0;
  1488. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1489. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1490. /* See if we got it */
  1491. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1492. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1493. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1494. HW_READY_TIMEOUT);
  1495. if (ret != -ETIMEDOUT)
  1496. priv->hw_ready = true;
  1497. else
  1498. priv->hw_ready = false;
  1499. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1500. (priv->hw_ready == 1) ? "ready" : "not ready");
  1501. return ret;
  1502. }
  1503. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1504. {
  1505. int ret = 0;
  1506. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1507. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1508. CSR_HW_IF_CONFIG_REG_PREPARE);
  1509. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1510. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1511. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1512. if (ret != -ETIMEDOUT)
  1513. iwl_set_hw_ready(priv);
  1514. return ret;
  1515. }
  1516. #define MAX_HW_RESTARTS 5
  1517. static int __iwl_up(struct iwl_priv *priv)
  1518. {
  1519. int i;
  1520. int ret;
  1521. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1522. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1523. return -EIO;
  1524. }
  1525. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1526. IWL_ERR(priv, "ucode not available for device bringup\n");
  1527. return -EIO;
  1528. }
  1529. iwl_prepare_card_hw(priv);
  1530. if (!priv->hw_ready) {
  1531. IWL_WARN(priv, "Exit HW not ready\n");
  1532. return -EIO;
  1533. }
  1534. /* If platform's RF_KILL switch is NOT set to KILL */
  1535. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1536. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1537. else
  1538. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1539. if (iwl_is_rfkill(priv)) {
  1540. iwl_enable_interrupts(priv);
  1541. IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
  1542. test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
  1543. return 0;
  1544. }
  1545. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1546. ret = iwl_hw_nic_init(priv);
  1547. if (ret) {
  1548. IWL_ERR(priv, "Unable to init nic\n");
  1549. return ret;
  1550. }
  1551. /* make sure rfkill handshake bits are cleared */
  1552. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1553. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1554. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1555. /* clear (again), then enable host interrupts */
  1556. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1557. /* enable dram interrupt */
  1558. iwl_reset_ict(priv);
  1559. iwl_enable_interrupts(priv);
  1560. /* really make sure rfkill handshake bits are cleared */
  1561. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1562. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1563. /* Copy original ucode data image from disk into backup cache.
  1564. * This will be used to initialize the on-board processor's
  1565. * data SRAM for a clean start when the runtime program first loads. */
  1566. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1567. priv->ucode_data.len);
  1568. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1569. priv->cfg->ops->smgmt->clear_station_table(priv);
  1570. /* load bootstrap state machine,
  1571. * load bootstrap program into processor's memory,
  1572. * prepare to load the "initialize" uCode */
  1573. ret = priv->cfg->ops->lib->load_ucode(priv);
  1574. if (ret) {
  1575. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1576. ret);
  1577. continue;
  1578. }
  1579. /* start card; "initialize" will load runtime ucode */
  1580. iwl_nic_start(priv);
  1581. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1582. return 0;
  1583. }
  1584. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1585. __iwl_down(priv);
  1586. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1587. /* tried to restart and config the device for as long as our
  1588. * patience could withstand */
  1589. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1590. return -EIO;
  1591. }
  1592. /*****************************************************************************
  1593. *
  1594. * Workqueue callbacks
  1595. *
  1596. *****************************************************************************/
  1597. static void iwl_bg_init_alive_start(struct work_struct *data)
  1598. {
  1599. struct iwl_priv *priv =
  1600. container_of(data, struct iwl_priv, init_alive_start.work);
  1601. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1602. return;
  1603. mutex_lock(&priv->mutex);
  1604. priv->cfg->ops->lib->init_alive_start(priv);
  1605. mutex_unlock(&priv->mutex);
  1606. }
  1607. static void iwl_bg_alive_start(struct work_struct *data)
  1608. {
  1609. struct iwl_priv *priv =
  1610. container_of(data, struct iwl_priv, alive_start.work);
  1611. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1612. return;
  1613. mutex_lock(&priv->mutex);
  1614. iwl_alive_start(priv);
  1615. mutex_unlock(&priv->mutex);
  1616. }
  1617. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1618. {
  1619. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1620. run_time_calib_work);
  1621. mutex_lock(&priv->mutex);
  1622. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1623. test_bit(STATUS_SCANNING, &priv->status)) {
  1624. mutex_unlock(&priv->mutex);
  1625. return;
  1626. }
  1627. if (priv->start_calib) {
  1628. iwl_chain_noise_calibration(priv, &priv->statistics);
  1629. iwl_sensitivity_calibration(priv, &priv->statistics);
  1630. }
  1631. mutex_unlock(&priv->mutex);
  1632. return;
  1633. }
  1634. static void iwl_bg_up(struct work_struct *data)
  1635. {
  1636. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1637. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1638. return;
  1639. mutex_lock(&priv->mutex);
  1640. __iwl_up(priv);
  1641. mutex_unlock(&priv->mutex);
  1642. iwl_rfkill_set_hw_state(priv);
  1643. }
  1644. static void iwl_bg_restart(struct work_struct *data)
  1645. {
  1646. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1647. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1648. return;
  1649. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1650. mutex_lock(&priv->mutex);
  1651. priv->vif = NULL;
  1652. priv->is_open = 0;
  1653. mutex_unlock(&priv->mutex);
  1654. iwl_down(priv);
  1655. ieee80211_restart_hw(priv->hw);
  1656. } else {
  1657. iwl_down(priv);
  1658. queue_work(priv->workqueue, &priv->up);
  1659. }
  1660. }
  1661. static void iwl_bg_rx_replenish(struct work_struct *data)
  1662. {
  1663. struct iwl_priv *priv =
  1664. container_of(data, struct iwl_priv, rx_replenish);
  1665. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1666. return;
  1667. mutex_lock(&priv->mutex);
  1668. iwl_rx_replenish(priv);
  1669. mutex_unlock(&priv->mutex);
  1670. }
  1671. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1672. void iwl_post_associate(struct iwl_priv *priv)
  1673. {
  1674. struct ieee80211_conf *conf = NULL;
  1675. int ret = 0;
  1676. unsigned long flags;
  1677. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1678. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1679. return;
  1680. }
  1681. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1682. priv->assoc_id, priv->active_rxon.bssid_addr);
  1683. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1684. return;
  1685. if (!priv->vif || !priv->is_open)
  1686. return;
  1687. iwl_scan_cancel_timeout(priv, 200);
  1688. conf = ieee80211_get_hw_conf(priv->hw);
  1689. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1690. iwlcore_commit_rxon(priv);
  1691. iwl_setup_rxon_timing(priv);
  1692. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1693. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1694. if (ret)
  1695. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1696. "Attempting to continue.\n");
  1697. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1698. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1699. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1700. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1701. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1702. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1703. priv->assoc_id, priv->beacon_int);
  1704. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1705. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1706. else
  1707. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1708. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1709. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1710. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1711. else
  1712. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1713. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1714. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1715. }
  1716. iwlcore_commit_rxon(priv);
  1717. switch (priv->iw_mode) {
  1718. case NL80211_IFTYPE_STATION:
  1719. break;
  1720. case NL80211_IFTYPE_ADHOC:
  1721. /* assume default assoc id */
  1722. priv->assoc_id = 1;
  1723. iwl_rxon_add_station(priv, priv->bssid, 0);
  1724. iwl_send_beacon_cmd(priv);
  1725. break;
  1726. default:
  1727. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1728. __func__, priv->iw_mode);
  1729. break;
  1730. }
  1731. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1732. priv->assoc_station_added = 1;
  1733. spin_lock_irqsave(&priv->lock, flags);
  1734. iwl_activate_qos(priv, 0);
  1735. spin_unlock_irqrestore(&priv->lock, flags);
  1736. /* the chain noise calibration will enabled PM upon completion
  1737. * If chain noise has already been run, then we need to enable
  1738. * power management here */
  1739. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1740. iwl_power_update_mode(priv, 0);
  1741. /* Enable Rx differential gain and sensitivity calibrations */
  1742. iwl_chain_noise_reset(priv);
  1743. priv->start_calib = 1;
  1744. }
  1745. /*****************************************************************************
  1746. *
  1747. * mac80211 entry point functions
  1748. *
  1749. *****************************************************************************/
  1750. #define UCODE_READY_TIMEOUT (4 * HZ)
  1751. static int iwl_mac_start(struct ieee80211_hw *hw)
  1752. {
  1753. struct iwl_priv *priv = hw->priv;
  1754. int ret;
  1755. IWL_DEBUG_MAC80211(priv, "enter\n");
  1756. /* we should be verifying the device is ready to be opened */
  1757. mutex_lock(&priv->mutex);
  1758. memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
  1759. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1760. * ucode filename and max sizes are card-specific. */
  1761. if (!priv->ucode_code.len) {
  1762. ret = iwl_read_ucode(priv);
  1763. if (ret) {
  1764. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1765. mutex_unlock(&priv->mutex);
  1766. return ret;
  1767. }
  1768. }
  1769. ret = __iwl_up(priv);
  1770. mutex_unlock(&priv->mutex);
  1771. iwl_rfkill_set_hw_state(priv);
  1772. if (ret)
  1773. return ret;
  1774. if (iwl_is_rfkill(priv))
  1775. goto out;
  1776. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1777. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1778. * mac80211 will not be run successfully. */
  1779. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1780. test_bit(STATUS_READY, &priv->status),
  1781. UCODE_READY_TIMEOUT);
  1782. if (!ret) {
  1783. if (!test_bit(STATUS_READY, &priv->status)) {
  1784. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1785. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1786. return -ETIMEDOUT;
  1787. }
  1788. }
  1789. out:
  1790. priv->is_open = 1;
  1791. IWL_DEBUG_MAC80211(priv, "leave\n");
  1792. return 0;
  1793. }
  1794. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1795. {
  1796. struct iwl_priv *priv = hw->priv;
  1797. IWL_DEBUG_MAC80211(priv, "enter\n");
  1798. if (!priv->is_open)
  1799. return;
  1800. priv->is_open = 0;
  1801. if (iwl_is_ready_rf(priv)) {
  1802. /* stop mac, cancel any scan request and clear
  1803. * RXON_FILTER_ASSOC_MSK BIT
  1804. */
  1805. mutex_lock(&priv->mutex);
  1806. iwl_scan_cancel_timeout(priv, 100);
  1807. mutex_unlock(&priv->mutex);
  1808. }
  1809. iwl_down(priv);
  1810. flush_workqueue(priv->workqueue);
  1811. /* enable interrupts again in order to receive rfkill changes */
  1812. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1813. iwl_enable_interrupts(priv);
  1814. IWL_DEBUG_MAC80211(priv, "leave\n");
  1815. }
  1816. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1817. {
  1818. struct iwl_priv *priv = hw->priv;
  1819. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1820. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1821. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1822. if (iwl_tx_skb(priv, skb))
  1823. dev_kfree_skb_any(skb);
  1824. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1825. return NETDEV_TX_OK;
  1826. }
  1827. void iwl_config_ap(struct iwl_priv *priv)
  1828. {
  1829. int ret = 0;
  1830. unsigned long flags;
  1831. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1832. return;
  1833. /* The following should be done only at AP bring up */
  1834. if (!iwl_is_associated(priv)) {
  1835. /* RXON - unassoc (to set timing command) */
  1836. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1837. iwlcore_commit_rxon(priv);
  1838. /* RXON Timing */
  1839. iwl_setup_rxon_timing(priv);
  1840. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1841. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1842. if (ret)
  1843. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1844. "Attempting to continue.\n");
  1845. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1846. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1847. /* FIXME: what should be the assoc_id for AP? */
  1848. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1849. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1850. priv->staging_rxon.flags |=
  1851. RXON_FLG_SHORT_PREAMBLE_MSK;
  1852. else
  1853. priv->staging_rxon.flags &=
  1854. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1855. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1856. if (priv->assoc_capability &
  1857. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1858. priv->staging_rxon.flags |=
  1859. RXON_FLG_SHORT_SLOT_MSK;
  1860. else
  1861. priv->staging_rxon.flags &=
  1862. ~RXON_FLG_SHORT_SLOT_MSK;
  1863. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1864. priv->staging_rxon.flags &=
  1865. ~RXON_FLG_SHORT_SLOT_MSK;
  1866. }
  1867. /* restore RXON assoc */
  1868. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1869. iwlcore_commit_rxon(priv);
  1870. spin_lock_irqsave(&priv->lock, flags);
  1871. iwl_activate_qos(priv, 1);
  1872. spin_unlock_irqrestore(&priv->lock, flags);
  1873. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1874. }
  1875. iwl_send_beacon_cmd(priv);
  1876. /* FIXME - we need to add code here to detect a totally new
  1877. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1878. * clear sta table, add BCAST sta... */
  1879. }
  1880. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1881. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1882. u32 iv32, u16 *phase1key)
  1883. {
  1884. struct iwl_priv *priv = hw->priv;
  1885. IWL_DEBUG_MAC80211(priv, "enter\n");
  1886. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1887. IWL_DEBUG_MAC80211(priv, "leave\n");
  1888. }
  1889. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1890. struct ieee80211_vif *vif,
  1891. struct ieee80211_sta *sta,
  1892. struct ieee80211_key_conf *key)
  1893. {
  1894. struct iwl_priv *priv = hw->priv;
  1895. const u8 *addr;
  1896. int ret;
  1897. u8 sta_id;
  1898. bool is_default_wep_key = false;
  1899. IWL_DEBUG_MAC80211(priv, "enter\n");
  1900. if (priv->hw_params.sw_crypto) {
  1901. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1902. return -EOPNOTSUPP;
  1903. }
  1904. addr = sta ? sta->addr : iwl_bcast_addr;
  1905. sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
  1906. if (sta_id == IWL_INVALID_STATION) {
  1907. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1908. addr);
  1909. return -EINVAL;
  1910. }
  1911. mutex_lock(&priv->mutex);
  1912. iwl_scan_cancel_timeout(priv, 100);
  1913. mutex_unlock(&priv->mutex);
  1914. /* If we are getting WEP group key and we didn't receive any key mapping
  1915. * so far, we are in legacy wep mode (group key only), otherwise we are
  1916. * in 1X mode.
  1917. * In legacy wep mode, we use another host command to the uCode */
  1918. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1919. priv->iw_mode != NL80211_IFTYPE_AP) {
  1920. if (cmd == SET_KEY)
  1921. is_default_wep_key = !priv->key_mapping_key;
  1922. else
  1923. is_default_wep_key =
  1924. (key->hw_key_idx == HW_KEY_DEFAULT);
  1925. }
  1926. switch (cmd) {
  1927. case SET_KEY:
  1928. if (is_default_wep_key)
  1929. ret = iwl_set_default_wep_key(priv, key);
  1930. else
  1931. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1932. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1933. break;
  1934. case DISABLE_KEY:
  1935. if (is_default_wep_key)
  1936. ret = iwl_remove_default_wep_key(priv, key);
  1937. else
  1938. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1939. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1940. break;
  1941. default:
  1942. ret = -EINVAL;
  1943. }
  1944. IWL_DEBUG_MAC80211(priv, "leave\n");
  1945. return ret;
  1946. }
  1947. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1948. enum ieee80211_ampdu_mlme_action action,
  1949. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1950. {
  1951. struct iwl_priv *priv = hw->priv;
  1952. int ret;
  1953. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1954. sta->addr, tid);
  1955. if (!(priv->cfg->sku & IWL_SKU_N))
  1956. return -EACCES;
  1957. switch (action) {
  1958. case IEEE80211_AMPDU_RX_START:
  1959. IWL_DEBUG_HT(priv, "start Rx\n");
  1960. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1961. case IEEE80211_AMPDU_RX_STOP:
  1962. IWL_DEBUG_HT(priv, "stop Rx\n");
  1963. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1964. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1965. return 0;
  1966. else
  1967. return ret;
  1968. case IEEE80211_AMPDU_TX_START:
  1969. IWL_DEBUG_HT(priv, "start Tx\n");
  1970. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1971. case IEEE80211_AMPDU_TX_STOP:
  1972. IWL_DEBUG_HT(priv, "stop Tx\n");
  1973. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1974. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1975. return 0;
  1976. else
  1977. return ret;
  1978. default:
  1979. IWL_DEBUG_HT(priv, "unknown\n");
  1980. return -EINVAL;
  1981. break;
  1982. }
  1983. return 0;
  1984. }
  1985. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1986. struct ieee80211_low_level_stats *stats)
  1987. {
  1988. struct iwl_priv *priv = hw->priv;
  1989. priv = hw->priv;
  1990. IWL_DEBUG_MAC80211(priv, "enter\n");
  1991. IWL_DEBUG_MAC80211(priv, "leave\n");
  1992. return 0;
  1993. }
  1994. /*****************************************************************************
  1995. *
  1996. * sysfs attributes
  1997. *
  1998. *****************************************************************************/
  1999. #ifdef CONFIG_IWLWIFI_DEBUG
  2000. /*
  2001. * The following adds a new attribute to the sysfs representation
  2002. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2003. * used for controlling the debug level.
  2004. *
  2005. * See the level definitions in iwl for details.
  2006. */
  2007. static ssize_t show_debug_level(struct device *d,
  2008. struct device_attribute *attr, char *buf)
  2009. {
  2010. struct iwl_priv *priv = dev_get_drvdata(d);
  2011. return sprintf(buf, "0x%08X\n", priv->debug_level);
  2012. }
  2013. static ssize_t store_debug_level(struct device *d,
  2014. struct device_attribute *attr,
  2015. const char *buf, size_t count)
  2016. {
  2017. struct iwl_priv *priv = dev_get_drvdata(d);
  2018. unsigned long val;
  2019. int ret;
  2020. ret = strict_strtoul(buf, 0, &val);
  2021. if (ret)
  2022. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2023. else
  2024. priv->debug_level = val;
  2025. return strnlen(buf, count);
  2026. }
  2027. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2028. show_debug_level, store_debug_level);
  2029. #endif /* CONFIG_IWLWIFI_DEBUG */
  2030. static ssize_t show_version(struct device *d,
  2031. struct device_attribute *attr, char *buf)
  2032. {
  2033. struct iwl_priv *priv = dev_get_drvdata(d);
  2034. struct iwl_alive_resp *palive = &priv->card_alive;
  2035. ssize_t pos = 0;
  2036. u16 eeprom_ver;
  2037. if (palive->is_valid)
  2038. pos += sprintf(buf + pos,
  2039. "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
  2040. "fw type: 0x%01X 0x%01X\n",
  2041. palive->ucode_major, palive->ucode_minor,
  2042. palive->sw_rev[0], palive->sw_rev[1],
  2043. palive->ver_type, palive->ver_subtype);
  2044. else
  2045. pos += sprintf(buf + pos, "fw not loaded\n");
  2046. if (priv->eeprom) {
  2047. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  2048. pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
  2049. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  2050. ? "OTP" : "EEPROM", eeprom_ver);
  2051. } else {
  2052. pos += sprintf(buf + pos, "EEPROM not initialzed\n");
  2053. }
  2054. return pos;
  2055. }
  2056. static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
  2057. static ssize_t show_temperature(struct device *d,
  2058. struct device_attribute *attr, char *buf)
  2059. {
  2060. struct iwl_priv *priv = dev_get_drvdata(d);
  2061. if (!iwl_is_alive(priv))
  2062. return -EAGAIN;
  2063. return sprintf(buf, "%d\n", priv->temperature);
  2064. }
  2065. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2066. static ssize_t show_tx_power(struct device *d,
  2067. struct device_attribute *attr, char *buf)
  2068. {
  2069. struct iwl_priv *priv = dev_get_drvdata(d);
  2070. if (!iwl_is_ready_rf(priv))
  2071. return sprintf(buf, "off\n");
  2072. else
  2073. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2074. }
  2075. static ssize_t store_tx_power(struct device *d,
  2076. struct device_attribute *attr,
  2077. const char *buf, size_t count)
  2078. {
  2079. struct iwl_priv *priv = dev_get_drvdata(d);
  2080. unsigned long val;
  2081. int ret;
  2082. ret = strict_strtoul(buf, 10, &val);
  2083. if (ret)
  2084. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2085. else
  2086. iwl_set_tx_power(priv, val, false);
  2087. return count;
  2088. }
  2089. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2090. static ssize_t show_flags(struct device *d,
  2091. struct device_attribute *attr, char *buf)
  2092. {
  2093. struct iwl_priv *priv = dev_get_drvdata(d);
  2094. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2095. }
  2096. static ssize_t store_flags(struct device *d,
  2097. struct device_attribute *attr,
  2098. const char *buf, size_t count)
  2099. {
  2100. struct iwl_priv *priv = dev_get_drvdata(d);
  2101. unsigned long val;
  2102. u32 flags;
  2103. int ret = strict_strtoul(buf, 0, &val);
  2104. if (ret)
  2105. return ret;
  2106. flags = (u32)val;
  2107. mutex_lock(&priv->mutex);
  2108. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2109. /* Cancel any currently running scans... */
  2110. if (iwl_scan_cancel_timeout(priv, 100))
  2111. IWL_WARN(priv, "Could not cancel scan.\n");
  2112. else {
  2113. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2114. priv->staging_rxon.flags = cpu_to_le32(flags);
  2115. iwlcore_commit_rxon(priv);
  2116. }
  2117. }
  2118. mutex_unlock(&priv->mutex);
  2119. return count;
  2120. }
  2121. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2122. static ssize_t show_filter_flags(struct device *d,
  2123. struct device_attribute *attr, char *buf)
  2124. {
  2125. struct iwl_priv *priv = dev_get_drvdata(d);
  2126. return sprintf(buf, "0x%04X\n",
  2127. le32_to_cpu(priv->active_rxon.filter_flags));
  2128. }
  2129. static ssize_t store_filter_flags(struct device *d,
  2130. struct device_attribute *attr,
  2131. const char *buf, size_t count)
  2132. {
  2133. struct iwl_priv *priv = dev_get_drvdata(d);
  2134. unsigned long val;
  2135. u32 filter_flags;
  2136. int ret = strict_strtoul(buf, 0, &val);
  2137. if (ret)
  2138. return ret;
  2139. filter_flags = (u32)val;
  2140. mutex_lock(&priv->mutex);
  2141. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2142. /* Cancel any currently running scans... */
  2143. if (iwl_scan_cancel_timeout(priv, 100))
  2144. IWL_WARN(priv, "Could not cancel scan.\n");
  2145. else {
  2146. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2147. "0x%04X\n", filter_flags);
  2148. priv->staging_rxon.filter_flags =
  2149. cpu_to_le32(filter_flags);
  2150. iwlcore_commit_rxon(priv);
  2151. }
  2152. }
  2153. mutex_unlock(&priv->mutex);
  2154. return count;
  2155. }
  2156. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2157. store_filter_flags);
  2158. static ssize_t store_power_level(struct device *d,
  2159. struct device_attribute *attr,
  2160. const char *buf, size_t count)
  2161. {
  2162. struct iwl_priv *priv = dev_get_drvdata(d);
  2163. int ret;
  2164. unsigned long mode;
  2165. mutex_lock(&priv->mutex);
  2166. ret = strict_strtoul(buf, 10, &mode);
  2167. if (ret)
  2168. goto out;
  2169. ret = iwl_power_set_user_mode(priv, mode);
  2170. if (ret) {
  2171. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  2172. goto out;
  2173. }
  2174. ret = count;
  2175. out:
  2176. mutex_unlock(&priv->mutex);
  2177. return ret;
  2178. }
  2179. static ssize_t show_power_level(struct device *d,
  2180. struct device_attribute *attr, char *buf)
  2181. {
  2182. struct iwl_priv *priv = dev_get_drvdata(d);
  2183. int mode = priv->power_data.user_power_setting;
  2184. int level = priv->power_data.power_mode;
  2185. char *p = buf;
  2186. p += sprintf(p, "INDEX:%d\t", level);
  2187. p += sprintf(p, "USER:%d\n", mode);
  2188. return p - buf + 1;
  2189. }
  2190. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2191. store_power_level);
  2192. static ssize_t show_qos(struct device *d,
  2193. struct device_attribute *attr, char *buf)
  2194. {
  2195. struct iwl_priv *priv = dev_get_drvdata(d);
  2196. char *p = buf;
  2197. int q;
  2198. for (q = 0; q < AC_NUM; q++) {
  2199. p += sprintf(p, "\tcw_min\tcw_max\taifsn\ttxop\n");
  2200. p += sprintf(p, "AC[%d]\t%u\t%u\t%u\t%u\n", q,
  2201. priv->qos_data.def_qos_parm.ac[q].cw_min,
  2202. priv->qos_data.def_qos_parm.ac[q].cw_max,
  2203. priv->qos_data.def_qos_parm.ac[q].aifsn,
  2204. priv->qos_data.def_qos_parm.ac[q].edca_txop);
  2205. }
  2206. return p - buf + 1;
  2207. }
  2208. static DEVICE_ATTR(qos, S_IRUGO, show_qos, NULL);
  2209. static ssize_t show_statistics(struct device *d,
  2210. struct device_attribute *attr, char *buf)
  2211. {
  2212. struct iwl_priv *priv = dev_get_drvdata(d);
  2213. u32 size = sizeof(struct iwl_notif_statistics);
  2214. u32 len = 0, ofs = 0;
  2215. u8 *data = (u8 *)&priv->statistics;
  2216. int rc = 0;
  2217. if (!iwl_is_alive(priv))
  2218. return -EAGAIN;
  2219. mutex_lock(&priv->mutex);
  2220. rc = iwl_send_statistics_request(priv, 0);
  2221. mutex_unlock(&priv->mutex);
  2222. if (rc) {
  2223. len = sprintf(buf,
  2224. "Error sending statistics request: 0x%08X\n", rc);
  2225. return len;
  2226. }
  2227. while (size && (PAGE_SIZE - len)) {
  2228. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2229. PAGE_SIZE - len, 1);
  2230. len = strlen(buf);
  2231. if (PAGE_SIZE - len)
  2232. buf[len++] = '\n';
  2233. ofs += 16;
  2234. size -= min(size, 16U);
  2235. }
  2236. return len;
  2237. }
  2238. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2239. /*****************************************************************************
  2240. *
  2241. * driver setup and teardown
  2242. *
  2243. *****************************************************************************/
  2244. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2245. {
  2246. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2247. init_waitqueue_head(&priv->wait_command_queue);
  2248. INIT_WORK(&priv->up, iwl_bg_up);
  2249. INIT_WORK(&priv->restart, iwl_bg_restart);
  2250. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2251. INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
  2252. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2253. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2254. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2255. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2256. iwl_setup_scan_deferred_work(priv);
  2257. if (priv->cfg->ops->lib->setup_deferred_work)
  2258. priv->cfg->ops->lib->setup_deferred_work(priv);
  2259. init_timer(&priv->statistics_periodic);
  2260. priv->statistics_periodic.data = (unsigned long)priv;
  2261. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2262. if (!priv->cfg->use_isr_legacy)
  2263. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2264. iwl_irq_tasklet, (unsigned long)priv);
  2265. else
  2266. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2267. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2268. }
  2269. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2270. {
  2271. if (priv->cfg->ops->lib->cancel_deferred_work)
  2272. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2273. cancel_delayed_work_sync(&priv->init_alive_start);
  2274. cancel_delayed_work(&priv->scan_check);
  2275. cancel_delayed_work(&priv->alive_start);
  2276. cancel_work_sync(&priv->beacon_update);
  2277. del_timer_sync(&priv->statistics_periodic);
  2278. }
  2279. static struct attribute *iwl_sysfs_entries[] = {
  2280. &dev_attr_flags.attr,
  2281. &dev_attr_filter_flags.attr,
  2282. &dev_attr_power_level.attr,
  2283. &dev_attr_statistics.attr,
  2284. &dev_attr_temperature.attr,
  2285. &dev_attr_tx_power.attr,
  2286. #ifdef CONFIG_IWLWIFI_DEBUG
  2287. &dev_attr_debug_level.attr,
  2288. #endif
  2289. &dev_attr_version.attr,
  2290. &dev_attr_qos.attr,
  2291. NULL
  2292. };
  2293. static struct attribute_group iwl_attribute_group = {
  2294. .name = NULL, /* put in device directory */
  2295. .attrs = iwl_sysfs_entries,
  2296. };
  2297. static struct ieee80211_ops iwl_hw_ops = {
  2298. .tx = iwl_mac_tx,
  2299. .start = iwl_mac_start,
  2300. .stop = iwl_mac_stop,
  2301. .add_interface = iwl_mac_add_interface,
  2302. .remove_interface = iwl_mac_remove_interface,
  2303. .config = iwl_mac_config,
  2304. .configure_filter = iwl_configure_filter,
  2305. .set_key = iwl_mac_set_key,
  2306. .update_tkip_key = iwl_mac_update_tkip_key,
  2307. .get_stats = iwl_mac_get_stats,
  2308. .get_tx_stats = iwl_mac_get_tx_stats,
  2309. .conf_tx = iwl_mac_conf_tx,
  2310. .reset_tsf = iwl_mac_reset_tsf,
  2311. .bss_info_changed = iwl_bss_info_changed,
  2312. .ampdu_action = iwl_mac_ampdu_action,
  2313. .hw_scan = iwl_mac_hw_scan
  2314. };
  2315. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2316. {
  2317. int err = 0;
  2318. struct iwl_priv *priv;
  2319. struct ieee80211_hw *hw;
  2320. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2321. unsigned long flags;
  2322. u16 pci_cmd;
  2323. /************************
  2324. * 1. Allocating HW data
  2325. ************************/
  2326. /* Disabling hardware scan means that mac80211 will perform scans
  2327. * "the hard way", rather than using device's scan. */
  2328. if (cfg->mod_params->disable_hw_scan) {
  2329. if (cfg->mod_params->debug & IWL_DL_INFO)
  2330. dev_printk(KERN_DEBUG, &(pdev->dev),
  2331. "Disabling hw_scan\n");
  2332. iwl_hw_ops.hw_scan = NULL;
  2333. }
  2334. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2335. if (!hw) {
  2336. err = -ENOMEM;
  2337. goto out;
  2338. }
  2339. priv = hw->priv;
  2340. /* At this point both hw and priv are allocated. */
  2341. SET_IEEE80211_DEV(hw, &pdev->dev);
  2342. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2343. priv->cfg = cfg;
  2344. priv->pci_dev = pdev;
  2345. priv->inta_mask = CSR_INI_SET_MASK;
  2346. #ifdef CONFIG_IWLWIFI_DEBUG
  2347. priv->debug_level = priv->cfg->mod_params->debug;
  2348. atomic_set(&priv->restrict_refcnt, 0);
  2349. #endif
  2350. /**************************
  2351. * 2. Initializing PCI bus
  2352. **************************/
  2353. if (pci_enable_device(pdev)) {
  2354. err = -ENODEV;
  2355. goto out_ieee80211_free_hw;
  2356. }
  2357. pci_set_master(pdev);
  2358. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2359. if (!err)
  2360. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2361. if (err) {
  2362. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2363. if (!err)
  2364. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2365. /* both attempts failed: */
  2366. if (err) {
  2367. IWL_WARN(priv, "No suitable DMA available.\n");
  2368. goto out_pci_disable_device;
  2369. }
  2370. }
  2371. err = pci_request_regions(pdev, DRV_NAME);
  2372. if (err)
  2373. goto out_pci_disable_device;
  2374. pci_set_drvdata(pdev, priv);
  2375. /***********************
  2376. * 3. Read REV register
  2377. ***********************/
  2378. priv->hw_base = pci_iomap(pdev, 0, 0);
  2379. if (!priv->hw_base) {
  2380. err = -ENODEV;
  2381. goto out_pci_release_regions;
  2382. }
  2383. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2384. (unsigned long long) pci_resource_len(pdev, 0));
  2385. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2386. /* this spin lock will be used in apm_ops.init and EEPROM access
  2387. * we should init now
  2388. */
  2389. spin_lock_init(&priv->reg_lock);
  2390. iwl_hw_detect(priv);
  2391. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2392. priv->cfg->name, priv->hw_rev);
  2393. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2394. * PCI Tx retries from interfering with C3 CPU state */
  2395. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2396. iwl_prepare_card_hw(priv);
  2397. if (!priv->hw_ready) {
  2398. IWL_WARN(priv, "Failed, HW not ready\n");
  2399. goto out_iounmap;
  2400. }
  2401. /* amp init */
  2402. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2403. if (err < 0) {
  2404. IWL_ERR(priv, "Failed to init APMG\n");
  2405. goto out_iounmap;
  2406. }
  2407. /*****************
  2408. * 4. Read EEPROM
  2409. *****************/
  2410. /* Read the EEPROM */
  2411. err = iwl_eeprom_init(priv);
  2412. if (err) {
  2413. IWL_ERR(priv, "Unable to init EEPROM\n");
  2414. goto out_iounmap;
  2415. }
  2416. err = iwl_eeprom_check_version(priv);
  2417. if (err)
  2418. goto out_free_eeprom;
  2419. /* extract MAC Address */
  2420. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2421. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2422. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2423. /************************
  2424. * 5. Setup HW constants
  2425. ************************/
  2426. if (iwl_set_hw_params(priv)) {
  2427. IWL_ERR(priv, "failed to set hw parameters\n");
  2428. goto out_free_eeprom;
  2429. }
  2430. /*******************
  2431. * 6. Setup priv
  2432. *******************/
  2433. err = iwl_init_drv(priv);
  2434. if (err)
  2435. goto out_free_eeprom;
  2436. /* At this point both hw and priv are initialized. */
  2437. /********************
  2438. * 7. Setup services
  2439. ********************/
  2440. spin_lock_irqsave(&priv->lock, flags);
  2441. iwl_disable_interrupts(priv);
  2442. spin_unlock_irqrestore(&priv->lock, flags);
  2443. pci_enable_msi(priv->pci_dev);
  2444. iwl_alloc_isr_ict(priv);
  2445. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2446. IRQF_SHARED, DRV_NAME, priv);
  2447. if (err) {
  2448. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2449. goto out_disable_msi;
  2450. }
  2451. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2452. if (err) {
  2453. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2454. goto out_free_irq;
  2455. }
  2456. iwl_setup_deferred_work(priv);
  2457. iwl_setup_rx_handlers(priv);
  2458. /**********************************
  2459. * 8. Setup and register mac80211
  2460. **********************************/
  2461. /* enable interrupts if needed: hw bug w/a */
  2462. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2463. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2464. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2465. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2466. }
  2467. iwl_enable_interrupts(priv);
  2468. err = iwl_setup_mac(priv);
  2469. if (err)
  2470. goto out_remove_sysfs;
  2471. err = iwl_dbgfs_register(priv, DRV_NAME);
  2472. if (err)
  2473. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2474. /* If platform's RF_KILL switch is NOT set to KILL */
  2475. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2476. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2477. else
  2478. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2479. err = iwl_rfkill_init(priv);
  2480. if (err)
  2481. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  2482. "Ignoring error: %d\n", err);
  2483. else
  2484. iwl_rfkill_set_hw_state(priv);
  2485. iwl_power_initialize(priv);
  2486. return 0;
  2487. out_remove_sysfs:
  2488. destroy_workqueue(priv->workqueue);
  2489. priv->workqueue = NULL;
  2490. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2491. out_free_irq:
  2492. free_irq(priv->pci_dev->irq, priv);
  2493. iwl_free_isr_ict(priv);
  2494. out_disable_msi:
  2495. pci_disable_msi(priv->pci_dev);
  2496. iwl_uninit_drv(priv);
  2497. out_free_eeprom:
  2498. iwl_eeprom_free(priv);
  2499. out_iounmap:
  2500. pci_iounmap(pdev, priv->hw_base);
  2501. out_pci_release_regions:
  2502. pci_set_drvdata(pdev, NULL);
  2503. pci_release_regions(pdev);
  2504. out_pci_disable_device:
  2505. pci_disable_device(pdev);
  2506. out_ieee80211_free_hw:
  2507. ieee80211_free_hw(priv->hw);
  2508. out:
  2509. return err;
  2510. }
  2511. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2512. {
  2513. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2514. unsigned long flags;
  2515. if (!priv)
  2516. return;
  2517. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2518. iwl_dbgfs_unregister(priv);
  2519. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2520. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2521. * to be called and iwl_down since we are removing the device
  2522. * we need to set STATUS_EXIT_PENDING bit.
  2523. */
  2524. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2525. if (priv->mac80211_registered) {
  2526. ieee80211_unregister_hw(priv->hw);
  2527. priv->mac80211_registered = 0;
  2528. } else {
  2529. iwl_down(priv);
  2530. }
  2531. /* make sure we flush any pending irq or
  2532. * tasklet for the driver
  2533. */
  2534. spin_lock_irqsave(&priv->lock, flags);
  2535. iwl_disable_interrupts(priv);
  2536. spin_unlock_irqrestore(&priv->lock, flags);
  2537. iwl_synchronize_irq(priv);
  2538. iwl_rfkill_unregister(priv);
  2539. iwl_dealloc_ucode_pci(priv);
  2540. if (priv->rxq.bd)
  2541. iwl_rx_queue_free(priv, &priv->rxq);
  2542. iwl_hw_txq_ctx_free(priv);
  2543. priv->cfg->ops->smgmt->clear_station_table(priv);
  2544. iwl_eeprom_free(priv);
  2545. /*netif_stop_queue(dev); */
  2546. flush_workqueue(priv->workqueue);
  2547. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2548. * priv->workqueue... so we can't take down the workqueue
  2549. * until now... */
  2550. destroy_workqueue(priv->workqueue);
  2551. priv->workqueue = NULL;
  2552. free_irq(priv->pci_dev->irq, priv);
  2553. pci_disable_msi(priv->pci_dev);
  2554. pci_iounmap(pdev, priv->hw_base);
  2555. pci_release_regions(pdev);
  2556. pci_disable_device(pdev);
  2557. pci_set_drvdata(pdev, NULL);
  2558. iwl_uninit_drv(priv);
  2559. iwl_free_isr_ict(priv);
  2560. if (priv->ibss_beacon)
  2561. dev_kfree_skb(priv->ibss_beacon);
  2562. ieee80211_free_hw(priv->hw);
  2563. }
  2564. /*****************************************************************************
  2565. *
  2566. * driver and module entry point
  2567. *
  2568. *****************************************************************************/
  2569. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2570. static struct pci_device_id iwl_hw_card_ids[] = {
  2571. #ifdef CONFIG_IWL4965
  2572. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2573. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2574. #endif /* CONFIG_IWL4965 */
  2575. #ifdef CONFIG_IWL5000
  2576. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2577. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2578. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2579. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2580. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2581. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2582. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2583. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2584. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2585. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2586. /* 5350 WiFi/WiMax */
  2587. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2588. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2589. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2590. /* 5150 Wifi/WiMax */
  2591. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2592. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2593. /* 6000/6050 Series */
  2594. {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
  2595. {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
  2596. {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
  2597. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2598. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2599. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2600. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2601. {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2602. {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2603. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2604. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2605. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2606. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2607. /* 1000 Series WiFi */
  2608. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2609. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2610. #endif /* CONFIG_IWL5000 */
  2611. {0}
  2612. };
  2613. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2614. static struct pci_driver iwl_driver = {
  2615. .name = DRV_NAME,
  2616. .id_table = iwl_hw_card_ids,
  2617. .probe = iwl_pci_probe,
  2618. .remove = __devexit_p(iwl_pci_remove),
  2619. #ifdef CONFIG_PM
  2620. .suspend = iwl_pci_suspend,
  2621. .resume = iwl_pci_resume,
  2622. #endif
  2623. };
  2624. static int __init iwl_init(void)
  2625. {
  2626. int ret;
  2627. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2628. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2629. ret = iwlagn_rate_control_register();
  2630. if (ret) {
  2631. printk(KERN_ERR DRV_NAME
  2632. "Unable to register rate control algorithm: %d\n", ret);
  2633. return ret;
  2634. }
  2635. ret = pci_register_driver(&iwl_driver);
  2636. if (ret) {
  2637. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2638. goto error_register;
  2639. }
  2640. return ret;
  2641. error_register:
  2642. iwlagn_rate_control_unregister();
  2643. return ret;
  2644. }
  2645. static void __exit iwl_exit(void)
  2646. {
  2647. pci_unregister_driver(&iwl_driver);
  2648. iwlagn_rate_control_unregister();
  2649. }
  2650. module_exit(iwl_exit);
  2651. module_init(iwl_init);