wm8958-dsp2.c 27 KB

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  1. /*
  2. * wm8958-dsp2.c -- WM8958 DSP2 support
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <trace/events/asoc.h>
  24. #include <linux/mfd/wm8994/core.h>
  25. #include <linux/mfd/wm8994/registers.h>
  26. #include <linux/mfd/wm8994/pdata.h>
  27. #include <linux/mfd/wm8994/gpio.h>
  28. #include "wm8994.h"
  29. #define WM_FW_BLOCK_INFO 0xff
  30. #define WM_FW_BLOCK_PM 0x00
  31. #define WM_FW_BLOCK_X 0x01
  32. #define WM_FW_BLOCK_Y 0x02
  33. #define WM_FW_BLOCK_Z 0x03
  34. #define WM_FW_BLOCK_I 0x06
  35. #define WM_FW_BLOCK_A 0x08
  36. #define WM_FW_BLOCK_C 0x0c
  37. static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
  38. const struct firmware *fw, bool check)
  39. {
  40. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  41. u64 data64;
  42. u32 data32;
  43. const u8 *data;
  44. char *str;
  45. size_t block_len, len;
  46. int ret = 0;
  47. /* Suppress unneeded downloads */
  48. if (wm8994->cur_fw == fw)
  49. return 0;
  50. if (fw->size < 32) {
  51. dev_err(codec->dev, "%s: firmware too short (%d bytes)\n",
  52. name, fw->size);
  53. goto err;
  54. }
  55. if (memcmp(fw->data, "WMFW", 4) != 0) {
  56. dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
  57. name, data32);
  58. goto err;
  59. }
  60. memcpy(&data32, fw->data + 4, sizeof(data32));
  61. len = be32_to_cpu(data32);
  62. memcpy(&data32, fw->data + 8, sizeof(data32));
  63. data32 = be32_to_cpu(data32);
  64. if ((data32 >> 24) & 0xff) {
  65. dev_err(codec->dev, "%s: unsupported firmware version %d\n",
  66. name, (data32 >> 24) & 0xff);
  67. goto err;
  68. }
  69. if ((data32 & 0xffff) != 8958) {
  70. dev_err(codec->dev, "%s: unsupported target device %d\n",
  71. name, data32 & 0xffff);
  72. goto err;
  73. }
  74. if (((data32 >> 16) & 0xff) != 0xc) {
  75. dev_err(codec->dev, "%s: unsupported target core %d\n",
  76. name, (data32 >> 16) & 0xff);
  77. goto err;
  78. }
  79. if (check) {
  80. memcpy(&data64, fw->data + 24, sizeof(u64));
  81. dev_info(codec->dev, "%s timestamp %llx\n",
  82. name, be64_to_cpu(data64));
  83. } else {
  84. snd_soc_write(codec, 0x102, 0x2);
  85. snd_soc_write(codec, 0x900, 0x2);
  86. }
  87. data = fw->data + len;
  88. len = fw->size - len;
  89. while (len) {
  90. if (len < 12) {
  91. dev_err(codec->dev, "%s short data block of %zd\n",
  92. name, len);
  93. goto err;
  94. }
  95. memcpy(&data32, data + 4, sizeof(data32));
  96. block_len = be32_to_cpu(data32);
  97. if (block_len + 8 > len) {
  98. dev_err(codec->dev, "%zd byte block longer than file\n",
  99. block_len);
  100. goto err;
  101. }
  102. if (block_len == 0) {
  103. dev_err(codec->dev, "Zero length block\n");
  104. goto err;
  105. }
  106. memcpy(&data32, data, sizeof(data32));
  107. data32 = be32_to_cpu(data32);
  108. switch ((data32 >> 24) & 0xff) {
  109. case WM_FW_BLOCK_INFO:
  110. /* Informational text */
  111. if (!check)
  112. break;
  113. str = kzalloc(block_len + 1, GFP_KERNEL);
  114. if (str) {
  115. memcpy(str, data + 8, block_len);
  116. dev_info(codec->dev, "%s: %s\n", name, str);
  117. kfree(str);
  118. } else {
  119. dev_err(codec->dev, "Out of memory\n");
  120. }
  121. break;
  122. case WM_FW_BLOCK_PM:
  123. case WM_FW_BLOCK_X:
  124. case WM_FW_BLOCK_Y:
  125. case WM_FW_BLOCK_Z:
  126. case WM_FW_BLOCK_I:
  127. case WM_FW_BLOCK_A:
  128. case WM_FW_BLOCK_C:
  129. dev_dbg(codec->dev, "%s: %zd bytes of %x@%x\n", name,
  130. block_len, (data32 >> 24) & 0xff,
  131. data32 & 0xffffff);
  132. if (check)
  133. break;
  134. data32 &= 0xffffff;
  135. wm8994_bulk_write(codec->control_data,
  136. data32 & 0xffffff,
  137. block_len / 2,
  138. (void *)(data + 8));
  139. break;
  140. default:
  141. dev_warn(codec->dev, "%s: unknown block type %d\n",
  142. name, (data32 >> 24) & 0xff);
  143. break;
  144. }
  145. /* Round up to the next 32 bit word */
  146. block_len += block_len % 4;
  147. data += block_len + 8;
  148. len -= block_len + 8;
  149. }
  150. if (!check) {
  151. dev_dbg(codec->dev, "%s: download done\n", name);
  152. wm8994->cur_fw = fw;
  153. } else {
  154. dev_info(codec->dev, "%s: got firmware\n", name);
  155. }
  156. goto ok;
  157. err:
  158. ret = -EINVAL;
  159. ok:
  160. if (!check) {
  161. snd_soc_write(codec, 0x900, 0x0);
  162. snd_soc_write(codec, 0x102, 0x0);
  163. }
  164. return ret;
  165. }
  166. static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
  167. {
  168. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  169. struct wm8994_pdata *pdata = wm8994->pdata;
  170. int i;
  171. /* If the DSP is already running then noop */
  172. if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  173. return;
  174. /* If we have MBC firmware download it */
  175. if (wm8994->mbc)
  176. wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
  177. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  178. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  179. /* If we've got user supplied MBC settings use them */
  180. if (pdata && pdata->num_mbc_cfgs) {
  181. struct wm8958_mbc_cfg *cfg
  182. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  183. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  184. snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
  185. cfg->coeff_regs[i]);
  186. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  187. snd_soc_write(codec,
  188. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  189. cfg->cutoff_regs[i]);
  190. }
  191. /* Run the DSP */
  192. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  193. WM8958_DSP2_RUNR);
  194. /* And we're off! */
  195. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  196. WM8958_MBC_ENA |
  197. WM8958_MBC_SEL_MASK,
  198. path << WM8958_MBC_SEL_SHIFT |
  199. WM8958_MBC_ENA);
  200. }
  201. static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
  202. {
  203. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  204. struct wm8994_pdata *pdata = wm8994->pdata;
  205. int i, ena;
  206. if (wm8994->mbc_vss)
  207. wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
  208. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  209. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  210. /* If we've got user supplied settings use them */
  211. if (pdata && pdata->num_mbc_cfgs) {
  212. struct wm8958_mbc_cfg *cfg
  213. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  214. for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
  215. snd_soc_write(codec, i + 0x2800,
  216. cfg->combined_regs[i]);
  217. }
  218. if (pdata && pdata->num_vss_cfgs) {
  219. struct wm8958_vss_cfg *cfg
  220. = &pdata->vss_cfgs[wm8994->vss_cfg];
  221. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  222. snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
  223. }
  224. if (pdata && pdata->num_vss_hpf_cfgs) {
  225. struct wm8958_vss_hpf_cfg *cfg
  226. = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
  227. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  228. snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
  229. }
  230. /* Run the DSP */
  231. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  232. WM8958_DSP2_RUNR);
  233. /* Enable the algorithms we've selected */
  234. ena = 0;
  235. if (wm8994->mbc_ena[path])
  236. ena |= 0x8;
  237. if (wm8994->hpf2_ena[path])
  238. ena |= 0x4;
  239. if (wm8994->hpf1_ena[path])
  240. ena |= 0x2;
  241. if (wm8994->vss_ena[path])
  242. ena |= 0x1;
  243. snd_soc_write(codec, 0x2201, ena);
  244. /* Switch the DSP into the data path */
  245. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  246. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  247. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  248. }
  249. static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
  250. {
  251. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  252. struct wm8994_pdata *pdata = wm8994->pdata;
  253. int i;
  254. wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
  255. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  256. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  257. /* If we've got user supplied settings use them */
  258. if (pdata && pdata->num_enh_eq_cfgs) {
  259. struct wm8958_enh_eq_cfg *cfg
  260. = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
  261. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  262. snd_soc_write(codec, i + 0x2200,
  263. cfg->regs[i]);
  264. }
  265. /* Run the DSP */
  266. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  267. WM8958_DSP2_RUNR);
  268. /* Switch the DSP into the data path */
  269. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  270. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  271. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  272. }
  273. static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
  274. {
  275. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  276. int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
  277. int ena, reg, aif;
  278. switch (path) {
  279. case 0:
  280. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  281. aif = 0;
  282. break;
  283. case 1:
  284. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  285. aif = 0;
  286. break;
  287. case 2:
  288. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  289. aif = 1;
  290. break;
  291. default:
  292. BUG();
  293. return;
  294. }
  295. /* Do we have both an active AIF and an active algorithm? */
  296. ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
  297. wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
  298. wm8994->enh_eq_ena[path];
  299. if (!pwr_reg)
  300. ena = 0;
  301. reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
  302. dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  303. path, wm8994->dsp_active, start, pwr_reg, reg);
  304. if (start && ena) {
  305. /* If the DSP is already running then noop */
  306. if (reg & WM8958_DSP2_ENA)
  307. return;
  308. /* If either AIFnCLK is not yet enabled postpone */
  309. if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  310. & WM8994_AIF1CLK_ENA_MASK) &&
  311. !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  312. & WM8994_AIF2CLK_ENA_MASK))
  313. return;
  314. /* Switch the clock over to the appropriate AIF */
  315. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  316. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  317. aif << WM8958_DSP2CLK_SRC_SHIFT |
  318. WM8958_DSP2CLK_ENA);
  319. if (wm8994->enh_eq_ena[path])
  320. wm8958_dsp_start_enh_eq(codec, path);
  321. else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
  322. wm8994->hpf2_ena[path])
  323. wm8958_dsp_start_vss(codec, path);
  324. else if (wm8994->mbc_ena[path])
  325. wm8958_dsp_start_mbc(codec, path);
  326. wm8994->dsp_active = path;
  327. dev_dbg(codec->dev, "DSP running in path %d\n", path);
  328. }
  329. if (!start && wm8994->dsp_active == path) {
  330. /* If the DSP is already stopped then noop */
  331. if (!(reg & WM8958_DSP2_ENA))
  332. return;
  333. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  334. WM8958_MBC_ENA, 0);
  335. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  336. WM8958_DSP2_STOP);
  337. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  338. WM8958_DSP2_ENA, 0);
  339. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  340. WM8958_DSP2CLK_ENA, 0);
  341. wm8994->dsp_active = -1;
  342. dev_dbg(codec->dev, "DSP stopped\n");
  343. }
  344. }
  345. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  346. struct snd_kcontrol *kcontrol, int event)
  347. {
  348. struct snd_soc_codec *codec = w->codec;
  349. int i;
  350. switch (event) {
  351. case SND_SOC_DAPM_POST_PMU:
  352. case SND_SOC_DAPM_PRE_PMU:
  353. for (i = 0; i < 3; i++)
  354. wm8958_dsp_apply(codec, i, 1);
  355. break;
  356. case SND_SOC_DAPM_POST_PMD:
  357. case SND_SOC_DAPM_PRE_PMD:
  358. for (i = 0; i < 3; i++)
  359. wm8958_dsp_apply(codec, i, 0);
  360. break;
  361. }
  362. return 0;
  363. }
  364. /* Check if DSP2 is in use on another AIF */
  365. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  366. {
  367. int i;
  368. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  369. if (i == aif)
  370. continue;
  371. if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
  372. wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
  373. return 1;
  374. }
  375. return 0;
  376. }
  377. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  378. struct snd_ctl_elem_value *ucontrol)
  379. {
  380. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  381. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  382. struct wm8994_pdata *pdata = wm8994->pdata;
  383. int value = ucontrol->value.integer.value[0];
  384. int reg;
  385. /* Don't allow on the fly reconfiguration */
  386. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  387. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  388. return -EBUSY;
  389. if (value >= pdata->num_mbc_cfgs)
  390. return -EINVAL;
  391. wm8994->mbc_cfg = value;
  392. return 0;
  393. }
  394. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  395. struct snd_ctl_elem_value *ucontrol)
  396. {
  397. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  398. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  399. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  400. return 0;
  401. }
  402. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  403. struct snd_ctl_elem_info *uinfo)
  404. {
  405. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  406. uinfo->count = 1;
  407. uinfo->value.integer.min = 0;
  408. uinfo->value.integer.max = 1;
  409. return 0;
  410. }
  411. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  412. struct snd_ctl_elem_value *ucontrol)
  413. {
  414. int mbc = kcontrol->private_value;
  415. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  416. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  417. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  418. return 0;
  419. }
  420. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  421. struct snd_ctl_elem_value *ucontrol)
  422. {
  423. int mbc = kcontrol->private_value;
  424. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  425. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  426. if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
  427. return 0;
  428. if (ucontrol->value.integer.value[0] > 1)
  429. return -EINVAL;
  430. if (wm8958_dsp2_busy(wm8994, mbc)) {
  431. dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
  432. return -EBUSY;
  433. }
  434. if (wm8994->enh_eq_ena[mbc])
  435. return -EBUSY;
  436. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  437. wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
  438. return 0;
  439. }
  440. #define WM8958_MBC_SWITCH(xname, xval) {\
  441. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  442. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  443. .info = wm8958_mbc_info, \
  444. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  445. .private_value = xval }
  446. static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
  447. struct snd_ctl_elem_value *ucontrol)
  448. {
  449. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  450. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  451. struct wm8994_pdata *pdata = wm8994->pdata;
  452. int value = ucontrol->value.integer.value[0];
  453. int reg;
  454. /* Don't allow on the fly reconfiguration */
  455. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  456. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  457. return -EBUSY;
  458. if (value >= pdata->num_vss_cfgs)
  459. return -EINVAL;
  460. wm8994->vss_cfg = value;
  461. return 0;
  462. }
  463. static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
  464. struct snd_ctl_elem_value *ucontrol)
  465. {
  466. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  467. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  468. ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
  469. return 0;
  470. }
  471. static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  472. struct snd_ctl_elem_value *ucontrol)
  473. {
  474. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  475. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  476. struct wm8994_pdata *pdata = wm8994->pdata;
  477. int value = ucontrol->value.integer.value[0];
  478. int reg;
  479. /* Don't allow on the fly reconfiguration */
  480. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  481. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  482. return -EBUSY;
  483. if (value >= pdata->num_vss_hpf_cfgs)
  484. return -EINVAL;
  485. wm8994->vss_hpf_cfg = value;
  486. return 0;
  487. }
  488. static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  489. struct snd_ctl_elem_value *ucontrol)
  490. {
  491. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  492. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  493. ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
  494. return 0;
  495. }
  496. static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
  497. struct snd_ctl_elem_info *uinfo)
  498. {
  499. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  500. uinfo->count = 1;
  501. uinfo->value.integer.min = 0;
  502. uinfo->value.integer.max = 1;
  503. return 0;
  504. }
  505. static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
  506. struct snd_ctl_elem_value *ucontrol)
  507. {
  508. int vss = kcontrol->private_value;
  509. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  510. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  511. ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
  512. return 0;
  513. }
  514. static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
  515. struct snd_ctl_elem_value *ucontrol)
  516. {
  517. int vss = kcontrol->private_value;
  518. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  519. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  520. if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
  521. return 0;
  522. if (ucontrol->value.integer.value[0] > 1)
  523. return -EINVAL;
  524. if (!wm8994->mbc_vss)
  525. return -ENODEV;
  526. if (wm8958_dsp2_busy(wm8994, vss)) {
  527. dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
  528. return -EBUSY;
  529. }
  530. if (wm8994->enh_eq_ena[vss])
  531. return -EBUSY;
  532. wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
  533. wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
  534. return 0;
  535. }
  536. #define WM8958_VSS_SWITCH(xname, xval) {\
  537. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  538. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  539. .info = wm8958_vss_info, \
  540. .get = wm8958_vss_get, .put = wm8958_vss_put, \
  541. .private_value = xval }
  542. static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
  543. struct snd_ctl_elem_info *uinfo)
  544. {
  545. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  546. uinfo->count = 1;
  547. uinfo->value.integer.min = 0;
  548. uinfo->value.integer.max = 1;
  549. return 0;
  550. }
  551. static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
  552. struct snd_ctl_elem_value *ucontrol)
  553. {
  554. int hpf = kcontrol->private_value;
  555. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  556. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  557. if (hpf < 3)
  558. ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
  559. else
  560. ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
  561. return 0;
  562. }
  563. static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
  564. struct snd_ctl_elem_value *ucontrol)
  565. {
  566. int hpf = kcontrol->private_value;
  567. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  568. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  569. if (hpf < 3) {
  570. if (wm8994->hpf1_ena[hpf % 3] ==
  571. ucontrol->value.integer.value[0])
  572. return 0;
  573. } else {
  574. if (wm8994->hpf2_ena[hpf % 3] ==
  575. ucontrol->value.integer.value[0])
  576. return 0;
  577. }
  578. if (ucontrol->value.integer.value[0] > 1)
  579. return -EINVAL;
  580. if (!wm8994->mbc_vss)
  581. return -ENODEV;
  582. if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
  583. dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
  584. return -EBUSY;
  585. }
  586. if (wm8994->enh_eq_ena[hpf % 3])
  587. return -EBUSY;
  588. if (hpf < 3)
  589. wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
  590. else
  591. wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
  592. wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
  593. return 0;
  594. }
  595. #define WM8958_HPF_SWITCH(xname, xval) {\
  596. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  597. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  598. .info = wm8958_hpf_info, \
  599. .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
  600. .private_value = xval }
  601. static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
  602. struct snd_ctl_elem_value *ucontrol)
  603. {
  604. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  605. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  606. struct wm8994_pdata *pdata = wm8994->pdata;
  607. int value = ucontrol->value.integer.value[0];
  608. int reg;
  609. /* Don't allow on the fly reconfiguration */
  610. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  611. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  612. return -EBUSY;
  613. if (value >= pdata->num_enh_eq_cfgs)
  614. return -EINVAL;
  615. wm8994->enh_eq_cfg = value;
  616. return 0;
  617. }
  618. static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
  619. struct snd_ctl_elem_value *ucontrol)
  620. {
  621. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  622. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  623. ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
  624. return 0;
  625. }
  626. static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
  627. struct snd_ctl_elem_info *uinfo)
  628. {
  629. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  630. uinfo->count = 1;
  631. uinfo->value.integer.min = 0;
  632. uinfo->value.integer.max = 1;
  633. return 0;
  634. }
  635. static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
  636. struct snd_ctl_elem_value *ucontrol)
  637. {
  638. int eq = kcontrol->private_value;
  639. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  640. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  641. ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
  642. return 0;
  643. }
  644. static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
  645. struct snd_ctl_elem_value *ucontrol)
  646. {
  647. int eq = kcontrol->private_value;
  648. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  649. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  650. if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
  651. return 0;
  652. if (ucontrol->value.integer.value[0] > 1)
  653. return -EINVAL;
  654. if (!wm8994->enh_eq)
  655. return -ENODEV;
  656. if (wm8958_dsp2_busy(wm8994, eq)) {
  657. dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
  658. return -EBUSY;
  659. }
  660. if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
  661. wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
  662. return -EBUSY;
  663. wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
  664. wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
  665. return 0;
  666. }
  667. #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
  668. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  669. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  670. .info = wm8958_enh_eq_info, \
  671. .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
  672. .private_value = xval }
  673. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  674. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  675. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  676. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  677. };
  678. static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
  679. WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
  680. WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
  681. WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
  682. WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
  683. WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
  684. WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
  685. WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
  686. WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
  687. WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
  688. };
  689. static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
  690. WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
  691. WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
  692. WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
  693. };
  694. static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
  695. {
  696. struct snd_soc_codec *codec = context;
  697. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  698. if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
  699. mutex_lock(&codec->mutex);
  700. wm8994->enh_eq = fw;
  701. mutex_unlock(&codec->mutex);
  702. }
  703. }
  704. static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
  705. {
  706. struct snd_soc_codec *codec = context;
  707. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  708. if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
  709. mutex_lock(&codec->mutex);
  710. wm8994->mbc_vss = fw;
  711. mutex_unlock(&codec->mutex);
  712. }
  713. /* We can't have more than one request outstanding at once so
  714. * we daisy chain.
  715. */
  716. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  717. "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
  718. codec, wm8958_enh_eq_loaded);
  719. }
  720. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  721. {
  722. struct snd_soc_codec *codec = context;
  723. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  724. if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
  725. return;
  726. mutex_lock(&codec->mutex);
  727. wm8994->mbc = fw;
  728. mutex_unlock(&codec->mutex);
  729. /* We can't have more than one request outstanding at once so
  730. * we daisy chain.
  731. */
  732. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  733. "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
  734. codec, wm8958_mbc_vss_loaded);
  735. }
  736. void wm8958_dsp2_init(struct snd_soc_codec *codec)
  737. {
  738. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  739. struct wm8994_pdata *pdata = wm8994->pdata;
  740. int ret, i;
  741. wm8994->dsp_active = -1;
  742. snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
  743. ARRAY_SIZE(wm8958_mbc_snd_controls));
  744. snd_soc_add_controls(codec, wm8958_vss_snd_controls,
  745. ARRAY_SIZE(wm8958_vss_snd_controls));
  746. snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
  747. ARRAY_SIZE(wm8958_enh_eq_snd_controls));
  748. /* We don't *require* firmware and don't want to delay boot */
  749. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  750. "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
  751. codec, wm8958_mbc_loaded);
  752. if (!pdata)
  753. return;
  754. if (pdata->num_mbc_cfgs) {
  755. struct snd_kcontrol_new control[] = {
  756. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  757. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  758. };
  759. /* We need an array of texts for the enum API */
  760. wm8994->mbc_texts = kmalloc(sizeof(char *)
  761. * pdata->num_mbc_cfgs, GFP_KERNEL);
  762. if (!wm8994->mbc_texts) {
  763. dev_err(wm8994->codec->dev,
  764. "Failed to allocate %d MBC config texts\n",
  765. pdata->num_mbc_cfgs);
  766. return;
  767. }
  768. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  769. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  770. wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
  771. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  772. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  773. if (ret != 0)
  774. dev_err(wm8994->codec->dev,
  775. "Failed to add MBC mode controls: %d\n", ret);
  776. }
  777. if (pdata->num_vss_cfgs) {
  778. struct snd_kcontrol_new control[] = {
  779. SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
  780. wm8958_get_vss_enum, wm8958_put_vss_enum),
  781. };
  782. /* We need an array of texts for the enum API */
  783. wm8994->vss_texts = kmalloc(sizeof(char *)
  784. * pdata->num_vss_cfgs, GFP_KERNEL);
  785. if (!wm8994->vss_texts) {
  786. dev_err(wm8994->codec->dev,
  787. "Failed to allocate %d VSS config texts\n",
  788. pdata->num_vss_cfgs);
  789. return;
  790. }
  791. for (i = 0; i < pdata->num_vss_cfgs; i++)
  792. wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
  793. wm8994->vss_enum.max = pdata->num_vss_cfgs;
  794. wm8994->vss_enum.texts = wm8994->vss_texts;
  795. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  796. if (ret != 0)
  797. dev_err(wm8994->codec->dev,
  798. "Failed to add VSS mode controls: %d\n", ret);
  799. }
  800. if (pdata->num_vss_hpf_cfgs) {
  801. struct snd_kcontrol_new control[] = {
  802. SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
  803. wm8958_get_vss_hpf_enum,
  804. wm8958_put_vss_hpf_enum),
  805. };
  806. /* We need an array of texts for the enum API */
  807. wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
  808. * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
  809. if (!wm8994->vss_hpf_texts) {
  810. dev_err(wm8994->codec->dev,
  811. "Failed to allocate %d VSS HPF config texts\n",
  812. pdata->num_vss_hpf_cfgs);
  813. return;
  814. }
  815. for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
  816. wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
  817. wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
  818. wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
  819. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  820. if (ret != 0)
  821. dev_err(wm8994->codec->dev,
  822. "Failed to add VSS HPFmode controls: %d\n",
  823. ret);
  824. }
  825. if (pdata->num_enh_eq_cfgs) {
  826. struct snd_kcontrol_new control[] = {
  827. SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
  828. wm8958_get_enh_eq_enum,
  829. wm8958_put_enh_eq_enum),
  830. };
  831. /* We need an array of texts for the enum API */
  832. wm8994->enh_eq_texts = kmalloc(sizeof(char *)
  833. * pdata->num_enh_eq_cfgs, GFP_KERNEL);
  834. if (!wm8994->enh_eq_texts) {
  835. dev_err(wm8994->codec->dev,
  836. "Failed to allocate %d enhanced EQ config texts\n",
  837. pdata->num_enh_eq_cfgs);
  838. return;
  839. }
  840. for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
  841. wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
  842. wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
  843. wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
  844. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  845. if (ret != 0)
  846. dev_err(wm8994->codec->dev,
  847. "Failed to add enhanced EQ controls: %d\n",
  848. ret);
  849. }
  850. }