qlcnic_init.c 42 KB

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  1. /*
  2. * Copyright (C) 2009 - QLogic Corporation.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called "COPYING".
  22. *
  23. */
  24. #include <linux/netdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/if_vlan.h>
  28. #include "qlcnic.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define QLCNIC_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
  35. #define crb_addr_transform(name) \
  36. (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
  37. QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
  38. #define QLCNIC_ADDR_ERROR (0xffffffff)
  39. static void
  40. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  41. struct qlcnic_host_rds_ring *rds_ring);
  42. static void crb_addr_transform_setup(void)
  43. {
  44. crb_addr_transform(XDMA);
  45. crb_addr_transform(TIMR);
  46. crb_addr_transform(SRE);
  47. crb_addr_transform(SQN3);
  48. crb_addr_transform(SQN2);
  49. crb_addr_transform(SQN1);
  50. crb_addr_transform(SQN0);
  51. crb_addr_transform(SQS3);
  52. crb_addr_transform(SQS2);
  53. crb_addr_transform(SQS1);
  54. crb_addr_transform(SQS0);
  55. crb_addr_transform(RPMX7);
  56. crb_addr_transform(RPMX6);
  57. crb_addr_transform(RPMX5);
  58. crb_addr_transform(RPMX4);
  59. crb_addr_transform(RPMX3);
  60. crb_addr_transform(RPMX2);
  61. crb_addr_transform(RPMX1);
  62. crb_addr_transform(RPMX0);
  63. crb_addr_transform(ROMUSB);
  64. crb_addr_transform(SN);
  65. crb_addr_transform(QMN);
  66. crb_addr_transform(QMS);
  67. crb_addr_transform(PGNI);
  68. crb_addr_transform(PGND);
  69. crb_addr_transform(PGN3);
  70. crb_addr_transform(PGN2);
  71. crb_addr_transform(PGN1);
  72. crb_addr_transform(PGN0);
  73. crb_addr_transform(PGSI);
  74. crb_addr_transform(PGSD);
  75. crb_addr_transform(PGS3);
  76. crb_addr_transform(PGS2);
  77. crb_addr_transform(PGS1);
  78. crb_addr_transform(PGS0);
  79. crb_addr_transform(PS);
  80. crb_addr_transform(PH);
  81. crb_addr_transform(NIU);
  82. crb_addr_transform(I2Q);
  83. crb_addr_transform(EG);
  84. crb_addr_transform(MN);
  85. crb_addr_transform(MS);
  86. crb_addr_transform(CAS2);
  87. crb_addr_transform(CAS1);
  88. crb_addr_transform(CAS0);
  89. crb_addr_transform(CAM);
  90. crb_addr_transform(C2C1);
  91. crb_addr_transform(C2C0);
  92. crb_addr_transform(SMB);
  93. crb_addr_transform(OCM0);
  94. crb_addr_transform(I2C0);
  95. }
  96. void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
  97. {
  98. struct qlcnic_recv_context *recv_ctx;
  99. struct qlcnic_host_rds_ring *rds_ring;
  100. struct qlcnic_rx_buffer *rx_buf;
  101. int i, ring;
  102. recv_ctx = &adapter->recv_ctx;
  103. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  104. rds_ring = &recv_ctx->rds_rings[ring];
  105. for (i = 0; i < rds_ring->num_desc; ++i) {
  106. rx_buf = &(rds_ring->rx_buf_arr[i]);
  107. if (rx_buf->skb == NULL)
  108. continue;
  109. pci_unmap_single(adapter->pdev,
  110. rx_buf->dma,
  111. rds_ring->dma_size,
  112. PCI_DMA_FROMDEVICE);
  113. dev_kfree_skb_any(rx_buf->skb);
  114. }
  115. }
  116. }
  117. void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter)
  118. {
  119. struct qlcnic_recv_context *recv_ctx;
  120. struct qlcnic_host_rds_ring *rds_ring;
  121. struct qlcnic_rx_buffer *rx_buf;
  122. int i, ring;
  123. recv_ctx = &adapter->recv_ctx;
  124. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  125. rds_ring = &recv_ctx->rds_rings[ring];
  126. INIT_LIST_HEAD(&rds_ring->free_list);
  127. rx_buf = rds_ring->rx_buf_arr;
  128. for (i = 0; i < rds_ring->num_desc; i++) {
  129. list_add_tail(&rx_buf->list,
  130. &rds_ring->free_list);
  131. rx_buf++;
  132. }
  133. }
  134. }
  135. void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
  136. {
  137. struct qlcnic_cmd_buffer *cmd_buf;
  138. struct qlcnic_skb_frag *buffrag;
  139. int i, j;
  140. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  141. cmd_buf = tx_ring->cmd_buf_arr;
  142. for (i = 0; i < tx_ring->num_desc; i++) {
  143. buffrag = cmd_buf->frag_array;
  144. if (buffrag->dma) {
  145. pci_unmap_single(adapter->pdev, buffrag->dma,
  146. buffrag->length, PCI_DMA_TODEVICE);
  147. buffrag->dma = 0ULL;
  148. }
  149. for (j = 0; j < cmd_buf->frag_count; j++) {
  150. buffrag++;
  151. if (buffrag->dma) {
  152. pci_unmap_page(adapter->pdev, buffrag->dma,
  153. buffrag->length,
  154. PCI_DMA_TODEVICE);
  155. buffrag->dma = 0ULL;
  156. }
  157. }
  158. if (cmd_buf->skb) {
  159. dev_kfree_skb_any(cmd_buf->skb);
  160. cmd_buf->skb = NULL;
  161. }
  162. cmd_buf++;
  163. }
  164. }
  165. void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
  166. {
  167. struct qlcnic_recv_context *recv_ctx;
  168. struct qlcnic_host_rds_ring *rds_ring;
  169. struct qlcnic_host_tx_ring *tx_ring;
  170. int ring;
  171. recv_ctx = &adapter->recv_ctx;
  172. if (recv_ctx->rds_rings == NULL)
  173. goto skip_rds;
  174. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  175. rds_ring = &recv_ctx->rds_rings[ring];
  176. vfree(rds_ring->rx_buf_arr);
  177. rds_ring->rx_buf_arr = NULL;
  178. }
  179. kfree(recv_ctx->rds_rings);
  180. skip_rds:
  181. if (adapter->tx_ring == NULL)
  182. return;
  183. tx_ring = adapter->tx_ring;
  184. vfree(tx_ring->cmd_buf_arr);
  185. tx_ring->cmd_buf_arr = NULL;
  186. kfree(adapter->tx_ring);
  187. adapter->tx_ring = NULL;
  188. }
  189. int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
  190. {
  191. struct qlcnic_recv_context *recv_ctx;
  192. struct qlcnic_host_rds_ring *rds_ring;
  193. struct qlcnic_host_sds_ring *sds_ring;
  194. struct qlcnic_host_tx_ring *tx_ring;
  195. struct qlcnic_rx_buffer *rx_buf;
  196. int ring, i, size;
  197. struct qlcnic_cmd_buffer *cmd_buf_arr;
  198. struct net_device *netdev = adapter->netdev;
  199. size = sizeof(struct qlcnic_host_tx_ring);
  200. tx_ring = kzalloc(size, GFP_KERNEL);
  201. if (tx_ring == NULL) {
  202. dev_err(&netdev->dev, "failed to allocate tx ring struct\n");
  203. return -ENOMEM;
  204. }
  205. adapter->tx_ring = tx_ring;
  206. tx_ring->num_desc = adapter->num_txd;
  207. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  208. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  209. if (cmd_buf_arr == NULL) {
  210. dev_err(&netdev->dev, "failed to allocate cmd buffer ring\n");
  211. goto err_out;
  212. }
  213. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  214. tx_ring->cmd_buf_arr = cmd_buf_arr;
  215. recv_ctx = &adapter->recv_ctx;
  216. size = adapter->max_rds_rings * sizeof(struct qlcnic_host_rds_ring);
  217. rds_ring = kzalloc(size, GFP_KERNEL);
  218. if (rds_ring == NULL) {
  219. dev_err(&netdev->dev, "failed to allocate rds ring struct\n");
  220. goto err_out;
  221. }
  222. recv_ctx->rds_rings = rds_ring;
  223. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  224. rds_ring = &recv_ctx->rds_rings[ring];
  225. switch (ring) {
  226. case RCV_RING_NORMAL:
  227. rds_ring->num_desc = adapter->num_rxd;
  228. rds_ring->dma_size = QLCNIC_P3_RX_BUF_MAX_LEN;
  229. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  230. break;
  231. case RCV_RING_JUMBO:
  232. rds_ring->num_desc = adapter->num_jumbo_rxd;
  233. rds_ring->dma_size =
  234. QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN;
  235. if (adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO)
  236. rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
  237. rds_ring->skb_size =
  238. rds_ring->dma_size + NET_IP_ALIGN;
  239. break;
  240. }
  241. rds_ring->rx_buf_arr = (struct qlcnic_rx_buffer *)
  242. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  243. if (rds_ring->rx_buf_arr == NULL) {
  244. dev_err(&netdev->dev, "Failed to allocate "
  245. "rx buffer ring %d\n", ring);
  246. goto err_out;
  247. }
  248. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  249. INIT_LIST_HEAD(&rds_ring->free_list);
  250. /*
  251. * Now go through all of them, set reference handles
  252. * and put them in the queues.
  253. */
  254. rx_buf = rds_ring->rx_buf_arr;
  255. for (i = 0; i < rds_ring->num_desc; i++) {
  256. list_add_tail(&rx_buf->list,
  257. &rds_ring->free_list);
  258. rx_buf->ref_handle = i;
  259. rx_buf++;
  260. }
  261. spin_lock_init(&rds_ring->lock);
  262. }
  263. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  264. sds_ring = &recv_ctx->sds_rings[ring];
  265. sds_ring->irq = adapter->msix_entries[ring].vector;
  266. sds_ring->adapter = adapter;
  267. sds_ring->num_desc = adapter->num_rxd;
  268. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  269. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  270. }
  271. return 0;
  272. err_out:
  273. qlcnic_free_sw_resources(adapter);
  274. return -ENOMEM;
  275. }
  276. /*
  277. * Utility to translate from internal Phantom CRB address
  278. * to external PCI CRB address.
  279. */
  280. static u32 qlcnic_decode_crb_addr(u32 addr)
  281. {
  282. int i;
  283. u32 base_addr, offset, pci_base;
  284. crb_addr_transform_setup();
  285. pci_base = QLCNIC_ADDR_ERROR;
  286. base_addr = addr & 0xfff00000;
  287. offset = addr & 0x000fffff;
  288. for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
  289. if (crb_addr_xform[i] == base_addr) {
  290. pci_base = i << 20;
  291. break;
  292. }
  293. }
  294. if (pci_base == QLCNIC_ADDR_ERROR)
  295. return pci_base;
  296. else
  297. return pci_base + offset;
  298. }
  299. #define QLCNIC_MAX_ROM_WAIT_USEC 100
  300. static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
  301. {
  302. long timeout = 0;
  303. long done = 0;
  304. cond_resched();
  305. while (done == 0) {
  306. done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
  307. done &= 2;
  308. if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
  309. dev_err(&adapter->pdev->dev,
  310. "Timeout reached waiting for rom done");
  311. return -EIO;
  312. }
  313. udelay(1);
  314. }
  315. return 0;
  316. }
  317. static int do_rom_fast_read(struct qlcnic_adapter *adapter,
  318. int addr, int *valp)
  319. {
  320. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
  321. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  322. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
  323. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  324. if (qlcnic_wait_rom_done(adapter)) {
  325. dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
  326. return -EIO;
  327. }
  328. /* reset abyte_cnt and dummy_byte_cnt */
  329. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
  330. udelay(10);
  331. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  332. *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
  333. return 0;
  334. }
  335. static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  336. u8 *bytes, size_t size)
  337. {
  338. int addridx;
  339. int ret = 0;
  340. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  341. int v;
  342. ret = do_rom_fast_read(adapter, addridx, &v);
  343. if (ret != 0)
  344. break;
  345. *(__le32 *)bytes = cpu_to_le32(v);
  346. bytes += 4;
  347. }
  348. return ret;
  349. }
  350. int
  351. qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  352. u8 *bytes, size_t size)
  353. {
  354. int ret;
  355. ret = qlcnic_rom_lock(adapter);
  356. if (ret < 0)
  357. return ret;
  358. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  359. qlcnic_rom_unlock(adapter);
  360. return ret;
  361. }
  362. int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp)
  363. {
  364. int ret;
  365. if (qlcnic_rom_lock(adapter) != 0)
  366. return -EIO;
  367. ret = do_rom_fast_read(adapter, addr, valp);
  368. qlcnic_rom_unlock(adapter);
  369. return ret;
  370. }
  371. int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
  372. {
  373. int addr, val;
  374. int i, n, init_delay;
  375. struct crb_addr_pair *buf;
  376. unsigned offset;
  377. u32 off;
  378. struct pci_dev *pdev = adapter->pdev;
  379. QLCWR32(adapter, CRB_CMDPEG_STATE, 0);
  380. QLCWR32(adapter, CRB_RCVPEG_STATE, 0);
  381. qlcnic_rom_lock(adapter);
  382. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  383. qlcnic_rom_unlock(adapter);
  384. /* Init HW CRB block */
  385. if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
  386. qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
  387. dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
  388. return -EIO;
  389. }
  390. offset = n & 0xffffU;
  391. n = (n >> 16) & 0xffffU;
  392. if (n >= 1024) {
  393. dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
  394. return -EIO;
  395. }
  396. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  397. if (buf == NULL) {
  398. dev_err(&pdev->dev, "Unable to calloc memory for rom read.\n");
  399. return -ENOMEM;
  400. }
  401. for (i = 0; i < n; i++) {
  402. if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  403. qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  404. kfree(buf);
  405. return -EIO;
  406. }
  407. buf[i].addr = addr;
  408. buf[i].data = val;
  409. }
  410. for (i = 0; i < n; i++) {
  411. off = qlcnic_decode_crb_addr(buf[i].addr);
  412. if (off == QLCNIC_ADDR_ERROR) {
  413. dev_err(&pdev->dev, "CRB init value out of range %x\n",
  414. buf[i].addr);
  415. continue;
  416. }
  417. off += QLCNIC_PCI_CRBSPACE;
  418. if (off & 1)
  419. continue;
  420. /* skipping cold reboot MAGIC */
  421. if (off == QLCNIC_CAM_RAM(0x1fc))
  422. continue;
  423. if (off == (QLCNIC_CRB_I2C0 + 0x1c))
  424. continue;
  425. if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
  426. continue;
  427. if (off == (ROMUSB_GLB + 0xa8))
  428. continue;
  429. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  430. continue;
  431. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  432. continue;
  433. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  434. continue;
  435. if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
  436. continue;
  437. /* skip the function enable register */
  438. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
  439. continue;
  440. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
  441. continue;
  442. if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
  443. continue;
  444. init_delay = 1;
  445. /* After writing this register, HW needs time for CRB */
  446. /* to quiet down (else crb_window returns 0xffffffff) */
  447. if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
  448. init_delay = 1000;
  449. QLCWR32(adapter, off, buf[i].data);
  450. msleep(init_delay);
  451. }
  452. kfree(buf);
  453. /* Initialize protocol process engine */
  454. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
  455. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
  456. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
  457. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
  458. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
  459. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
  460. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
  461. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
  462. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
  463. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
  464. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
  465. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0);
  466. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0);
  467. msleep(1);
  468. QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0);
  469. QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0);
  470. return 0;
  471. }
  472. int
  473. qlcnic_check_fw_status(struct qlcnic_adapter *adapter)
  474. {
  475. u32 heartbit, cmdpeg_state, ret = -EIO;
  476. int retries = QLCNIC_HEARTBEAT_RETRY_COUNT;
  477. adapter->heartbit = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  478. do {
  479. msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
  480. heartbit = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  481. if (heartbit != adapter->heartbit) {
  482. cmdpeg_state = QLCRD32(adapter, CRB_CMDPEG_STATE);
  483. /* Ensure peg states are initialized */
  484. if (cmdpeg_state == PHAN_INITIALIZE_COMPLETE ||
  485. cmdpeg_state == PHAN_INITIALIZE_ACK) {
  486. /* Complete firmware handshake */
  487. QLCWR32(adapter, CRB_CMDPEG_STATE,
  488. PHAN_INITIALIZE_ACK);
  489. ret = QLCNIC_RCODE_SUCCESS;
  490. break;
  491. }
  492. }
  493. } while (--retries);
  494. return ret;
  495. }
  496. int
  497. qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
  498. int timeo;
  499. u32 val;
  500. val = QLCRD32(adapter, QLCNIC_CRB_DEV_PARTITION_INFO);
  501. val = QLC_DEV_GET_DRV(val, adapter->portnum);
  502. if ((val & 0x3) != QLCNIC_TYPE_NIC) {
  503. dev_err(&adapter->pdev->dev,
  504. "Not an Ethernet NIC func=%u\n", val);
  505. return -EIO;
  506. }
  507. adapter->physical_port = (val >> 2);
  508. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
  509. timeo = QLCNIC_INIT_TIMEOUT_SECS;
  510. adapter->dev_init_timeo = timeo;
  511. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
  512. timeo = QLCNIC_RESET_TIMEOUT_SECS;
  513. adapter->reset_ack_timeo = timeo;
  514. return 0;
  515. }
  516. int
  517. qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
  518. {
  519. u32 ver = -1, min_ver;
  520. qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET, (int *)&ver);
  521. ver = QLCNIC_DECODE_VERSION(ver);
  522. min_ver = QLCNIC_MIN_FW_VERSION;
  523. if (ver < min_ver) {
  524. dev_err(&adapter->pdev->dev,
  525. "firmware version %d.%d.%d unsupported."
  526. "Min supported version %d.%d.%d\n",
  527. _major(ver), _minor(ver), _build(ver),
  528. _major(min_ver), _minor(min_ver), _build(min_ver));
  529. return -EINVAL;
  530. }
  531. return 0;
  532. }
  533. static int
  534. qlcnic_has_mn(struct qlcnic_adapter *adapter)
  535. {
  536. u32 capability;
  537. capability = 0;
  538. capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
  539. if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
  540. return 1;
  541. return 0;
  542. }
  543. static
  544. struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
  545. {
  546. u32 i;
  547. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  548. __le32 entries = cpu_to_le32(directory->num_entries);
  549. for (i = 0; i < entries; i++) {
  550. __le32 offs = cpu_to_le32(directory->findex) +
  551. (i * cpu_to_le32(directory->entry_size));
  552. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  553. if (tab_type == section)
  554. return (struct uni_table_desc *) &unirom[offs];
  555. }
  556. return NULL;
  557. }
  558. #define FILEHEADER_SIZE (14 * 4)
  559. static int
  560. qlcnic_validate_header(struct qlcnic_adapter *adapter)
  561. {
  562. const u8 *unirom = adapter->fw->data;
  563. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  564. __le32 fw_file_size = adapter->fw->size;
  565. __le32 entries;
  566. __le32 entry_size;
  567. __le32 tab_size;
  568. if (fw_file_size < FILEHEADER_SIZE)
  569. return -EINVAL;
  570. entries = cpu_to_le32(directory->num_entries);
  571. entry_size = cpu_to_le32(directory->entry_size);
  572. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  573. if (fw_file_size < tab_size)
  574. return -EINVAL;
  575. return 0;
  576. }
  577. static int
  578. qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
  579. {
  580. struct uni_table_desc *tab_desc;
  581. struct uni_data_desc *descr;
  582. const u8 *unirom = adapter->fw->data;
  583. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  584. QLCNIC_UNI_BOOTLD_IDX_OFF));
  585. __le32 offs;
  586. __le32 tab_size;
  587. __le32 data_size;
  588. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
  589. if (!tab_desc)
  590. return -EINVAL;
  591. tab_size = cpu_to_le32(tab_desc->findex) +
  592. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  593. if (adapter->fw->size < tab_size)
  594. return -EINVAL;
  595. offs = cpu_to_le32(tab_desc->findex) +
  596. (cpu_to_le32(tab_desc->entry_size) * (idx));
  597. descr = (struct uni_data_desc *)&unirom[offs];
  598. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  599. if (adapter->fw->size < data_size)
  600. return -EINVAL;
  601. return 0;
  602. }
  603. static int
  604. qlcnic_validate_fw(struct qlcnic_adapter *adapter)
  605. {
  606. struct uni_table_desc *tab_desc;
  607. struct uni_data_desc *descr;
  608. const u8 *unirom = adapter->fw->data;
  609. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  610. QLCNIC_UNI_FIRMWARE_IDX_OFF));
  611. __le32 offs;
  612. __le32 tab_size;
  613. __le32 data_size;
  614. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
  615. if (!tab_desc)
  616. return -EINVAL;
  617. tab_size = cpu_to_le32(tab_desc->findex) +
  618. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  619. if (adapter->fw->size < tab_size)
  620. return -EINVAL;
  621. offs = cpu_to_le32(tab_desc->findex) +
  622. (cpu_to_le32(tab_desc->entry_size) * (idx));
  623. descr = (struct uni_data_desc *)&unirom[offs];
  624. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  625. if (adapter->fw->size < data_size)
  626. return -EINVAL;
  627. return 0;
  628. }
  629. static int
  630. qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
  631. {
  632. struct uni_table_desc *ptab_descr;
  633. const u8 *unirom = adapter->fw->data;
  634. int mn_present = qlcnic_has_mn(adapter);
  635. __le32 entries;
  636. __le32 entry_size;
  637. __le32 tab_size;
  638. u32 i;
  639. ptab_descr = qlcnic_get_table_desc(unirom,
  640. QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
  641. if (!ptab_descr)
  642. return -EINVAL;
  643. entries = cpu_to_le32(ptab_descr->num_entries);
  644. entry_size = cpu_to_le32(ptab_descr->entry_size);
  645. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  646. if (adapter->fw->size < tab_size)
  647. return -EINVAL;
  648. nomn:
  649. for (i = 0; i < entries; i++) {
  650. __le32 flags, file_chiprev, offs;
  651. u8 chiprev = adapter->ahw.revision_id;
  652. u32 flagbit;
  653. offs = cpu_to_le32(ptab_descr->findex) +
  654. (i * cpu_to_le32(ptab_descr->entry_size));
  655. flags = cpu_to_le32(*((int *)&unirom[offs] +
  656. QLCNIC_UNI_FLAGS_OFF));
  657. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  658. QLCNIC_UNI_CHIP_REV_OFF));
  659. flagbit = mn_present ? 1 : 2;
  660. if ((chiprev == file_chiprev) &&
  661. ((1ULL << flagbit) & flags)) {
  662. adapter->file_prd_off = offs;
  663. return 0;
  664. }
  665. }
  666. if (mn_present) {
  667. mn_present = 0;
  668. goto nomn;
  669. }
  670. return -EINVAL;
  671. }
  672. static int
  673. qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
  674. {
  675. if (qlcnic_validate_header(adapter)) {
  676. dev_err(&adapter->pdev->dev,
  677. "unified image: header validation failed\n");
  678. return -EINVAL;
  679. }
  680. if (qlcnic_validate_product_offs(adapter)) {
  681. dev_err(&adapter->pdev->dev,
  682. "unified image: product validation failed\n");
  683. return -EINVAL;
  684. }
  685. if (qlcnic_validate_bootld(adapter)) {
  686. dev_err(&adapter->pdev->dev,
  687. "unified image: bootld validation failed\n");
  688. return -EINVAL;
  689. }
  690. if (qlcnic_validate_fw(adapter)) {
  691. dev_err(&adapter->pdev->dev,
  692. "unified image: firmware validation failed\n");
  693. return -EINVAL;
  694. }
  695. return 0;
  696. }
  697. static
  698. struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
  699. u32 section, u32 idx_offset)
  700. {
  701. const u8 *unirom = adapter->fw->data;
  702. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  703. idx_offset));
  704. struct uni_table_desc *tab_desc;
  705. __le32 offs;
  706. tab_desc = qlcnic_get_table_desc(unirom, section);
  707. if (tab_desc == NULL)
  708. return NULL;
  709. offs = cpu_to_le32(tab_desc->findex) +
  710. (cpu_to_le32(tab_desc->entry_size) * idx);
  711. return (struct uni_data_desc *)&unirom[offs];
  712. }
  713. static u8 *
  714. qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
  715. {
  716. u32 offs = QLCNIC_BOOTLD_START;
  717. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  718. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  719. QLCNIC_UNI_DIR_SECT_BOOTLD,
  720. QLCNIC_UNI_BOOTLD_IDX_OFF))->findex);
  721. return (u8 *)&adapter->fw->data[offs];
  722. }
  723. static u8 *
  724. qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
  725. {
  726. u32 offs = QLCNIC_IMAGE_START;
  727. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  728. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  729. QLCNIC_UNI_DIR_SECT_FW,
  730. QLCNIC_UNI_FIRMWARE_IDX_OFF))->findex);
  731. return (u8 *)&adapter->fw->data[offs];
  732. }
  733. static __le32
  734. qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
  735. {
  736. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  737. return cpu_to_le32((qlcnic_get_data_desc(adapter,
  738. QLCNIC_UNI_DIR_SECT_FW,
  739. QLCNIC_UNI_FIRMWARE_IDX_OFF))->size);
  740. else
  741. return cpu_to_le32(
  742. *(u32 *)&adapter->fw->data[QLCNIC_FW_SIZE_OFFSET]);
  743. }
  744. static __le32
  745. qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
  746. {
  747. struct uni_data_desc *fw_data_desc;
  748. const struct firmware *fw = adapter->fw;
  749. __le32 major, minor, sub;
  750. const u8 *ver_str;
  751. int i, ret;
  752. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  753. return cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET]);
  754. fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  755. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  756. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  757. cpu_to_le32(fw_data_desc->size) - 17;
  758. for (i = 0; i < 12; i++) {
  759. if (!strncmp(&ver_str[i], "REV=", 4)) {
  760. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  761. &major, &minor, &sub);
  762. if (ret != 3)
  763. return 0;
  764. else
  765. return major + (minor << 8) + (sub << 16);
  766. }
  767. }
  768. return 0;
  769. }
  770. static __le32
  771. qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
  772. {
  773. const struct firmware *fw = adapter->fw;
  774. __le32 bios_ver, prd_off = adapter->file_prd_off;
  775. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  776. return cpu_to_le32(
  777. *(u32 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET]);
  778. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  779. + QLCNIC_UNI_BIOS_VERSION_OFF));
  780. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
  781. }
  782. static void qlcnic_rom_lock_recovery(struct qlcnic_adapter *adapter)
  783. {
  784. if (qlcnic_pcie_sem_lock(adapter, 2, QLCNIC_ROM_LOCK_ID))
  785. dev_info(&adapter->pdev->dev, "Resetting rom_lock\n");
  786. qlcnic_pcie_sem_unlock(adapter, 2);
  787. }
  788. int
  789. qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
  790. {
  791. u32 val, version, major, minor, build;
  792. if (qlcnic_check_fw_status(adapter)) {
  793. qlcnic_rom_lock_recovery(adapter);
  794. return 1;
  795. }
  796. if (adapter->need_fw_reset)
  797. return 1;
  798. /* check if we have got newer or different file firmware */
  799. if (adapter->fw) {
  800. val = qlcnic_get_fw_version(adapter);
  801. version = QLCNIC_DECODE_VERSION(val);
  802. major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
  803. minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
  804. build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
  805. if (version > QLCNIC_VERSION_CODE(major, minor, build))
  806. return 1;
  807. }
  808. return 0;
  809. }
  810. static const char *fw_name[] = {
  811. QLCNIC_UNIFIED_ROMIMAGE_NAME,
  812. QLCNIC_FLASH_ROMIMAGE_NAME,
  813. };
  814. int
  815. qlcnic_load_firmware(struct qlcnic_adapter *adapter)
  816. {
  817. u64 *ptr64;
  818. u32 i, flashaddr, size;
  819. const struct firmware *fw = adapter->fw;
  820. struct pci_dev *pdev = adapter->pdev;
  821. dev_info(&pdev->dev, "loading firmware from %s\n",
  822. fw_name[adapter->fw_type]);
  823. if (fw) {
  824. __le64 data;
  825. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  826. ptr64 = (u64 *)qlcnic_get_bootld_offs(adapter);
  827. flashaddr = QLCNIC_BOOTLD_START;
  828. for (i = 0; i < size; i++) {
  829. data = cpu_to_le64(ptr64[i]);
  830. if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
  831. return -EIO;
  832. flashaddr += 8;
  833. }
  834. size = (__force u32)qlcnic_get_fw_size(adapter) / 8;
  835. ptr64 = (u64 *)qlcnic_get_fw_offs(adapter);
  836. flashaddr = QLCNIC_IMAGE_START;
  837. for (i = 0; i < size; i++) {
  838. data = cpu_to_le64(ptr64[i]);
  839. if (qlcnic_pci_mem_write_2M(adapter,
  840. flashaddr, data))
  841. return -EIO;
  842. flashaddr += 8;
  843. }
  844. size = (__force u32)qlcnic_get_fw_size(adapter) % 8;
  845. if (size) {
  846. data = cpu_to_le64(ptr64[i]);
  847. if (qlcnic_pci_mem_write_2M(adapter,
  848. flashaddr, data))
  849. return -EIO;
  850. }
  851. } else {
  852. u64 data;
  853. u32 hi, lo;
  854. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  855. flashaddr = QLCNIC_BOOTLD_START;
  856. for (i = 0; i < size; i++) {
  857. if (qlcnic_rom_fast_read(adapter,
  858. flashaddr, (int *)&lo) != 0)
  859. return -EIO;
  860. if (qlcnic_rom_fast_read(adapter,
  861. flashaddr + 4, (int *)&hi) != 0)
  862. return -EIO;
  863. data = (((u64)hi << 32) | lo);
  864. if (qlcnic_pci_mem_write_2M(adapter,
  865. flashaddr, data))
  866. return -EIO;
  867. flashaddr += 8;
  868. }
  869. }
  870. msleep(1);
  871. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
  872. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
  873. return 0;
  874. }
  875. static int
  876. qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
  877. {
  878. __le32 val;
  879. u32 ver, bios, min_size;
  880. struct pci_dev *pdev = adapter->pdev;
  881. const struct firmware *fw = adapter->fw;
  882. u8 fw_type = adapter->fw_type;
  883. if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
  884. if (qlcnic_validate_unified_romimage(adapter))
  885. return -EINVAL;
  886. min_size = QLCNIC_UNI_FW_MIN_SIZE;
  887. } else {
  888. val = cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
  889. if ((__force u32)val != QLCNIC_BDINFO_MAGIC)
  890. return -EINVAL;
  891. min_size = QLCNIC_FW_MIN_SIZE;
  892. }
  893. if (fw->size < min_size)
  894. return -EINVAL;
  895. val = qlcnic_get_fw_version(adapter);
  896. ver = QLCNIC_DECODE_VERSION(val);
  897. if (ver < QLCNIC_MIN_FW_VERSION) {
  898. dev_err(&pdev->dev,
  899. "%s: firmware version %d.%d.%d unsupported\n",
  900. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  901. return -EINVAL;
  902. }
  903. val = qlcnic_get_bios_version(adapter);
  904. qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
  905. if ((__force u32)val != bios) {
  906. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  907. fw_name[fw_type]);
  908. return -EINVAL;
  909. }
  910. /* check if flashed firmware is newer */
  911. if (qlcnic_rom_fast_read(adapter,
  912. QLCNIC_FW_VERSION_OFFSET, (int *)&val))
  913. return -EIO;
  914. val = QLCNIC_DECODE_VERSION(val);
  915. if (val > ver) {
  916. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  917. fw_name[fw_type]);
  918. return -EINVAL;
  919. }
  920. QLCWR32(adapter, QLCNIC_CAM_RAM(0x1fc), QLCNIC_BDINFO_MAGIC);
  921. return 0;
  922. }
  923. static void
  924. qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
  925. {
  926. u8 fw_type;
  927. switch (adapter->fw_type) {
  928. case QLCNIC_UNKNOWN_ROMIMAGE:
  929. fw_type = QLCNIC_UNIFIED_ROMIMAGE;
  930. break;
  931. case QLCNIC_UNIFIED_ROMIMAGE:
  932. default:
  933. fw_type = QLCNIC_FLASH_ROMIMAGE;
  934. break;
  935. }
  936. adapter->fw_type = fw_type;
  937. }
  938. void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
  939. {
  940. struct pci_dev *pdev = adapter->pdev;
  941. int rc;
  942. adapter->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
  943. next:
  944. qlcnic_get_next_fwtype(adapter);
  945. if (adapter->fw_type == QLCNIC_FLASH_ROMIMAGE) {
  946. adapter->fw = NULL;
  947. } else {
  948. rc = request_firmware(&adapter->fw,
  949. fw_name[adapter->fw_type], &pdev->dev);
  950. if (rc != 0)
  951. goto next;
  952. rc = qlcnic_validate_firmware(adapter);
  953. if (rc != 0) {
  954. release_firmware(adapter->fw);
  955. msleep(1);
  956. goto next;
  957. }
  958. }
  959. }
  960. void
  961. qlcnic_release_firmware(struct qlcnic_adapter *adapter)
  962. {
  963. if (adapter->fw)
  964. release_firmware(adapter->fw);
  965. adapter->fw = NULL;
  966. }
  967. static void
  968. qlcnic_handle_linkevent(struct qlcnic_adapter *adapter,
  969. struct qlcnic_fw_msg *msg)
  970. {
  971. u32 cable_OUI;
  972. u16 cable_len;
  973. u16 link_speed;
  974. u8 link_status, module, duplex, autoneg;
  975. struct net_device *netdev = adapter->netdev;
  976. adapter->has_link_events = 1;
  977. cable_OUI = msg->body[1] & 0xffffffff;
  978. cable_len = (msg->body[1] >> 32) & 0xffff;
  979. link_speed = (msg->body[1] >> 48) & 0xffff;
  980. link_status = msg->body[2] & 0xff;
  981. duplex = (msg->body[2] >> 16) & 0xff;
  982. autoneg = (msg->body[2] >> 24) & 0xff;
  983. module = (msg->body[2] >> 8) & 0xff;
  984. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE)
  985. dev_info(&netdev->dev, "unsupported cable: OUI 0x%x, "
  986. "length %d\n", cable_OUI, cable_len);
  987. else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN)
  988. dev_info(&netdev->dev, "unsupported cable length %d\n",
  989. cable_len);
  990. qlcnic_advert_link_change(adapter, link_status);
  991. if (duplex == LINKEVENT_FULL_DUPLEX)
  992. adapter->link_duplex = DUPLEX_FULL;
  993. else
  994. adapter->link_duplex = DUPLEX_HALF;
  995. adapter->module_type = module;
  996. adapter->link_autoneg = autoneg;
  997. adapter->link_speed = link_speed;
  998. }
  999. static void
  1000. qlcnic_handle_fw_message(int desc_cnt, int index,
  1001. struct qlcnic_host_sds_ring *sds_ring)
  1002. {
  1003. struct qlcnic_fw_msg msg;
  1004. struct status_desc *desc;
  1005. int i = 0, opcode;
  1006. while (desc_cnt > 0 && i < 8) {
  1007. desc = &sds_ring->desc_head[index];
  1008. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1009. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1010. index = get_next_index(index, sds_ring->num_desc);
  1011. desc_cnt--;
  1012. }
  1013. opcode = qlcnic_get_nic_msg_opcode(msg.body[0]);
  1014. switch (opcode) {
  1015. case QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1016. qlcnic_handle_linkevent(sds_ring->adapter, &msg);
  1017. break;
  1018. default:
  1019. break;
  1020. }
  1021. }
  1022. static int
  1023. qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter,
  1024. struct qlcnic_host_rds_ring *rds_ring,
  1025. struct qlcnic_rx_buffer *buffer)
  1026. {
  1027. struct sk_buff *skb;
  1028. dma_addr_t dma;
  1029. struct pci_dev *pdev = adapter->pdev;
  1030. skb = dev_alloc_skb(rds_ring->skb_size);
  1031. if (!skb) {
  1032. adapter->stats.skb_alloc_failure++;
  1033. return -ENOMEM;
  1034. }
  1035. skb_reserve(skb, 2);
  1036. dma = pci_map_single(pdev, skb->data,
  1037. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1038. if (pci_dma_mapping_error(pdev, dma)) {
  1039. adapter->stats.rx_dma_map_error++;
  1040. dev_kfree_skb_any(skb);
  1041. return -ENOMEM;
  1042. }
  1043. buffer->skb = skb;
  1044. buffer->dma = dma;
  1045. return 0;
  1046. }
  1047. static struct sk_buff *qlcnic_process_rxbuf(struct qlcnic_adapter *adapter,
  1048. struct qlcnic_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1049. {
  1050. struct qlcnic_rx_buffer *buffer;
  1051. struct sk_buff *skb;
  1052. buffer = &rds_ring->rx_buf_arr[index];
  1053. if (unlikely(buffer->skb == NULL)) {
  1054. WARN_ON(1);
  1055. return NULL;
  1056. }
  1057. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1058. PCI_DMA_FROMDEVICE);
  1059. skb = buffer->skb;
  1060. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1061. adapter->stats.csummed++;
  1062. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1063. } else {
  1064. skb->ip_summed = CHECKSUM_NONE;
  1065. }
  1066. skb->dev = adapter->netdev;
  1067. buffer->skb = NULL;
  1068. return skb;
  1069. }
  1070. static int
  1071. qlcnic_check_rx_tagging(struct qlcnic_adapter *adapter, struct sk_buff *skb)
  1072. {
  1073. u16 vlan_tag;
  1074. struct ethhdr *eth_hdr;
  1075. if (!__vlan_get_tag(skb, &vlan_tag)) {
  1076. if (vlan_tag == adapter->pvid) {
  1077. /* strip the tag from the packet and send it up */
  1078. eth_hdr = (struct ethhdr *) skb->data;
  1079. memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
  1080. skb_pull(skb, VLAN_HLEN);
  1081. return 0;
  1082. }
  1083. }
  1084. if (adapter->flags & QLCNIC_TAGGING_ENABLED)
  1085. return 0;
  1086. return -EIO;
  1087. }
  1088. static struct qlcnic_rx_buffer *
  1089. qlcnic_process_rcv(struct qlcnic_adapter *adapter,
  1090. struct qlcnic_host_sds_ring *sds_ring,
  1091. int ring, u64 sts_data0)
  1092. {
  1093. struct net_device *netdev = adapter->netdev;
  1094. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1095. struct qlcnic_rx_buffer *buffer;
  1096. struct sk_buff *skb;
  1097. struct qlcnic_host_rds_ring *rds_ring;
  1098. int index, length, cksum, pkt_offset;
  1099. if (unlikely(ring >= adapter->max_rds_rings))
  1100. return NULL;
  1101. rds_ring = &recv_ctx->rds_rings[ring];
  1102. index = qlcnic_get_sts_refhandle(sts_data0);
  1103. if (unlikely(index >= rds_ring->num_desc))
  1104. return NULL;
  1105. buffer = &rds_ring->rx_buf_arr[index];
  1106. length = qlcnic_get_sts_totallength(sts_data0);
  1107. cksum = qlcnic_get_sts_status(sts_data0);
  1108. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1109. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1110. if (!skb)
  1111. return buffer;
  1112. if (length > rds_ring->skb_size)
  1113. skb_put(skb, rds_ring->skb_size);
  1114. else
  1115. skb_put(skb, length);
  1116. if (pkt_offset)
  1117. skb_pull(skb, pkt_offset);
  1118. skb->truesize = skb->len + sizeof(struct sk_buff);
  1119. if (unlikely(adapter->pvid)) {
  1120. if (qlcnic_check_rx_tagging(adapter, skb)) {
  1121. adapter->stats.rxdropped++;
  1122. dev_kfree_skb_any(skb);
  1123. return buffer;
  1124. }
  1125. }
  1126. skb->protocol = eth_type_trans(skb, netdev);
  1127. napi_gro_receive(&sds_ring->napi, skb);
  1128. adapter->stats.rx_pkts++;
  1129. adapter->stats.rxbytes += length;
  1130. return buffer;
  1131. }
  1132. #define QLC_TCP_HDR_SIZE 20
  1133. #define QLC_TCP_TS_OPTION_SIZE 12
  1134. #define QLC_TCP_TS_HDR_SIZE (QLC_TCP_HDR_SIZE + QLC_TCP_TS_OPTION_SIZE)
  1135. static struct qlcnic_rx_buffer *
  1136. qlcnic_process_lro(struct qlcnic_adapter *adapter,
  1137. struct qlcnic_host_sds_ring *sds_ring,
  1138. int ring, u64 sts_data0, u64 sts_data1)
  1139. {
  1140. struct net_device *netdev = adapter->netdev;
  1141. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1142. struct qlcnic_rx_buffer *buffer;
  1143. struct sk_buff *skb;
  1144. struct qlcnic_host_rds_ring *rds_ring;
  1145. struct iphdr *iph;
  1146. struct tcphdr *th;
  1147. bool push, timestamp;
  1148. int l2_hdr_offset, l4_hdr_offset;
  1149. int index;
  1150. u16 lro_length, length, data_offset;
  1151. u32 seq_number;
  1152. if (unlikely(ring > adapter->max_rds_rings))
  1153. return NULL;
  1154. rds_ring = &recv_ctx->rds_rings[ring];
  1155. index = qlcnic_get_lro_sts_refhandle(sts_data0);
  1156. if (unlikely(index > rds_ring->num_desc))
  1157. return NULL;
  1158. buffer = &rds_ring->rx_buf_arr[index];
  1159. timestamp = qlcnic_get_lro_sts_timestamp(sts_data0);
  1160. lro_length = qlcnic_get_lro_sts_length(sts_data0);
  1161. l2_hdr_offset = qlcnic_get_lro_sts_l2_hdr_offset(sts_data0);
  1162. l4_hdr_offset = qlcnic_get_lro_sts_l4_hdr_offset(sts_data0);
  1163. push = qlcnic_get_lro_sts_push_flag(sts_data0);
  1164. seq_number = qlcnic_get_lro_sts_seq_number(sts_data1);
  1165. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1166. if (!skb)
  1167. return buffer;
  1168. if (timestamp)
  1169. data_offset = l4_hdr_offset + QLC_TCP_TS_HDR_SIZE;
  1170. else
  1171. data_offset = l4_hdr_offset + QLC_TCP_HDR_SIZE;
  1172. skb_put(skb, lro_length + data_offset);
  1173. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1174. skb_pull(skb, l2_hdr_offset);
  1175. if (unlikely(adapter->pvid)) {
  1176. if (qlcnic_check_rx_tagging(adapter, skb)) {
  1177. adapter->stats.rxdropped++;
  1178. dev_kfree_skb_any(skb);
  1179. return buffer;
  1180. }
  1181. }
  1182. skb->protocol = eth_type_trans(skb, netdev);
  1183. iph = (struct iphdr *)skb->data;
  1184. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1185. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1186. iph->tot_len = htons(length);
  1187. iph->check = 0;
  1188. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1189. th->psh = push;
  1190. th->seq = htonl(seq_number);
  1191. length = skb->len;
  1192. netif_receive_skb(skb);
  1193. adapter->stats.lro_pkts++;
  1194. adapter->stats.lrobytes += length;
  1195. return buffer;
  1196. }
  1197. int
  1198. qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max)
  1199. {
  1200. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1201. struct list_head *cur;
  1202. struct status_desc *desc;
  1203. struct qlcnic_rx_buffer *rxbuf;
  1204. u64 sts_data0, sts_data1;
  1205. int count = 0;
  1206. int opcode, ring, desc_cnt;
  1207. u32 consumer = sds_ring->consumer;
  1208. while (count < max) {
  1209. desc = &sds_ring->desc_head[consumer];
  1210. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1211. if (!(sts_data0 & STATUS_OWNER_HOST))
  1212. break;
  1213. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1214. opcode = qlcnic_get_sts_opcode(sts_data0);
  1215. switch (opcode) {
  1216. case QLCNIC_RXPKT_DESC:
  1217. case QLCNIC_OLD_RXPKT_DESC:
  1218. case QLCNIC_SYN_OFFLOAD:
  1219. ring = qlcnic_get_sts_type(sts_data0);
  1220. rxbuf = qlcnic_process_rcv(adapter, sds_ring,
  1221. ring, sts_data0);
  1222. break;
  1223. case QLCNIC_LRO_DESC:
  1224. ring = qlcnic_get_lro_sts_type(sts_data0);
  1225. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1226. rxbuf = qlcnic_process_lro(adapter, sds_ring,
  1227. ring, sts_data0, sts_data1);
  1228. break;
  1229. case QLCNIC_RESPONSE_DESC:
  1230. qlcnic_handle_fw_message(desc_cnt, consumer, sds_ring);
  1231. default:
  1232. goto skip;
  1233. }
  1234. WARN_ON(desc_cnt > 1);
  1235. if (likely(rxbuf))
  1236. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1237. else
  1238. adapter->stats.null_rxbuf++;
  1239. skip:
  1240. for (; desc_cnt > 0; desc_cnt--) {
  1241. desc = &sds_ring->desc_head[consumer];
  1242. desc->status_desc_data[0] =
  1243. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1244. consumer = get_next_index(consumer, sds_ring->num_desc);
  1245. }
  1246. count++;
  1247. }
  1248. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1249. struct qlcnic_host_rds_ring *rds_ring =
  1250. &adapter->recv_ctx.rds_rings[ring];
  1251. if (!list_empty(&sds_ring->free_list[ring])) {
  1252. list_for_each(cur, &sds_ring->free_list[ring]) {
  1253. rxbuf = list_entry(cur,
  1254. struct qlcnic_rx_buffer, list);
  1255. qlcnic_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1256. }
  1257. spin_lock(&rds_ring->lock);
  1258. list_splice_tail_init(&sds_ring->free_list[ring],
  1259. &rds_ring->free_list);
  1260. spin_unlock(&rds_ring->lock);
  1261. }
  1262. qlcnic_post_rx_buffers_nodb(adapter, rds_ring);
  1263. }
  1264. if (count) {
  1265. sds_ring->consumer = consumer;
  1266. writel(consumer, sds_ring->crb_sts_consumer);
  1267. }
  1268. return count;
  1269. }
  1270. void
  1271. qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
  1272. struct qlcnic_host_rds_ring *rds_ring)
  1273. {
  1274. struct rcv_desc *pdesc;
  1275. struct qlcnic_rx_buffer *buffer;
  1276. int producer, count = 0;
  1277. struct list_head *head;
  1278. producer = rds_ring->producer;
  1279. head = &rds_ring->free_list;
  1280. while (!list_empty(head)) {
  1281. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1282. if (!buffer->skb) {
  1283. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1284. break;
  1285. }
  1286. count++;
  1287. list_del(&buffer->list);
  1288. /* make a rcv descriptor */
  1289. pdesc = &rds_ring->desc_head[producer];
  1290. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1291. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1292. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1293. producer = get_next_index(producer, rds_ring->num_desc);
  1294. }
  1295. if (count) {
  1296. rds_ring->producer = producer;
  1297. writel((producer-1) & (rds_ring->num_desc-1),
  1298. rds_ring->crb_rcv_producer);
  1299. }
  1300. }
  1301. static void
  1302. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  1303. struct qlcnic_host_rds_ring *rds_ring)
  1304. {
  1305. struct rcv_desc *pdesc;
  1306. struct qlcnic_rx_buffer *buffer;
  1307. int producer, count = 0;
  1308. struct list_head *head;
  1309. if (!spin_trylock(&rds_ring->lock))
  1310. return;
  1311. producer = rds_ring->producer;
  1312. head = &rds_ring->free_list;
  1313. while (!list_empty(head)) {
  1314. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1315. if (!buffer->skb) {
  1316. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1317. break;
  1318. }
  1319. count++;
  1320. list_del(&buffer->list);
  1321. /* make a rcv descriptor */
  1322. pdesc = &rds_ring->desc_head[producer];
  1323. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1324. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1325. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1326. producer = get_next_index(producer, rds_ring->num_desc);
  1327. }
  1328. if (count) {
  1329. rds_ring->producer = producer;
  1330. writel((producer - 1) & (rds_ring->num_desc - 1),
  1331. rds_ring->crb_rcv_producer);
  1332. }
  1333. spin_unlock(&rds_ring->lock);
  1334. }
  1335. static struct qlcnic_rx_buffer *
  1336. qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
  1337. struct qlcnic_host_sds_ring *sds_ring,
  1338. int ring, u64 sts_data0)
  1339. {
  1340. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1341. struct qlcnic_rx_buffer *buffer;
  1342. struct sk_buff *skb;
  1343. struct qlcnic_host_rds_ring *rds_ring;
  1344. int index, length, cksum, pkt_offset;
  1345. if (unlikely(ring >= adapter->max_rds_rings))
  1346. return NULL;
  1347. rds_ring = &recv_ctx->rds_rings[ring];
  1348. index = qlcnic_get_sts_refhandle(sts_data0);
  1349. if (unlikely(index >= rds_ring->num_desc))
  1350. return NULL;
  1351. buffer = &rds_ring->rx_buf_arr[index];
  1352. length = qlcnic_get_sts_totallength(sts_data0);
  1353. cksum = qlcnic_get_sts_status(sts_data0);
  1354. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1355. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1356. if (!skb)
  1357. return buffer;
  1358. skb_put(skb, rds_ring->skb_size);
  1359. if (pkt_offset)
  1360. skb_pull(skb, pkt_offset);
  1361. skb->truesize = skb->len + sizeof(struct sk_buff);
  1362. if (!qlcnic_check_loopback_buff(skb->data))
  1363. adapter->diag_cnt++;
  1364. dev_kfree_skb_any(skb);
  1365. adapter->stats.rx_pkts++;
  1366. adapter->stats.rxbytes += length;
  1367. return buffer;
  1368. }
  1369. void
  1370. qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
  1371. {
  1372. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1373. struct status_desc *desc;
  1374. struct qlcnic_rx_buffer *rxbuf;
  1375. u64 sts_data0;
  1376. int opcode, ring, desc_cnt;
  1377. u32 consumer = sds_ring->consumer;
  1378. desc = &sds_ring->desc_head[consumer];
  1379. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1380. if (!(sts_data0 & STATUS_OWNER_HOST))
  1381. return;
  1382. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1383. opcode = qlcnic_get_sts_opcode(sts_data0);
  1384. ring = qlcnic_get_sts_type(sts_data0);
  1385. rxbuf = qlcnic_process_rcv_diag(adapter, sds_ring,
  1386. ring, sts_data0);
  1387. desc->status_desc_data[0] = cpu_to_le64(STATUS_OWNER_PHANTOM);
  1388. consumer = get_next_index(consumer, sds_ring->num_desc);
  1389. sds_ring->consumer = consumer;
  1390. writel(consumer, sds_ring->crb_sts_consumer);
  1391. }
  1392. void
  1393. qlcnic_fetch_mac(struct qlcnic_adapter *adapter, u32 off1, u32 off2,
  1394. u8 alt_mac, u8 *mac)
  1395. {
  1396. u32 mac_low, mac_high;
  1397. int i;
  1398. mac_low = QLCRD32(adapter, off1);
  1399. mac_high = QLCRD32(adapter, off2);
  1400. if (alt_mac) {
  1401. mac_low |= (mac_low >> 16) | (mac_high << 16);
  1402. mac_high >>= 16;
  1403. }
  1404. for (i = 0; i < 2; i++)
  1405. mac[i] = (u8)(mac_high >> ((1 - i) * 8));
  1406. for (i = 2; i < 6; i++)
  1407. mac[i] = (u8)(mac_low >> ((5 - i) * 8));
  1408. }