pxa2xx-i2s.c 7.6 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <linux/platform_device.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc.h>
  23. #include <mach/hardware.h>
  24. #include <mach/pxa-regs.h>
  25. #include <mach/pxa2xx-gpio.h>
  26. #include <mach/audio.h>
  27. #include "pxa2xx-pcm.h"
  28. #include "pxa2xx-i2s.h"
  29. struct pxa_i2s_port {
  30. u32 sadiv;
  31. u32 sacr0;
  32. u32 sacr1;
  33. u32 saimr;
  34. int master;
  35. u32 fmt;
  36. };
  37. static struct pxa_i2s_port pxa_i2s;
  38. static struct clk *clk_i2s;
  39. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  40. .name = "I2S PCM Stereo out",
  41. .dev_addr = __PREG(SADR),
  42. .drcmr = &DRCMRTXSADR,
  43. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  44. DCMD_BURST32 | DCMD_WIDTH4,
  45. };
  46. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  47. .name = "I2S PCM Stereo in",
  48. .dev_addr = __PREG(SADR),
  49. .drcmr = &DRCMRRXSADR,
  50. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  51. DCMD_BURST32 | DCMD_WIDTH4,
  52. };
  53. static struct pxa2xx_gpio gpio_bus[] = {
  54. { /* I2S SoC Slave */
  55. .rx = GPIO29_SDATA_IN_I2S_MD,
  56. .tx = GPIO30_SDATA_OUT_I2S_MD,
  57. .clk = GPIO28_BITCLK_IN_I2S_MD,
  58. .frm = GPIO31_SYNC_I2S_MD,
  59. },
  60. { /* I2S SoC Master */
  61. .rx = GPIO29_SDATA_IN_I2S_MD,
  62. .tx = GPIO30_SDATA_OUT_I2S_MD,
  63. .clk = GPIO28_BITCLK_OUT_I2S_MD,
  64. .frm = GPIO31_SYNC_I2S_MD,
  65. },
  66. };
  67. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
  68. {
  69. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  70. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  71. if (IS_ERR(clk_i2s))
  72. return PTR_ERR(clk_i2s);
  73. if (!cpu_dai->active) {
  74. SACR0 |= SACR0_RST;
  75. SACR0 = 0;
  76. }
  77. return 0;
  78. }
  79. /* wait for I2S controller to be ready */
  80. static int pxa_i2s_wait(void)
  81. {
  82. int i;
  83. /* flush the Rx FIFO */
  84. for(i = 0; i < 16; i++)
  85. SADR;
  86. return 0;
  87. }
  88. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  89. unsigned int fmt)
  90. {
  91. /* interface format */
  92. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  93. case SND_SOC_DAIFMT_I2S:
  94. pxa_i2s.fmt = 0;
  95. break;
  96. case SND_SOC_DAIFMT_LEFT_J:
  97. pxa_i2s.fmt = SACR1_AMSL;
  98. break;
  99. }
  100. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  101. case SND_SOC_DAIFMT_CBS_CFS:
  102. pxa_i2s.master = 1;
  103. break;
  104. case SND_SOC_DAIFMT_CBM_CFS:
  105. pxa_i2s.master = 0;
  106. break;
  107. default:
  108. break;
  109. }
  110. return 0;
  111. }
  112. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  113. int clk_id, unsigned int freq, int dir)
  114. {
  115. if (clk_id != PXA2XX_I2S_SYSCLK)
  116. return -ENODEV;
  117. if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
  118. pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
  119. return 0;
  120. }
  121. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  122. struct snd_pcm_hw_params *params)
  123. {
  124. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  125. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  126. pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
  127. pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
  128. pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
  129. pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
  130. BUG_ON(IS_ERR(clk_i2s));
  131. clk_enable(clk_i2s);
  132. pxa_i2s_wait();
  133. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  134. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
  135. else
  136. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
  137. /* is port used by another stream */
  138. if (!(SACR0 & SACR0_ENB)) {
  139. SACR0 = 0;
  140. SACR1 = 0;
  141. if (pxa_i2s.master)
  142. SACR0 |= SACR0_BCKD;
  143. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  144. SACR1 |= pxa_i2s.fmt;
  145. }
  146. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  147. SAIMR |= SAIMR_TFS;
  148. else
  149. SAIMR |= SAIMR_RFS;
  150. switch (params_rate(params)) {
  151. case 8000:
  152. SADIV = 0x48;
  153. break;
  154. case 11025:
  155. SADIV = 0x34;
  156. break;
  157. case 16000:
  158. SADIV = 0x24;
  159. break;
  160. case 22050:
  161. SADIV = 0x1a;
  162. break;
  163. case 44100:
  164. SADIV = 0xd;
  165. break;
  166. case 48000:
  167. SADIV = 0xc;
  168. break;
  169. case 96000: /* not in manual and possibly slightly inaccurate */
  170. SADIV = 0x6;
  171. break;
  172. }
  173. return 0;
  174. }
  175. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  176. {
  177. int ret = 0;
  178. switch (cmd) {
  179. case SNDRV_PCM_TRIGGER_START:
  180. SACR0 |= SACR0_ENB;
  181. break;
  182. case SNDRV_PCM_TRIGGER_RESUME:
  183. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  184. case SNDRV_PCM_TRIGGER_STOP:
  185. case SNDRV_PCM_TRIGGER_SUSPEND:
  186. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  187. break;
  188. default:
  189. ret = -EINVAL;
  190. }
  191. return ret;
  192. }
  193. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
  194. {
  195. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  196. SACR1 |= SACR1_DRPL;
  197. SAIMR &= ~SAIMR_TFS;
  198. } else {
  199. SACR1 |= SACR1_DREC;
  200. SAIMR &= ~SAIMR_RFS;
  201. }
  202. if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
  203. SACR0 &= ~SACR0_ENB;
  204. pxa_i2s_wait();
  205. clk_disable(clk_i2s);
  206. }
  207. clk_put(clk_i2s);
  208. }
  209. #ifdef CONFIG_PM
  210. static int pxa2xx_i2s_suspend(struct platform_device *dev,
  211. struct snd_soc_dai *dai)
  212. {
  213. if (!dai->active)
  214. return 0;
  215. /* store registers */
  216. pxa_i2s.sacr0 = SACR0;
  217. pxa_i2s.sacr1 = SACR1;
  218. pxa_i2s.saimr = SAIMR;
  219. pxa_i2s.sadiv = SADIV;
  220. /* deactivate link */
  221. SACR0 &= ~SACR0_ENB;
  222. pxa_i2s_wait();
  223. return 0;
  224. }
  225. static int pxa2xx_i2s_resume(struct platform_device *pdev,
  226. struct snd_soc_dai *dai)
  227. {
  228. if (!dai->active)
  229. return 0;
  230. pxa_i2s_wait();
  231. SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
  232. SACR1 = pxa_i2s.sacr1;
  233. SAIMR = pxa_i2s.saimr;
  234. SADIV = pxa_i2s.sadiv;
  235. SACR0 |= SACR0_ENB;
  236. return 0;
  237. }
  238. #else
  239. #define pxa2xx_i2s_suspend NULL
  240. #define pxa2xx_i2s_resume NULL
  241. #endif
  242. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  243. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  244. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  245. struct snd_soc_dai pxa_i2s_dai = {
  246. .name = "pxa2xx-i2s",
  247. .id = 0,
  248. .type = SND_SOC_DAI_I2S,
  249. .suspend = pxa2xx_i2s_suspend,
  250. .resume = pxa2xx_i2s_resume,
  251. .playback = {
  252. .channels_min = 2,
  253. .channels_max = 2,
  254. .rates = PXA2XX_I2S_RATES,
  255. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  256. .capture = {
  257. .channels_min = 2,
  258. .channels_max = 2,
  259. .rates = PXA2XX_I2S_RATES,
  260. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  261. .ops = {
  262. .startup = pxa2xx_i2s_startup,
  263. .shutdown = pxa2xx_i2s_shutdown,
  264. .trigger = pxa2xx_i2s_trigger,
  265. .hw_params = pxa2xx_i2s_hw_params,},
  266. .dai_ops = {
  267. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  268. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  269. },
  270. };
  271. EXPORT_SYMBOL_GPL(pxa_i2s_dai);
  272. static int pxa2xx_i2s_probe(struct platform_device *dev)
  273. {
  274. clk_i2s = clk_get(&dev->dev, "I2SCLK");
  275. return IS_ERR(clk_i2s) ? PTR_ERR(clk_i2s) : 0;
  276. }
  277. static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
  278. {
  279. clk_put(clk_i2s);
  280. clk_i2s = ERR_PTR(-ENOENT);
  281. return 0;
  282. }
  283. static struct platform_driver pxa2xx_i2s_driver = {
  284. .probe = pxa2xx_i2s_probe,
  285. .remove = __devexit_p(pxa2xx_i2s_remove),
  286. .driver = {
  287. .name = "pxa2xx-i2s",
  288. .owner = THIS_MODULE,
  289. },
  290. };
  291. static int __init pxa2xx_i2s_init(void)
  292. {
  293. if (cpu_is_pxa27x())
  294. gpio_bus[1].sys = GPIO113_I2S_SYSCLK_MD;
  295. else
  296. gpio_bus[1].sys = GPIO32_SYSCLK_I2S_MD;
  297. clk_i2s = ERR_PTR(-ENOENT);
  298. return platform_driver_register(&pxa2xx_i2s_driver);
  299. }
  300. static void __exit pxa2xx_i2s_exit(void)
  301. {
  302. platform_driver_unregister(&pxa2xx_i2s_driver);
  303. }
  304. module_init(pxa2xx_i2s_init);
  305. module_exit(pxa2xx_i2s_exit);
  306. /* Module information */
  307. MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
  308. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  309. MODULE_LICENSE("GPL");