qlcnic_ctx.c 38 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416
  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
  40. };
  41. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  42. {
  43. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  44. (0xcafe << 16);
  45. }
  46. /* Allocate mailbox registers */
  47. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  48. struct qlcnic_adapter *adapter, u32 type)
  49. {
  50. int i, size;
  51. const struct qlcnic_mailbox_metadata *mbx_tbl;
  52. mbx_tbl = qlcnic_mbx_tbl;
  53. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  54. for (i = 0; i < size; i++) {
  55. if (type == mbx_tbl[i].cmd) {
  56. mbx->req.num = mbx_tbl[i].in_args;
  57. mbx->rsp.num = mbx_tbl[i].out_args;
  58. mbx->req.arg = kcalloc(mbx->req.num,
  59. sizeof(u32), GFP_ATOMIC);
  60. if (!mbx->req.arg)
  61. return -ENOMEM;
  62. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  63. sizeof(u32), GFP_ATOMIC);
  64. if (!mbx->rsp.arg) {
  65. kfree(mbx->req.arg);
  66. mbx->req.arg = NULL;
  67. return -ENOMEM;
  68. }
  69. memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
  70. memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
  71. mbx->req.arg[0] = type;
  72. break;
  73. }
  74. }
  75. return 0;
  76. }
  77. /* Free up mailbox registers */
  78. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  79. {
  80. kfree(cmd->req.arg);
  81. cmd->req.arg = NULL;
  82. kfree(cmd->rsp.arg);
  83. cmd->rsp.arg = NULL;
  84. }
  85. static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
  86. {
  87. int i;
  88. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  89. if (adapter->npars[i].pci_func == pci_func)
  90. return i;
  91. }
  92. return -1;
  93. }
  94. static u32
  95. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  96. {
  97. u32 rsp;
  98. int timeout = 0, err = 0;
  99. do {
  100. /* give atleast 1ms for firmware to respond */
  101. mdelay(1);
  102. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  103. return QLCNIC_CDRP_RSP_TIMEOUT;
  104. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
  105. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  106. return rsp;
  107. }
  108. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  109. struct qlcnic_cmd_args *cmd)
  110. {
  111. int i, err = 0;
  112. u32 rsp;
  113. u32 signature;
  114. struct pci_dev *pdev = adapter->pdev;
  115. struct qlcnic_hardware_context *ahw = adapter->ahw;
  116. const char *fmt;
  117. signature = qlcnic_get_cmd_signature(ahw);
  118. /* Acquire semaphore before accessing CRB */
  119. if (qlcnic_api_lock(adapter)) {
  120. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  121. return cmd->rsp.arg[0];
  122. }
  123. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  124. for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
  125. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  126. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  127. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  128. rsp = qlcnic_poll_rsp(adapter);
  129. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  130. dev_err(&pdev->dev, "card response timeout.\n");
  131. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  132. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  133. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
  134. switch (cmd->rsp.arg[0]) {
  135. case QLCNIC_RCODE_INVALID_ARGS:
  136. fmt = "CDRP invalid args: [%d]\n";
  137. break;
  138. case QLCNIC_RCODE_NOT_SUPPORTED:
  139. case QLCNIC_RCODE_NOT_IMPL:
  140. fmt = "CDRP command not supported: [%d]\n";
  141. break;
  142. case QLCNIC_RCODE_NOT_PERMITTED:
  143. fmt = "CDRP requested action not permitted: [%d]\n";
  144. break;
  145. case QLCNIC_RCODE_INVALID:
  146. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  147. break;
  148. case QLCNIC_RCODE_TIMEOUT:
  149. fmt = "CDRP command timeout: [%d]\n";
  150. break;
  151. default:
  152. fmt = "CDRP command failed: [%d]\n";
  153. break;
  154. }
  155. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  156. qlcnic_dump_mbx(adapter, cmd);
  157. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  158. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  159. for (i = 1; i < cmd->rsp.num; i++)
  160. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
  161. /* Release semaphore */
  162. qlcnic_api_unlock(adapter);
  163. return cmd->rsp.arg[0];
  164. }
  165. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  166. {
  167. struct qlcnic_cmd_args cmd;
  168. u32 arg1, arg2, arg3;
  169. char drv_string[12];
  170. int err = 0;
  171. memset(drv_string, 0, sizeof(drv_string));
  172. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  173. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  174. _QLCNIC_LINUX_SUBVERSION);
  175. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  176. if (err)
  177. return err;
  178. memcpy(&arg1, drv_string, sizeof(u32));
  179. memcpy(&arg2, drv_string + 4, sizeof(u32));
  180. memcpy(&arg3, drv_string + 8, sizeof(u32));
  181. cmd.req.arg[1] = arg1;
  182. cmd.req.arg[2] = arg2;
  183. cmd.req.arg[3] = arg3;
  184. err = qlcnic_issue_cmd(adapter, &cmd);
  185. if (err) {
  186. dev_info(&adapter->pdev->dev,
  187. "Failed to set driver version in firmware\n");
  188. err = -EIO;
  189. }
  190. qlcnic_free_mbx_args(&cmd);
  191. return err;
  192. }
  193. int
  194. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  195. {
  196. int err = 0;
  197. struct qlcnic_cmd_args cmd;
  198. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  199. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  200. return err;
  201. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  202. if (err)
  203. return err;
  204. cmd.req.arg[1] = recv_ctx->context_id;
  205. cmd.req.arg[2] = mtu;
  206. err = qlcnic_issue_cmd(adapter, &cmd);
  207. if (err) {
  208. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  209. err = -EIO;
  210. }
  211. qlcnic_free_mbx_args(&cmd);
  212. return err;
  213. }
  214. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  215. {
  216. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  217. struct qlcnic_hardware_context *ahw = adapter->ahw;
  218. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  219. struct net_device *netdev = adapter->netdev;
  220. u32 temp_intr_crb_mode, temp_rds_crb_mode;
  221. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  222. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  223. struct qlcnic_hostrq_rds_ring *prq_rds;
  224. struct qlcnic_hostrq_sds_ring *prq_sds;
  225. struct qlcnic_host_rds_ring *rds_ring;
  226. struct qlcnic_host_sds_ring *sds_ring;
  227. struct qlcnic_cardrsp_rx_ctx *prsp;
  228. struct qlcnic_hostrq_rx_ctx *prq;
  229. u8 i, nrds_rings, nsds_rings;
  230. struct qlcnic_cmd_args cmd;
  231. size_t rq_size, rsp_size;
  232. u32 cap, reg, val, reg2;
  233. u64 phys_addr;
  234. u16 temp_u16;
  235. void *addr;
  236. int err;
  237. nrds_rings = adapter->max_rds_rings;
  238. nsds_rings = adapter->max_sds_rings;
  239. rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  240. nsds_rings);
  241. rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  242. nsds_rings);
  243. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  244. &hostrq_phys_addr, GFP_KERNEL);
  245. if (addr == NULL)
  246. return -ENOMEM;
  247. prq = addr;
  248. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  249. &cardrsp_phys_addr, GFP_KERNEL);
  250. if (addr == NULL) {
  251. err = -ENOMEM;
  252. goto out_free_rq;
  253. }
  254. prsp = addr;
  255. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  256. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  257. | QLCNIC_CAP0_VALIDOFF);
  258. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  259. if (qlcnic_check_multi_tx(adapter) &&
  260. !adapter->ahw->diag_test) {
  261. cap |= QLCNIC_CAP0_TX_MULTI;
  262. } else {
  263. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  264. prq->valid_field_offset = cpu_to_le16(temp_u16);
  265. prq->txrx_sds_binding = nsds_rings - 1;
  266. temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  267. prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
  268. temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
  269. prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
  270. }
  271. prq->capabilities[0] = cpu_to_le32(cap);
  272. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  273. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  274. prq->rds_ring_offset = 0;
  275. val = le32_to_cpu(prq->rds_ring_offset) +
  276. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  277. prq->sds_ring_offset = cpu_to_le32(val);
  278. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  279. le32_to_cpu(prq->rds_ring_offset));
  280. for (i = 0; i < nrds_rings; i++) {
  281. rds_ring = &recv_ctx->rds_rings[i];
  282. rds_ring->producer = 0;
  283. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  284. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  285. prq_rds[i].ring_kind = cpu_to_le32(i);
  286. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  287. }
  288. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  289. le32_to_cpu(prq->sds_ring_offset));
  290. for (i = 0; i < nsds_rings; i++) {
  291. sds_ring = &recv_ctx->sds_rings[i];
  292. sds_ring->consumer = 0;
  293. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  294. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  295. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  296. if (qlcnic_check_multi_tx(adapter) &&
  297. !adapter->ahw->diag_test)
  298. prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
  299. else
  300. prq_sds[i].msi_index = cpu_to_le16(i);
  301. }
  302. phys_addr = hostrq_phys_addr;
  303. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  304. if (err)
  305. goto out_free_rsp;
  306. cmd.req.arg[1] = MSD(phys_addr);
  307. cmd.req.arg[2] = LSD(phys_addr);
  308. cmd.req.arg[3] = rq_size;
  309. err = qlcnic_issue_cmd(adapter, &cmd);
  310. if (err) {
  311. dev_err(&adapter->pdev->dev,
  312. "Failed to create rx ctx in firmware%d\n", err);
  313. goto out_free_rsp;
  314. }
  315. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  316. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  317. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  318. rds_ring = &recv_ctx->rds_rings[i];
  319. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  320. rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
  321. }
  322. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  323. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  324. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  325. sds_ring = &recv_ctx->sds_rings[i];
  326. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  327. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  328. reg2 = ahw->intr_tbl[i].src;
  329. else
  330. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  331. sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
  332. sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
  333. }
  334. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  335. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  336. recv_ctx->virt_port = prsp->virt_port;
  337. netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
  338. recv_ctx->context_id, recv_ctx->state);
  339. qlcnic_free_mbx_args(&cmd);
  340. out_free_rsp:
  341. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  342. cardrsp_phys_addr);
  343. out_free_rq:
  344. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  345. return err;
  346. }
  347. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  348. {
  349. int err;
  350. struct qlcnic_cmd_args cmd;
  351. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  352. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  353. if (err)
  354. return;
  355. cmd.req.arg[1] = recv_ctx->context_id;
  356. err = qlcnic_issue_cmd(adapter, &cmd);
  357. if (err)
  358. dev_err(&adapter->pdev->dev,
  359. "Failed to destroy rx ctx in firmware\n");
  360. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  361. qlcnic_free_mbx_args(&cmd);
  362. }
  363. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  364. struct qlcnic_host_tx_ring *tx_ring,
  365. int ring)
  366. {
  367. struct qlcnic_hardware_context *ahw = adapter->ahw;
  368. struct net_device *netdev = adapter->netdev;
  369. struct qlcnic_hostrq_tx_ctx *prq;
  370. struct qlcnic_hostrq_cds_ring *prq_cds;
  371. struct qlcnic_cardrsp_tx_ctx *prsp;
  372. struct qlcnic_cmd_args cmd;
  373. u32 temp, intr_mask, temp_int_crb_mode;
  374. dma_addr_t rq_phys_addr, rsp_phys_addr;
  375. int temp_nsds_rings, index, err;
  376. void *rq_addr, *rsp_addr;
  377. size_t rq_size, rsp_size;
  378. u64 phys_addr;
  379. u16 msix_id;
  380. /* reset host resources */
  381. tx_ring->producer = 0;
  382. tx_ring->sw_consumer = 0;
  383. *(tx_ring->hw_consumer) = 0;
  384. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  385. rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  386. &rq_phys_addr, GFP_KERNEL | __GFP_ZERO);
  387. if (!rq_addr)
  388. return -ENOMEM;
  389. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  390. rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  391. &rsp_phys_addr, GFP_KERNEL | __GFP_ZERO);
  392. if (!rsp_addr) {
  393. err = -ENOMEM;
  394. goto out_free_rq;
  395. }
  396. prq = rq_addr;
  397. prsp = rsp_addr;
  398. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  399. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  400. QLCNIC_CAP0_LSO);
  401. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  402. temp |= QLCNIC_CAP0_TX_MULTI;
  403. prq->capabilities[0] = cpu_to_le32(temp);
  404. if (qlcnic_check_multi_tx(adapter) &&
  405. !adapter->ahw->diag_test) {
  406. temp_nsds_rings = adapter->max_sds_rings;
  407. index = temp_nsds_rings + ring;
  408. msix_id = ahw->intr_tbl[index].id;
  409. prq->msi_index = cpu_to_le16(msix_id);
  410. } else {
  411. temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  412. prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
  413. prq->msi_index = 0;
  414. }
  415. prq->interrupt_ctl = 0;
  416. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  417. prq_cds = &prq->cds_ring;
  418. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  419. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  420. phys_addr = rq_phys_addr;
  421. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  422. if (err)
  423. goto out_free_rsp;
  424. cmd.req.arg[1] = MSD(phys_addr);
  425. cmd.req.arg[2] = LSD(phys_addr);
  426. cmd.req.arg[3] = rq_size;
  427. err = qlcnic_issue_cmd(adapter, &cmd);
  428. if (err == QLCNIC_RCODE_SUCCESS) {
  429. tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
  430. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  431. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  432. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  433. if (qlcnic_check_multi_tx(adapter) &&
  434. !adapter->ahw->diag_test &&
  435. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  436. index = adapter->max_sds_rings + ring;
  437. intr_mask = ahw->intr_tbl[index].src;
  438. tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
  439. }
  440. netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
  441. tx_ring->ctx_id, tx_ring->state);
  442. } else {
  443. netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
  444. err);
  445. err = -EIO;
  446. }
  447. qlcnic_free_mbx_args(&cmd);
  448. out_free_rsp:
  449. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  450. rsp_phys_addr);
  451. out_free_rq:
  452. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  453. return err;
  454. }
  455. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  456. struct qlcnic_host_tx_ring *tx_ring)
  457. {
  458. struct qlcnic_cmd_args cmd;
  459. int ret;
  460. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  461. if (ret)
  462. return;
  463. cmd.req.arg[1] = tx_ring->ctx_id;
  464. if (qlcnic_issue_cmd(adapter, &cmd))
  465. dev_err(&adapter->pdev->dev,
  466. "Failed to destroy tx ctx in firmware\n");
  467. qlcnic_free_mbx_args(&cmd);
  468. }
  469. int
  470. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  471. {
  472. int err;
  473. struct qlcnic_cmd_args cmd;
  474. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  475. if (err)
  476. return err;
  477. cmd.req.arg[1] = config;
  478. err = qlcnic_issue_cmd(adapter, &cmd);
  479. qlcnic_free_mbx_args(&cmd);
  480. return err;
  481. }
  482. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  483. {
  484. void *addr;
  485. int err, ring;
  486. struct qlcnic_recv_context *recv_ctx;
  487. struct qlcnic_host_rds_ring *rds_ring;
  488. struct qlcnic_host_sds_ring *sds_ring;
  489. struct qlcnic_host_tx_ring *tx_ring;
  490. __le32 *ptr;
  491. struct pci_dev *pdev = adapter->pdev;
  492. recv_ctx = adapter->recv_ctx;
  493. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  494. tx_ring = &adapter->tx_ring[ring];
  495. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  496. &tx_ring->hw_cons_phys_addr,
  497. GFP_KERNEL);
  498. if (ptr == NULL)
  499. return -ENOMEM;
  500. tx_ring->hw_consumer = ptr;
  501. /* cmd desc ring */
  502. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  503. &tx_ring->phys_addr,
  504. GFP_KERNEL);
  505. if (addr == NULL) {
  506. err = -ENOMEM;
  507. goto err_out_free;
  508. }
  509. tx_ring->desc_head = addr;
  510. }
  511. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  512. rds_ring = &recv_ctx->rds_rings[ring];
  513. addr = dma_alloc_coherent(&adapter->pdev->dev,
  514. RCV_DESC_RINGSIZE(rds_ring),
  515. &rds_ring->phys_addr, GFP_KERNEL);
  516. if (addr == NULL) {
  517. err = -ENOMEM;
  518. goto err_out_free;
  519. }
  520. rds_ring->desc_head = addr;
  521. }
  522. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  523. sds_ring = &recv_ctx->sds_rings[ring];
  524. addr = dma_alloc_coherent(&adapter->pdev->dev,
  525. STATUS_DESC_RINGSIZE(sds_ring),
  526. &sds_ring->phys_addr, GFP_KERNEL);
  527. if (addr == NULL) {
  528. err = -ENOMEM;
  529. goto err_out_free;
  530. }
  531. sds_ring->desc_head = addr;
  532. }
  533. return 0;
  534. err_out_free:
  535. qlcnic_free_hw_resources(adapter);
  536. return err;
  537. }
  538. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  539. {
  540. int i, err, ring;
  541. if (dev->flags & QLCNIC_NEED_FLR) {
  542. pci_reset_function(dev->pdev);
  543. dev->flags &= ~QLCNIC_NEED_FLR;
  544. }
  545. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  546. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  547. err = qlcnic_83xx_config_intrpt(dev, 1);
  548. if (err)
  549. return err;
  550. }
  551. }
  552. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  553. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
  554. err = qlcnic_82xx_mq_intrpt(dev, 1);
  555. if (err)
  556. return err;
  557. }
  558. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  559. if (err)
  560. goto err_out;
  561. for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
  562. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  563. &dev->tx_ring[ring],
  564. ring);
  565. if (err) {
  566. qlcnic_fw_cmd_del_rx_ctx(dev);
  567. if (ring == 0)
  568. goto err_out;
  569. for (i = 0; i < ring; i++)
  570. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  571. goto err_out;
  572. }
  573. }
  574. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  575. return 0;
  576. err_out:
  577. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  578. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
  579. qlcnic_82xx_config_intrpt(dev, 0);
  580. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  581. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  582. qlcnic_83xx_config_intrpt(dev, 0);
  583. }
  584. return err;
  585. }
  586. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  587. {
  588. int ring;
  589. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  590. qlcnic_fw_cmd_del_rx_ctx(adapter);
  591. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
  592. qlcnic_fw_cmd_del_tx_ctx(adapter,
  593. &adapter->tx_ring[ring]);
  594. if (qlcnic_82xx_check(adapter) &&
  595. (adapter->flags & QLCNIC_MSIX_ENABLED) &&
  596. qlcnic_check_multi_tx(adapter) &&
  597. !adapter->ahw->diag_test)
  598. qlcnic_82xx_config_intrpt(adapter, 0);
  599. if (qlcnic_83xx_check(adapter) &&
  600. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  601. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  602. qlcnic_83xx_config_intrpt(adapter, 0);
  603. }
  604. /* Allow dma queues to drain after context reset */
  605. mdelay(20);
  606. }
  607. }
  608. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  609. {
  610. struct qlcnic_recv_context *recv_ctx;
  611. struct qlcnic_host_rds_ring *rds_ring;
  612. struct qlcnic_host_sds_ring *sds_ring;
  613. struct qlcnic_host_tx_ring *tx_ring;
  614. int ring;
  615. recv_ctx = adapter->recv_ctx;
  616. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  617. tx_ring = &adapter->tx_ring[ring];
  618. if (tx_ring->hw_consumer != NULL) {
  619. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  620. tx_ring->hw_consumer,
  621. tx_ring->hw_cons_phys_addr);
  622. tx_ring->hw_consumer = NULL;
  623. }
  624. if (tx_ring->desc_head != NULL) {
  625. dma_free_coherent(&adapter->pdev->dev,
  626. TX_DESC_RINGSIZE(tx_ring),
  627. tx_ring->desc_head,
  628. tx_ring->phys_addr);
  629. tx_ring->desc_head = NULL;
  630. }
  631. }
  632. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  633. rds_ring = &recv_ctx->rds_rings[ring];
  634. if (rds_ring->desc_head != NULL) {
  635. dma_free_coherent(&adapter->pdev->dev,
  636. RCV_DESC_RINGSIZE(rds_ring),
  637. rds_ring->desc_head,
  638. rds_ring->phys_addr);
  639. rds_ring->desc_head = NULL;
  640. }
  641. }
  642. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  643. sds_ring = &recv_ctx->sds_rings[ring];
  644. if (sds_ring->desc_head != NULL) {
  645. dma_free_coherent(&adapter->pdev->dev,
  646. STATUS_DESC_RINGSIZE(sds_ring),
  647. sds_ring->desc_head,
  648. sds_ring->phys_addr);
  649. sds_ring->desc_head = NULL;
  650. }
  651. }
  652. }
  653. int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
  654. {
  655. struct qlcnic_hardware_context *ahw = adapter->ahw;
  656. struct net_device *netdev = adapter->netdev;
  657. struct qlcnic_cmd_args cmd;
  658. u32 type, val;
  659. int i, err = 0;
  660. for (i = 0; i < ahw->num_msix; i++) {
  661. qlcnic_alloc_mbx_args(&cmd, adapter,
  662. QLCNIC_CMD_MQ_TX_CONFIG_INTR);
  663. type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
  664. val = type | (ahw->intr_tbl[i].type << 4);
  665. if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
  666. val |= (ahw->intr_tbl[i].id << 16);
  667. cmd.req.arg[1] = val;
  668. err = qlcnic_issue_cmd(adapter, &cmd);
  669. if (err) {
  670. netdev_err(netdev, "Failed to %s interrupts %d\n",
  671. op_type == QLCNIC_INTRPT_ADD ? "Add" :
  672. "Delete", err);
  673. qlcnic_free_mbx_args(&cmd);
  674. return err;
  675. }
  676. val = cmd.rsp.arg[1];
  677. if (LSB(val)) {
  678. netdev_info(netdev,
  679. "failed to configure interrupt for %d\n",
  680. ahw->intr_tbl[i].id);
  681. continue;
  682. }
  683. if (op_type) {
  684. ahw->intr_tbl[i].id = MSW(val);
  685. ahw->intr_tbl[i].enabled = 1;
  686. ahw->intr_tbl[i].src = cmd.rsp.arg[2];
  687. } else {
  688. ahw->intr_tbl[i].id = i;
  689. ahw->intr_tbl[i].enabled = 0;
  690. ahw->intr_tbl[i].src = 0;
  691. }
  692. qlcnic_free_mbx_args(&cmd);
  693. }
  694. return err;
  695. }
  696. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
  697. u8 function)
  698. {
  699. int err, i;
  700. struct qlcnic_cmd_args cmd;
  701. u32 mac_low, mac_high;
  702. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  703. if (err)
  704. return err;
  705. cmd.req.arg[1] = function | BIT_8;
  706. err = qlcnic_issue_cmd(adapter, &cmd);
  707. if (err == QLCNIC_RCODE_SUCCESS) {
  708. mac_low = cmd.rsp.arg[1];
  709. mac_high = cmd.rsp.arg[2];
  710. for (i = 0; i < 2; i++)
  711. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  712. for (i = 2; i < 6; i++)
  713. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  714. } else {
  715. dev_err(&adapter->pdev->dev,
  716. "Failed to get mac address%d\n", err);
  717. err = -EIO;
  718. }
  719. qlcnic_free_mbx_args(&cmd);
  720. return err;
  721. }
  722. /* Get info of a NIC partition */
  723. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  724. struct qlcnic_info *npar_info, u8 func_id)
  725. {
  726. int err;
  727. dma_addr_t nic_dma_t;
  728. const struct qlcnic_info_le *nic_info;
  729. void *nic_info_addr;
  730. struct qlcnic_cmd_args cmd;
  731. size_t nic_size = sizeof(struct qlcnic_info_le);
  732. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  733. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  734. if (!nic_info_addr)
  735. return -ENOMEM;
  736. nic_info = nic_info_addr;
  737. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  738. if (err)
  739. goto out_free_dma;
  740. cmd.req.arg[1] = MSD(nic_dma_t);
  741. cmd.req.arg[2] = LSD(nic_dma_t);
  742. cmd.req.arg[3] = (func_id << 16 | nic_size);
  743. err = qlcnic_issue_cmd(adapter, &cmd);
  744. if (err != QLCNIC_RCODE_SUCCESS) {
  745. dev_err(&adapter->pdev->dev,
  746. "Failed to get nic info%d\n", err);
  747. err = -EIO;
  748. } else {
  749. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  750. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  751. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  752. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  753. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  754. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  755. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  756. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  757. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  758. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  759. }
  760. qlcnic_free_mbx_args(&cmd);
  761. out_free_dma:
  762. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  763. nic_dma_t);
  764. return err;
  765. }
  766. /* Configure a NIC partition */
  767. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  768. struct qlcnic_info *nic)
  769. {
  770. int err = -EIO;
  771. dma_addr_t nic_dma_t;
  772. void *nic_info_addr;
  773. struct qlcnic_cmd_args cmd;
  774. struct qlcnic_info_le *nic_info;
  775. size_t nic_size = sizeof(struct qlcnic_info_le);
  776. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  777. return err;
  778. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  779. &nic_dma_t, GFP_KERNEL | __GFP_ZERO);
  780. if (!nic_info_addr)
  781. return -ENOMEM;
  782. nic_info = nic_info_addr;
  783. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  784. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  785. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  786. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  787. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  788. nic_info->max_mac_filters = nic->max_mac_filters;
  789. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  790. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  791. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  792. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  793. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  794. if (err)
  795. goto out_free_dma;
  796. cmd.req.arg[1] = MSD(nic_dma_t);
  797. cmd.req.arg[2] = LSD(nic_dma_t);
  798. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  799. err = qlcnic_issue_cmd(adapter, &cmd);
  800. if (err != QLCNIC_RCODE_SUCCESS) {
  801. dev_err(&adapter->pdev->dev,
  802. "Failed to set nic info%d\n", err);
  803. err = -EIO;
  804. }
  805. qlcnic_free_mbx_args(&cmd);
  806. out_free_dma:
  807. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  808. nic_dma_t);
  809. return err;
  810. }
  811. /* Get PCI Info of a partition */
  812. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  813. struct qlcnic_pci_info *pci_info)
  814. {
  815. int err = 0, i;
  816. struct qlcnic_cmd_args cmd;
  817. dma_addr_t pci_info_dma_t;
  818. struct qlcnic_pci_info_le *npar;
  819. void *pci_info_addr;
  820. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  821. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  822. pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
  823. &pci_info_dma_t,
  824. GFP_KERNEL | __GFP_ZERO);
  825. if (!pci_info_addr)
  826. return -ENOMEM;
  827. npar = pci_info_addr;
  828. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  829. if (err)
  830. goto out_free_dma;
  831. cmd.req.arg[1] = MSD(pci_info_dma_t);
  832. cmd.req.arg[2] = LSD(pci_info_dma_t);
  833. cmd.req.arg[3] = pci_size;
  834. err = qlcnic_issue_cmd(adapter, &cmd);
  835. adapter->ahw->act_pci_func = 0;
  836. if (err == QLCNIC_RCODE_SUCCESS) {
  837. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
  838. pci_info->id = le16_to_cpu(npar->id);
  839. pci_info->active = le16_to_cpu(npar->active);
  840. pci_info->type = le16_to_cpu(npar->type);
  841. if (pci_info->type == QLCNIC_TYPE_NIC)
  842. adapter->ahw->act_pci_func++;
  843. pci_info->default_port =
  844. le16_to_cpu(npar->default_port);
  845. pci_info->tx_min_bw =
  846. le16_to_cpu(npar->tx_min_bw);
  847. pci_info->tx_max_bw =
  848. le16_to_cpu(npar->tx_max_bw);
  849. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  850. }
  851. } else {
  852. dev_err(&adapter->pdev->dev,
  853. "Failed to get PCI Info%d\n", err);
  854. err = -EIO;
  855. }
  856. qlcnic_free_mbx_args(&cmd);
  857. out_free_dma:
  858. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  859. pci_info_dma_t);
  860. return err;
  861. }
  862. /* Configure eSwitch for port mirroring */
  863. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  864. u8 enable_mirroring, u8 pci_func)
  865. {
  866. struct device *dev = &adapter->pdev->dev;
  867. struct qlcnic_cmd_args cmd;
  868. int err = -EIO;
  869. u32 arg1;
  870. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  871. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  872. return err;
  873. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  874. arg1 |= pci_func << 8;
  875. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  876. QLCNIC_CMD_SET_PORTMIRRORING);
  877. if (err)
  878. return err;
  879. cmd.req.arg[1] = arg1;
  880. err = qlcnic_issue_cmd(adapter, &cmd);
  881. if (err != QLCNIC_RCODE_SUCCESS)
  882. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  883. pci_func, id);
  884. else
  885. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  886. pci_func, id);
  887. qlcnic_free_mbx_args(&cmd);
  888. return err;
  889. }
  890. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  891. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  892. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  893. struct qlcnic_esw_stats_le *stats;
  894. dma_addr_t stats_dma_t;
  895. void *stats_addr;
  896. u32 arg1;
  897. struct qlcnic_cmd_args cmd;
  898. int err;
  899. if (esw_stats == NULL)
  900. return -ENOMEM;
  901. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  902. (func != adapter->ahw->pci_func)) {
  903. dev_err(&adapter->pdev->dev,
  904. "Not privilege to query stats for func=%d", func);
  905. return -EIO;
  906. }
  907. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  908. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  909. if (!stats_addr)
  910. return -ENOMEM;
  911. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  912. arg1 |= rx_tx << 15 | stats_size << 16;
  913. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  914. QLCNIC_CMD_GET_ESWITCH_STATS);
  915. if (err)
  916. goto out_free_dma;
  917. cmd.req.arg[1] = arg1;
  918. cmd.req.arg[2] = MSD(stats_dma_t);
  919. cmd.req.arg[3] = LSD(stats_dma_t);
  920. err = qlcnic_issue_cmd(adapter, &cmd);
  921. if (!err) {
  922. stats = stats_addr;
  923. esw_stats->context_id = le16_to_cpu(stats->context_id);
  924. esw_stats->version = le16_to_cpu(stats->version);
  925. esw_stats->size = le16_to_cpu(stats->size);
  926. esw_stats->multicast_frames =
  927. le64_to_cpu(stats->multicast_frames);
  928. esw_stats->broadcast_frames =
  929. le64_to_cpu(stats->broadcast_frames);
  930. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  931. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  932. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  933. esw_stats->errors = le64_to_cpu(stats->errors);
  934. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  935. }
  936. qlcnic_free_mbx_args(&cmd);
  937. out_free_dma:
  938. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  939. stats_dma_t);
  940. return err;
  941. }
  942. /* This routine will retrieve the MAC statistics from firmware */
  943. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  944. struct qlcnic_mac_statistics *mac_stats)
  945. {
  946. struct qlcnic_mac_statistics_le *stats;
  947. struct qlcnic_cmd_args cmd;
  948. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  949. dma_addr_t stats_dma_t;
  950. void *stats_addr;
  951. int err;
  952. if (mac_stats == NULL)
  953. return -ENOMEM;
  954. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  955. &stats_dma_t, GFP_KERNEL | __GFP_ZERO);
  956. if (!stats_addr)
  957. return -ENOMEM;
  958. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  959. if (err)
  960. goto out_free_dma;
  961. cmd.req.arg[1] = stats_size << 16;
  962. cmd.req.arg[2] = MSD(stats_dma_t);
  963. cmd.req.arg[3] = LSD(stats_dma_t);
  964. err = qlcnic_issue_cmd(adapter, &cmd);
  965. if (!err) {
  966. stats = stats_addr;
  967. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  968. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  969. mac_stats->mac_tx_mcast_pkts =
  970. le64_to_cpu(stats->mac_tx_mcast_pkts);
  971. mac_stats->mac_tx_bcast_pkts =
  972. le64_to_cpu(stats->mac_tx_bcast_pkts);
  973. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  974. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  975. mac_stats->mac_rx_mcast_pkts =
  976. le64_to_cpu(stats->mac_rx_mcast_pkts);
  977. mac_stats->mac_rx_length_error =
  978. le64_to_cpu(stats->mac_rx_length_error);
  979. mac_stats->mac_rx_length_small =
  980. le64_to_cpu(stats->mac_rx_length_small);
  981. mac_stats->mac_rx_length_large =
  982. le64_to_cpu(stats->mac_rx_length_large);
  983. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  984. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  985. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  986. } else {
  987. dev_err(&adapter->pdev->dev,
  988. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  989. }
  990. qlcnic_free_mbx_args(&cmd);
  991. out_free_dma:
  992. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  993. stats_dma_t);
  994. return err;
  995. }
  996. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  997. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  998. struct __qlcnic_esw_statistics port_stats;
  999. u8 i;
  1000. int ret = -EIO;
  1001. if (esw_stats == NULL)
  1002. return -ENOMEM;
  1003. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1004. return -EIO;
  1005. if (adapter->npars == NULL)
  1006. return -EIO;
  1007. memset(esw_stats, 0, sizeof(u64));
  1008. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1009. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1010. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  1011. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  1012. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  1013. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  1014. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  1015. esw_stats->context_id = eswitch;
  1016. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  1017. if (adapter->npars[i].phy_port != eswitch)
  1018. continue;
  1019. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  1020. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  1021. rx_tx, &port_stats))
  1022. continue;
  1023. esw_stats->size = port_stats.size;
  1024. esw_stats->version = port_stats.version;
  1025. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  1026. port_stats.unicast_frames);
  1027. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  1028. port_stats.multicast_frames);
  1029. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  1030. port_stats.broadcast_frames);
  1031. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  1032. port_stats.dropped_frames);
  1033. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  1034. port_stats.errors);
  1035. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  1036. port_stats.local_frames);
  1037. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  1038. port_stats.numbytes);
  1039. ret = 0;
  1040. }
  1041. return ret;
  1042. }
  1043. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  1044. const u8 port, const u8 rx_tx)
  1045. {
  1046. int err;
  1047. u32 arg1;
  1048. struct qlcnic_cmd_args cmd;
  1049. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1050. return -EIO;
  1051. if (func_esw == QLCNIC_STATS_PORT) {
  1052. if (port >= QLCNIC_MAX_PCI_FUNC)
  1053. goto err_ret;
  1054. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  1055. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  1056. goto err_ret;
  1057. } else {
  1058. goto err_ret;
  1059. }
  1060. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  1061. goto err_ret;
  1062. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  1063. arg1 |= BIT_14 | rx_tx << 15;
  1064. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1065. QLCNIC_CMD_GET_ESWITCH_STATS);
  1066. if (err)
  1067. return err;
  1068. cmd.req.arg[1] = arg1;
  1069. err = qlcnic_issue_cmd(adapter, &cmd);
  1070. qlcnic_free_mbx_args(&cmd);
  1071. return err;
  1072. err_ret:
  1073. dev_err(&adapter->pdev->dev,
  1074. "Invalid args func_esw %d port %d rx_ctx %d\n",
  1075. func_esw, port, rx_tx);
  1076. return -EIO;
  1077. }
  1078. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1079. u32 *arg1, u32 *arg2)
  1080. {
  1081. struct device *dev = &adapter->pdev->dev;
  1082. struct qlcnic_cmd_args cmd;
  1083. u8 pci_func = *arg1 >> 8;
  1084. int err;
  1085. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1086. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  1087. if (err)
  1088. return err;
  1089. cmd.req.arg[1] = *arg1;
  1090. err = qlcnic_issue_cmd(adapter, &cmd);
  1091. *arg1 = cmd.rsp.arg[1];
  1092. *arg2 = cmd.rsp.arg[2];
  1093. qlcnic_free_mbx_args(&cmd);
  1094. if (err == QLCNIC_RCODE_SUCCESS)
  1095. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  1096. pci_func);
  1097. else
  1098. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1099. pci_func);
  1100. return err;
  1101. }
  1102. /* Configure eSwitch port
  1103. op_mode = 0 for setting default port behavior
  1104. op_mode = 1 for setting vlan id
  1105. op_mode = 2 for deleting vlan id
  1106. op_type = 0 for vlan_id
  1107. op_type = 1 for port vlan_id
  1108. */
  1109. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1110. struct qlcnic_esw_func_cfg *esw_cfg)
  1111. {
  1112. struct device *dev = &adapter->pdev->dev;
  1113. struct qlcnic_cmd_args cmd;
  1114. int err = -EIO, index;
  1115. u32 arg1, arg2 = 0;
  1116. u8 pci_func;
  1117. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1118. return err;
  1119. pci_func = esw_cfg->pci_func;
  1120. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1121. if (index < 0)
  1122. return err;
  1123. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1124. arg1 |= (pci_func << 8);
  1125. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1126. return err;
  1127. arg1 &= ~(0x0ff << 8);
  1128. arg1 |= (pci_func << 8);
  1129. arg1 &= ~(BIT_2 | BIT_3);
  1130. switch (esw_cfg->op_mode) {
  1131. case QLCNIC_PORT_DEFAULTS:
  1132. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1133. arg2 |= (BIT_0 | BIT_1);
  1134. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1135. arg2 |= (BIT_2 | BIT_3);
  1136. if (!(esw_cfg->discard_tagged))
  1137. arg1 &= ~BIT_4;
  1138. if (!(esw_cfg->promisc_mode))
  1139. arg1 &= ~BIT_6;
  1140. if (!(esw_cfg->mac_override))
  1141. arg1 &= ~BIT_7;
  1142. if (!(esw_cfg->mac_anti_spoof))
  1143. arg2 &= ~BIT_0;
  1144. if (!(esw_cfg->offload_flags & BIT_0))
  1145. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1146. if (!(esw_cfg->offload_flags & BIT_1))
  1147. arg2 &= ~BIT_2;
  1148. if (!(esw_cfg->offload_flags & BIT_2))
  1149. arg2 &= ~BIT_3;
  1150. break;
  1151. case QLCNIC_ADD_VLAN:
  1152. arg1 |= (BIT_2 | BIT_5);
  1153. arg1 |= (esw_cfg->vlan_id << 16);
  1154. break;
  1155. case QLCNIC_DEL_VLAN:
  1156. arg1 |= (BIT_3 | BIT_5);
  1157. arg1 &= ~(0x0ffff << 16);
  1158. break;
  1159. default:
  1160. return err;
  1161. }
  1162. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1163. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1164. if (err)
  1165. return err;
  1166. cmd.req.arg[1] = arg1;
  1167. cmd.req.arg[2] = arg2;
  1168. err = qlcnic_issue_cmd(adapter, &cmd);
  1169. qlcnic_free_mbx_args(&cmd);
  1170. if (err != QLCNIC_RCODE_SUCCESS)
  1171. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1172. pci_func);
  1173. else
  1174. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1175. pci_func);
  1176. return err;
  1177. }
  1178. int
  1179. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1180. struct qlcnic_esw_func_cfg *esw_cfg)
  1181. {
  1182. u32 arg1, arg2;
  1183. int index;
  1184. u8 phy_port;
  1185. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1186. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1187. if (index < 0)
  1188. return -EIO;
  1189. phy_port = adapter->npars[index].phy_port;
  1190. } else {
  1191. phy_port = adapter->ahw->physical_port;
  1192. }
  1193. arg1 = phy_port;
  1194. arg1 |= (esw_cfg->pci_func << 8);
  1195. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1196. return -EIO;
  1197. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1198. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1199. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1200. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1201. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1202. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1203. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1204. return 0;
  1205. }