mpc832x_mds.dts 7.5 KB

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  1. /*
  2. * MPC8323E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323EMDS";
  13. compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8323@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. };
  30. };
  31. memory {
  32. device_type = "memory";
  33. reg = <00000000 08000000>;
  34. };
  35. bcsr@f8000000 {
  36. device_type = "board-control";
  37. reg = <f8000000 8000>;
  38. };
  39. soc8323@e0000000 {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. device_type = "soc";
  43. ranges = <0 e0000000 00100000>;
  44. reg = <e0000000 00000200>;
  45. bus-frequency = <7DE2900>;
  46. wdt@200 {
  47. device_type = "watchdog";
  48. compatible = "mpc83xx_wdt";
  49. reg = <200 100>;
  50. };
  51. i2c@3000 {
  52. device_type = "i2c";
  53. compatible = "fsl-i2c";
  54. reg = <3000 100>;
  55. interrupts = <e 8>;
  56. interrupt-parent = < &ipic >;
  57. dfsrr;
  58. };
  59. serial@4500 {
  60. device_type = "serial";
  61. compatible = "ns16550";
  62. reg = <4500 100>;
  63. clock-frequency = <0>;
  64. interrupts = <9 8>;
  65. interrupt-parent = < &ipic >;
  66. };
  67. serial@4600 {
  68. device_type = "serial";
  69. compatible = "ns16550";
  70. reg = <4600 100>;
  71. clock-frequency = <0>;
  72. interrupts = <a 8>;
  73. interrupt-parent = < &ipic >;
  74. };
  75. crypto@30000 {
  76. device_type = "crypto";
  77. model = "SEC2";
  78. compatible = "talitos";
  79. reg = <30000 7000>;
  80. interrupts = <b 8>;
  81. interrupt-parent = < &ipic >;
  82. /* Rev. 2.2 */
  83. num-channels = <1>;
  84. channel-fifo-len = <18>;
  85. exec-units-mask = <0000004c>;
  86. descriptor-types-mask = <0122003f>;
  87. };
  88. ipic: pic@700 {
  89. interrupt-controller;
  90. #address-cells = <0>;
  91. #interrupt-cells = <2>;
  92. reg = <700 100>;
  93. device_type = "ipic";
  94. };
  95. par_io@1400 {
  96. reg = <1400 100>;
  97. device_type = "par_io";
  98. num-ports = <7>;
  99. pio3: ucc_pin@03 {
  100. pio-map = <
  101. /* port pin dir open_drain assignment has_irq */
  102. 3 4 3 0 2 0 /* MDIO */
  103. 3 5 1 0 2 0 /* MDC */
  104. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  105. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  106. 1 0 1 0 1 0 /* TxD0 */
  107. 1 1 1 0 1 0 /* TxD1 */
  108. 1 2 1 0 1 0 /* TxD2 */
  109. 1 3 1 0 1 0 /* TxD3 */
  110. 1 4 2 0 1 0 /* RxD0 */
  111. 1 5 2 0 1 0 /* RxD1 */
  112. 1 6 2 0 1 0 /* RxD2 */
  113. 1 7 2 0 1 0 /* RxD3 */
  114. 1 8 2 0 1 0 /* RX_ER */
  115. 1 9 1 0 1 0 /* TX_ER */
  116. 1 a 2 0 1 0 /* RX_DV */
  117. 1 b 2 0 1 0 /* COL */
  118. 1 c 1 0 1 0 /* TX_EN */
  119. 1 d 2 0 1 0>;/* CRS */
  120. };
  121. pio4: ucc_pin@04 {
  122. pio-map = <
  123. /* port pin dir open_drain assignment has_irq */
  124. 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
  125. 3 6 2 0 1 0 /* TX_CLK (CLK8) */
  126. 1 12 1 0 1 0 /* TxD0 */
  127. 1 13 1 0 1 0 /* TxD1 */
  128. 1 14 1 0 1 0 /* TxD2 */
  129. 1 15 1 0 1 0 /* TxD3 */
  130. 1 16 2 0 1 0 /* RxD0 */
  131. 1 17 2 0 1 0 /* RxD1 */
  132. 1 18 2 0 1 0 /* RxD2 */
  133. 1 19 2 0 1 0 /* RxD3 */
  134. 1 1a 2 0 1 0 /* RX_ER */
  135. 1 1b 1 0 1 0 /* TX_ER */
  136. 1 1c 2 0 1 0 /* RX_DV */
  137. 1 1d 2 0 1 0 /* COL */
  138. 1 1e 1 0 1 0 /* TX_EN */
  139. 1 1f 2 0 1 0>;/* CRS */
  140. };
  141. };
  142. };
  143. qe@e0100000 {
  144. #address-cells = <1>;
  145. #size-cells = <1>;
  146. device_type = "qe";
  147. model = "QE";
  148. ranges = <0 e0100000 00100000>;
  149. reg = <e0100000 480>;
  150. brg-frequency = <0>;
  151. bus-frequency = <BCD3D80>;
  152. muram@10000 {
  153. device_type = "muram";
  154. ranges = <0 00010000 00004000>;
  155. data-only@0 {
  156. reg = <0 4000>;
  157. };
  158. };
  159. spi@4c0 {
  160. device_type = "spi";
  161. compatible = "fsl_spi";
  162. reg = <4c0 40>;
  163. interrupts = <2>;
  164. interrupt-parent = < &qeic >;
  165. mode = "cpu";
  166. };
  167. spi@500 {
  168. device_type = "spi";
  169. compatible = "fsl_spi";
  170. reg = <500 40>;
  171. interrupts = <1>;
  172. interrupt-parent = < &qeic >;
  173. mode = "cpu";
  174. };
  175. usb@6c0 {
  176. device_type = "usb";
  177. compatible = "qe_udc";
  178. reg = <6c0 40 8B00 100>;
  179. interrupts = <b>;
  180. interrupt-parent = < &qeic >;
  181. mode = "slave";
  182. };
  183. ucc@2200 {
  184. device_type = "network";
  185. compatible = "ucc_geth";
  186. model = "UCC";
  187. device-id = <3>;
  188. reg = <2200 200>;
  189. interrupts = <22>;
  190. interrupt-parent = < &qeic >;
  191. /*
  192. * mac-address is deprecated and will be removed
  193. * in 2.6.25. Only recent versions of
  194. * U-Boot support local-mac-address, however.
  195. */
  196. mac-address = [ 00 00 00 00 00 00 ];
  197. local-mac-address = [ 00 00 00 00 00 00 ];
  198. rx-clock = <19>;
  199. tx-clock = <1a>;
  200. phy-handle = < &phy3 >;
  201. pio-handle = < &pio3 >;
  202. };
  203. ucc@3200 {
  204. device_type = "network";
  205. compatible = "ucc_geth";
  206. model = "UCC";
  207. device-id = <4>;
  208. reg = <3200 200>;
  209. interrupts = <23>;
  210. interrupt-parent = < &qeic >;
  211. /*
  212. * mac-address is deprecated and will be removed
  213. * in 2.6.25. Only recent versions of
  214. * U-Boot support local-mac-address, however.
  215. */
  216. mac-address = [ 00 00 00 00 00 00 ];
  217. local-mac-address = [ 00 00 00 00 00 00 ];
  218. rx-clock = <17>;
  219. tx-clock = <18>;
  220. phy-handle = < &phy4 >;
  221. pio-handle = < &pio4 >;
  222. };
  223. mdio@2320 {
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. reg = <2320 18>;
  227. device_type = "mdio";
  228. compatible = "ucc_geth_phy";
  229. phy3: ethernet-phy@03 {
  230. interrupt-parent = < &ipic >;
  231. interrupts = <11 8>;
  232. reg = <3>;
  233. device_type = "ethernet-phy";
  234. };
  235. phy4: ethernet-phy@04 {
  236. interrupt-parent = < &ipic >;
  237. interrupts = <12 8>;
  238. reg = <4>;
  239. device_type = "ethernet-phy";
  240. };
  241. };
  242. qeic: qeic@80 {
  243. interrupt-controller;
  244. device_type = "qeic";
  245. #address-cells = <0>;
  246. #interrupt-cells = <1>;
  247. reg = <80 80>;
  248. big-endian;
  249. interrupts = <20 8 21 8>; //high:32 low:33
  250. interrupt-parent = < &ipic >;
  251. };
  252. };
  253. pci@e0008500 {
  254. interrupt-map-mask = <f800 0 0 7>;
  255. interrupt-map = <
  256. /* IDSEL 0x11 AD17 */
  257. 8800 0 0 1 &ipic 14 8
  258. 8800 0 0 2 &ipic 15 8
  259. 8800 0 0 3 &ipic 16 8
  260. 8800 0 0 4 &ipic 17 8
  261. /* IDSEL 0x12 AD18 */
  262. 9000 0 0 1 &ipic 16 8
  263. 9000 0 0 2 &ipic 17 8
  264. 9000 0 0 3 &ipic 14 8
  265. 9000 0 0 4 &ipic 15 8
  266. /* IDSEL 0x13 AD19 */
  267. 9800 0 0 1 &ipic 17 8
  268. 9800 0 0 2 &ipic 14 8
  269. 9800 0 0 3 &ipic 15 8
  270. 9800 0 0 4 &ipic 16 8
  271. /* IDSEL 0x15 AD21*/
  272. a800 0 0 1 &ipic 14 8
  273. a800 0 0 2 &ipic 15 8
  274. a800 0 0 3 &ipic 16 8
  275. a800 0 0 4 &ipic 17 8
  276. /* IDSEL 0x16 AD22*/
  277. b000 0 0 1 &ipic 17 8
  278. b000 0 0 2 &ipic 14 8
  279. b000 0 0 3 &ipic 15 8
  280. b000 0 0 4 &ipic 16 8
  281. /* IDSEL 0x17 AD23*/
  282. b800 0 0 1 &ipic 16 8
  283. b800 0 0 2 &ipic 17 8
  284. b800 0 0 3 &ipic 14 8
  285. b800 0 0 4 &ipic 15 8
  286. /* IDSEL 0x18 AD24*/
  287. c000 0 0 1 &ipic 15 8
  288. c000 0 0 2 &ipic 16 8
  289. c000 0 0 3 &ipic 17 8
  290. c000 0 0 4 &ipic 14 8>;
  291. interrupt-parent = < &ipic >;
  292. interrupts = <42 8>;
  293. bus-range = <0 0>;
  294. ranges = <02000000 0 90000000 90000000 0 10000000
  295. 42000000 0 80000000 80000000 0 10000000
  296. 01000000 0 00000000 d0000000 0 00100000>;
  297. clock-frequency = <0>;
  298. #interrupt-cells = <1>;
  299. #size-cells = <2>;
  300. #address-cells = <3>;
  301. reg = <e0008500 100>;
  302. compatible = "fsl,mpc8349-pci";
  303. device_type = "pci";
  304. };
  305. };