phy_lp.c 83 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. IEEE 802.11g LP-PHY driver
  4. Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; see the file COPYING. If not, write to
  15. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  16. Boston, MA 02110-1301, USA.
  17. */
  18. #include "b43.h"
  19. #include "main.h"
  20. #include "phy_lp.h"
  21. #include "phy_common.h"
  22. #include "tables_lpphy.h"
  23. static inline u16 channel2freq_lp(u8 channel)
  24. {
  25. if (channel < 14)
  26. return (2407 + 5 * channel);
  27. else if (channel == 14)
  28. return 2484;
  29. else if (channel < 184)
  30. return (5000 + 5 * channel);
  31. else
  32. return (4000 + 5 * channel);
  33. }
  34. static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
  35. {
  36. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  37. return 1;
  38. return 36;
  39. }
  40. static int b43_lpphy_op_allocate(struct b43_wldev *dev)
  41. {
  42. struct b43_phy_lp *lpphy;
  43. lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
  44. if (!lpphy)
  45. return -ENOMEM;
  46. dev->phy.lp = lpphy;
  47. return 0;
  48. }
  49. static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
  50. {
  51. struct b43_phy *phy = &dev->phy;
  52. struct b43_phy_lp *lpphy = phy->lp;
  53. memset(lpphy, 0, sizeof(*lpphy));
  54. //TODO
  55. }
  56. static void b43_lpphy_op_free(struct b43_wldev *dev)
  57. {
  58. struct b43_phy_lp *lpphy = dev->phy.lp;
  59. kfree(lpphy);
  60. dev->phy.lp = NULL;
  61. }
  62. static void lpphy_read_band_sprom(struct b43_wldev *dev)
  63. {
  64. struct b43_phy_lp *lpphy = dev->phy.lp;
  65. struct ssb_bus *bus = dev->dev->bus;
  66. u16 cckpo, maxpwr;
  67. u32 ofdmpo;
  68. int i;
  69. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  70. lpphy->tx_isolation_med_band = bus->sprom.tri2g;
  71. lpphy->bx_arch = bus->sprom.bxa2g;
  72. lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
  73. lpphy->rssi_vf = bus->sprom.rssismf2g;
  74. lpphy->rssi_vc = bus->sprom.rssismc2g;
  75. lpphy->rssi_gs = bus->sprom.rssisav2g;
  76. lpphy->txpa[0] = bus->sprom.pa0b0;
  77. lpphy->txpa[1] = bus->sprom.pa0b1;
  78. lpphy->txpa[2] = bus->sprom.pa0b2;
  79. maxpwr = bus->sprom.maxpwr_bg;
  80. lpphy->max_tx_pwr_med_band = maxpwr;
  81. cckpo = bus->sprom.cck2gpo;
  82. ofdmpo = bus->sprom.ofdm2gpo;
  83. if (cckpo) {
  84. for (i = 0; i < 4; i++) {
  85. lpphy->tx_max_rate[i] =
  86. maxpwr - (ofdmpo & 0xF) * 2;
  87. ofdmpo >>= 4;
  88. }
  89. ofdmpo = bus->sprom.ofdm2gpo;
  90. for (i = 4; i < 15; i++) {
  91. lpphy->tx_max_rate[i] =
  92. maxpwr - (ofdmpo & 0xF) * 2;
  93. ofdmpo >>= 4;
  94. }
  95. } else {
  96. ofdmpo &= 0xFF;
  97. for (i = 0; i < 4; i++)
  98. lpphy->tx_max_rate[i] = maxpwr;
  99. for (i = 4; i < 15; i++)
  100. lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
  101. }
  102. } else { /* 5GHz */
  103. lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
  104. lpphy->tx_isolation_med_band = bus->sprom.tri5g;
  105. lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
  106. lpphy->bx_arch = bus->sprom.bxa5g;
  107. lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
  108. lpphy->rssi_vf = bus->sprom.rssismf5g;
  109. lpphy->rssi_vc = bus->sprom.rssismc5g;
  110. lpphy->rssi_gs = bus->sprom.rssisav5g;
  111. lpphy->txpa[0] = bus->sprom.pa1b0;
  112. lpphy->txpa[1] = bus->sprom.pa1b1;
  113. lpphy->txpa[2] = bus->sprom.pa1b2;
  114. lpphy->txpal[0] = bus->sprom.pa1lob0;
  115. lpphy->txpal[1] = bus->sprom.pa1lob1;
  116. lpphy->txpal[2] = bus->sprom.pa1lob2;
  117. lpphy->txpah[0] = bus->sprom.pa1hib0;
  118. lpphy->txpah[1] = bus->sprom.pa1hib1;
  119. lpphy->txpah[2] = bus->sprom.pa1hib2;
  120. maxpwr = bus->sprom.maxpwr_al;
  121. ofdmpo = bus->sprom.ofdm5glpo;
  122. lpphy->max_tx_pwr_low_band = maxpwr;
  123. for (i = 4; i < 12; i++) {
  124. lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
  125. ofdmpo >>= 4;
  126. }
  127. maxpwr = bus->sprom.maxpwr_a;
  128. ofdmpo = bus->sprom.ofdm5gpo;
  129. lpphy->max_tx_pwr_med_band = maxpwr;
  130. for (i = 4; i < 12; i++) {
  131. lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
  132. ofdmpo >>= 4;
  133. }
  134. maxpwr = bus->sprom.maxpwr_ah;
  135. ofdmpo = bus->sprom.ofdm5ghpo;
  136. lpphy->max_tx_pwr_hi_band = maxpwr;
  137. for (i = 4; i < 12; i++) {
  138. lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
  139. ofdmpo >>= 4;
  140. }
  141. }
  142. }
  143. static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
  144. {
  145. struct b43_phy_lp *lpphy = dev->phy.lp;
  146. u16 temp[3];
  147. u16 isolation;
  148. B43_WARN_ON(dev->phy.rev >= 2);
  149. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  150. isolation = lpphy->tx_isolation_med_band;
  151. else if (freq <= 5320)
  152. isolation = lpphy->tx_isolation_low_band;
  153. else if (freq <= 5700)
  154. isolation = lpphy->tx_isolation_med_band;
  155. else
  156. isolation = lpphy->tx_isolation_hi_band;
  157. temp[0] = ((isolation - 26) / 12) << 12;
  158. temp[1] = temp[0] + 0x1000;
  159. temp[2] = temp[0] + 0x2000;
  160. b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
  161. b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
  162. }
  163. static void lpphy_table_init(struct b43_wldev *dev)
  164. {
  165. u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
  166. if (dev->phy.rev < 2)
  167. lpphy_rev0_1_table_init(dev);
  168. else
  169. lpphy_rev2plus_table_init(dev);
  170. lpphy_init_tx_gain_table(dev);
  171. if (dev->phy.rev < 2)
  172. lpphy_adjust_gain_table(dev, freq);
  173. }
  174. static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
  175. {
  176. struct ssb_bus *bus = dev->dev->bus;
  177. struct b43_phy_lp *lpphy = dev->phy.lp;
  178. u16 tmp, tmp2;
  179. b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
  180. b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
  181. b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
  182. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
  183. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
  184. b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
  185. b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
  186. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
  187. b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
  188. b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
  189. b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
  190. b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
  191. b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
  192. b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
  193. b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
  194. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
  195. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
  196. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
  197. b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
  198. b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
  199. b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
  200. b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
  201. b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
  202. 0xFF00, lpphy->rx_pwr_offset);
  203. if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
  204. ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
  205. (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
  206. ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
  207. ssb_pmu_set_ldo_paref(&bus->chipco, true);
  208. if (dev->phy.rev == 0) {
  209. b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
  210. 0xFFCF, 0x0010);
  211. }
  212. b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
  213. } else {
  214. ssb_pmu_set_ldo_paref(&bus->chipco, false);
  215. b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
  216. 0xFFCF, 0x0020);
  217. b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
  218. }
  219. tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
  220. b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
  221. if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
  222. b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
  223. else
  224. b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
  225. b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
  226. b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
  227. 0xFFF9, (lpphy->bx_arch << 1));
  228. if (dev->phy.rev == 1 &&
  229. (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
  230. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
  231. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
  232. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
  233. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
  234. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
  235. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
  236. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
  237. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
  238. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
  239. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
  240. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
  241. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
  242. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
  243. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
  244. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
  245. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
  246. } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
  247. (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
  248. (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
  249. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
  250. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
  251. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
  252. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
  253. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
  254. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
  255. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
  256. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
  257. } else if (dev->phy.rev == 1 ||
  258. (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
  259. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
  260. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
  261. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
  262. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
  263. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
  264. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
  265. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
  266. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
  267. } else {
  268. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
  269. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
  270. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
  271. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
  272. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
  273. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
  274. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
  275. b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
  276. }
  277. if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
  278. b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
  279. b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
  280. b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
  281. b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
  282. }
  283. if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
  284. (bus->chip_id == 0x5354) &&
  285. (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
  286. b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
  287. b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
  288. b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
  289. //FIXME the Broadcom driver caches & delays this HF write!
  290. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
  291. }
  292. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  293. b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
  294. b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
  295. b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
  296. b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
  297. b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
  298. b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
  299. b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
  300. b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
  301. } else { /* 5GHz */
  302. b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
  303. b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
  304. }
  305. if (dev->phy.rev == 1) {
  306. tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
  307. tmp2 = (tmp & 0x03E0) >> 5;
  308. tmp2 |= tmp2 << 5;
  309. b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
  310. tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
  311. tmp2 = (tmp & 0x1F00) >> 8;
  312. tmp2 |= tmp2 << 5;
  313. b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
  314. tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
  315. tmp2 = tmp & 0x00FF;
  316. tmp2 |= tmp << 8;
  317. b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
  318. }
  319. }
  320. static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
  321. {
  322. static const u16 addr[] = {
  323. B43_PHY_OFDM(0xC1),
  324. B43_PHY_OFDM(0xC2),
  325. B43_PHY_OFDM(0xC3),
  326. B43_PHY_OFDM(0xC4),
  327. B43_PHY_OFDM(0xC5),
  328. B43_PHY_OFDM(0xC6),
  329. B43_PHY_OFDM(0xC7),
  330. B43_PHY_OFDM(0xC8),
  331. B43_PHY_OFDM(0xCF),
  332. };
  333. static const u16 coefs[] = {
  334. 0xDE5E, 0xE832, 0xE331, 0x4D26,
  335. 0x0026, 0x1420, 0x0020, 0xFE08,
  336. 0x0008,
  337. };
  338. struct b43_phy_lp *lpphy = dev->phy.lp;
  339. int i;
  340. for (i = 0; i < ARRAY_SIZE(addr); i++) {
  341. lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
  342. b43_phy_write(dev, addr[i], coefs[i]);
  343. }
  344. }
  345. static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
  346. {
  347. static const u16 addr[] = {
  348. B43_PHY_OFDM(0xC1),
  349. B43_PHY_OFDM(0xC2),
  350. B43_PHY_OFDM(0xC3),
  351. B43_PHY_OFDM(0xC4),
  352. B43_PHY_OFDM(0xC5),
  353. B43_PHY_OFDM(0xC6),
  354. B43_PHY_OFDM(0xC7),
  355. B43_PHY_OFDM(0xC8),
  356. B43_PHY_OFDM(0xCF),
  357. };
  358. struct b43_phy_lp *lpphy = dev->phy.lp;
  359. int i;
  360. for (i = 0; i < ARRAY_SIZE(addr); i++)
  361. b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
  362. }
  363. static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
  364. {
  365. struct ssb_bus *bus = dev->dev->bus;
  366. struct b43_phy_lp *lpphy = dev->phy.lp;
  367. b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
  368. b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
  369. b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
  370. b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
  371. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
  372. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
  373. b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
  374. b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
  375. b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
  376. b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
  377. b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
  378. b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
  379. b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
  380. b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
  381. b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
  382. b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
  383. b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
  384. if (bus->boardinfo.rev >= 0x18) {
  385. b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
  386. b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
  387. } else {
  388. b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
  389. }
  390. b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
  391. b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
  392. b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
  393. b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
  394. b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
  395. b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
  396. b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
  397. b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
  398. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
  399. b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
  400. b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
  401. if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
  402. b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
  403. b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
  404. } else {
  405. b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
  406. b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
  407. }
  408. b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
  409. b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
  410. b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
  411. b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
  412. b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
  413. b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
  414. b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
  415. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
  416. b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
  417. b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
  418. if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
  419. b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
  420. b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
  421. }
  422. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  423. b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
  424. b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
  425. b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
  426. b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
  427. b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
  428. b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
  429. } else /* 5GHz */
  430. b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
  431. b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
  432. b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
  433. b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
  434. b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
  435. b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
  436. b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
  437. b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
  438. 0x2000 | ((u16)lpphy->rssi_gs << 10) |
  439. ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
  440. if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
  441. b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
  442. b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
  443. b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
  444. }
  445. lpphy_save_dig_flt_state(dev);
  446. }
  447. static void lpphy_baseband_init(struct b43_wldev *dev)
  448. {
  449. lpphy_table_init(dev);
  450. if (dev->phy.rev >= 2)
  451. lpphy_baseband_rev2plus_init(dev);
  452. else
  453. lpphy_baseband_rev0_1_init(dev);
  454. }
  455. struct b2062_freqdata {
  456. u16 freq;
  457. u8 data[6];
  458. };
  459. /* Initialize the 2062 radio. */
  460. static void lpphy_2062_init(struct b43_wldev *dev)
  461. {
  462. struct b43_phy_lp *lpphy = dev->phy.lp;
  463. struct ssb_bus *bus = dev->dev->bus;
  464. u32 crystalfreq, tmp, ref;
  465. unsigned int i;
  466. const struct b2062_freqdata *fd = NULL;
  467. static const struct b2062_freqdata freqdata_tab[] = {
  468. { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
  469. .data[3] = 6, .data[4] = 10, .data[5] = 6, },
  470. { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
  471. .data[3] = 4, .data[4] = 11, .data[5] = 7, },
  472. { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
  473. .data[3] = 3, .data[4] = 12, .data[5] = 7, },
  474. { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
  475. .data[3] = 3, .data[4] = 13, .data[5] = 8, },
  476. { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
  477. .data[3] = 2, .data[4] = 14, .data[5] = 8, },
  478. { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
  479. .data[3] = 1, .data[4] = 14, .data[5] = 9, },
  480. };
  481. b2062_upload_init_table(dev);
  482. b43_radio_write(dev, B2062_N_TX_CTL3, 0);
  483. b43_radio_write(dev, B2062_N_TX_CTL4, 0);
  484. b43_radio_write(dev, B2062_N_TX_CTL5, 0);
  485. b43_radio_write(dev, B2062_N_TX_CTL6, 0);
  486. b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
  487. b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
  488. b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
  489. b43_radio_write(dev, B2062_N_CALIB_TS, 0);
  490. if (dev->phy.rev > 0) {
  491. b43_radio_write(dev, B2062_S_BG_CTL1,
  492. (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
  493. }
  494. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  495. b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
  496. else
  497. b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
  498. /* Get the crystal freq, in Hz. */
  499. crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
  500. B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
  501. B43_WARN_ON(crystalfreq == 0);
  502. if (crystalfreq <= 30000000) {
  503. lpphy->pdiv = 1;
  504. b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
  505. } else {
  506. lpphy->pdiv = 2;
  507. b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
  508. }
  509. tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
  510. (2 * crystalfreq)) - 8) & 0xFF;
  511. b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
  512. tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
  513. (32000000 * lpphy->pdiv)) - 1) & 0xFF;
  514. b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
  515. tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
  516. (2000000 * lpphy->pdiv)) - 1) & 0xFF;
  517. b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
  518. ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
  519. ref &= 0xFFFF;
  520. for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
  521. if (ref < freqdata_tab[i].freq) {
  522. fd = &freqdata_tab[i];
  523. break;
  524. }
  525. }
  526. if (!fd)
  527. fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
  528. b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
  529. fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
  530. b43_radio_write(dev, B2062_S_RFPLL_CTL8,
  531. ((u16)(fd->data[1]) << 4) | fd->data[0]);
  532. b43_radio_write(dev, B2062_S_RFPLL_CTL9,
  533. ((u16)(fd->data[3]) << 4) | fd->data[2]);
  534. b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
  535. b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
  536. }
  537. /* Initialize the 2063 radio. */
  538. static void lpphy_2063_init(struct b43_wldev *dev)
  539. {
  540. b2063_upload_init_table(dev);
  541. b43_radio_write(dev, B2063_LOGEN_SP5, 0);
  542. b43_radio_set(dev, B2063_COMM8, 0x38);
  543. b43_radio_write(dev, B2063_REG_SP1, 0x56);
  544. b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
  545. b43_radio_write(dev, B2063_PA_SP7, 0);
  546. b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
  547. b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
  548. if (dev->phy.rev == 2) {
  549. b43_radio_write(dev, B2063_PA_SP3, 0xa0);
  550. b43_radio_write(dev, B2063_PA_SP4, 0xa0);
  551. b43_radio_write(dev, B2063_PA_SP2, 0x18);
  552. } else {
  553. b43_radio_write(dev, B2063_PA_SP3, 0x20);
  554. b43_radio_write(dev, B2063_PA_SP2, 0x20);
  555. }
  556. }
  557. struct lpphy_stx_table_entry {
  558. u16 phy_offset;
  559. u16 phy_shift;
  560. u16 rf_addr;
  561. u16 rf_shift;
  562. u16 mask;
  563. };
  564. static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
  565. { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
  566. { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
  567. { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
  568. { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
  569. { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
  570. { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
  571. { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
  572. { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
  573. { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
  574. { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
  575. { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
  576. { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
  577. { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
  578. { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
  579. { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
  580. { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
  581. { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
  582. { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
  583. { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
  584. { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
  585. { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
  586. { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
  587. { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
  588. { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
  589. { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
  590. { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
  591. { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
  592. { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
  593. { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
  594. };
  595. static void lpphy_sync_stx(struct b43_wldev *dev)
  596. {
  597. const struct lpphy_stx_table_entry *e;
  598. unsigned int i;
  599. u16 tmp;
  600. for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
  601. e = &lpphy_stx_table[i];
  602. tmp = b43_radio_read(dev, e->rf_addr);
  603. tmp >>= e->rf_shift;
  604. tmp <<= e->phy_shift;
  605. b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
  606. ~(e->mask << e->phy_shift), tmp);
  607. }
  608. }
  609. static void lpphy_radio_init(struct b43_wldev *dev)
  610. {
  611. /* The radio is attached through the 4wire bus. */
  612. b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
  613. udelay(1);
  614. b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
  615. udelay(1);
  616. if (dev->phy.radio_ver == 0x2062) {
  617. lpphy_2062_init(dev);
  618. } else {
  619. lpphy_2063_init(dev);
  620. lpphy_sync_stx(dev);
  621. b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
  622. b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
  623. if (dev->dev->bus->chip_id == 0x4325) {
  624. // TODO SSB PMU recalibration
  625. }
  626. }
  627. }
  628. struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
  629. static void lpphy_set_rc_cap(struct b43_wldev *dev)
  630. {
  631. struct b43_phy_lp *lpphy = dev->phy.lp;
  632. u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
  633. if (dev->phy.rev == 1) //FIXME check channel 14!
  634. rc_cap = min_t(u8, rc_cap + 5, 15);
  635. b43_radio_write(dev, B2062_N_RXBB_CALIB2,
  636. max_t(u8, lpphy->rc_cap - 4, 0x80));
  637. b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
  638. b43_radio_write(dev, B2062_S_RXG_CNT16,
  639. ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
  640. }
  641. static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
  642. {
  643. return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
  644. }
  645. static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
  646. {
  647. b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
  648. }
  649. static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
  650. {
  651. struct b43_phy_lp *lpphy = dev->phy.lp;
  652. if (user)
  653. lpphy->crs_usr_disable = 1;
  654. else
  655. lpphy->crs_sys_disable = 1;
  656. b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
  657. }
  658. static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
  659. {
  660. struct b43_phy_lp *lpphy = dev->phy.lp;
  661. if (user)
  662. lpphy->crs_usr_disable = 0;
  663. else
  664. lpphy->crs_sys_disable = 0;
  665. if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
  666. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  667. b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
  668. 0xFF1F, 0x60);
  669. else
  670. b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
  671. 0xFF1F, 0x20);
  672. }
  673. }
  674. static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
  675. {
  676. lpphy_set_deaf(dev, user);
  677. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
  678. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
  679. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
  680. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
  681. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
  682. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
  683. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
  684. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
  685. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
  686. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
  687. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
  688. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
  689. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
  690. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
  691. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
  692. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
  693. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
  694. b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
  695. b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
  696. b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
  697. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
  698. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
  699. b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
  700. b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
  701. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
  702. }
  703. static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
  704. {
  705. lpphy_clear_deaf(dev, user);
  706. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
  707. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
  708. }
  709. struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
  710. static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
  711. {
  712. struct lpphy_tx_gains gains;
  713. u16 tmp;
  714. gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
  715. if (dev->phy.rev < 2) {
  716. tmp = b43_phy_read(dev,
  717. B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
  718. gains.gm = tmp & 0x0007;
  719. gains.pga = (tmp & 0x0078) >> 3;
  720. gains.pad = (tmp & 0x780) >> 7;
  721. } else {
  722. tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
  723. gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
  724. gains.gm = tmp & 0xFF;
  725. gains.pga = (tmp >> 8) & 0xFF;
  726. }
  727. return gains;
  728. }
  729. static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
  730. {
  731. u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
  732. ctl |= dac << 7;
  733. b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
  734. }
  735. static void lpphy_set_tx_gains(struct b43_wldev *dev,
  736. struct lpphy_tx_gains gains)
  737. {
  738. u16 rf_gain, pa_gain;
  739. if (dev->phy.rev < 2) {
  740. rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
  741. b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
  742. 0xF800, rf_gain);
  743. } else {
  744. pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
  745. pa_gain <<= 2;
  746. b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
  747. (gains.pga << 8) | gains.gm);
  748. b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
  749. 0x8000, gains.pad | pa_gain);
  750. b43_phy_write(dev, B43_PHY_OFDM(0xFC),
  751. (gains.pga << 8) | gains.gm);
  752. b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
  753. 0x8000, gains.pad | pa_gain);
  754. }
  755. lpphy_set_dac_gain(dev, gains.dac);
  756. if (dev->phy.rev < 2) {
  757. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
  758. } else {
  759. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
  760. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
  761. }
  762. b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
  763. }
  764. static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
  765. {
  766. u16 trsw = gain & 0x1;
  767. u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
  768. u16 ext_lna = (gain & 2) >> 1;
  769. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
  770. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
  771. 0xFBFF, ext_lna << 10);
  772. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
  773. 0xF7FF, ext_lna << 11);
  774. b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
  775. }
  776. static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
  777. {
  778. u16 low_gain = gain & 0xFFFF;
  779. u16 high_gain = (gain >> 16) & 0xF;
  780. u16 ext_lna = (gain >> 21) & 0x1;
  781. u16 trsw = ~(gain >> 20) & 0x1;
  782. u16 tmp;
  783. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
  784. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
  785. 0xFDFF, ext_lna << 9);
  786. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
  787. 0xFBFF, ext_lna << 10);
  788. b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
  789. b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
  790. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  791. tmp = (gain >> 2) & 0x3;
  792. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
  793. 0xE7FF, tmp<<11);
  794. b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
  795. }
  796. }
  797. static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
  798. {
  799. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
  800. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
  801. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
  802. if (dev->phy.rev >= 2) {
  803. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
  804. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  805. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
  806. b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
  807. }
  808. } else {
  809. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
  810. }
  811. }
  812. static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
  813. {
  814. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
  815. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
  816. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
  817. if (dev->phy.rev >= 2) {
  818. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
  819. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  820. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
  821. b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
  822. }
  823. } else {
  824. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
  825. }
  826. }
  827. static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
  828. {
  829. if (dev->phy.rev < 2)
  830. lpphy_rev0_1_set_rx_gain(dev, gain);
  831. else
  832. lpphy_rev2plus_set_rx_gain(dev, gain);
  833. lpphy_enable_rx_gain_override(dev);
  834. }
  835. static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
  836. {
  837. u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
  838. lpphy_set_rx_gain(dev, gain);
  839. }
  840. static void lpphy_stop_ddfs(struct b43_wldev *dev)
  841. {
  842. b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
  843. b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
  844. }
  845. static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
  846. int incr1, int incr2, int scale_idx)
  847. {
  848. lpphy_stop_ddfs(dev);
  849. b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
  850. b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
  851. b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
  852. b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
  853. b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
  854. b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
  855. b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
  856. b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
  857. b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
  858. b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
  859. }
  860. static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
  861. struct lpphy_iq_est *iq_est)
  862. {
  863. int i;
  864. b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
  865. b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
  866. b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
  867. b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
  868. b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
  869. for (i = 0; i < 500; i++) {
  870. if (!(b43_phy_read(dev,
  871. B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
  872. break;
  873. msleep(1);
  874. }
  875. if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
  876. b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
  877. return false;
  878. }
  879. iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
  880. iq_est->iq_prod <<= 16;
  881. iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
  882. iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
  883. iq_est->i_pwr <<= 16;
  884. iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
  885. iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
  886. iq_est->q_pwr <<= 16;
  887. iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
  888. b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
  889. return true;
  890. }
  891. static int lpphy_loopback(struct b43_wldev *dev)
  892. {
  893. struct lpphy_iq_est iq_est;
  894. int i, index = -1;
  895. u32 tmp;
  896. memset(&iq_est, 0, sizeof(iq_est));
  897. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
  898. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
  899. b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
  900. b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
  901. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
  902. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
  903. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
  904. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
  905. b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
  906. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
  907. b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
  908. for (i = 0; i < 32; i++) {
  909. lpphy_set_rx_gain_by_index(dev, i);
  910. lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
  911. if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
  912. continue;
  913. tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
  914. if ((tmp > 4000) && (tmp < 10000)) {
  915. index = i;
  916. break;
  917. }
  918. }
  919. lpphy_stop_ddfs(dev);
  920. return index;
  921. }
  922. /* Fixed-point division algorithm using only integer math. */
  923. static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
  924. {
  925. u32 quotient, remainder;
  926. if (divisor == 0)
  927. return 0;
  928. quotient = dividend / divisor;
  929. remainder = dividend % divisor;
  930. while (precision > 0) {
  931. quotient <<= 1;
  932. if (remainder << 1 >= divisor) {
  933. quotient++;
  934. remainder = (remainder << 1) - divisor;
  935. }
  936. precision--;
  937. }
  938. if (remainder << 1 >= divisor)
  939. quotient++;
  940. return quotient;
  941. }
  942. /* Read the TX power control mode from hardware. */
  943. static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
  944. {
  945. struct b43_phy_lp *lpphy = dev->phy.lp;
  946. u16 ctl;
  947. ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
  948. switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
  949. case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
  950. lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
  951. break;
  952. case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
  953. lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
  954. break;
  955. case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
  956. lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
  957. break;
  958. default:
  959. lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
  960. B43_WARN_ON(1);
  961. break;
  962. }
  963. }
  964. /* Set the TX power control mode in hardware. */
  965. static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
  966. {
  967. struct b43_phy_lp *lpphy = dev->phy.lp;
  968. u16 ctl;
  969. switch (lpphy->txpctl_mode) {
  970. case B43_LPPHY_TXPCTL_OFF:
  971. ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
  972. break;
  973. case B43_LPPHY_TXPCTL_HW:
  974. ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
  975. break;
  976. case B43_LPPHY_TXPCTL_SW:
  977. ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
  978. break;
  979. default:
  980. ctl = 0;
  981. B43_WARN_ON(1);
  982. }
  983. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
  984. (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
  985. }
  986. static void lpphy_set_tx_power_control(struct b43_wldev *dev,
  987. enum b43_lpphy_txpctl_mode mode)
  988. {
  989. struct b43_phy_lp *lpphy = dev->phy.lp;
  990. enum b43_lpphy_txpctl_mode oldmode;
  991. lpphy_read_tx_pctl_mode_from_hardware(dev);
  992. oldmode = lpphy->txpctl_mode;
  993. if (oldmode == mode)
  994. return;
  995. lpphy->txpctl_mode = mode;
  996. if (oldmode == B43_LPPHY_TXPCTL_HW) {
  997. //TODO Update TX Power NPT
  998. //TODO Clear all TX Power offsets
  999. } else {
  1000. if (mode == B43_LPPHY_TXPCTL_HW) {
  1001. //TODO Recalculate target TX power
  1002. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
  1003. 0xFF80, lpphy->tssi_idx);
  1004. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
  1005. 0x8FFF, ((u16)lpphy->tssi_npt << 16));
  1006. //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
  1007. //TODO Disable TX gain override
  1008. lpphy->tx_pwr_idx_over = -1;
  1009. }
  1010. }
  1011. if (dev->phy.rev >= 2) {
  1012. if (mode == B43_LPPHY_TXPCTL_HW)
  1013. b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
  1014. else
  1015. b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
  1016. }
  1017. lpphy_write_tx_pctl_mode_to_hardware(dev);
  1018. }
  1019. static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
  1020. unsigned int new_channel);
  1021. static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
  1022. {
  1023. struct b43_phy_lp *lpphy = dev->phy.lp;
  1024. struct lpphy_iq_est iq_est;
  1025. struct lpphy_tx_gains tx_gains;
  1026. static const u32 ideal_pwr_table[21] = {
  1027. 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
  1028. 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
  1029. 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
  1030. 0x0004c, 0x0002c, 0x0001a,
  1031. };
  1032. bool old_txg_ovr;
  1033. u8 old_bbmult;
  1034. u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
  1035. old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
  1036. enum b43_lpphy_txpctl_mode old_txpctl;
  1037. u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
  1038. int loopback, i, j, inner_sum, err;
  1039. memset(&iq_est, 0, sizeof(iq_est));
  1040. err = b43_lpphy_op_switch_channel(dev, 7);
  1041. if (err) {
  1042. b43dbg(dev->wl,
  1043. "RC calib: Failed to switch to channel 7, error = %d\n",
  1044. err);
  1045. }
  1046. old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
  1047. old_bbmult = lpphy_get_bb_mult(dev);
  1048. if (old_txg_ovr)
  1049. tx_gains = lpphy_get_tx_gains(dev);
  1050. old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
  1051. old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
  1052. old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
  1053. old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
  1054. old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
  1055. old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
  1056. old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
  1057. lpphy_read_tx_pctl_mode_from_hardware(dev);
  1058. old_txpctl = lpphy->txpctl_mode;
  1059. lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
  1060. lpphy_disable_crs(dev, true);
  1061. loopback = lpphy_loopback(dev);
  1062. if (loopback == -1)
  1063. goto finish;
  1064. lpphy_set_rx_gain_by_index(dev, loopback);
  1065. b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
  1066. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
  1067. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
  1068. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
  1069. for (i = 128; i <= 159; i++) {
  1070. b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
  1071. inner_sum = 0;
  1072. for (j = 5; j <= 25; j++) {
  1073. lpphy_run_ddfs(dev, 1, 1, j, j, 0);
  1074. if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
  1075. goto finish;
  1076. mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
  1077. if (j == 5)
  1078. tmp = mean_sq_pwr;
  1079. ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
  1080. normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
  1081. mean_sq_pwr = ideal_pwr - normal_pwr;
  1082. mean_sq_pwr *= mean_sq_pwr;
  1083. inner_sum += mean_sq_pwr;
  1084. if ((i == 128) || (inner_sum < mean_sq_pwr_min)) {
  1085. lpphy->rc_cap = i;
  1086. mean_sq_pwr_min = inner_sum;
  1087. }
  1088. }
  1089. }
  1090. lpphy_stop_ddfs(dev);
  1091. finish:
  1092. lpphy_restore_crs(dev, true);
  1093. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
  1094. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
  1095. b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
  1096. b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
  1097. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
  1098. b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
  1099. b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
  1100. lpphy_set_bb_mult(dev, old_bbmult);
  1101. if (old_txg_ovr) {
  1102. /*
  1103. * SPEC FIXME: The specs say "get_tx_gains" here, which is
  1104. * illogical. According to lwfinger, vendor driver v4.150.10.5
  1105. * has a Set here, while v4.174.64.19 has a Get - regression in
  1106. * the vendor driver? This should be tested this once the code
  1107. * is testable.
  1108. */
  1109. lpphy_set_tx_gains(dev, tx_gains);
  1110. }
  1111. lpphy_set_tx_power_control(dev, old_txpctl);
  1112. if (lpphy->rc_cap)
  1113. lpphy_set_rc_cap(dev);
  1114. }
  1115. static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
  1116. {
  1117. struct ssb_bus *bus = dev->dev->bus;
  1118. u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
  1119. u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
  1120. int i;
  1121. b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
  1122. b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
  1123. b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
  1124. b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
  1125. b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
  1126. b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
  1127. b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
  1128. b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
  1129. b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
  1130. for (i = 0; i < 10000; i++) {
  1131. if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
  1132. break;
  1133. msleep(1);
  1134. }
  1135. if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
  1136. b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
  1137. tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
  1138. b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
  1139. b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
  1140. b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
  1141. b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
  1142. b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
  1143. if (crystal_freq == 24000000) {
  1144. b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
  1145. b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
  1146. } else {
  1147. b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
  1148. b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
  1149. }
  1150. b43_radio_write(dev, B2063_PA_SP7, 0x7D);
  1151. for (i = 0; i < 10000; i++) {
  1152. if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
  1153. break;
  1154. msleep(1);
  1155. }
  1156. if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
  1157. b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
  1158. b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
  1159. }
  1160. static void lpphy_calibrate_rc(struct b43_wldev *dev)
  1161. {
  1162. struct b43_phy_lp *lpphy = dev->phy.lp;
  1163. if (dev->phy.rev >= 2) {
  1164. lpphy_rev2plus_rc_calib(dev);
  1165. } else if (!lpphy->rc_cap) {
  1166. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  1167. lpphy_rev0_1_rc_calib(dev);
  1168. } else {
  1169. lpphy_set_rc_cap(dev);
  1170. }
  1171. }
  1172. static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
  1173. {
  1174. struct b43_phy_lp *lpphy = dev->phy.lp;
  1175. lpphy->tx_pwr_idx_over = index;
  1176. if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
  1177. lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
  1178. //TODO
  1179. }
  1180. static void lpphy_btcoex_override(struct b43_wldev *dev)
  1181. {
  1182. b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
  1183. b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
  1184. }
  1185. static void lpphy_pr41573_workaround(struct b43_wldev *dev)
  1186. {
  1187. struct b43_phy_lp *lpphy = dev->phy.lp;
  1188. u32 *saved_tab;
  1189. const unsigned int saved_tab_size = 256;
  1190. enum b43_lpphy_txpctl_mode txpctl_mode;
  1191. s8 tx_pwr_idx_over;
  1192. u16 tssi_npt, tssi_idx;
  1193. saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
  1194. if (!saved_tab) {
  1195. b43err(dev->wl, "PR41573 failed. Out of memory!\n");
  1196. return;
  1197. }
  1198. lpphy_read_tx_pctl_mode_from_hardware(dev);
  1199. txpctl_mode = lpphy->txpctl_mode;
  1200. tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
  1201. tssi_npt = lpphy->tssi_npt;
  1202. tssi_idx = lpphy->tssi_idx;
  1203. if (dev->phy.rev < 2) {
  1204. b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
  1205. saved_tab_size, saved_tab);
  1206. } else {
  1207. b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
  1208. saved_tab_size, saved_tab);
  1209. }
  1210. //TODO
  1211. kfree(saved_tab);
  1212. }
  1213. static void lpphy_calibration(struct b43_wldev *dev)
  1214. {
  1215. struct b43_phy_lp *lpphy = dev->phy.lp;
  1216. enum b43_lpphy_txpctl_mode saved_pctl_mode;
  1217. b43_mac_suspend(dev);
  1218. lpphy_btcoex_override(dev);
  1219. lpphy_read_tx_pctl_mode_from_hardware(dev);
  1220. saved_pctl_mode = lpphy->txpctl_mode;
  1221. lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
  1222. //TODO Perform transmit power table I/Q LO calibration
  1223. if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
  1224. lpphy_pr41573_workaround(dev);
  1225. //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
  1226. lpphy_set_tx_power_control(dev, saved_pctl_mode);
  1227. //TODO Perform I/Q calibration with a single control value set
  1228. b43_mac_enable(dev);
  1229. }
  1230. static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
  1231. {
  1232. if (mode != TSSI_MUX_EXT) {
  1233. b43_radio_set(dev, B2063_PA_SP1, 0x2);
  1234. b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
  1235. b43_radio_write(dev, B2063_PA_CTL10, 0x51);
  1236. if (mode == TSSI_MUX_POSTPA) {
  1237. b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
  1238. b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
  1239. } else {
  1240. b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
  1241. b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
  1242. 0xFFC7, 0x20);
  1243. }
  1244. } else {
  1245. B43_WARN_ON(1);
  1246. }
  1247. }
  1248. static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
  1249. {
  1250. u16 tmp;
  1251. int i;
  1252. //SPEC TODO Call LP PHY Clear TX Power offsets
  1253. for (i = 0; i < 64; i++) {
  1254. if (dev->phy.rev >= 2)
  1255. b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
  1256. else
  1257. b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
  1258. }
  1259. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
  1260. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
  1261. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
  1262. if (dev->phy.rev < 2) {
  1263. b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
  1264. b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
  1265. } else {
  1266. b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
  1267. b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
  1268. b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
  1269. b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
  1270. lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
  1271. }
  1272. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
  1273. b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
  1274. b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
  1275. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
  1276. (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
  1277. B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
  1278. b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
  1279. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
  1280. (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
  1281. B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
  1282. if (dev->phy.rev < 2) {
  1283. b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
  1284. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
  1285. } else {
  1286. lpphy_set_tx_power_by_index(dev, 0x7F);
  1287. }
  1288. b43_dummy_transmission(dev, true, true);
  1289. tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
  1290. if (tmp & 0x8000) {
  1291. b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
  1292. 0xFFC0, (tmp & 0xFF) - 32);
  1293. }
  1294. b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
  1295. // (SPEC?) TODO Set "Target TX frequency" variable to 0
  1296. // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
  1297. }
  1298. static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
  1299. {
  1300. struct lpphy_tx_gains gains;
  1301. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  1302. gains.gm = 4;
  1303. gains.pad = 12;
  1304. gains.pga = 12;
  1305. gains.dac = 0;
  1306. } else {
  1307. gains.gm = 7;
  1308. gains.pad = 14;
  1309. gains.pga = 15;
  1310. gains.dac = 0;
  1311. }
  1312. lpphy_set_tx_gains(dev, gains);
  1313. lpphy_set_bb_mult(dev, 150);
  1314. }
  1315. /* Initialize TX power control */
  1316. static void lpphy_tx_pctl_init(struct b43_wldev *dev)
  1317. {
  1318. if (0/*FIXME HWPCTL capable */) {
  1319. lpphy_tx_pctl_init_hw(dev);
  1320. } else { /* This device is only software TX power control capable. */
  1321. lpphy_tx_pctl_init_sw(dev);
  1322. }
  1323. }
  1324. static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
  1325. {
  1326. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  1327. return b43_read16(dev, B43_MMIO_PHY_DATA);
  1328. }
  1329. static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
  1330. {
  1331. b43_write32(dev, B43_MMIO_PHY_CONTROL, ((u32)value << 16) | reg);
  1332. }
  1333. static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
  1334. u16 set)
  1335. {
  1336. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  1337. b43_write16(dev, B43_MMIO_PHY_DATA,
  1338. (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
  1339. }
  1340. static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
  1341. {
  1342. /* Register 1 is a 32-bit register. */
  1343. B43_WARN_ON(reg == 1);
  1344. /* LP-PHY needs a special bit set for read access */
  1345. if (dev->phy.rev < 2) {
  1346. if (reg != 0x4001)
  1347. reg |= 0x100;
  1348. } else
  1349. reg |= 0x200;
  1350. b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
  1351. return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
  1352. }
  1353. static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
  1354. {
  1355. /* Register 1 is a 32-bit register. */
  1356. B43_WARN_ON(reg == 1);
  1357. b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
  1358. b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
  1359. }
  1360. static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
  1361. bool blocked)
  1362. {
  1363. //TODO
  1364. }
  1365. struct b206x_channel {
  1366. u8 channel;
  1367. u16 freq;
  1368. u8 data[12];
  1369. };
  1370. static const struct b206x_channel b2062_chantbl[] = {
  1371. { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
  1372. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1373. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1374. { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
  1375. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1376. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1377. { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
  1378. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1379. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1380. { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
  1381. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1382. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1383. { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
  1384. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1385. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1386. { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
  1387. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1388. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1389. { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
  1390. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1391. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1392. { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
  1393. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1394. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1395. { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
  1396. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1397. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1398. { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
  1399. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1400. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1401. { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
  1402. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1403. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1404. { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
  1405. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1406. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1407. { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
  1408. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1409. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1410. { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
  1411. .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
  1412. .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
  1413. { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
  1414. .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
  1415. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1416. { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
  1417. .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1418. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1419. { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
  1420. .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1421. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1422. { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
  1423. .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1424. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1425. { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
  1426. .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1427. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1428. { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
  1429. .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
  1430. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1431. { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
  1432. .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1433. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1434. { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
  1435. .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1436. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1437. { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
  1438. .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1439. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1440. { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
  1441. .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
  1442. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1443. { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
  1444. .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
  1445. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1446. { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
  1447. .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
  1448. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1449. { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
  1450. .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
  1451. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1452. { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
  1453. .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
  1454. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1455. { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
  1456. .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
  1457. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1458. { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
  1459. .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
  1460. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1461. { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
  1462. .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
  1463. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1464. { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
  1465. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1466. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1467. { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
  1468. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1469. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1470. { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
  1471. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1472. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1473. { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
  1474. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1475. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1476. { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
  1477. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1478. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1479. { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
  1480. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1481. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1482. { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
  1483. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1484. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1485. { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
  1486. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1487. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1488. { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
  1489. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1490. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1491. { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
  1492. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1493. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1494. { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
  1495. .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
  1496. .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
  1497. { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
  1498. .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
  1499. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1500. { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
  1501. .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
  1502. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1503. { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
  1504. .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
  1505. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1506. { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
  1507. .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
  1508. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1509. { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
  1510. .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
  1511. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1512. { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
  1513. .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
  1514. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1515. { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
  1516. .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
  1517. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
  1518. { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
  1519. .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
  1520. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1521. { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
  1522. .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
  1523. .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
  1524. };
  1525. static const struct b206x_channel b2063_chantbl[] = {
  1526. { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
  1527. .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1528. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1529. .data[10] = 0x80, .data[11] = 0x70, },
  1530. { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
  1531. .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1532. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1533. .data[10] = 0x80, .data[11] = 0x70, },
  1534. { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
  1535. .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1536. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1537. .data[10] = 0x80, .data[11] = 0x70, },
  1538. { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
  1539. .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1540. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1541. .data[10] = 0x80, .data[11] = 0x70, },
  1542. { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
  1543. .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1544. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1545. .data[10] = 0x80, .data[11] = 0x70, },
  1546. { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
  1547. .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1548. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1549. .data[10] = 0x80, .data[11] = 0x70, },
  1550. { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
  1551. .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1552. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1553. .data[10] = 0x80, .data[11] = 0x70, },
  1554. { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
  1555. .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1556. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1557. .data[10] = 0x80, .data[11] = 0x70, },
  1558. { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
  1559. .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1560. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1561. .data[10] = 0x80, .data[11] = 0x70, },
  1562. { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
  1563. .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1564. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1565. .data[10] = 0x80, .data[11] = 0x70, },
  1566. { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
  1567. .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1568. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1569. .data[10] = 0x80, .data[11] = 0x70, },
  1570. { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
  1571. .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1572. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1573. .data[10] = 0x80, .data[11] = 0x70, },
  1574. { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
  1575. .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1576. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1577. .data[10] = 0x80, .data[11] = 0x70, },
  1578. { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
  1579. .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
  1580. .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
  1581. .data[10] = 0x80, .data[11] = 0x70, },
  1582. { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
  1583. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
  1584. .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
  1585. .data[10] = 0x20, .data[11] = 0x00, },
  1586. { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
  1587. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
  1588. .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
  1589. .data[10] = 0x20, .data[11] = 0x00, },
  1590. { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
  1591. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
  1592. .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
  1593. .data[10] = 0x20, .data[11] = 0x00, },
  1594. { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
  1595. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
  1596. .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
  1597. .data[10] = 0x20, .data[11] = 0x00, },
  1598. { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
  1599. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
  1600. .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
  1601. .data[10] = 0x20, .data[11] = 0x00, },
  1602. { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
  1603. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
  1604. .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
  1605. .data[10] = 0x20, .data[11] = 0x00, },
  1606. { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
  1607. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
  1608. .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
  1609. .data[10] = 0x20, .data[11] = 0x00, },
  1610. { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
  1611. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
  1612. .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
  1613. .data[10] = 0x20, .data[11] = 0x00, },
  1614. { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
  1615. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
  1616. .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
  1617. .data[10] = 0x20, .data[11] = 0x00, },
  1618. { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
  1619. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
  1620. .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
  1621. .data[10] = 0x10, .data[11] = 0x00, },
  1622. { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
  1623. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
  1624. .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
  1625. .data[10] = 0x10, .data[11] = 0x00, },
  1626. { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
  1627. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1628. .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
  1629. .data[10] = 0x10, .data[11] = 0x00, },
  1630. { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
  1631. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1632. .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
  1633. .data[10] = 0x00, .data[11] = 0x00, },
  1634. { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
  1635. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1636. .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
  1637. .data[10] = 0x00, .data[11] = 0x00, },
  1638. { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
  1639. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1640. .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
  1641. .data[10] = 0x00, .data[11] = 0x00, },
  1642. { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
  1643. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1644. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
  1645. .data[10] = 0x00, .data[11] = 0x00, },
  1646. { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
  1647. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1648. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
  1649. .data[10] = 0x00, .data[11] = 0x00, },
  1650. { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
  1651. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1652. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1653. .data[10] = 0x00, .data[11] = 0x00, },
  1654. { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
  1655. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1656. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1657. .data[10] = 0x00, .data[11] = 0x00, },
  1658. { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
  1659. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1660. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1661. .data[10] = 0x00, .data[11] = 0x00, },
  1662. { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
  1663. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1664. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1665. .data[10] = 0x00, .data[11] = 0x00, },
  1666. { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
  1667. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1668. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1669. .data[10] = 0x00, .data[11] = 0x00, },
  1670. { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
  1671. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1672. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1673. .data[10] = 0x00, .data[11] = 0x00, },
  1674. { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
  1675. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1676. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1677. .data[10] = 0x00, .data[11] = 0x00, },
  1678. { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
  1679. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1680. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1681. .data[10] = 0x00, .data[11] = 0x00, },
  1682. { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
  1683. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1684. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1685. .data[10] = 0x00, .data[11] = 0x00, },
  1686. { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
  1687. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1688. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1689. .data[10] = 0x00, .data[11] = 0x00, },
  1690. { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
  1691. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
  1692. .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
  1693. .data[10] = 0x00, .data[11] = 0x00, },
  1694. { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
  1695. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
  1696. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
  1697. .data[10] = 0x50, .data[11] = 0x00, },
  1698. { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
  1699. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
  1700. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
  1701. .data[10] = 0x50, .data[11] = 0x00, },
  1702. { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
  1703. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
  1704. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
  1705. .data[10] = 0x50, .data[11] = 0x00, },
  1706. { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
  1707. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
  1708. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
  1709. .data[10] = 0x40, .data[11] = 0x00, },
  1710. { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
  1711. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
  1712. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
  1713. .data[10] = 0x40, .data[11] = 0x00, },
  1714. { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
  1715. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
  1716. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
  1717. .data[10] = 0x40, .data[11] = 0x00, },
  1718. { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
  1719. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
  1720. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
  1721. .data[10] = 0x40, .data[11] = 0x00, },
  1722. { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
  1723. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
  1724. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
  1725. .data[10] = 0x40, .data[11] = 0x00, },
  1726. { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
  1727. .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
  1728. .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
  1729. .data[10] = 0x40, .data[11] = 0x00, },
  1730. };
  1731. static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
  1732. {
  1733. struct ssb_bus *bus = dev->dev->bus;
  1734. b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
  1735. udelay(20);
  1736. if (bus->chip_id == 0x5354) {
  1737. b43_radio_write(dev, B2062_N_COMM1, 4);
  1738. b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
  1739. } else {
  1740. b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
  1741. }
  1742. udelay(5);
  1743. }
  1744. static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
  1745. {
  1746. b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42);
  1747. b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62);
  1748. udelay(200);
  1749. }
  1750. static int lpphy_b2062_tune(struct b43_wldev *dev,
  1751. unsigned int channel)
  1752. {
  1753. struct b43_phy_lp *lpphy = dev->phy.lp;
  1754. struct ssb_bus *bus = dev->dev->bus;
  1755. const struct b206x_channel *chandata = NULL;
  1756. u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
  1757. u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
  1758. int i, err = 0;
  1759. for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
  1760. if (b2062_chantbl[i].channel == channel) {
  1761. chandata = &b2062_chantbl[i];
  1762. break;
  1763. }
  1764. }
  1765. if (B43_WARN_ON(!chandata))
  1766. return -EINVAL;
  1767. b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
  1768. b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
  1769. b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
  1770. b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
  1771. b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
  1772. b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
  1773. b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
  1774. b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
  1775. b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
  1776. b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
  1777. tmp1 = crystal_freq / 1000;
  1778. tmp2 = lpphy->pdiv * 1000;
  1779. b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
  1780. b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
  1781. lpphy_b2062_reset_pll_bias(dev);
  1782. tmp3 = tmp2 * channel2freq_lp(channel);
  1783. if (channel2freq_lp(channel) < 4000)
  1784. tmp3 *= 2;
  1785. tmp4 = 48 * tmp1;
  1786. tmp6 = tmp3 / tmp4;
  1787. tmp7 = tmp3 % tmp4;
  1788. b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
  1789. tmp5 = tmp7 * 0x100;
  1790. tmp6 = tmp5 / tmp4;
  1791. tmp7 = tmp5 % tmp4;
  1792. b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
  1793. tmp5 = tmp7 * 0x100;
  1794. tmp6 = tmp5 / tmp4;
  1795. tmp7 = tmp5 % tmp4;
  1796. b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
  1797. tmp5 = tmp7 * 0x100;
  1798. tmp6 = tmp5 / tmp4;
  1799. tmp7 = tmp5 % tmp4;
  1800. b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
  1801. tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19);
  1802. tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
  1803. b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
  1804. b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
  1805. lpphy_b2062_vco_calib(dev);
  1806. if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
  1807. b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
  1808. b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
  1809. lpphy_b2062_reset_pll_bias(dev);
  1810. lpphy_b2062_vco_calib(dev);
  1811. if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
  1812. err = -EIO;
  1813. }
  1814. b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
  1815. return err;
  1816. }
  1817. /* This was previously called lpphy_japan_filter */
  1818. static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
  1819. {
  1820. struct b43_phy_lp *lpphy = dev->phy.lp;
  1821. u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
  1822. if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
  1823. b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
  1824. if ((dev->phy.rev == 1) && (lpphy->rc_cap))
  1825. lpphy_set_rc_cap(dev);
  1826. } else {
  1827. b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
  1828. }
  1829. }
  1830. static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
  1831. {
  1832. u16 tmp;
  1833. b43_radio_mask(dev, B2063_PLL_SP1, ~0x40);
  1834. tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
  1835. b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
  1836. udelay(1);
  1837. b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
  1838. udelay(1);
  1839. b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
  1840. udelay(1);
  1841. b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
  1842. udelay(300);
  1843. b43_radio_set(dev, B2063_PLL_SP1, 0x40);
  1844. }
  1845. static int lpphy_b2063_tune(struct b43_wldev *dev,
  1846. unsigned int channel)
  1847. {
  1848. struct ssb_bus *bus = dev->dev->bus;
  1849. static const struct b206x_channel *chandata = NULL;
  1850. u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
  1851. u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
  1852. u16 old_comm15, scale;
  1853. u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
  1854. int i, div = (crystal_freq <= 26000000 ? 1 : 2);
  1855. for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
  1856. if (b2063_chantbl[i].channel == channel) {
  1857. chandata = &b2063_chantbl[i];
  1858. break;
  1859. }
  1860. }
  1861. if (B43_WARN_ON(!chandata))
  1862. return -EINVAL;
  1863. b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
  1864. b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
  1865. b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
  1866. b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
  1867. b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
  1868. b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
  1869. b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
  1870. b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
  1871. b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
  1872. b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
  1873. b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
  1874. b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
  1875. old_comm15 = b43_radio_read(dev, B2063_COMM15);
  1876. b43_radio_set(dev, B2063_COMM15, 0x1E);
  1877. if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
  1878. vco_freq = chandata->freq << 1;
  1879. else
  1880. vco_freq = chandata->freq << 2;
  1881. freqref = crystal_freq * 3;
  1882. val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
  1883. val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
  1884. val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
  1885. timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
  1886. b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
  1887. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
  1888. 0xFFF8, timeout >> 2);
  1889. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
  1890. 0xFF9F,timeout << 5);
  1891. timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
  1892. 999999) / 1000000) + 1;
  1893. b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
  1894. count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
  1895. count *= (timeout + 1) * (timeoutref + 1);
  1896. count--;
  1897. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
  1898. 0xF0, count >> 8);
  1899. b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
  1900. tmp1 = ((val3 * 62500) / freqref) << 4;
  1901. tmp2 = ((val3 * 62500) % freqref) << 4;
  1902. while (tmp2 >= freqref) {
  1903. tmp1++;
  1904. tmp2 -= freqref;
  1905. }
  1906. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
  1907. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
  1908. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
  1909. b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
  1910. b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
  1911. b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
  1912. b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
  1913. b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
  1914. b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
  1915. tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
  1916. tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
  1917. if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
  1918. scale = 1;
  1919. tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
  1920. } else {
  1921. scale = 0;
  1922. tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
  1923. }
  1924. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
  1925. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
  1926. tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
  1927. tmp6 *= (tmp5 * 8) * (scale + 1);
  1928. if (tmp6 > 150)
  1929. tmp6 = 0;
  1930. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
  1931. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
  1932. b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
  1933. if (crystal_freq > 26000000)
  1934. b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
  1935. else
  1936. b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
  1937. if (val1 == 45)
  1938. b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
  1939. else
  1940. b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
  1941. b43_radio_set(dev, B2063_PLL_SP2, 0x3);
  1942. udelay(1);
  1943. b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC);
  1944. lpphy_b2063_vco_calib(dev);
  1945. b43_radio_write(dev, B2063_COMM15, old_comm15);
  1946. return 0;
  1947. }
  1948. static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
  1949. unsigned int new_channel)
  1950. {
  1951. struct b43_phy_lp *lpphy = dev->phy.lp;
  1952. int err;
  1953. if (dev->phy.radio_ver == 0x2063) {
  1954. err = lpphy_b2063_tune(dev, new_channel);
  1955. if (err)
  1956. return err;
  1957. } else {
  1958. err = lpphy_b2062_tune(dev, new_channel);
  1959. if (err)
  1960. return err;
  1961. lpphy_set_analog_filter(dev, new_channel);
  1962. lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
  1963. }
  1964. lpphy->channel = new_channel;
  1965. b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
  1966. return 0;
  1967. }
  1968. static int b43_lpphy_op_init(struct b43_wldev *dev)
  1969. {
  1970. int err;
  1971. lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
  1972. lpphy_baseband_init(dev);
  1973. lpphy_radio_init(dev);
  1974. lpphy_calibrate_rc(dev);
  1975. err = b43_lpphy_op_switch_channel(dev, 7);
  1976. if (err) {
  1977. b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n",
  1978. err);
  1979. }
  1980. lpphy_tx_pctl_init(dev);
  1981. lpphy_calibration(dev);
  1982. //TODO ACI init
  1983. return 0;
  1984. }
  1985. static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
  1986. {
  1987. //TODO
  1988. }
  1989. static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
  1990. {
  1991. //TODO
  1992. }
  1993. static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
  1994. bool ignore_tssi)
  1995. {
  1996. //TODO
  1997. return B43_TXPWR_RES_DONE;
  1998. }
  1999. const struct b43_phy_operations b43_phyops_lp = {
  2000. .allocate = b43_lpphy_op_allocate,
  2001. .free = b43_lpphy_op_free,
  2002. .prepare_structs = b43_lpphy_op_prepare_structs,
  2003. .init = b43_lpphy_op_init,
  2004. .phy_read = b43_lpphy_op_read,
  2005. .phy_write = b43_lpphy_op_write,
  2006. .phy_maskset = b43_lpphy_op_maskset,
  2007. .radio_read = b43_lpphy_op_radio_read,
  2008. .radio_write = b43_lpphy_op_radio_write,
  2009. .software_rfkill = b43_lpphy_op_software_rfkill,
  2010. .switch_analog = b43_phyop_switch_analog_generic,
  2011. .switch_channel = b43_lpphy_op_switch_channel,
  2012. .get_default_chan = b43_lpphy_op_get_default_chan,
  2013. .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
  2014. .recalc_txpower = b43_lpphy_op_recalc_txpower,
  2015. .adjust_txpower = b43_lpphy_op_adjust_txpower,
  2016. };