clock.c 21 KB

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  1. /* linux/arch/arm/mach-s5pv310/clock.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * S5PV310 - Clock support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/err.h>
  14. #include <linux/io.h>
  15. #include <plat/cpu-freq.h>
  16. #include <plat/clock.h>
  17. #include <plat/cpu.h>
  18. #include <plat/pll.h>
  19. #include <plat/s5p-clock.h>
  20. #include <plat/clock-clksrc.h>
  21. #include <mach/map.h>
  22. #include <mach/regs-clock.h>
  23. static struct clk clk_sclk_hdmi27m = {
  24. .name = "sclk_hdmi27m",
  25. .id = -1,
  26. .rate = 27000000,
  27. };
  28. static struct clk clk_sclk_hdmiphy = {
  29. .name = "sclk_hdmiphy",
  30. .id = -1,
  31. };
  32. static struct clk clk_sclk_usbphy0 = {
  33. .name = "sclk_usbphy0",
  34. .id = -1,
  35. .rate = 27000000,
  36. };
  37. static struct clk clk_sclk_usbphy1 = {
  38. .name = "sclk_usbphy1",
  39. .id = -1,
  40. };
  41. static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  42. {
  43. return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
  44. }
  45. static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
  46. {
  47. return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
  48. }
  49. static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
  50. {
  51. return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
  52. }
  53. static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
  54. {
  55. return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
  56. }
  57. static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
  58. {
  59. return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
  60. }
  61. static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
  62. {
  63. return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
  64. }
  65. static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
  66. {
  67. return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
  68. }
  69. static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
  70. {
  71. return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
  72. }
  73. static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
  74. {
  75. return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
  76. }
  77. static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
  78. {
  79. return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
  80. }
  81. /* Core list of CMU_CPU side */
  82. static struct clksrc_clk clk_mout_apll = {
  83. .clk = {
  84. .name = "mout_apll",
  85. .id = -1,
  86. },
  87. .sources = &clk_src_apll,
  88. .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
  89. };
  90. static struct clksrc_clk clk_sclk_apll = {
  91. .clk = {
  92. .name = "sclk_apll",
  93. .id = -1,
  94. .parent = &clk_mout_apll.clk,
  95. },
  96. .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
  97. };
  98. static struct clksrc_clk clk_mout_epll = {
  99. .clk = {
  100. .name = "mout_epll",
  101. .id = -1,
  102. },
  103. .sources = &clk_src_epll,
  104. .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
  105. };
  106. static struct clksrc_clk clk_mout_mpll = {
  107. .clk = {
  108. .name = "mout_mpll",
  109. .id = -1,
  110. },
  111. .sources = &clk_src_mpll,
  112. .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
  113. };
  114. static struct clk *clkset_moutcore_list[] = {
  115. [0] = &clk_sclk_apll.clk,
  116. [1] = &clk_mout_mpll.clk,
  117. };
  118. static struct clksrc_sources clkset_moutcore = {
  119. .sources = clkset_moutcore_list,
  120. .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
  121. };
  122. static struct clksrc_clk clk_moutcore = {
  123. .clk = {
  124. .name = "moutcore",
  125. .id = -1,
  126. },
  127. .sources = &clkset_moutcore,
  128. .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
  129. };
  130. static struct clksrc_clk clk_coreclk = {
  131. .clk = {
  132. .name = "core_clk",
  133. .id = -1,
  134. .parent = &clk_moutcore.clk,
  135. },
  136. .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
  137. };
  138. static struct clksrc_clk clk_armclk = {
  139. .clk = {
  140. .name = "armclk",
  141. .id = -1,
  142. .parent = &clk_coreclk.clk,
  143. },
  144. };
  145. static struct clksrc_clk clk_aclk_corem0 = {
  146. .clk = {
  147. .name = "aclk_corem0",
  148. .id = -1,
  149. .parent = &clk_coreclk.clk,
  150. },
  151. .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
  152. };
  153. static struct clksrc_clk clk_aclk_cores = {
  154. .clk = {
  155. .name = "aclk_cores",
  156. .id = -1,
  157. .parent = &clk_coreclk.clk,
  158. },
  159. .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
  160. };
  161. static struct clksrc_clk clk_aclk_corem1 = {
  162. .clk = {
  163. .name = "aclk_corem1",
  164. .id = -1,
  165. .parent = &clk_coreclk.clk,
  166. },
  167. .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
  168. };
  169. static struct clksrc_clk clk_periphclk = {
  170. .clk = {
  171. .name = "periphclk",
  172. .id = -1,
  173. .parent = &clk_coreclk.clk,
  174. },
  175. .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
  176. };
  177. /* Core list of CMU_CORE side */
  178. static struct clk *clkset_corebus_list[] = {
  179. [0] = &clk_mout_mpll.clk,
  180. [1] = &clk_sclk_apll.clk,
  181. };
  182. static struct clksrc_sources clkset_mout_corebus = {
  183. .sources = clkset_corebus_list,
  184. .nr_sources = ARRAY_SIZE(clkset_corebus_list),
  185. };
  186. static struct clksrc_clk clk_mout_corebus = {
  187. .clk = {
  188. .name = "mout_corebus",
  189. .id = -1,
  190. },
  191. .sources = &clkset_mout_corebus,
  192. .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
  193. };
  194. static struct clksrc_clk clk_sclk_dmc = {
  195. .clk = {
  196. .name = "sclk_dmc",
  197. .id = -1,
  198. .parent = &clk_mout_corebus.clk,
  199. },
  200. .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
  201. };
  202. static struct clksrc_clk clk_aclk_cored = {
  203. .clk = {
  204. .name = "aclk_cored",
  205. .id = -1,
  206. .parent = &clk_sclk_dmc.clk,
  207. },
  208. .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
  209. };
  210. static struct clksrc_clk clk_aclk_corep = {
  211. .clk = {
  212. .name = "aclk_corep",
  213. .id = -1,
  214. .parent = &clk_aclk_cored.clk,
  215. },
  216. .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
  217. };
  218. static struct clksrc_clk clk_aclk_acp = {
  219. .clk = {
  220. .name = "aclk_acp",
  221. .id = -1,
  222. .parent = &clk_mout_corebus.clk,
  223. },
  224. .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
  225. };
  226. static struct clksrc_clk clk_pclk_acp = {
  227. .clk = {
  228. .name = "pclk_acp",
  229. .id = -1,
  230. .parent = &clk_aclk_acp.clk,
  231. },
  232. .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
  233. };
  234. /* Core list of CMU_TOP side */
  235. static struct clk *clkset_aclk_top_list[] = {
  236. [0] = &clk_mout_mpll.clk,
  237. [1] = &clk_sclk_apll.clk,
  238. };
  239. static struct clksrc_sources clkset_aclk = {
  240. .sources = clkset_aclk_top_list,
  241. .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
  242. };
  243. static struct clksrc_clk clk_aclk_200 = {
  244. .clk = {
  245. .name = "aclk_200",
  246. .id = -1,
  247. },
  248. .sources = &clkset_aclk,
  249. .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
  250. .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
  251. };
  252. static struct clksrc_clk clk_aclk_100 = {
  253. .clk = {
  254. .name = "aclk_100",
  255. .id = -1,
  256. },
  257. .sources = &clkset_aclk,
  258. .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
  259. .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
  260. };
  261. static struct clksrc_clk clk_aclk_160 = {
  262. .clk = {
  263. .name = "aclk_160",
  264. .id = -1,
  265. },
  266. .sources = &clkset_aclk,
  267. .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
  268. .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
  269. };
  270. static struct clksrc_clk clk_aclk_133 = {
  271. .clk = {
  272. .name = "aclk_133",
  273. .id = -1,
  274. },
  275. .sources = &clkset_aclk,
  276. .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
  277. .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
  278. };
  279. static struct clk *clkset_vpllsrc_list[] = {
  280. [0] = &clk_fin_vpll,
  281. [1] = &clk_sclk_hdmi27m,
  282. };
  283. static struct clksrc_sources clkset_vpllsrc = {
  284. .sources = clkset_vpllsrc_list,
  285. .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
  286. };
  287. static struct clksrc_clk clk_vpllsrc = {
  288. .clk = {
  289. .name = "vpll_src",
  290. .id = -1,
  291. .enable = s5pv310_clksrc_mask_top_ctrl,
  292. .ctrlbit = (1 << 0),
  293. },
  294. .sources = &clkset_vpllsrc,
  295. .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
  296. };
  297. static struct clk *clkset_sclk_vpll_list[] = {
  298. [0] = &clk_vpllsrc.clk,
  299. [1] = &clk_fout_vpll,
  300. };
  301. static struct clksrc_sources clkset_sclk_vpll = {
  302. .sources = clkset_sclk_vpll_list,
  303. .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
  304. };
  305. static struct clksrc_clk clk_sclk_vpll = {
  306. .clk = {
  307. .name = "sclk_vpll",
  308. .id = -1,
  309. },
  310. .sources = &clkset_sclk_vpll,
  311. .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
  312. };
  313. static struct clk init_clocks_disable[] = {
  314. {
  315. .name = "timers",
  316. .id = -1,
  317. .parent = &clk_aclk_100.clk,
  318. .enable = s5pv310_clk_ip_peril_ctrl,
  319. .ctrlbit = (1<<24),
  320. }, {
  321. .name = "csis",
  322. .id = 0,
  323. .enable = s5pv310_clk_ip_cam_ctrl,
  324. .ctrlbit = (1 << 4),
  325. }, {
  326. .name = "csis",
  327. .id = 1,
  328. .enable = s5pv310_clk_ip_cam_ctrl,
  329. .ctrlbit = (1 << 5),
  330. }, {
  331. .name = "fimc",
  332. .id = 0,
  333. .enable = s5pv310_clk_ip_cam_ctrl,
  334. .ctrlbit = (1 << 0),
  335. }, {
  336. .name = "fimc",
  337. .id = 1,
  338. .enable = s5pv310_clk_ip_cam_ctrl,
  339. .ctrlbit = (1 << 1),
  340. }, {
  341. .name = "fimc",
  342. .id = 2,
  343. .enable = s5pv310_clk_ip_cam_ctrl,
  344. .ctrlbit = (1 << 2),
  345. }, {
  346. .name = "fimc",
  347. .id = 3,
  348. .enable = s5pv310_clk_ip_cam_ctrl,
  349. .ctrlbit = (1 << 3),
  350. }, {
  351. .name = "fimd",
  352. .id = 0,
  353. .enable = s5pv310_clk_ip_lcd0_ctrl,
  354. .ctrlbit = (1 << 0),
  355. }, {
  356. .name = "fimd",
  357. .id = 1,
  358. .enable = s5pv310_clk_ip_lcd1_ctrl,
  359. .ctrlbit = (1 << 0),
  360. }, {
  361. .name = "hsmmc",
  362. .id = 0,
  363. .parent = &clk_aclk_133.clk,
  364. .enable = s5pv310_clk_ip_fsys_ctrl,
  365. .ctrlbit = (1 << 5),
  366. }, {
  367. .name = "hsmmc",
  368. .id = 1,
  369. .parent = &clk_aclk_133.clk,
  370. .enable = s5pv310_clk_ip_fsys_ctrl,
  371. .ctrlbit = (1 << 6),
  372. }, {
  373. .name = "hsmmc",
  374. .id = 2,
  375. .parent = &clk_aclk_133.clk,
  376. .enable = s5pv310_clk_ip_fsys_ctrl,
  377. .ctrlbit = (1 << 7),
  378. }, {
  379. .name = "hsmmc",
  380. .id = 3,
  381. .parent = &clk_aclk_133.clk,
  382. .enable = s5pv310_clk_ip_fsys_ctrl,
  383. .ctrlbit = (1 << 8),
  384. }, {
  385. .name = "hsmmc",
  386. .id = 4,
  387. .parent = &clk_aclk_133.clk,
  388. .enable = s5pv310_clk_ip_fsys_ctrl,
  389. .ctrlbit = (1 << 9),
  390. }, {
  391. .name = "sata",
  392. .id = -1,
  393. .enable = s5pv310_clk_ip_fsys_ctrl,
  394. .ctrlbit = (1 << 10),
  395. }, {
  396. .name = "adc",
  397. .id = -1,
  398. .enable = s5pv310_clk_ip_peril_ctrl,
  399. .ctrlbit = (1 << 15),
  400. }, {
  401. .name = "watchdog",
  402. .id = -1,
  403. .enable = s5pv310_clk_ip_perir_ctrl,
  404. .ctrlbit = (1 << 14),
  405. }, {
  406. .name = "usbhost",
  407. .id = -1,
  408. .enable = s5pv310_clk_ip_fsys_ctrl ,
  409. .ctrlbit = (1 << 12),
  410. }, {
  411. .name = "otg",
  412. .id = -1,
  413. .enable = s5pv310_clk_ip_fsys_ctrl,
  414. .ctrlbit = (1 << 13),
  415. }, {
  416. .name = "spi",
  417. .id = 0,
  418. .enable = s5pv310_clk_ip_peril_ctrl,
  419. .ctrlbit = (1 << 16),
  420. }, {
  421. .name = "spi",
  422. .id = 1,
  423. .enable = s5pv310_clk_ip_peril_ctrl,
  424. .ctrlbit = (1 << 17),
  425. }, {
  426. .name = "spi",
  427. .id = 2,
  428. .enable = s5pv310_clk_ip_peril_ctrl,
  429. .ctrlbit = (1 << 18),
  430. }, {
  431. .name = "fimg2d",
  432. .id = -1,
  433. .enable = s5pv310_clk_ip_image_ctrl,
  434. .ctrlbit = (1 << 0),
  435. }, {
  436. .name = "i2c",
  437. .id = 0,
  438. .parent = &clk_aclk_100.clk,
  439. .enable = s5pv310_clk_ip_peril_ctrl,
  440. .ctrlbit = (1 << 6),
  441. }, {
  442. .name = "i2c",
  443. .id = 1,
  444. .parent = &clk_aclk_100.clk,
  445. .enable = s5pv310_clk_ip_peril_ctrl,
  446. .ctrlbit = (1 << 7),
  447. }, {
  448. .name = "i2c",
  449. .id = 2,
  450. .parent = &clk_aclk_100.clk,
  451. .enable = s5pv310_clk_ip_peril_ctrl,
  452. .ctrlbit = (1 << 8),
  453. }, {
  454. .name = "i2c",
  455. .id = 3,
  456. .parent = &clk_aclk_100.clk,
  457. .enable = s5pv310_clk_ip_peril_ctrl,
  458. .ctrlbit = (1 << 9),
  459. }, {
  460. .name = "i2c",
  461. .id = 4,
  462. .parent = &clk_aclk_100.clk,
  463. .enable = s5pv310_clk_ip_peril_ctrl,
  464. .ctrlbit = (1 << 10),
  465. }, {
  466. .name = "i2c",
  467. .id = 5,
  468. .parent = &clk_aclk_100.clk,
  469. .enable = s5pv310_clk_ip_peril_ctrl,
  470. .ctrlbit = (1 << 11),
  471. }, {
  472. .name = "i2c",
  473. .id = 6,
  474. .parent = &clk_aclk_100.clk,
  475. .enable = s5pv310_clk_ip_peril_ctrl,
  476. .ctrlbit = (1 << 12),
  477. }, {
  478. .name = "i2c",
  479. .id = 7,
  480. .parent = &clk_aclk_100.clk,
  481. .enable = s5pv310_clk_ip_peril_ctrl,
  482. .ctrlbit = (1 << 13),
  483. },
  484. };
  485. static struct clk init_clocks[] = {
  486. {
  487. .name = "uart",
  488. .id = 0,
  489. .enable = s5pv310_clk_ip_peril_ctrl,
  490. .ctrlbit = (1 << 0),
  491. }, {
  492. .name = "uart",
  493. .id = 1,
  494. .enable = s5pv310_clk_ip_peril_ctrl,
  495. .ctrlbit = (1 << 1),
  496. }, {
  497. .name = "uart",
  498. .id = 2,
  499. .enable = s5pv310_clk_ip_peril_ctrl,
  500. .ctrlbit = (1 << 2),
  501. }, {
  502. .name = "uart",
  503. .id = 3,
  504. .enable = s5pv310_clk_ip_peril_ctrl,
  505. .ctrlbit = (1 << 3),
  506. }, {
  507. .name = "uart",
  508. .id = 4,
  509. .enable = s5pv310_clk_ip_peril_ctrl,
  510. .ctrlbit = (1 << 4),
  511. }, {
  512. .name = "uart",
  513. .id = 5,
  514. .enable = s5pv310_clk_ip_peril_ctrl,
  515. .ctrlbit = (1 << 5),
  516. }
  517. };
  518. static struct clk *clkset_group_list[] = {
  519. [0] = &clk_ext_xtal_mux,
  520. [1] = &clk_xusbxti,
  521. [2] = &clk_sclk_hdmi27m,
  522. [3] = &clk_sclk_usbphy0,
  523. [4] = &clk_sclk_usbphy1,
  524. [5] = &clk_sclk_hdmiphy,
  525. [6] = &clk_mout_mpll.clk,
  526. [7] = &clk_mout_epll.clk,
  527. [8] = &clk_sclk_vpll.clk,
  528. };
  529. static struct clksrc_sources clkset_group = {
  530. .sources = clkset_group_list,
  531. .nr_sources = ARRAY_SIZE(clkset_group_list),
  532. };
  533. static struct clk *clkset_mout_g2d0_list[] = {
  534. [0] = &clk_mout_mpll.clk,
  535. [1] = &clk_sclk_apll.clk,
  536. };
  537. static struct clksrc_sources clkset_mout_g2d0 = {
  538. .sources = clkset_mout_g2d0_list,
  539. .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
  540. };
  541. static struct clksrc_clk clk_mout_g2d0 = {
  542. .clk = {
  543. .name = "mout_g2d0",
  544. .id = -1,
  545. },
  546. .sources = &clkset_mout_g2d0,
  547. .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
  548. };
  549. static struct clk *clkset_mout_g2d1_list[] = {
  550. [0] = &clk_mout_epll.clk,
  551. [1] = &clk_sclk_vpll.clk,
  552. };
  553. static struct clksrc_sources clkset_mout_g2d1 = {
  554. .sources = clkset_mout_g2d1_list,
  555. .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
  556. };
  557. static struct clksrc_clk clk_mout_g2d1 = {
  558. .clk = {
  559. .name = "mout_g2d1",
  560. .id = -1,
  561. },
  562. .sources = &clkset_mout_g2d1,
  563. .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
  564. };
  565. static struct clk *clkset_mout_g2d_list[] = {
  566. [0] = &clk_mout_g2d0.clk,
  567. [1] = &clk_mout_g2d1.clk,
  568. };
  569. static struct clksrc_sources clkset_mout_g2d = {
  570. .sources = clkset_mout_g2d_list,
  571. .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
  572. };
  573. static struct clksrc_clk clk_dout_mmc0 = {
  574. .clk = {
  575. .name = "dout_mmc0",
  576. .id = -1,
  577. },
  578. .sources = &clkset_group,
  579. .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
  580. .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
  581. };
  582. static struct clksrc_clk clk_dout_mmc1 = {
  583. .clk = {
  584. .name = "dout_mmc1",
  585. .id = -1,
  586. },
  587. .sources = &clkset_group,
  588. .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
  589. .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
  590. };
  591. static struct clksrc_clk clk_dout_mmc2 = {
  592. .clk = {
  593. .name = "dout_mmc2",
  594. .id = -1,
  595. },
  596. .sources = &clkset_group,
  597. .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
  598. .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
  599. };
  600. static struct clksrc_clk clk_dout_mmc3 = {
  601. .clk = {
  602. .name = "dout_mmc3",
  603. .id = -1,
  604. },
  605. .sources = &clkset_group,
  606. .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
  607. .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
  608. };
  609. static struct clksrc_clk clk_dout_mmc4 = {
  610. .clk = {
  611. .name = "dout_mmc4",
  612. .id = -1,
  613. },
  614. .sources = &clkset_group,
  615. .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
  616. .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
  617. };
  618. static struct clksrc_clk clksrcs[] = {
  619. {
  620. .clk = {
  621. .name = "uclk1",
  622. .id = 0,
  623. .enable = s5pv310_clksrc_mask_peril0_ctrl,
  624. .ctrlbit = (1 << 0),
  625. },
  626. .sources = &clkset_group,
  627. .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
  628. .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
  629. }, {
  630. .clk = {
  631. .name = "uclk1",
  632. .id = 1,
  633. .enable = s5pv310_clksrc_mask_peril0_ctrl,
  634. .ctrlbit = (1 << 4),
  635. },
  636. .sources = &clkset_group,
  637. .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
  638. .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
  639. }, {
  640. .clk = {
  641. .name = "uclk1",
  642. .id = 2,
  643. .enable = s5pv310_clksrc_mask_peril0_ctrl,
  644. .ctrlbit = (1 << 8),
  645. },
  646. .sources = &clkset_group,
  647. .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
  648. .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
  649. }, {
  650. .clk = {
  651. .name = "uclk1",
  652. .id = 3,
  653. .enable = s5pv310_clksrc_mask_peril0_ctrl,
  654. .ctrlbit = (1 << 12),
  655. },
  656. .sources = &clkset_group,
  657. .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
  658. .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
  659. }, {
  660. .clk = {
  661. .name = "sclk_pwm",
  662. .id = -1,
  663. .enable = s5pv310_clksrc_mask_peril0_ctrl,
  664. .ctrlbit = (1 << 24),
  665. },
  666. .sources = &clkset_group,
  667. .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
  668. .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
  669. }, {
  670. .clk = {
  671. .name = "sclk_mmc",
  672. .id = 0,
  673. .parent = &clk_dout_mmc0.clk,
  674. .enable = s5pv310_clksrc_mask_fsys_ctrl,
  675. .ctrlbit = (1 << 0),
  676. },
  677. .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
  678. }, {
  679. .clk = {
  680. .name = "sclk_mmc",
  681. .id = 1,
  682. .parent = &clk_dout_mmc1.clk,
  683. .enable = s5pv310_clksrc_mask_fsys_ctrl,
  684. .ctrlbit = (1 << 4),
  685. },
  686. .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
  687. }, {
  688. .clk = {
  689. .name = "sclk_mmc",
  690. .id = 2,
  691. .parent = &clk_dout_mmc2.clk,
  692. .enable = s5pv310_clksrc_mask_fsys_ctrl,
  693. .ctrlbit = (1 << 8),
  694. },
  695. .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
  696. }, {
  697. .clk = {
  698. .name = "sclk_mmc",
  699. .id = 3,
  700. .parent = &clk_dout_mmc3.clk,
  701. .enable = s5pv310_clksrc_mask_fsys_ctrl,
  702. .ctrlbit = (1 << 12),
  703. },
  704. .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
  705. }, {
  706. .clk = {
  707. .name = "sclk_mmc",
  708. .id = 4,
  709. .parent = &clk_dout_mmc4.clk,
  710. .enable = s5pv310_clksrc_mask_fsys_ctrl,
  711. .ctrlbit = (1 << 16),
  712. },
  713. .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
  714. }
  715. };
  716. /* Clock initialization code */
  717. static struct clksrc_clk *sysclks[] = {
  718. &clk_mout_apll,
  719. &clk_sclk_apll,
  720. &clk_mout_epll,
  721. &clk_mout_mpll,
  722. &clk_moutcore,
  723. &clk_coreclk,
  724. &clk_armclk,
  725. &clk_aclk_corem0,
  726. &clk_aclk_cores,
  727. &clk_aclk_corem1,
  728. &clk_periphclk,
  729. &clk_mout_corebus,
  730. &clk_sclk_dmc,
  731. &clk_aclk_cored,
  732. &clk_aclk_corep,
  733. &clk_aclk_acp,
  734. &clk_pclk_acp,
  735. &clk_vpllsrc,
  736. &clk_sclk_vpll,
  737. &clk_aclk_200,
  738. &clk_aclk_100,
  739. &clk_aclk_160,
  740. &clk_aclk_133,
  741. &clk_dout_mmc0,
  742. &clk_dout_mmc1,
  743. &clk_dout_mmc2,
  744. &clk_dout_mmc3,
  745. &clk_dout_mmc4,
  746. };
  747. void __init_or_cpufreq s5pv310_setup_clocks(void)
  748. {
  749. struct clk *xtal_clk;
  750. unsigned long apll;
  751. unsigned long mpll;
  752. unsigned long epll;
  753. unsigned long vpll;
  754. unsigned long vpllsrc;
  755. unsigned long xtal;
  756. unsigned long armclk;
  757. unsigned long sclk_dmc;
  758. unsigned long aclk_200;
  759. unsigned long aclk_100;
  760. unsigned long aclk_160;
  761. unsigned long aclk_133;
  762. unsigned int ptr;
  763. printk(KERN_DEBUG "%s: registering clocks\n", __func__);
  764. xtal_clk = clk_get(NULL, "xtal");
  765. BUG_ON(IS_ERR(xtal_clk));
  766. xtal = clk_get_rate(xtal_clk);
  767. clk_put(xtal_clk);
  768. printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
  769. apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
  770. mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
  771. epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
  772. __raw_readl(S5P_EPLL_CON1), pll_4600);
  773. vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
  774. vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
  775. __raw_readl(S5P_VPLL_CON1), pll_4650);
  776. clk_fout_apll.rate = apll;
  777. clk_fout_mpll.rate = mpll;
  778. clk_fout_epll.rate = epll;
  779. clk_fout_vpll.rate = vpll;
  780. printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
  781. apll, mpll, epll, vpll);
  782. armclk = clk_get_rate(&clk_armclk.clk);
  783. sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
  784. aclk_200 = clk_get_rate(&clk_aclk_200.clk);
  785. aclk_100 = clk_get_rate(&clk_aclk_100.clk);
  786. aclk_160 = clk_get_rate(&clk_aclk_160.clk);
  787. aclk_133 = clk_get_rate(&clk_aclk_133.clk);
  788. printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
  789. "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
  790. armclk, sclk_dmc, aclk_200,
  791. aclk_100, aclk_160, aclk_133);
  792. clk_f.rate = armclk;
  793. clk_h.rate = sclk_dmc;
  794. clk_p.rate = aclk_100;
  795. for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
  796. s3c_set_clksrc(&clksrcs[ptr], true);
  797. }
  798. static struct clk *clks[] __initdata = {
  799. /* Nothing here yet */
  800. };
  801. void __init s5pv310_register_clocks(void)
  802. {
  803. struct clk *clkp;
  804. int ret;
  805. int ptr;
  806. ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
  807. if (ret > 0)
  808. printk(KERN_ERR "Failed to register %u clocks\n", ret);
  809. for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
  810. s3c_register_clksrc(sysclks[ptr], 1);
  811. s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
  812. s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
  813. clkp = init_clocks_disable;
  814. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
  815. ret = s3c24xx_register_clock(clkp);
  816. if (ret < 0) {
  817. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  818. clkp->name, ret);
  819. }
  820. (clkp->enable)(clkp, 0);
  821. }
  822. s3c_pwmclk_init();
  823. }