nand_base.c 68 KB

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  1. /*
  2. * drivers/mtd/nand.c
  3. *
  4. * Overview:
  5. * This is the generic MTD driver for NAND flash devices. It should be
  6. * capable of working with almost all NAND chips currently available.
  7. * Basic support for AG-AND chips is provided.
  8. *
  9. * Additional technical information is available on
  10. * http://www.linux-mtd.infradead.org/tech/nand.html
  11. *
  12. * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13. * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14. *
  15. * Credits:
  16. * David Woodhouse for adding multichip support
  17. *
  18. * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19. * rework for 2K page size chips
  20. *
  21. * TODO:
  22. * Enable cached programming for 2k page size chips
  23. * Check, if mtd->ecctype should be set to MTD_ECC_HW
  24. * if we have HW ecc support.
  25. * The AG-AND chips have nice features for speed improvement,
  26. * which are not supported yet. Read / program 4 pages in one go.
  27. * BBT table is not serialized, has to be fixed
  28. *
  29. * This program is free software; you can redistribute it and/or modify
  30. * it under the terms of the GNU General Public License version 2 as
  31. * published by the Free Software Foundation.
  32. *
  33. */
  34. #include <linux/module.h>
  35. #include <linux/delay.h>
  36. #include <linux/errno.h>
  37. #include <linux/err.h>
  38. #include <linux/sched.h>
  39. #include <linux/slab.h>
  40. #include <linux/types.h>
  41. #include <linux/mtd/mtd.h>
  42. #include <linux/mtd/nand.h>
  43. #include <linux/mtd/nand_ecc.h>
  44. #include <linux/mtd/compatmac.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/bitops.h>
  47. #include <linux/leds.h>
  48. #include <asm/io.h>
  49. #ifdef CONFIG_MTD_PARTITIONS
  50. #include <linux/mtd/partitions.h>
  51. #endif
  52. /* Define default oob placement schemes for large and small page devices */
  53. static struct nand_ecclayout nand_oob_8 = {
  54. .eccbytes = 3,
  55. .eccpos = {0, 1, 2},
  56. .oobfree = {
  57. {.offset = 3,
  58. .length = 2},
  59. {.offset = 6,
  60. .length = 2}}
  61. };
  62. static struct nand_ecclayout nand_oob_16 = {
  63. .eccbytes = 6,
  64. .eccpos = {0, 1, 2, 3, 6, 7},
  65. .oobfree = {
  66. {.offset = 8,
  67. . length = 8}}
  68. };
  69. static struct nand_ecclayout nand_oob_64 = {
  70. .eccbytes = 24,
  71. .eccpos = {
  72. 40, 41, 42, 43, 44, 45, 46, 47,
  73. 48, 49, 50, 51, 52, 53, 54, 55,
  74. 56, 57, 58, 59, 60, 61, 62, 63},
  75. .oobfree = {
  76. {.offset = 2,
  77. .length = 38}}
  78. };
  79. static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  80. int new_state);
  81. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  82. struct mtd_oob_ops *ops);
  83. /*
  84. * For devices which display every fart in the system on a seperate LED. Is
  85. * compiled away when LED support is disabled.
  86. */
  87. DEFINE_LED_TRIGGER(nand_led_trigger);
  88. /**
  89. * nand_release_device - [GENERIC] release chip
  90. * @mtd: MTD device structure
  91. *
  92. * Deselect, release chip lock and wake up anyone waiting on the device
  93. */
  94. static void nand_release_device(struct mtd_info *mtd)
  95. {
  96. struct nand_chip *chip = mtd->priv;
  97. /* De-select the NAND device */
  98. chip->select_chip(mtd, -1);
  99. /* Release the controller and the chip */
  100. spin_lock(&chip->controller->lock);
  101. chip->controller->active = NULL;
  102. chip->state = FL_READY;
  103. wake_up(&chip->controller->wq);
  104. spin_unlock(&chip->controller->lock);
  105. }
  106. /**
  107. * nand_read_byte - [DEFAULT] read one byte from the chip
  108. * @mtd: MTD device structure
  109. *
  110. * Default read function for 8bit buswith
  111. */
  112. static uint8_t nand_read_byte(struct mtd_info *mtd)
  113. {
  114. struct nand_chip *chip = mtd->priv;
  115. return readb(chip->IO_ADDR_R);
  116. }
  117. /**
  118. * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
  119. * @mtd: MTD device structure
  120. *
  121. * Default read function for 16bit buswith with
  122. * endianess conversion
  123. */
  124. static uint8_t nand_read_byte16(struct mtd_info *mtd)
  125. {
  126. struct nand_chip *chip = mtd->priv;
  127. return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
  128. }
  129. /**
  130. * nand_read_word - [DEFAULT] read one word from the chip
  131. * @mtd: MTD device structure
  132. *
  133. * Default read function for 16bit buswith without
  134. * endianess conversion
  135. */
  136. static u16 nand_read_word(struct mtd_info *mtd)
  137. {
  138. struct nand_chip *chip = mtd->priv;
  139. return readw(chip->IO_ADDR_R);
  140. }
  141. /**
  142. * nand_select_chip - [DEFAULT] control CE line
  143. * @mtd: MTD device structure
  144. * @chipnr: chipnumber to select, -1 for deselect
  145. *
  146. * Default select function for 1 chip devices.
  147. */
  148. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  149. {
  150. struct nand_chip *chip = mtd->priv;
  151. switch (chipnr) {
  152. case -1:
  153. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  154. break;
  155. case 0:
  156. break;
  157. default:
  158. BUG();
  159. }
  160. }
  161. /**
  162. * nand_write_buf - [DEFAULT] write buffer to chip
  163. * @mtd: MTD device structure
  164. * @buf: data buffer
  165. * @len: number of bytes to write
  166. *
  167. * Default write function for 8bit buswith
  168. */
  169. static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  170. {
  171. int i;
  172. struct nand_chip *chip = mtd->priv;
  173. for (i = 0; i < len; i++)
  174. writeb(buf[i], chip->IO_ADDR_W);
  175. }
  176. /**
  177. * nand_read_buf - [DEFAULT] read chip data into buffer
  178. * @mtd: MTD device structure
  179. * @buf: buffer to store date
  180. * @len: number of bytes to read
  181. *
  182. * Default read function for 8bit buswith
  183. */
  184. static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  185. {
  186. int i;
  187. struct nand_chip *chip = mtd->priv;
  188. for (i = 0; i < len; i++)
  189. buf[i] = readb(chip->IO_ADDR_R);
  190. }
  191. /**
  192. * nand_verify_buf - [DEFAULT] Verify chip data against buffer
  193. * @mtd: MTD device structure
  194. * @buf: buffer containing the data to compare
  195. * @len: number of bytes to compare
  196. *
  197. * Default verify function for 8bit buswith
  198. */
  199. static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  200. {
  201. int i;
  202. struct nand_chip *chip = mtd->priv;
  203. for (i = 0; i < len; i++)
  204. if (buf[i] != readb(chip->IO_ADDR_R))
  205. return -EFAULT;
  206. return 0;
  207. }
  208. /**
  209. * nand_write_buf16 - [DEFAULT] write buffer to chip
  210. * @mtd: MTD device structure
  211. * @buf: data buffer
  212. * @len: number of bytes to write
  213. *
  214. * Default write function for 16bit buswith
  215. */
  216. static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  217. {
  218. int i;
  219. struct nand_chip *chip = mtd->priv;
  220. u16 *p = (u16 *) buf;
  221. len >>= 1;
  222. for (i = 0; i < len; i++)
  223. writew(p[i], chip->IO_ADDR_W);
  224. }
  225. /**
  226. * nand_read_buf16 - [DEFAULT] read chip data into buffer
  227. * @mtd: MTD device structure
  228. * @buf: buffer to store date
  229. * @len: number of bytes to read
  230. *
  231. * Default read function for 16bit buswith
  232. */
  233. static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  234. {
  235. int i;
  236. struct nand_chip *chip = mtd->priv;
  237. u16 *p = (u16 *) buf;
  238. len >>= 1;
  239. for (i = 0; i < len; i++)
  240. p[i] = readw(chip->IO_ADDR_R);
  241. }
  242. /**
  243. * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
  244. * @mtd: MTD device structure
  245. * @buf: buffer containing the data to compare
  246. * @len: number of bytes to compare
  247. *
  248. * Default verify function for 16bit buswith
  249. */
  250. static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  251. {
  252. int i;
  253. struct nand_chip *chip = mtd->priv;
  254. u16 *p = (u16 *) buf;
  255. len >>= 1;
  256. for (i = 0; i < len; i++)
  257. if (p[i] != readw(chip->IO_ADDR_R))
  258. return -EFAULT;
  259. return 0;
  260. }
  261. /**
  262. * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  263. * @mtd: MTD device structure
  264. * @ofs: offset from device start
  265. * @getchip: 0, if the chip is already selected
  266. *
  267. * Check, if the block is bad.
  268. */
  269. static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  270. {
  271. int page, chipnr, res = 0;
  272. struct nand_chip *chip = mtd->priv;
  273. u16 bad;
  274. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  275. if (getchip) {
  276. chipnr = (int)(ofs >> chip->chip_shift);
  277. nand_get_device(chip, mtd, FL_READING);
  278. /* Select the NAND device */
  279. chip->select_chip(mtd, chipnr);
  280. }
  281. if (chip->options & NAND_BUSWIDTH_16) {
  282. chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
  283. page);
  284. bad = cpu_to_le16(chip->read_word(mtd));
  285. if (chip->badblockpos & 0x1)
  286. bad >>= 8;
  287. if ((bad & 0xFF) != 0xff)
  288. res = 1;
  289. } else {
  290. chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
  291. if (chip->read_byte(mtd) != 0xff)
  292. res = 1;
  293. }
  294. if (getchip)
  295. nand_release_device(mtd);
  296. return res;
  297. }
  298. /**
  299. * nand_default_block_markbad - [DEFAULT] mark a block bad
  300. * @mtd: MTD device structure
  301. * @ofs: offset from device start
  302. *
  303. * This is the default implementation, which can be overridden by
  304. * a hardware specific driver.
  305. */
  306. static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
  307. {
  308. struct nand_chip *chip = mtd->priv;
  309. uint8_t buf[2] = { 0, 0 };
  310. int block, ret;
  311. /* Get block number */
  312. block = (int)(ofs >> chip->bbt_erase_shift);
  313. if (chip->bbt)
  314. chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
  315. /* Do we have a flash based bad block table ? */
  316. if (chip->options & NAND_USE_FLASH_BBT)
  317. ret = nand_update_bbt(mtd, ofs);
  318. else {
  319. /* We write two bytes, so we dont have to mess with 16 bit
  320. * access
  321. */
  322. nand_get_device(chip, mtd, FL_WRITING);
  323. ofs += mtd->oobsize;
  324. chip->ops.len = chip->ops.ooblen = 2;
  325. chip->ops.datbuf = NULL;
  326. chip->ops.oobbuf = buf;
  327. chip->ops.ooboffs = chip->badblockpos & ~0x01;
  328. ret = nand_do_write_oob(mtd, ofs, &chip->ops);
  329. nand_release_device(mtd);
  330. }
  331. if (!ret)
  332. mtd->ecc_stats.badblocks++;
  333. return ret;
  334. }
  335. /**
  336. * nand_check_wp - [GENERIC] check if the chip is write protected
  337. * @mtd: MTD device structure
  338. * Check, if the device is write protected
  339. *
  340. * The function expects, that the device is already selected
  341. */
  342. static int nand_check_wp(struct mtd_info *mtd)
  343. {
  344. struct nand_chip *chip = mtd->priv;
  345. /* Check the WP bit */
  346. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  347. return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
  348. }
  349. /**
  350. * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  351. * @mtd: MTD device structure
  352. * @ofs: offset from device start
  353. * @getchip: 0, if the chip is already selected
  354. * @allowbbt: 1, if its allowed to access the bbt area
  355. *
  356. * Check, if the block is bad. Either by reading the bad block table or
  357. * calling of the scan function.
  358. */
  359. static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
  360. int allowbbt)
  361. {
  362. struct nand_chip *chip = mtd->priv;
  363. if (!chip->bbt)
  364. return chip->block_bad(mtd, ofs, getchip);
  365. /* Return info from the table */
  366. return nand_isbad_bbt(mtd, ofs, allowbbt);
  367. }
  368. /*
  369. * Wait for the ready pin, after a command
  370. * The timeout is catched later.
  371. */
  372. void nand_wait_ready(struct mtd_info *mtd)
  373. {
  374. struct nand_chip *chip = mtd->priv;
  375. unsigned long timeo = jiffies + 2;
  376. led_trigger_event(nand_led_trigger, LED_FULL);
  377. /* wait until command is processed or timeout occures */
  378. do {
  379. if (chip->dev_ready(mtd))
  380. break;
  381. touch_softlockup_watchdog();
  382. } while (time_before(jiffies, timeo));
  383. led_trigger_event(nand_led_trigger, LED_OFF);
  384. }
  385. EXPORT_SYMBOL_GPL(nand_wait_ready);
  386. /**
  387. * nand_command - [DEFAULT] Send command to NAND device
  388. * @mtd: MTD device structure
  389. * @command: the command to be sent
  390. * @column: the column address for this command, -1 if none
  391. * @page_addr: the page address for this command, -1 if none
  392. *
  393. * Send command to NAND device. This function is used for small page
  394. * devices (256/512 Bytes per page)
  395. */
  396. static void nand_command(struct mtd_info *mtd, unsigned int command,
  397. int column, int page_addr)
  398. {
  399. register struct nand_chip *chip = mtd->priv;
  400. int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
  401. /*
  402. * Write out the command to the device.
  403. */
  404. if (command == NAND_CMD_SEQIN) {
  405. int readcmd;
  406. if (column >= mtd->writesize) {
  407. /* OOB area */
  408. column -= mtd->writesize;
  409. readcmd = NAND_CMD_READOOB;
  410. } else if (column < 256) {
  411. /* First 256 bytes --> READ0 */
  412. readcmd = NAND_CMD_READ0;
  413. } else {
  414. column -= 256;
  415. readcmd = NAND_CMD_READ1;
  416. }
  417. chip->cmd_ctrl(mtd, readcmd, ctrl);
  418. ctrl &= ~NAND_CTRL_CHANGE;
  419. }
  420. chip->cmd_ctrl(mtd, command, ctrl);
  421. /*
  422. * Address cycle, when necessary
  423. */
  424. ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
  425. /* Serially input address */
  426. if (column != -1) {
  427. /* Adjust columns for 16 bit buswidth */
  428. if (chip->options & NAND_BUSWIDTH_16)
  429. column >>= 1;
  430. chip->cmd_ctrl(mtd, column, ctrl);
  431. ctrl &= ~NAND_CTRL_CHANGE;
  432. }
  433. if (page_addr != -1) {
  434. chip->cmd_ctrl(mtd, page_addr, ctrl);
  435. ctrl &= ~NAND_CTRL_CHANGE;
  436. chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
  437. /* One more address cycle for devices > 32MiB */
  438. if (chip->chipsize > (32 << 20))
  439. chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
  440. }
  441. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  442. /*
  443. * program and erase have their own busy handlers
  444. * status and sequential in needs no delay
  445. */
  446. switch (command) {
  447. case NAND_CMD_PAGEPROG:
  448. case NAND_CMD_ERASE1:
  449. case NAND_CMD_ERASE2:
  450. case NAND_CMD_SEQIN:
  451. case NAND_CMD_STATUS:
  452. return;
  453. case NAND_CMD_RESET:
  454. if (chip->dev_ready)
  455. break;
  456. udelay(chip->chip_delay);
  457. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  458. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  459. chip->cmd_ctrl(mtd,
  460. NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  461. while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
  462. return;
  463. /* This applies to read commands */
  464. default:
  465. /*
  466. * If we don't have access to the busy pin, we apply the given
  467. * command delay
  468. */
  469. if (!chip->dev_ready) {
  470. udelay(chip->chip_delay);
  471. return;
  472. }
  473. }
  474. /* Apply this short delay always to ensure that we do wait tWB in
  475. * any case on any machine. */
  476. ndelay(100);
  477. nand_wait_ready(mtd);
  478. }
  479. /**
  480. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  481. * @mtd: MTD device structure
  482. * @command: the command to be sent
  483. * @column: the column address for this command, -1 if none
  484. * @page_addr: the page address for this command, -1 if none
  485. *
  486. * Send command to NAND device. This is the version for the new large page
  487. * devices We dont have the separate regions as we have in the small page
  488. * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  489. */
  490. static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
  491. int column, int page_addr)
  492. {
  493. register struct nand_chip *chip = mtd->priv;
  494. /* Emulate NAND_CMD_READOOB */
  495. if (command == NAND_CMD_READOOB) {
  496. column += mtd->writesize;
  497. command = NAND_CMD_READ0;
  498. }
  499. /* Command latch cycle */
  500. chip->cmd_ctrl(mtd, command & 0xff,
  501. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  502. if (column != -1 || page_addr != -1) {
  503. int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
  504. /* Serially input address */
  505. if (column != -1) {
  506. /* Adjust columns for 16 bit buswidth */
  507. if (chip->options & NAND_BUSWIDTH_16)
  508. column >>= 1;
  509. chip->cmd_ctrl(mtd, column, ctrl);
  510. ctrl &= ~NAND_CTRL_CHANGE;
  511. chip->cmd_ctrl(mtd, column >> 8, ctrl);
  512. }
  513. if (page_addr != -1) {
  514. chip->cmd_ctrl(mtd, page_addr, ctrl);
  515. chip->cmd_ctrl(mtd, page_addr >> 8,
  516. NAND_NCE | NAND_ALE);
  517. /* One more address cycle for devices > 128MiB */
  518. if (chip->chipsize > (128 << 20))
  519. chip->cmd_ctrl(mtd, page_addr >> 16,
  520. NAND_NCE | NAND_ALE);
  521. }
  522. }
  523. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  524. /*
  525. * program and erase have their own busy handlers
  526. * status, sequential in, and deplete1 need no delay
  527. */
  528. switch (command) {
  529. case NAND_CMD_CACHEDPROG:
  530. case NAND_CMD_PAGEPROG:
  531. case NAND_CMD_ERASE1:
  532. case NAND_CMD_ERASE2:
  533. case NAND_CMD_SEQIN:
  534. case NAND_CMD_RNDIN:
  535. case NAND_CMD_STATUS:
  536. case NAND_CMD_DEPLETE1:
  537. return;
  538. /*
  539. * read error status commands require only a short delay
  540. */
  541. case NAND_CMD_STATUS_ERROR:
  542. case NAND_CMD_STATUS_ERROR0:
  543. case NAND_CMD_STATUS_ERROR1:
  544. case NAND_CMD_STATUS_ERROR2:
  545. case NAND_CMD_STATUS_ERROR3:
  546. udelay(chip->chip_delay);
  547. return;
  548. case NAND_CMD_RESET:
  549. if (chip->dev_ready)
  550. break;
  551. udelay(chip->chip_delay);
  552. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  553. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  554. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  555. NAND_NCE | NAND_CTRL_CHANGE);
  556. while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
  557. return;
  558. case NAND_CMD_RNDOUT:
  559. /* No ready / busy check necessary */
  560. chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
  561. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  562. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  563. NAND_NCE | NAND_CTRL_CHANGE);
  564. return;
  565. case NAND_CMD_READ0:
  566. chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
  567. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  568. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  569. NAND_NCE | NAND_CTRL_CHANGE);
  570. /* This applies to read commands */
  571. default:
  572. /*
  573. * If we don't have access to the busy pin, we apply the given
  574. * command delay
  575. */
  576. if (!chip->dev_ready) {
  577. udelay(chip->chip_delay);
  578. return;
  579. }
  580. }
  581. /* Apply this short delay always to ensure that we do wait tWB in
  582. * any case on any machine. */
  583. ndelay(100);
  584. nand_wait_ready(mtd);
  585. }
  586. /**
  587. * nand_get_device - [GENERIC] Get chip for selected access
  588. * @chip: the nand chip descriptor
  589. * @mtd: MTD device structure
  590. * @new_state: the state which is requested
  591. *
  592. * Get the device and lock it for exclusive access
  593. */
  594. static int
  595. nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
  596. {
  597. spinlock_t *lock = &chip->controller->lock;
  598. wait_queue_head_t *wq = &chip->controller->wq;
  599. DECLARE_WAITQUEUE(wait, current);
  600. retry:
  601. spin_lock(lock);
  602. /* Hardware controller shared among independend devices */
  603. /* Hardware controller shared among independend devices */
  604. if (!chip->controller->active)
  605. chip->controller->active = chip;
  606. if (chip->controller->active == chip && chip->state == FL_READY) {
  607. chip->state = new_state;
  608. spin_unlock(lock);
  609. return 0;
  610. }
  611. if (new_state == FL_PM_SUSPENDED) {
  612. spin_unlock(lock);
  613. return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
  614. }
  615. set_current_state(TASK_UNINTERRUPTIBLE);
  616. add_wait_queue(wq, &wait);
  617. spin_unlock(lock);
  618. schedule();
  619. remove_wait_queue(wq, &wait);
  620. goto retry;
  621. }
  622. /**
  623. * nand_wait - [DEFAULT] wait until the command is done
  624. * @mtd: MTD device structure
  625. * @chip: NAND chip structure
  626. *
  627. * Wait for command done. This applies to erase and program only
  628. * Erase can take up to 400ms and program up to 20ms according to
  629. * general NAND and SmartMedia specs
  630. */
  631. static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
  632. {
  633. unsigned long timeo = jiffies;
  634. int status, state = chip->state;
  635. if (state == FL_ERASING)
  636. timeo += (HZ * 400) / 1000;
  637. else
  638. timeo += (HZ * 20) / 1000;
  639. led_trigger_event(nand_led_trigger, LED_FULL);
  640. /* Apply this short delay always to ensure that we do wait tWB in
  641. * any case on any machine. */
  642. ndelay(100);
  643. if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
  644. chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
  645. else
  646. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  647. while (time_before(jiffies, timeo)) {
  648. if (chip->dev_ready) {
  649. if (chip->dev_ready(mtd))
  650. break;
  651. } else {
  652. if (chip->read_byte(mtd) & NAND_STATUS_READY)
  653. break;
  654. }
  655. cond_resched();
  656. }
  657. led_trigger_event(nand_led_trigger, LED_OFF);
  658. status = (int)chip->read_byte(mtd);
  659. return status;
  660. }
  661. /**
  662. * nand_read_page_raw - [Intern] read raw page data without ecc
  663. * @mtd: mtd info structure
  664. * @chip: nand chip info structure
  665. * @buf: buffer to store read data
  666. */
  667. static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  668. uint8_t *buf)
  669. {
  670. chip->read_buf(mtd, buf, mtd->writesize);
  671. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  672. return 0;
  673. }
  674. /**
  675. * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
  676. * @mtd: mtd info structure
  677. * @chip: nand chip info structure
  678. * @buf: buffer to store read data
  679. */
  680. static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  681. uint8_t *buf)
  682. {
  683. int i, eccsize = chip->ecc.size;
  684. int eccbytes = chip->ecc.bytes;
  685. int eccsteps = chip->ecc.steps;
  686. uint8_t *p = buf;
  687. uint8_t *ecc_calc = chip->buffers->ecccalc;
  688. uint8_t *ecc_code = chip->buffers->ecccode;
  689. int *eccpos = chip->ecc.layout->eccpos;
  690. chip->ecc.read_page_raw(mtd, chip, buf);
  691. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  692. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  693. for (i = 0; i < chip->ecc.total; i++)
  694. ecc_code[i] = chip->oob_poi[eccpos[i]];
  695. eccsteps = chip->ecc.steps;
  696. p = buf;
  697. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  698. int stat;
  699. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  700. if (stat == -1)
  701. mtd->ecc_stats.failed++;
  702. else
  703. mtd->ecc_stats.corrected += stat;
  704. }
  705. return 0;
  706. }
  707. /**
  708. * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
  709. * @mtd: mtd info structure
  710. * @chip: nand chip info structure
  711. * @buf: buffer to store read data
  712. *
  713. * Not for syndrome calculating ecc controllers which need a special oob layout
  714. */
  715. static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  716. uint8_t *buf)
  717. {
  718. int i, eccsize = chip->ecc.size;
  719. int eccbytes = chip->ecc.bytes;
  720. int eccsteps = chip->ecc.steps;
  721. uint8_t *p = buf;
  722. uint8_t *ecc_calc = chip->buffers->ecccalc;
  723. uint8_t *ecc_code = chip->buffers->ecccode;
  724. int *eccpos = chip->ecc.layout->eccpos;
  725. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  726. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  727. chip->read_buf(mtd, p, eccsize);
  728. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  729. }
  730. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  731. for (i = 0; i < chip->ecc.total; i++)
  732. ecc_code[i] = chip->oob_poi[eccpos[i]];
  733. eccsteps = chip->ecc.steps;
  734. p = buf;
  735. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  736. int stat;
  737. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  738. if (stat == -1)
  739. mtd->ecc_stats.failed++;
  740. else
  741. mtd->ecc_stats.corrected += stat;
  742. }
  743. return 0;
  744. }
  745. /**
  746. * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
  747. * @mtd: mtd info structure
  748. * @chip: nand chip info structure
  749. * @buf: buffer to store read data
  750. *
  751. * The hw generator calculates the error syndrome automatically. Therefor
  752. * we need a special oob layout and handling.
  753. */
  754. static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  755. uint8_t *buf)
  756. {
  757. int i, eccsize = chip->ecc.size;
  758. int eccbytes = chip->ecc.bytes;
  759. int eccsteps = chip->ecc.steps;
  760. uint8_t *p = buf;
  761. uint8_t *oob = chip->oob_poi;
  762. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  763. int stat;
  764. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  765. chip->read_buf(mtd, p, eccsize);
  766. if (chip->ecc.prepad) {
  767. chip->read_buf(mtd, oob, chip->ecc.prepad);
  768. oob += chip->ecc.prepad;
  769. }
  770. chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
  771. chip->read_buf(mtd, oob, eccbytes);
  772. stat = chip->ecc.correct(mtd, p, oob, NULL);
  773. if (stat == -1)
  774. mtd->ecc_stats.failed++;
  775. else
  776. mtd->ecc_stats.corrected += stat;
  777. oob += eccbytes;
  778. if (chip->ecc.postpad) {
  779. chip->read_buf(mtd, oob, chip->ecc.postpad);
  780. oob += chip->ecc.postpad;
  781. }
  782. }
  783. /* Calculate remaining oob bytes */
  784. i = mtd->oobsize - (oob - chip->oob_poi);
  785. if (i)
  786. chip->read_buf(mtd, oob, i);
  787. return 0;
  788. }
  789. /**
  790. * nand_transfer_oob - [Internal] Transfer oob to client buffer
  791. * @chip: nand chip structure
  792. * @oob: oob destination address
  793. * @ops: oob ops structure
  794. * @len: size of oob to transfer
  795. */
  796. static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  797. struct mtd_oob_ops *ops, size_t len)
  798. {
  799. switch(ops->mode) {
  800. case MTD_OOB_PLACE:
  801. case MTD_OOB_RAW:
  802. memcpy(oob, chip->oob_poi + ops->ooboffs, len);
  803. return oob + len;
  804. case MTD_OOB_AUTO: {
  805. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  806. uint32_t boffs = 0, roffs = ops->ooboffs;
  807. size_t bytes = 0;
  808. for(; free->length && len; free++, len -= bytes) {
  809. /* Read request not from offset 0 ? */
  810. if (unlikely(roffs)) {
  811. if (roffs >= free->length) {
  812. roffs -= free->length;
  813. continue;
  814. }
  815. boffs = free->offset + roffs;
  816. bytes = min_t(size_t, len,
  817. (free->length - roffs));
  818. roffs = 0;
  819. } else {
  820. bytes = min_t(size_t, len, free->length);
  821. boffs = free->offset;
  822. }
  823. memcpy(oob, chip->oob_poi + boffs, bytes);
  824. oob += bytes;
  825. }
  826. return oob;
  827. }
  828. default:
  829. BUG();
  830. }
  831. return NULL;
  832. }
  833. /**
  834. * nand_do_read_ops - [Internal] Read data with ECC
  835. *
  836. * @mtd: MTD device structure
  837. * @from: offset to read from
  838. * @ops: oob ops structure
  839. *
  840. * Internal function. Called with chip held.
  841. */
  842. static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
  843. struct mtd_oob_ops *ops)
  844. {
  845. int chipnr, page, realpage, col, bytes, aligned;
  846. struct nand_chip *chip = mtd->priv;
  847. struct mtd_ecc_stats stats;
  848. int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
  849. int sndcmd = 1;
  850. int ret = 0;
  851. uint32_t readlen = ops->len;
  852. uint32_t oobreadlen = ops->ooblen;
  853. uint8_t *bufpoi, *oob, *buf;
  854. stats = mtd->ecc_stats;
  855. chipnr = (int)(from >> chip->chip_shift);
  856. chip->select_chip(mtd, chipnr);
  857. realpage = (int)(from >> chip->page_shift);
  858. page = realpage & chip->pagemask;
  859. col = (int)(from & (mtd->writesize - 1));
  860. buf = ops->datbuf;
  861. oob = ops->oobbuf;
  862. while(1) {
  863. bytes = min(mtd->writesize - col, readlen);
  864. aligned = (bytes == mtd->writesize);
  865. /* Is the current page in the buffer ? */
  866. if (realpage != chip->pagebuf || oob) {
  867. bufpoi = aligned ? buf : chip->buffers->databuf;
  868. if (likely(sndcmd)) {
  869. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  870. sndcmd = 0;
  871. }
  872. /* Now read the page into the buffer */
  873. if (unlikely(ops->mode == MTD_OOB_RAW))
  874. ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
  875. else
  876. ret = chip->ecc.read_page(mtd, chip, bufpoi);
  877. if (ret < 0)
  878. break;
  879. /* Transfer not aligned data */
  880. if (!aligned) {
  881. chip->pagebuf = realpage;
  882. memcpy(buf, chip->buffers->databuf + col, bytes);
  883. }
  884. buf += bytes;
  885. if (unlikely(oob)) {
  886. /* Raw mode does data:oob:data:oob */
  887. if (ops->mode != MTD_OOB_RAW) {
  888. int toread = min(oobreadlen,
  889. chip->ecc.layout->oobavail);
  890. if (toread) {
  891. oob = nand_transfer_oob(chip,
  892. oob, ops, toread);
  893. oobreadlen -= toread;
  894. }
  895. } else
  896. buf = nand_transfer_oob(chip,
  897. buf, ops, mtd->oobsize);
  898. }
  899. if (!(chip->options & NAND_NO_READRDY)) {
  900. /*
  901. * Apply delay or wait for ready/busy pin. Do
  902. * this before the AUTOINCR check, so no
  903. * problems arise if a chip which does auto
  904. * increment is marked as NOAUTOINCR by the
  905. * board driver.
  906. */
  907. if (!chip->dev_ready)
  908. udelay(chip->chip_delay);
  909. else
  910. nand_wait_ready(mtd);
  911. }
  912. } else {
  913. memcpy(buf, chip->buffers->databuf + col, bytes);
  914. buf += bytes;
  915. }
  916. readlen -= bytes;
  917. if (!readlen)
  918. break;
  919. /* For subsequent reads align to page boundary. */
  920. col = 0;
  921. /* Increment page address */
  922. realpage++;
  923. page = realpage & chip->pagemask;
  924. /* Check, if we cross a chip boundary */
  925. if (!page) {
  926. chipnr++;
  927. chip->select_chip(mtd, -1);
  928. chip->select_chip(mtd, chipnr);
  929. }
  930. /* Check, if the chip supports auto page increment
  931. * or if we have hit a block boundary.
  932. */
  933. if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
  934. sndcmd = 1;
  935. }
  936. ops->retlen = ops->len - (size_t) readlen;
  937. if (oob)
  938. ops->oobretlen = ops->ooblen - oobreadlen;
  939. if (ret)
  940. return ret;
  941. if (mtd->ecc_stats.failed - stats.failed)
  942. return -EBADMSG;
  943. return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
  944. }
  945. /**
  946. * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
  947. * @mtd: MTD device structure
  948. * @from: offset to read from
  949. * @len: number of bytes to read
  950. * @retlen: pointer to variable to store the number of read bytes
  951. * @buf: the databuffer to put data
  952. *
  953. * Get hold of the chip and call nand_do_read
  954. */
  955. static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
  956. size_t *retlen, uint8_t *buf)
  957. {
  958. struct nand_chip *chip = mtd->priv;
  959. int ret;
  960. /* Do not allow reads past end of device */
  961. if ((from + len) > mtd->size)
  962. return -EINVAL;
  963. if (!len)
  964. return 0;
  965. nand_get_device(chip, mtd, FL_READING);
  966. chip->ops.len = len;
  967. chip->ops.datbuf = buf;
  968. chip->ops.oobbuf = NULL;
  969. ret = nand_do_read_ops(mtd, from, &chip->ops);
  970. *retlen = chip->ops.retlen;
  971. nand_release_device(mtd);
  972. return ret;
  973. }
  974. /**
  975. * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
  976. * @mtd: mtd info structure
  977. * @chip: nand chip info structure
  978. * @page: page number to read
  979. * @sndcmd: flag whether to issue read command or not
  980. */
  981. static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  982. int page, int sndcmd)
  983. {
  984. if (sndcmd) {
  985. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  986. sndcmd = 0;
  987. }
  988. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  989. return sndcmd;
  990. }
  991. /**
  992. * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
  993. * with syndromes
  994. * @mtd: mtd info structure
  995. * @chip: nand chip info structure
  996. * @page: page number to read
  997. * @sndcmd: flag whether to issue read command or not
  998. */
  999. static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  1000. int page, int sndcmd)
  1001. {
  1002. uint8_t *buf = chip->oob_poi;
  1003. int length = mtd->oobsize;
  1004. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  1005. int eccsize = chip->ecc.size;
  1006. uint8_t *bufpoi = buf;
  1007. int i, toread, sndrnd = 0, pos;
  1008. chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
  1009. for (i = 0; i < chip->ecc.steps; i++) {
  1010. if (sndrnd) {
  1011. pos = eccsize + i * (eccsize + chunk);
  1012. if (mtd->writesize > 512)
  1013. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
  1014. else
  1015. chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
  1016. } else
  1017. sndrnd = 1;
  1018. toread = min_t(int, length, chunk);
  1019. chip->read_buf(mtd, bufpoi, toread);
  1020. bufpoi += toread;
  1021. length -= toread;
  1022. }
  1023. if (length > 0)
  1024. chip->read_buf(mtd, bufpoi, length);
  1025. return 1;
  1026. }
  1027. /**
  1028. * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
  1029. * @mtd: mtd info structure
  1030. * @chip: nand chip info structure
  1031. * @page: page number to write
  1032. */
  1033. static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  1034. int page)
  1035. {
  1036. int status = 0;
  1037. const uint8_t *buf = chip->oob_poi;
  1038. int length = mtd->oobsize;
  1039. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  1040. chip->write_buf(mtd, buf, length);
  1041. /* Send command to program the OOB data */
  1042. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1043. status = chip->waitfunc(mtd, chip);
  1044. return status & NAND_STATUS_FAIL ? -EIO : 0;
  1045. }
  1046. /**
  1047. * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
  1048. * with syndrome - only for large page flash !
  1049. * @mtd: mtd info structure
  1050. * @chip: nand chip info structure
  1051. * @page: page number to write
  1052. */
  1053. static int nand_write_oob_syndrome(struct mtd_info *mtd,
  1054. struct nand_chip *chip, int page)
  1055. {
  1056. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  1057. int eccsize = chip->ecc.size, length = mtd->oobsize;
  1058. int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
  1059. const uint8_t *bufpoi = chip->oob_poi;
  1060. /*
  1061. * data-ecc-data-ecc ... ecc-oob
  1062. * or
  1063. * data-pad-ecc-pad-data-pad .... ecc-pad-oob
  1064. */
  1065. if (!chip->ecc.prepad && !chip->ecc.postpad) {
  1066. pos = steps * (eccsize + chunk);
  1067. steps = 0;
  1068. } else
  1069. pos = eccsize;
  1070. chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
  1071. for (i = 0; i < steps; i++) {
  1072. if (sndcmd) {
  1073. if (mtd->writesize <= 512) {
  1074. uint32_t fill = 0xFFFFFFFF;
  1075. len = eccsize;
  1076. while (len > 0) {
  1077. int num = min_t(int, len, 4);
  1078. chip->write_buf(mtd, (uint8_t *)&fill,
  1079. num);
  1080. len -= num;
  1081. }
  1082. } else {
  1083. pos = eccsize + i * (eccsize + chunk);
  1084. chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
  1085. }
  1086. } else
  1087. sndcmd = 1;
  1088. len = min_t(int, length, chunk);
  1089. chip->write_buf(mtd, bufpoi, len);
  1090. bufpoi += len;
  1091. length -= len;
  1092. }
  1093. if (length > 0)
  1094. chip->write_buf(mtd, bufpoi, length);
  1095. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1096. status = chip->waitfunc(mtd, chip);
  1097. return status & NAND_STATUS_FAIL ? -EIO : 0;
  1098. }
  1099. /**
  1100. * nand_do_read_oob - [Intern] NAND read out-of-band
  1101. * @mtd: MTD device structure
  1102. * @from: offset to read from
  1103. * @ops: oob operations description structure
  1104. *
  1105. * NAND read out-of-band data from the spare area
  1106. */
  1107. static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
  1108. struct mtd_oob_ops *ops)
  1109. {
  1110. int page, realpage, chipnr, sndcmd = 1;
  1111. struct nand_chip *chip = mtd->priv;
  1112. int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
  1113. int readlen = ops->ooblen;
  1114. int len;
  1115. uint8_t *buf = ops->oobbuf;
  1116. DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
  1117. (unsigned long long)from, readlen);
  1118. if (ops->mode == MTD_OOB_AUTO)
  1119. len = chip->ecc.layout->oobavail;
  1120. else
  1121. len = mtd->oobsize;
  1122. if (unlikely(ops->ooboffs >= len)) {
  1123. DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
  1124. "Attempt to start read outside oob\n");
  1125. return -EINVAL;
  1126. }
  1127. /* Do not allow reads past end of device */
  1128. if (unlikely(from >= mtd->size ||
  1129. ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
  1130. (from >> chip->page_shift)) * len)) {
  1131. DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
  1132. "Attempt read beyond end of device\n");
  1133. return -EINVAL;
  1134. }
  1135. chipnr = (int)(from >> chip->chip_shift);
  1136. chip->select_chip(mtd, chipnr);
  1137. /* Shift to get page */
  1138. realpage = (int)(from >> chip->page_shift);
  1139. page = realpage & chip->pagemask;
  1140. while(1) {
  1141. sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
  1142. len = min(len, readlen);
  1143. buf = nand_transfer_oob(chip, buf, ops, len);
  1144. if (!(chip->options & NAND_NO_READRDY)) {
  1145. /*
  1146. * Apply delay or wait for ready/busy pin. Do this
  1147. * before the AUTOINCR check, so no problems arise if a
  1148. * chip which does auto increment is marked as
  1149. * NOAUTOINCR by the board driver.
  1150. */
  1151. if (!chip->dev_ready)
  1152. udelay(chip->chip_delay);
  1153. else
  1154. nand_wait_ready(mtd);
  1155. }
  1156. readlen -= len;
  1157. if (!readlen)
  1158. break;
  1159. /* Increment page address */
  1160. realpage++;
  1161. page = realpage & chip->pagemask;
  1162. /* Check, if we cross a chip boundary */
  1163. if (!page) {
  1164. chipnr++;
  1165. chip->select_chip(mtd, -1);
  1166. chip->select_chip(mtd, chipnr);
  1167. }
  1168. /* Check, if the chip supports auto page increment
  1169. * or if we have hit a block boundary.
  1170. */
  1171. if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
  1172. sndcmd = 1;
  1173. }
  1174. ops->oobretlen = ops->ooblen;
  1175. return 0;
  1176. }
  1177. /**
  1178. * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  1179. * @mtd: MTD device structure
  1180. * @from: offset to read from
  1181. * @ops: oob operation description structure
  1182. *
  1183. * NAND read data and/or out-of-band data
  1184. */
  1185. static int nand_read_oob(struct mtd_info *mtd, loff_t from,
  1186. struct mtd_oob_ops *ops)
  1187. {
  1188. struct nand_chip *chip = mtd->priv;
  1189. int ret = -ENOTSUPP;
  1190. ops->retlen = 0;
  1191. /* Do not allow reads past end of device */
  1192. if (ops->datbuf && (from + ops->len) > mtd->size) {
  1193. DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
  1194. "Attempt read beyond end of device\n");
  1195. return -EINVAL;
  1196. }
  1197. nand_get_device(chip, mtd, FL_READING);
  1198. switch(ops->mode) {
  1199. case MTD_OOB_PLACE:
  1200. case MTD_OOB_AUTO:
  1201. case MTD_OOB_RAW:
  1202. break;
  1203. default:
  1204. goto out;
  1205. }
  1206. if (!ops->datbuf)
  1207. ret = nand_do_read_oob(mtd, from, ops);
  1208. else
  1209. ret = nand_do_read_ops(mtd, from, ops);
  1210. out:
  1211. nand_release_device(mtd);
  1212. return ret;
  1213. }
  1214. /**
  1215. * nand_write_page_raw - [Intern] raw page write function
  1216. * @mtd: mtd info structure
  1217. * @chip: nand chip info structure
  1218. * @buf: data buffer
  1219. */
  1220. static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1221. const uint8_t *buf)
  1222. {
  1223. chip->write_buf(mtd, buf, mtd->writesize);
  1224. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1225. }
  1226. /**
  1227. * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
  1228. * @mtd: mtd info structure
  1229. * @chip: nand chip info structure
  1230. * @buf: data buffer
  1231. */
  1232. static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  1233. const uint8_t *buf)
  1234. {
  1235. int i, eccsize = chip->ecc.size;
  1236. int eccbytes = chip->ecc.bytes;
  1237. int eccsteps = chip->ecc.steps;
  1238. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1239. const uint8_t *p = buf;
  1240. int *eccpos = chip->ecc.layout->eccpos;
  1241. /* Software ecc calculation */
  1242. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1243. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1244. for (i = 0; i < chip->ecc.total; i++)
  1245. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  1246. chip->ecc.write_page_raw(mtd, chip, buf);
  1247. }
  1248. /**
  1249. * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
  1250. * @mtd: mtd info structure
  1251. * @chip: nand chip info structure
  1252. * @buf: data buffer
  1253. */
  1254. static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  1255. const uint8_t *buf)
  1256. {
  1257. int i, eccsize = chip->ecc.size;
  1258. int eccbytes = chip->ecc.bytes;
  1259. int eccsteps = chip->ecc.steps;
  1260. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1261. const uint8_t *p = buf;
  1262. int *eccpos = chip->ecc.layout->eccpos;
  1263. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1264. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  1265. chip->write_buf(mtd, p, eccsize);
  1266. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1267. }
  1268. for (i = 0; i < chip->ecc.total; i++)
  1269. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  1270. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1271. }
  1272. /**
  1273. * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
  1274. * @mtd: mtd info structure
  1275. * @chip: nand chip info structure
  1276. * @buf: data buffer
  1277. *
  1278. * The hw generator calculates the error syndrome automatically. Therefor
  1279. * we need a special oob layout and handling.
  1280. */
  1281. static void nand_write_page_syndrome(struct mtd_info *mtd,
  1282. struct nand_chip *chip, const uint8_t *buf)
  1283. {
  1284. int i, eccsize = chip->ecc.size;
  1285. int eccbytes = chip->ecc.bytes;
  1286. int eccsteps = chip->ecc.steps;
  1287. const uint8_t *p = buf;
  1288. uint8_t *oob = chip->oob_poi;
  1289. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1290. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  1291. chip->write_buf(mtd, p, eccsize);
  1292. if (chip->ecc.prepad) {
  1293. chip->write_buf(mtd, oob, chip->ecc.prepad);
  1294. oob += chip->ecc.prepad;
  1295. }
  1296. chip->ecc.calculate(mtd, p, oob);
  1297. chip->write_buf(mtd, oob, eccbytes);
  1298. oob += eccbytes;
  1299. if (chip->ecc.postpad) {
  1300. chip->write_buf(mtd, oob, chip->ecc.postpad);
  1301. oob += chip->ecc.postpad;
  1302. }
  1303. }
  1304. /* Calculate remaining oob bytes */
  1305. i = mtd->oobsize - (oob - chip->oob_poi);
  1306. if (i)
  1307. chip->write_buf(mtd, oob, i);
  1308. }
  1309. /**
  1310. * nand_write_page - [REPLACEABLE] write one page
  1311. * @mtd: MTD device structure
  1312. * @chip: NAND chip descriptor
  1313. * @buf: the data to write
  1314. * @page: page number to write
  1315. * @cached: cached programming
  1316. * @raw: use _raw version of write_page
  1317. */
  1318. static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  1319. const uint8_t *buf, int page, int cached, int raw)
  1320. {
  1321. int status;
  1322. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
  1323. if (unlikely(raw))
  1324. chip->ecc.write_page_raw(mtd, chip, buf);
  1325. else
  1326. chip->ecc.write_page(mtd, chip, buf);
  1327. /*
  1328. * Cached progamming disabled for now, Not sure if its worth the
  1329. * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
  1330. */
  1331. cached = 0;
  1332. if (!cached || !(chip->options & NAND_CACHEPRG)) {
  1333. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1334. status = chip->waitfunc(mtd, chip);
  1335. /*
  1336. * See if operation failed and additional status checks are
  1337. * available
  1338. */
  1339. if ((status & NAND_STATUS_FAIL) && (chip->errstat))
  1340. status = chip->errstat(mtd, chip, FL_WRITING, status,
  1341. page);
  1342. if (status & NAND_STATUS_FAIL)
  1343. return -EIO;
  1344. } else {
  1345. chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
  1346. status = chip->waitfunc(mtd, chip);
  1347. }
  1348. #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
  1349. /* Send command to read back the data */
  1350. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  1351. if (chip->verify_buf(mtd, buf, mtd->writesize))
  1352. return -EIO;
  1353. #endif
  1354. return 0;
  1355. }
  1356. /**
  1357. * nand_fill_oob - [Internal] Transfer client buffer to oob
  1358. * @chip: nand chip structure
  1359. * @oob: oob data buffer
  1360. * @ops: oob ops structure
  1361. */
  1362. static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
  1363. struct mtd_oob_ops *ops)
  1364. {
  1365. size_t len = ops->ooblen;
  1366. switch(ops->mode) {
  1367. case MTD_OOB_PLACE:
  1368. case MTD_OOB_RAW:
  1369. memcpy(chip->oob_poi + ops->ooboffs, oob, len);
  1370. return oob + len;
  1371. case MTD_OOB_AUTO: {
  1372. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  1373. uint32_t boffs = 0, woffs = ops->ooboffs;
  1374. size_t bytes = 0;
  1375. for(; free->length && len; free++, len -= bytes) {
  1376. /* Write request not from offset 0 ? */
  1377. if (unlikely(woffs)) {
  1378. if (woffs >= free->length) {
  1379. woffs -= free->length;
  1380. continue;
  1381. }
  1382. boffs = free->offset + woffs;
  1383. bytes = min_t(size_t, len,
  1384. (free->length - woffs));
  1385. woffs = 0;
  1386. } else {
  1387. bytes = min_t(size_t, len, free->length);
  1388. boffs = free->offset;
  1389. }
  1390. memcpy(chip->oob_poi + boffs, oob, bytes);
  1391. oob += bytes;
  1392. }
  1393. return oob;
  1394. }
  1395. default:
  1396. BUG();
  1397. }
  1398. return NULL;
  1399. }
  1400. #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
  1401. /**
  1402. * nand_do_write_ops - [Internal] NAND write with ECC
  1403. * @mtd: MTD device structure
  1404. * @to: offset to write to
  1405. * @ops: oob operations description structure
  1406. *
  1407. * NAND write with ECC
  1408. */
  1409. static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
  1410. struct mtd_oob_ops *ops)
  1411. {
  1412. int chipnr, realpage, page, blockmask, column;
  1413. struct nand_chip *chip = mtd->priv;
  1414. uint32_t writelen = ops->len;
  1415. uint8_t *oob = ops->oobbuf;
  1416. uint8_t *buf = ops->datbuf;
  1417. int ret, subpage;
  1418. ops->retlen = 0;
  1419. if (!writelen)
  1420. return 0;
  1421. /* reject writes, which are not page aligned */
  1422. if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
  1423. printk(KERN_NOTICE "nand_write: "
  1424. "Attempt to write not page aligned data\n");
  1425. return -EINVAL;
  1426. }
  1427. column = to & (mtd->writesize - 1);
  1428. subpage = column || (writelen & (mtd->writesize - 1));
  1429. if (subpage && oob)
  1430. return -EINVAL;
  1431. chipnr = (int)(to >> chip->chip_shift);
  1432. chip->select_chip(mtd, chipnr);
  1433. /* Check, if it is write protected */
  1434. if (nand_check_wp(mtd))
  1435. return -EIO;
  1436. realpage = (int)(to >> chip->page_shift);
  1437. page = realpage & chip->pagemask;
  1438. blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
  1439. /* Invalidate the page cache, when we write to the cached page */
  1440. if (to <= (chip->pagebuf << chip->page_shift) &&
  1441. (chip->pagebuf << chip->page_shift) < (to + ops->len))
  1442. chip->pagebuf = -1;
  1443. /* If we're not given explicit OOB data, let it be 0xFF */
  1444. if (likely(!oob))
  1445. memset(chip->oob_poi, 0xff, mtd->oobsize);
  1446. while(1) {
  1447. int bytes = mtd->writesize;
  1448. int cached = writelen > bytes && page != blockmask;
  1449. uint8_t *wbuf = buf;
  1450. /* Partial page write ? */
  1451. if (unlikely(column || writelen < (mtd->writesize - 1))) {
  1452. cached = 0;
  1453. bytes = min_t(int, bytes - column, (int) writelen);
  1454. chip->pagebuf = -1;
  1455. memset(chip->buffers->databuf, 0xff, mtd->writesize);
  1456. memcpy(&chip->buffers->databuf[column], buf, bytes);
  1457. wbuf = chip->buffers->databuf;
  1458. }
  1459. if (unlikely(oob))
  1460. oob = nand_fill_oob(chip, oob, ops);
  1461. ret = chip->write_page(mtd, chip, wbuf, page, cached,
  1462. (ops->mode == MTD_OOB_RAW));
  1463. if (ret)
  1464. break;
  1465. writelen -= bytes;
  1466. if (!writelen)
  1467. break;
  1468. column = 0;
  1469. buf += bytes;
  1470. realpage++;
  1471. page = realpage & chip->pagemask;
  1472. /* Check, if we cross a chip boundary */
  1473. if (!page) {
  1474. chipnr++;
  1475. chip->select_chip(mtd, -1);
  1476. chip->select_chip(mtd, chipnr);
  1477. }
  1478. }
  1479. ops->retlen = ops->len - writelen;
  1480. if (unlikely(oob))
  1481. ops->oobretlen = ops->ooblen;
  1482. return ret;
  1483. }
  1484. /**
  1485. * nand_write - [MTD Interface] NAND write with ECC
  1486. * @mtd: MTD device structure
  1487. * @to: offset to write to
  1488. * @len: number of bytes to write
  1489. * @retlen: pointer to variable to store the number of written bytes
  1490. * @buf: the data to write
  1491. *
  1492. * NAND write with ECC
  1493. */
  1494. static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
  1495. size_t *retlen, const uint8_t *buf)
  1496. {
  1497. struct nand_chip *chip = mtd->priv;
  1498. int ret;
  1499. /* Do not allow reads past end of device */
  1500. if ((to + len) > mtd->size)
  1501. return -EINVAL;
  1502. if (!len)
  1503. return 0;
  1504. nand_get_device(chip, mtd, FL_WRITING);
  1505. chip->ops.len = len;
  1506. chip->ops.datbuf = (uint8_t *)buf;
  1507. chip->ops.oobbuf = NULL;
  1508. ret = nand_do_write_ops(mtd, to, &chip->ops);
  1509. *retlen = chip->ops.retlen;
  1510. nand_release_device(mtd);
  1511. return ret;
  1512. }
  1513. /**
  1514. * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  1515. * @mtd: MTD device structure
  1516. * @to: offset to write to
  1517. * @ops: oob operation description structure
  1518. *
  1519. * NAND write out-of-band
  1520. */
  1521. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  1522. struct mtd_oob_ops *ops)
  1523. {
  1524. int chipnr, page, status, len;
  1525. struct nand_chip *chip = mtd->priv;
  1526. DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
  1527. (unsigned int)to, (int)ops->ooblen);
  1528. if (ops->mode == MTD_OOB_AUTO)
  1529. len = chip->ecc.layout->oobavail;
  1530. else
  1531. len = mtd->oobsize;
  1532. /* Do not allow write past end of page */
  1533. if ((ops->ooboffs + ops->ooblen) > len) {
  1534. DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
  1535. "Attempt to write past end of page\n");
  1536. return -EINVAL;
  1537. }
  1538. if (unlikely(ops->ooboffs >= len)) {
  1539. DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
  1540. "Attempt to start write outside oob\n");
  1541. return -EINVAL;
  1542. }
  1543. /* Do not allow reads past end of device */
  1544. if (unlikely(to >= mtd->size ||
  1545. ops->ooboffs + ops->ooblen >
  1546. ((mtd->size >> chip->page_shift) -
  1547. (to >> chip->page_shift)) * len)) {
  1548. DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
  1549. "Attempt write beyond end of device\n");
  1550. return -EINVAL;
  1551. }
  1552. chipnr = (int)(to >> chip->chip_shift);
  1553. chip->select_chip(mtd, chipnr);
  1554. /* Shift to get page */
  1555. page = (int)(to >> chip->page_shift);
  1556. /*
  1557. * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
  1558. * of my DiskOnChip 2000 test units) will clear the whole data page too
  1559. * if we don't do this. I have no clue why, but I seem to have 'fixed'
  1560. * it in the doc2000 driver in August 1999. dwmw2.
  1561. */
  1562. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1563. /* Check, if it is write protected */
  1564. if (nand_check_wp(mtd))
  1565. return -EROFS;
  1566. /* Invalidate the page cache, if we write to the cached page */
  1567. if (page == chip->pagebuf)
  1568. chip->pagebuf = -1;
  1569. memset(chip->oob_poi, 0xff, mtd->oobsize);
  1570. nand_fill_oob(chip, ops->oobbuf, ops);
  1571. status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
  1572. memset(chip->oob_poi, 0xff, mtd->oobsize);
  1573. if (status)
  1574. return status;
  1575. ops->oobretlen = ops->ooblen;
  1576. return 0;
  1577. }
  1578. /**
  1579. * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
  1580. * @mtd: MTD device structure
  1581. * @to: offset to write to
  1582. * @ops: oob operation description structure
  1583. */
  1584. static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  1585. struct mtd_oob_ops *ops)
  1586. {
  1587. struct nand_chip *chip = mtd->priv;
  1588. int ret = -ENOTSUPP;
  1589. ops->retlen = 0;
  1590. /* Do not allow writes past end of device */
  1591. if (ops->datbuf && (to + ops->len) > mtd->size) {
  1592. DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
  1593. "Attempt read beyond end of device\n");
  1594. return -EINVAL;
  1595. }
  1596. nand_get_device(chip, mtd, FL_WRITING);
  1597. switch(ops->mode) {
  1598. case MTD_OOB_PLACE:
  1599. case MTD_OOB_AUTO:
  1600. case MTD_OOB_RAW:
  1601. break;
  1602. default:
  1603. goto out;
  1604. }
  1605. if (!ops->datbuf)
  1606. ret = nand_do_write_oob(mtd, to, ops);
  1607. else
  1608. ret = nand_do_write_ops(mtd, to, ops);
  1609. out:
  1610. nand_release_device(mtd);
  1611. return ret;
  1612. }
  1613. /**
  1614. * single_erease_cmd - [GENERIC] NAND standard block erase command function
  1615. * @mtd: MTD device structure
  1616. * @page: the page address of the block which will be erased
  1617. *
  1618. * Standard erase command for NAND chips
  1619. */
  1620. static void single_erase_cmd(struct mtd_info *mtd, int page)
  1621. {
  1622. struct nand_chip *chip = mtd->priv;
  1623. /* Send commands to erase a block */
  1624. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1625. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1626. }
  1627. /**
  1628. * multi_erease_cmd - [GENERIC] AND specific block erase command function
  1629. * @mtd: MTD device structure
  1630. * @page: the page address of the block which will be erased
  1631. *
  1632. * AND multi block erase command function
  1633. * Erase 4 consecutive blocks
  1634. */
  1635. static void multi_erase_cmd(struct mtd_info *mtd, int page)
  1636. {
  1637. struct nand_chip *chip = mtd->priv;
  1638. /* Send commands to erase a block */
  1639. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
  1640. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
  1641. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
  1642. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1643. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1644. }
  1645. /**
  1646. * nand_erase - [MTD Interface] erase block(s)
  1647. * @mtd: MTD device structure
  1648. * @instr: erase instruction
  1649. *
  1650. * Erase one ore more blocks
  1651. */
  1652. static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
  1653. {
  1654. return nand_erase_nand(mtd, instr, 0);
  1655. }
  1656. #define BBT_PAGE_MASK 0xffffff3f
  1657. /**
  1658. * nand_erase_nand - [Internal] erase block(s)
  1659. * @mtd: MTD device structure
  1660. * @instr: erase instruction
  1661. * @allowbbt: allow erasing the bbt area
  1662. *
  1663. * Erase one ore more blocks
  1664. */
  1665. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  1666. int allowbbt)
  1667. {
  1668. int page, len, status, pages_per_block, ret, chipnr;
  1669. struct nand_chip *chip = mtd->priv;
  1670. int rewrite_bbt[NAND_MAX_CHIPS]={0};
  1671. unsigned int bbt_masked_page = 0xffffffff;
  1672. DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
  1673. (unsigned int)instr->addr, (unsigned int)instr->len);
  1674. /* Start address must align on block boundary */
  1675. if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
  1676. DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
  1677. return -EINVAL;
  1678. }
  1679. /* Length must align on block boundary */
  1680. if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
  1681. DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
  1682. "Length not block aligned\n");
  1683. return -EINVAL;
  1684. }
  1685. /* Do not allow erase past end of device */
  1686. if ((instr->len + instr->addr) > mtd->size) {
  1687. DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
  1688. "Erase past end of device\n");
  1689. return -EINVAL;
  1690. }
  1691. instr->fail_addr = 0xffffffff;
  1692. /* Grab the lock and see if the device is available */
  1693. nand_get_device(chip, mtd, FL_ERASING);
  1694. /* Shift to get first page */
  1695. page = (int)(instr->addr >> chip->page_shift);
  1696. chipnr = (int)(instr->addr >> chip->chip_shift);
  1697. /* Calculate pages in each block */
  1698. pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
  1699. /* Select the NAND device */
  1700. chip->select_chip(mtd, chipnr);
  1701. /* Check, if it is write protected */
  1702. if (nand_check_wp(mtd)) {
  1703. DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
  1704. "Device is write protected!!!\n");
  1705. instr->state = MTD_ERASE_FAILED;
  1706. goto erase_exit;
  1707. }
  1708. /*
  1709. * If BBT requires refresh, set the BBT page mask to see if the BBT
  1710. * should be rewritten. Otherwise the mask is set to 0xffffffff which
  1711. * can not be matched. This is also done when the bbt is actually
  1712. * erased to avoid recusrsive updates
  1713. */
  1714. if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
  1715. bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
  1716. /* Loop through the pages */
  1717. len = instr->len;
  1718. instr->state = MTD_ERASING;
  1719. while (len) {
  1720. /*
  1721. * heck if we have a bad block, we do not erase bad blocks !
  1722. */
  1723. if (nand_block_checkbad(mtd, ((loff_t) page) <<
  1724. chip->page_shift, 0, allowbbt)) {
  1725. printk(KERN_WARNING "nand_erase: attempt to erase a "
  1726. "bad block at page 0x%08x\n", page);
  1727. instr->state = MTD_ERASE_FAILED;
  1728. goto erase_exit;
  1729. }
  1730. /*
  1731. * Invalidate the page cache, if we erase the block which
  1732. * contains the current cached page
  1733. */
  1734. if (page <= chip->pagebuf && chip->pagebuf <
  1735. (page + pages_per_block))
  1736. chip->pagebuf = -1;
  1737. chip->erase_cmd(mtd, page & chip->pagemask);
  1738. status = chip->waitfunc(mtd, chip);
  1739. /*
  1740. * See if operation failed and additional status checks are
  1741. * available
  1742. */
  1743. if ((status & NAND_STATUS_FAIL) && (chip->errstat))
  1744. status = chip->errstat(mtd, chip, FL_ERASING,
  1745. status, page);
  1746. /* See if block erase succeeded */
  1747. if (status & NAND_STATUS_FAIL) {
  1748. DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
  1749. "Failed erase, page 0x%08x\n", page);
  1750. instr->state = MTD_ERASE_FAILED;
  1751. instr->fail_addr = (page << chip->page_shift);
  1752. goto erase_exit;
  1753. }
  1754. /*
  1755. * If BBT requires refresh, set the BBT rewrite flag to the
  1756. * page being erased
  1757. */
  1758. if (bbt_masked_page != 0xffffffff &&
  1759. (page & BBT_PAGE_MASK) == bbt_masked_page)
  1760. rewrite_bbt[chipnr] = (page << chip->page_shift);
  1761. /* Increment page address and decrement length */
  1762. len -= (1 << chip->phys_erase_shift);
  1763. page += pages_per_block;
  1764. /* Check, if we cross a chip boundary */
  1765. if (len && !(page & chip->pagemask)) {
  1766. chipnr++;
  1767. chip->select_chip(mtd, -1);
  1768. chip->select_chip(mtd, chipnr);
  1769. /*
  1770. * If BBT requires refresh and BBT-PERCHIP, set the BBT
  1771. * page mask to see if this BBT should be rewritten
  1772. */
  1773. if (bbt_masked_page != 0xffffffff &&
  1774. (chip->bbt_td->options & NAND_BBT_PERCHIP))
  1775. bbt_masked_page = chip->bbt_td->pages[chipnr] &
  1776. BBT_PAGE_MASK;
  1777. }
  1778. }
  1779. instr->state = MTD_ERASE_DONE;
  1780. erase_exit:
  1781. ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
  1782. /* Do call back function */
  1783. if (!ret)
  1784. mtd_erase_callback(instr);
  1785. /* Deselect and wake up anyone waiting on the device */
  1786. nand_release_device(mtd);
  1787. /*
  1788. * If BBT requires refresh and erase was successful, rewrite any
  1789. * selected bad block tables
  1790. */
  1791. if (bbt_masked_page == 0xffffffff || ret)
  1792. return ret;
  1793. for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
  1794. if (!rewrite_bbt[chipnr])
  1795. continue;
  1796. /* update the BBT for chip */
  1797. DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
  1798. "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
  1799. chip->bbt_td->pages[chipnr]);
  1800. nand_update_bbt(mtd, rewrite_bbt[chipnr]);
  1801. }
  1802. /* Return more or less happy */
  1803. return ret;
  1804. }
  1805. /**
  1806. * nand_sync - [MTD Interface] sync
  1807. * @mtd: MTD device structure
  1808. *
  1809. * Sync is actually a wait for chip ready function
  1810. */
  1811. static void nand_sync(struct mtd_info *mtd)
  1812. {
  1813. struct nand_chip *chip = mtd->priv;
  1814. DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
  1815. /* Grab the lock and see if the device is available */
  1816. nand_get_device(chip, mtd, FL_SYNCING);
  1817. /* Release it and go back */
  1818. nand_release_device(mtd);
  1819. }
  1820. /**
  1821. * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  1822. * @mtd: MTD device structure
  1823. * @offs: offset relative to mtd start
  1824. */
  1825. static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
  1826. {
  1827. /* Check for invalid offset */
  1828. if (offs > mtd->size)
  1829. return -EINVAL;
  1830. return nand_block_checkbad(mtd, offs, 1, 0);
  1831. }
  1832. /**
  1833. * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  1834. * @mtd: MTD device structure
  1835. * @ofs: offset relative to mtd start
  1836. */
  1837. static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
  1838. {
  1839. struct nand_chip *chip = mtd->priv;
  1840. int ret;
  1841. if ((ret = nand_block_isbad(mtd, ofs))) {
  1842. /* If it was bad already, return success and do nothing. */
  1843. if (ret > 0)
  1844. return 0;
  1845. return ret;
  1846. }
  1847. return chip->block_markbad(mtd, ofs);
  1848. }
  1849. /**
  1850. * nand_suspend - [MTD Interface] Suspend the NAND flash
  1851. * @mtd: MTD device structure
  1852. */
  1853. static int nand_suspend(struct mtd_info *mtd)
  1854. {
  1855. struct nand_chip *chip = mtd->priv;
  1856. return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
  1857. }
  1858. /**
  1859. * nand_resume - [MTD Interface] Resume the NAND flash
  1860. * @mtd: MTD device structure
  1861. */
  1862. static void nand_resume(struct mtd_info *mtd)
  1863. {
  1864. struct nand_chip *chip = mtd->priv;
  1865. if (chip->state == FL_PM_SUSPENDED)
  1866. nand_release_device(mtd);
  1867. else
  1868. printk(KERN_ERR "nand_resume() called for a chip which is not "
  1869. "in suspended state\n");
  1870. }
  1871. /*
  1872. * Set default functions
  1873. */
  1874. static void nand_set_defaults(struct nand_chip *chip, int busw)
  1875. {
  1876. /* check for proper chip_delay setup, set 20us if not */
  1877. if (!chip->chip_delay)
  1878. chip->chip_delay = 20;
  1879. /* check, if a user supplied command function given */
  1880. if (chip->cmdfunc == NULL)
  1881. chip->cmdfunc = nand_command;
  1882. /* check, if a user supplied wait function given */
  1883. if (chip->waitfunc == NULL)
  1884. chip->waitfunc = nand_wait;
  1885. if (!chip->select_chip)
  1886. chip->select_chip = nand_select_chip;
  1887. if (!chip->read_byte)
  1888. chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
  1889. if (!chip->read_word)
  1890. chip->read_word = nand_read_word;
  1891. if (!chip->block_bad)
  1892. chip->block_bad = nand_block_bad;
  1893. if (!chip->block_markbad)
  1894. chip->block_markbad = nand_default_block_markbad;
  1895. if (!chip->write_buf)
  1896. chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
  1897. if (!chip->read_buf)
  1898. chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
  1899. if (!chip->verify_buf)
  1900. chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
  1901. if (!chip->scan_bbt)
  1902. chip->scan_bbt = nand_default_bbt;
  1903. if (!chip->controller) {
  1904. chip->controller = &chip->hwcontrol;
  1905. spin_lock_init(&chip->controller->lock);
  1906. init_waitqueue_head(&chip->controller->wq);
  1907. }
  1908. }
  1909. /*
  1910. * Get the flash and manufacturer id and lookup if the type is supported
  1911. */
  1912. static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
  1913. struct nand_chip *chip,
  1914. int busw, int *maf_id)
  1915. {
  1916. struct nand_flash_dev *type = NULL;
  1917. int i, dev_id, maf_idx;
  1918. /* Select the device */
  1919. chip->select_chip(mtd, 0);
  1920. /* Send the command for reading device ID */
  1921. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  1922. /* Read manufacturer and device IDs */
  1923. *maf_id = chip->read_byte(mtd);
  1924. dev_id = chip->read_byte(mtd);
  1925. /* Lookup the flash id */
  1926. for (i = 0; nand_flash_ids[i].name != NULL; i++) {
  1927. if (dev_id == nand_flash_ids[i].id) {
  1928. type = &nand_flash_ids[i];
  1929. break;
  1930. }
  1931. }
  1932. if (!type)
  1933. return ERR_PTR(-ENODEV);
  1934. if (!mtd->name)
  1935. mtd->name = type->name;
  1936. chip->chipsize = type->chipsize << 20;
  1937. /* Newer devices have all the information in additional id bytes */
  1938. if (!type->pagesize) {
  1939. int extid;
  1940. /* The 3rd id byte holds MLC / multichip data */
  1941. chip->cellinfo = chip->read_byte(mtd);
  1942. /* The 4th id byte is the important one */
  1943. extid = chip->read_byte(mtd);
  1944. /* Calc pagesize */
  1945. mtd->writesize = 1024 << (extid & 0x3);
  1946. extid >>= 2;
  1947. /* Calc oobsize */
  1948. mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
  1949. extid >>= 2;
  1950. /* Calc blocksize. Blocksize is multiples of 64KiB */
  1951. mtd->erasesize = (64 * 1024) << (extid & 0x03);
  1952. extid >>= 2;
  1953. /* Get buswidth information */
  1954. busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
  1955. } else {
  1956. /*
  1957. * Old devices have chip data hardcoded in the device id table
  1958. */
  1959. mtd->erasesize = type->erasesize;
  1960. mtd->writesize = type->pagesize;
  1961. mtd->oobsize = mtd->writesize / 32;
  1962. busw = type->options & NAND_BUSWIDTH_16;
  1963. }
  1964. /* Try to identify manufacturer */
  1965. for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
  1966. if (nand_manuf_ids[maf_idx].id == *maf_id)
  1967. break;
  1968. }
  1969. /*
  1970. * Check, if buswidth is correct. Hardware drivers should set
  1971. * chip correct !
  1972. */
  1973. if (busw != (chip->options & NAND_BUSWIDTH_16)) {
  1974. printk(KERN_INFO "NAND device: Manufacturer ID:"
  1975. " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
  1976. dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
  1977. printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
  1978. (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
  1979. busw ? 16 : 8);
  1980. return ERR_PTR(-EINVAL);
  1981. }
  1982. /* Calculate the address shift from the page size */
  1983. chip->page_shift = ffs(mtd->writesize) - 1;
  1984. /* Convert chipsize to number of pages per chip -1. */
  1985. chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
  1986. chip->bbt_erase_shift = chip->phys_erase_shift =
  1987. ffs(mtd->erasesize) - 1;
  1988. chip->chip_shift = ffs(chip->chipsize) - 1;
  1989. /* Set the bad block position */
  1990. chip->badblockpos = mtd->writesize > 512 ?
  1991. NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
  1992. /* Get chip options, preserve non chip based options */
  1993. chip->options &= ~NAND_CHIPOPTIONS_MSK;
  1994. chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
  1995. /*
  1996. * Set chip as a default. Board drivers can override it, if necessary
  1997. */
  1998. chip->options |= NAND_NO_AUTOINCR;
  1999. /* Check if chip is a not a samsung device. Do not clear the
  2000. * options for chips which are not having an extended id.
  2001. */
  2002. if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
  2003. chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
  2004. /* Check for AND chips with 4 page planes */
  2005. if (chip->options & NAND_4PAGE_ARRAY)
  2006. chip->erase_cmd = multi_erase_cmd;
  2007. else
  2008. chip->erase_cmd = single_erase_cmd;
  2009. /* Do not replace user supplied command function ! */
  2010. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  2011. chip->cmdfunc = nand_command_lp;
  2012. printk(KERN_INFO "NAND device: Manufacturer ID:"
  2013. " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
  2014. nand_manuf_ids[maf_idx].name, type->name);
  2015. return type;
  2016. }
  2017. /**
  2018. * nand_scan_ident - [NAND Interface] Scan for the NAND device
  2019. * @mtd: MTD device structure
  2020. * @maxchips: Number of chips to scan for
  2021. *
  2022. * This is the first phase of the normal nand_scan() function. It
  2023. * reads the flash ID and sets up MTD fields accordingly.
  2024. *
  2025. * The mtd->owner field must be set to the module of the caller.
  2026. */
  2027. int nand_scan_ident(struct mtd_info *mtd, int maxchips)
  2028. {
  2029. int i, busw, nand_maf_id;
  2030. struct nand_chip *chip = mtd->priv;
  2031. struct nand_flash_dev *type;
  2032. /* Get buswidth to select the correct functions */
  2033. busw = chip->options & NAND_BUSWIDTH_16;
  2034. /* Set the default functions */
  2035. nand_set_defaults(chip, busw);
  2036. /* Read the flash type */
  2037. type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
  2038. if (IS_ERR(type)) {
  2039. printk(KERN_WARNING "No NAND device found!!!\n");
  2040. chip->select_chip(mtd, -1);
  2041. return PTR_ERR(type);
  2042. }
  2043. /* Check for a chip array */
  2044. for (i = 1; i < maxchips; i++) {
  2045. chip->select_chip(mtd, i);
  2046. /* Send the command for reading device ID */
  2047. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  2048. /* Read manufacturer and device IDs */
  2049. if (nand_maf_id != chip->read_byte(mtd) ||
  2050. type->id != chip->read_byte(mtd))
  2051. break;
  2052. }
  2053. if (i > 1)
  2054. printk(KERN_INFO "%d NAND chips detected\n", i);
  2055. /* Store the number of chips and calc total size for mtd */
  2056. chip->numchips = i;
  2057. mtd->size = i * chip->chipsize;
  2058. return 0;
  2059. }
  2060. /**
  2061. * nand_scan_tail - [NAND Interface] Scan for the NAND device
  2062. * @mtd: MTD device structure
  2063. * @maxchips: Number of chips to scan for
  2064. *
  2065. * This is the second phase of the normal nand_scan() function. It
  2066. * fills out all the uninitialized function pointers with the defaults
  2067. * and scans for a bad block table if appropriate.
  2068. */
  2069. int nand_scan_tail(struct mtd_info *mtd)
  2070. {
  2071. int i;
  2072. struct nand_chip *chip = mtd->priv;
  2073. if (!(chip->options & NAND_OWN_BUFFERS))
  2074. chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
  2075. if (!chip->buffers)
  2076. return -ENOMEM;
  2077. /* Set the internal oob buffer location, just after the page data */
  2078. chip->oob_poi = chip->buffers->databuf + mtd->writesize;
  2079. /*
  2080. * If no default placement scheme is given, select an appropriate one
  2081. */
  2082. if (!chip->ecc.layout) {
  2083. switch (mtd->oobsize) {
  2084. case 8:
  2085. chip->ecc.layout = &nand_oob_8;
  2086. break;
  2087. case 16:
  2088. chip->ecc.layout = &nand_oob_16;
  2089. break;
  2090. case 64:
  2091. chip->ecc.layout = &nand_oob_64;
  2092. break;
  2093. default:
  2094. printk(KERN_WARNING "No oob scheme defined for "
  2095. "oobsize %d\n", mtd->oobsize);
  2096. BUG();
  2097. }
  2098. }
  2099. if (!chip->write_page)
  2100. chip->write_page = nand_write_page;
  2101. /*
  2102. * check ECC mode, default to software if 3byte/512byte hardware ECC is
  2103. * selected and we have 256 byte pagesize fallback to software ECC
  2104. */
  2105. if (!chip->ecc.read_page_raw)
  2106. chip->ecc.read_page_raw = nand_read_page_raw;
  2107. if (!chip->ecc.write_page_raw)
  2108. chip->ecc.write_page_raw = nand_write_page_raw;
  2109. switch (chip->ecc.mode) {
  2110. case NAND_ECC_HW:
  2111. /* Use standard hwecc read page function ? */
  2112. if (!chip->ecc.read_page)
  2113. chip->ecc.read_page = nand_read_page_hwecc;
  2114. if (!chip->ecc.write_page)
  2115. chip->ecc.write_page = nand_write_page_hwecc;
  2116. if (!chip->ecc.read_oob)
  2117. chip->ecc.read_oob = nand_read_oob_std;
  2118. if (!chip->ecc.write_oob)
  2119. chip->ecc.write_oob = nand_write_oob_std;
  2120. case NAND_ECC_HW_SYNDROME:
  2121. if (!chip->ecc.calculate || !chip->ecc.correct ||
  2122. !chip->ecc.hwctl) {
  2123. printk(KERN_WARNING "No ECC functions supplied, "
  2124. "Hardware ECC not possible\n");
  2125. BUG();
  2126. }
  2127. /* Use standard syndrome read/write page function ? */
  2128. if (!chip->ecc.read_page)
  2129. chip->ecc.read_page = nand_read_page_syndrome;
  2130. if (!chip->ecc.write_page)
  2131. chip->ecc.write_page = nand_write_page_syndrome;
  2132. if (!chip->ecc.read_oob)
  2133. chip->ecc.read_oob = nand_read_oob_syndrome;
  2134. if (!chip->ecc.write_oob)
  2135. chip->ecc.write_oob = nand_write_oob_syndrome;
  2136. if (mtd->writesize >= chip->ecc.size)
  2137. break;
  2138. printk(KERN_WARNING "%d byte HW ECC not possible on "
  2139. "%d byte page size, fallback to SW ECC\n",
  2140. chip->ecc.size, mtd->writesize);
  2141. chip->ecc.mode = NAND_ECC_SOFT;
  2142. case NAND_ECC_SOFT:
  2143. chip->ecc.calculate = nand_calculate_ecc;
  2144. chip->ecc.correct = nand_correct_data;
  2145. chip->ecc.read_page = nand_read_page_swecc;
  2146. chip->ecc.write_page = nand_write_page_swecc;
  2147. chip->ecc.read_oob = nand_read_oob_std;
  2148. chip->ecc.write_oob = nand_write_oob_std;
  2149. chip->ecc.size = 256;
  2150. chip->ecc.bytes = 3;
  2151. break;
  2152. case NAND_ECC_NONE:
  2153. printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
  2154. "This is not recommended !!\n");
  2155. chip->ecc.read_page = nand_read_page_raw;
  2156. chip->ecc.write_page = nand_write_page_raw;
  2157. chip->ecc.read_oob = nand_read_oob_std;
  2158. chip->ecc.write_oob = nand_write_oob_std;
  2159. chip->ecc.size = mtd->writesize;
  2160. chip->ecc.bytes = 0;
  2161. break;
  2162. default:
  2163. printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
  2164. chip->ecc.mode);
  2165. BUG();
  2166. }
  2167. /*
  2168. * The number of bytes available for a client to place data into
  2169. * the out of band area
  2170. */
  2171. chip->ecc.layout->oobavail = 0;
  2172. for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
  2173. chip->ecc.layout->oobavail +=
  2174. chip->ecc.layout->oobfree[i].length;
  2175. mtd->oobavail = chip->ecc.layout->oobavail;
  2176. /*
  2177. * Set the number of read / write steps for one page depending on ECC
  2178. * mode
  2179. */
  2180. chip->ecc.steps = mtd->writesize / chip->ecc.size;
  2181. if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
  2182. printk(KERN_WARNING "Invalid ecc parameters\n");
  2183. BUG();
  2184. }
  2185. chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
  2186. /*
  2187. * Allow subpage writes up to ecc.steps. Not possible for MLC
  2188. * FLASH.
  2189. */
  2190. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
  2191. !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
  2192. switch(chip->ecc.steps) {
  2193. case 2:
  2194. mtd->subpage_sft = 1;
  2195. break;
  2196. case 4:
  2197. case 8:
  2198. mtd->subpage_sft = 2;
  2199. break;
  2200. }
  2201. }
  2202. chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
  2203. /* Initialize state */
  2204. chip->state = FL_READY;
  2205. /* De-select the device */
  2206. chip->select_chip(mtd, -1);
  2207. /* Invalidate the pagebuffer reference */
  2208. chip->pagebuf = -1;
  2209. /* Fill in remaining MTD driver data */
  2210. mtd->type = MTD_NANDFLASH;
  2211. mtd->flags = MTD_CAP_NANDFLASH;
  2212. mtd->erase = nand_erase;
  2213. mtd->point = NULL;
  2214. mtd->unpoint = NULL;
  2215. mtd->read = nand_read;
  2216. mtd->write = nand_write;
  2217. mtd->read_oob = nand_read_oob;
  2218. mtd->write_oob = nand_write_oob;
  2219. mtd->sync = nand_sync;
  2220. mtd->lock = NULL;
  2221. mtd->unlock = NULL;
  2222. mtd->suspend = nand_suspend;
  2223. mtd->resume = nand_resume;
  2224. mtd->block_isbad = nand_block_isbad;
  2225. mtd->block_markbad = nand_block_markbad;
  2226. /* propagate ecc.layout to mtd_info */
  2227. mtd->ecclayout = chip->ecc.layout;
  2228. /* Check, if we should skip the bad block table scan */
  2229. if (chip->options & NAND_SKIP_BBTSCAN)
  2230. return 0;
  2231. /* Build bad block table */
  2232. return chip->scan_bbt(mtd);
  2233. }
  2234. /* module_text_address() isn't exported, and it's mostly a pointless
  2235. test if this is a module _anyway_ -- they'd have to try _really_ hard
  2236. to call us from in-kernel code if the core NAND support is modular. */
  2237. #ifdef MODULE
  2238. #define caller_is_module() (1)
  2239. #else
  2240. #define caller_is_module() \
  2241. module_text_address((unsigned long)__builtin_return_address(0))
  2242. #endif
  2243. /**
  2244. * nand_scan - [NAND Interface] Scan for the NAND device
  2245. * @mtd: MTD device structure
  2246. * @maxchips: Number of chips to scan for
  2247. *
  2248. * This fills out all the uninitialized function pointers
  2249. * with the defaults.
  2250. * The flash ID is read and the mtd/chip structures are
  2251. * filled with the appropriate values.
  2252. * The mtd->owner field must be set to the module of the caller
  2253. *
  2254. */
  2255. int nand_scan(struct mtd_info *mtd, int maxchips)
  2256. {
  2257. int ret;
  2258. /* Many callers got this wrong, so check for it for a while... */
  2259. if (!mtd->owner && caller_is_module()) {
  2260. printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
  2261. BUG();
  2262. }
  2263. ret = nand_scan_ident(mtd, maxchips);
  2264. if (!ret)
  2265. ret = nand_scan_tail(mtd);
  2266. return ret;
  2267. }
  2268. /**
  2269. * nand_release - [NAND Interface] Free resources held by the NAND device
  2270. * @mtd: MTD device structure
  2271. */
  2272. void nand_release(struct mtd_info *mtd)
  2273. {
  2274. struct nand_chip *chip = mtd->priv;
  2275. #ifdef CONFIG_MTD_PARTITIONS
  2276. /* Deregister partitions */
  2277. del_mtd_partitions(mtd);
  2278. #endif
  2279. /* Deregister the device */
  2280. del_mtd_device(mtd);
  2281. /* Free bad block table memory */
  2282. kfree(chip->bbt);
  2283. if (!(chip->options & NAND_OWN_BUFFERS))
  2284. kfree(chip->buffers);
  2285. }
  2286. EXPORT_SYMBOL_GPL(nand_scan);
  2287. EXPORT_SYMBOL_GPL(nand_scan_ident);
  2288. EXPORT_SYMBOL_GPL(nand_scan_tail);
  2289. EXPORT_SYMBOL_GPL(nand_release);
  2290. static int __init nand_base_init(void)
  2291. {
  2292. led_trigger_register_simple("nand-disk", &nand_led_trigger);
  2293. return 0;
  2294. }
  2295. static void __exit nand_base_exit(void)
  2296. {
  2297. led_trigger_unregister_simple(nand_led_trigger);
  2298. }
  2299. module_init(nand_base_init);
  2300. module_exit(nand_base_exit);
  2301. MODULE_LICENSE("GPL");
  2302. MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
  2303. MODULE_DESCRIPTION("Generic NAND flash driver code");