mthca_main.c 37 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/errno.h>
  39. #include <linux/pci.h>
  40. #include <linux/interrupt.h>
  41. #include "mthca_dev.h"
  42. #include "mthca_config_reg.h"
  43. #include "mthca_cmd.h"
  44. #include "mthca_profile.h"
  45. #include "mthca_memfree.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. MODULE_VERSION(DRV_VERSION);
  50. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  51. int mthca_debug_level = 0;
  52. module_param_named(debug_level, mthca_debug_level, int, 0644);
  53. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  54. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  55. #ifdef CONFIG_PCI_MSI
  56. static int msi_x = 0;
  57. module_param(msi_x, int, 0444);
  58. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  59. static int msi = 0;
  60. module_param(msi, int, 0444);
  61. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  62. #else /* CONFIG_PCI_MSI */
  63. #define msi_x (0)
  64. #define msi (0)
  65. #endif /* CONFIG_PCI_MSI */
  66. static int tune_pci = 0;
  67. module_param(tune_pci, int, 0444);
  68. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  69. DEFINE_MUTEX(mthca_device_mutex);
  70. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  71. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  72. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  73. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  74. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  75. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  76. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  77. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  78. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  79. static struct mthca_profile hca_profile = {
  80. .num_qp = MTHCA_DEFAULT_NUM_QP,
  81. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  82. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  83. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  84. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  85. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  86. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  87. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  88. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  89. };
  90. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  91. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  92. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  93. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  94. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  95. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  96. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  97. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  98. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  99. MODULE_PARM_DESC(num_mpt,
  100. "maximum number of memory protection table entries per HCA");
  101. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  102. MODULE_PARM_DESC(num_mtt,
  103. "maximum number of memory translation table segments per HCA");
  104. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  105. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  106. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  107. MODULE_PARM_DESC(fmr_reserved_mtts,
  108. "number of memory translation table segments reserved for FMR");
  109. static const char mthca_version[] __devinitdata =
  110. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  111. DRV_VERSION " (" DRV_RELDATE ")\n";
  112. static int mthca_tune_pci(struct mthca_dev *mdev)
  113. {
  114. int cap;
  115. u16 val;
  116. if (!tune_pci)
  117. return 0;
  118. /* First try to max out Read Byte Count */
  119. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  120. if (cap) {
  121. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  122. mthca_err(mdev, "Couldn't read PCI-X command register, "
  123. "aborting.\n");
  124. return -ENODEV;
  125. }
  126. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  127. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  128. mthca_err(mdev, "Couldn't write PCI-X command register, "
  129. "aborting.\n");
  130. return -ENODEV;
  131. }
  132. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  133. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  134. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  135. if (cap) {
  136. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  137. mthca_err(mdev, "Couldn't read PCI Express device control "
  138. "register, aborting.\n");
  139. return -ENODEV;
  140. }
  141. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  142. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  143. mthca_err(mdev, "Couldn't write PCI Express device control "
  144. "register, aborting.\n");
  145. return -ENODEV;
  146. }
  147. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  148. mthca_info(mdev, "No PCI Express capability, "
  149. "not setting Max Read Request Size.\n");
  150. return 0;
  151. }
  152. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  153. {
  154. int err;
  155. u8 status;
  156. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  157. if (err) {
  158. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  159. return err;
  160. }
  161. if (status) {
  162. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  163. "aborting.\n", status);
  164. return -EINVAL;
  165. }
  166. if (dev_lim->min_page_sz > PAGE_SIZE) {
  167. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  168. "kernel PAGE_SIZE of %ld, aborting.\n",
  169. dev_lim->min_page_sz, PAGE_SIZE);
  170. return -ENODEV;
  171. }
  172. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  173. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  174. "aborting.\n",
  175. dev_lim->num_ports, MTHCA_MAX_PORTS);
  176. return -ENODEV;
  177. }
  178. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  179. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  180. "PCI resource 2 size of 0x%llx, aborting.\n",
  181. dev_lim->uar_size,
  182. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  183. return -ENODEV;
  184. }
  185. mdev->limits.num_ports = dev_lim->num_ports;
  186. mdev->limits.vl_cap = dev_lim->max_vl;
  187. mdev->limits.mtu_cap = dev_lim->max_mtu;
  188. mdev->limits.gid_table_len = dev_lim->max_gids;
  189. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  190. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  191. mdev->limits.max_sg = dev_lim->max_sg;
  192. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  193. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  194. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  195. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  196. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  197. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  198. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  199. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  200. /*
  201. * Subtract 1 from the limit because we need to allocate a
  202. * spare CQE so the HCA HW can tell the difference between an
  203. * empty CQ and a full CQ.
  204. */
  205. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  206. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  207. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  208. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  209. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  210. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  211. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  212. mdev->limits.port_width_cap = dev_lim->max_port_width;
  213. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  214. mdev->limits.flags = dev_lim->flags;
  215. /*
  216. * For old FW that doesn't return static rate support, use a
  217. * value of 0x3 (only static rate values of 0 or 1 are handled),
  218. * except on Sinai, where even old FW can handle static rate
  219. * values of 2 and 3.
  220. */
  221. if (dev_lim->stat_rate_support)
  222. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  223. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  224. mdev->limits.stat_rate_support = 0xf;
  225. else
  226. mdev->limits.stat_rate_support = 0x3;
  227. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  228. May be doable since hardware supports it for SRQ.
  229. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  230. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  231. supported by driver. */
  232. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  233. IB_DEVICE_PORT_ACTIVE_EVENT |
  234. IB_DEVICE_SYS_IMAGE_GUID |
  235. IB_DEVICE_RC_RNR_NAK_GEN;
  236. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  237. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  238. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  239. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  240. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  241. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  242. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  243. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  244. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  245. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  246. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  247. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  248. return 0;
  249. }
  250. static int mthca_init_tavor(struct mthca_dev *mdev)
  251. {
  252. u8 status;
  253. int err;
  254. struct mthca_dev_lim dev_lim;
  255. struct mthca_profile profile;
  256. struct mthca_init_hca_param init_hca;
  257. err = mthca_SYS_EN(mdev, &status);
  258. if (err) {
  259. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  260. return err;
  261. }
  262. if (status) {
  263. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  264. "aborting.\n", status);
  265. return -EINVAL;
  266. }
  267. err = mthca_QUERY_FW(mdev, &status);
  268. if (err) {
  269. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  270. goto err_disable;
  271. }
  272. if (status) {
  273. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  274. "aborting.\n", status);
  275. err = -EINVAL;
  276. goto err_disable;
  277. }
  278. err = mthca_QUERY_DDR(mdev, &status);
  279. if (err) {
  280. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  281. goto err_disable;
  282. }
  283. if (status) {
  284. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  285. "aborting.\n", status);
  286. err = -EINVAL;
  287. goto err_disable;
  288. }
  289. err = mthca_dev_lim(mdev, &dev_lim);
  290. if (err) {
  291. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  292. goto err_disable;
  293. }
  294. profile = hca_profile;
  295. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  296. profile.uarc_size = 0;
  297. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  298. profile.num_srq = dev_lim.max_srqs;
  299. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  300. if (err < 0)
  301. goto err_disable;
  302. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  303. if (err) {
  304. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  305. goto err_disable;
  306. }
  307. if (status) {
  308. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  309. "aborting.\n", status);
  310. err = -EINVAL;
  311. goto err_disable;
  312. }
  313. return 0;
  314. err_disable:
  315. mthca_SYS_DIS(mdev, &status);
  316. return err;
  317. }
  318. static int mthca_load_fw(struct mthca_dev *mdev)
  319. {
  320. u8 status;
  321. int err;
  322. /* FIXME: use HCA-attached memory for FW if present */
  323. mdev->fw.arbel.fw_icm =
  324. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  325. GFP_HIGHUSER | __GFP_NOWARN);
  326. if (!mdev->fw.arbel.fw_icm) {
  327. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  328. return -ENOMEM;
  329. }
  330. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  331. if (err) {
  332. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  333. goto err_free;
  334. }
  335. if (status) {
  336. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  337. err = -EINVAL;
  338. goto err_free;
  339. }
  340. err = mthca_RUN_FW(mdev, &status);
  341. if (err) {
  342. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  343. goto err_unmap_fa;
  344. }
  345. if (status) {
  346. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  347. err = -EINVAL;
  348. goto err_unmap_fa;
  349. }
  350. return 0;
  351. err_unmap_fa:
  352. mthca_UNMAP_FA(mdev, &status);
  353. err_free:
  354. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  355. return err;
  356. }
  357. static int mthca_init_icm(struct mthca_dev *mdev,
  358. struct mthca_dev_lim *dev_lim,
  359. struct mthca_init_hca_param *init_hca,
  360. u64 icm_size)
  361. {
  362. u64 aux_pages;
  363. u8 status;
  364. int err;
  365. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  366. if (err) {
  367. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  368. return err;
  369. }
  370. if (status) {
  371. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  372. "aborting.\n", status);
  373. return -EINVAL;
  374. }
  375. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  376. (unsigned long long) icm_size >> 10,
  377. (unsigned long long) aux_pages << 2);
  378. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  379. GFP_HIGHUSER | __GFP_NOWARN);
  380. if (!mdev->fw.arbel.aux_icm) {
  381. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  382. return -ENOMEM;
  383. }
  384. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  385. if (err) {
  386. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  387. goto err_free_aux;
  388. }
  389. if (status) {
  390. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  391. err = -EINVAL;
  392. goto err_free_aux;
  393. }
  394. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  395. if (err) {
  396. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  397. goto err_unmap_aux;
  398. }
  399. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  400. MTHCA_MTT_SEG_SIZE,
  401. mdev->limits.num_mtt_segs,
  402. mdev->limits.reserved_mtts, 1);
  403. if (!mdev->mr_table.mtt_table) {
  404. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  405. err = -ENOMEM;
  406. goto err_unmap_eq;
  407. }
  408. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  409. dev_lim->mpt_entry_sz,
  410. mdev->limits.num_mpts,
  411. mdev->limits.reserved_mrws, 1);
  412. if (!mdev->mr_table.mpt_table) {
  413. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  414. err = -ENOMEM;
  415. goto err_unmap_mtt;
  416. }
  417. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  418. dev_lim->qpc_entry_sz,
  419. mdev->limits.num_qps,
  420. mdev->limits.reserved_qps, 0);
  421. if (!mdev->qp_table.qp_table) {
  422. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  423. err = -ENOMEM;
  424. goto err_unmap_mpt;
  425. }
  426. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  427. dev_lim->eqpc_entry_sz,
  428. mdev->limits.num_qps,
  429. mdev->limits.reserved_qps, 0);
  430. if (!mdev->qp_table.eqp_table) {
  431. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  432. err = -ENOMEM;
  433. goto err_unmap_qp;
  434. }
  435. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  436. MTHCA_RDB_ENTRY_SIZE,
  437. mdev->limits.num_qps <<
  438. mdev->qp_table.rdb_shift,
  439. 0, 0);
  440. if (!mdev->qp_table.rdb_table) {
  441. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  442. err = -ENOMEM;
  443. goto err_unmap_eqp;
  444. }
  445. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  446. dev_lim->cqc_entry_sz,
  447. mdev->limits.num_cqs,
  448. mdev->limits.reserved_cqs, 0);
  449. if (!mdev->cq_table.table) {
  450. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  451. err = -ENOMEM;
  452. goto err_unmap_rdb;
  453. }
  454. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  455. mdev->srq_table.table =
  456. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  457. dev_lim->srq_entry_sz,
  458. mdev->limits.num_srqs,
  459. mdev->limits.reserved_srqs, 0);
  460. if (!mdev->srq_table.table) {
  461. mthca_err(mdev, "Failed to map SRQ context memory, "
  462. "aborting.\n");
  463. err = -ENOMEM;
  464. goto err_unmap_cq;
  465. }
  466. }
  467. /*
  468. * It's not strictly required, but for simplicity just map the
  469. * whole multicast group table now. The table isn't very big
  470. * and it's a lot easier than trying to track ref counts.
  471. */
  472. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  473. MTHCA_MGM_ENTRY_SIZE,
  474. mdev->limits.num_mgms +
  475. mdev->limits.num_amgms,
  476. mdev->limits.num_mgms +
  477. mdev->limits.num_amgms,
  478. 0);
  479. if (!mdev->mcg_table.table) {
  480. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  481. err = -ENOMEM;
  482. goto err_unmap_srq;
  483. }
  484. return 0;
  485. err_unmap_srq:
  486. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  487. mthca_free_icm_table(mdev, mdev->srq_table.table);
  488. err_unmap_cq:
  489. mthca_free_icm_table(mdev, mdev->cq_table.table);
  490. err_unmap_rdb:
  491. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  492. err_unmap_eqp:
  493. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  494. err_unmap_qp:
  495. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  496. err_unmap_mpt:
  497. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  498. err_unmap_mtt:
  499. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  500. err_unmap_eq:
  501. mthca_unmap_eq_icm(mdev);
  502. err_unmap_aux:
  503. mthca_UNMAP_ICM_AUX(mdev, &status);
  504. err_free_aux:
  505. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  506. return err;
  507. }
  508. static void mthca_free_icms(struct mthca_dev *mdev)
  509. {
  510. u8 status;
  511. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  512. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  513. mthca_free_icm_table(mdev, mdev->srq_table.table);
  514. mthca_free_icm_table(mdev, mdev->cq_table.table);
  515. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  516. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  517. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  518. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  519. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  520. mthca_unmap_eq_icm(mdev);
  521. mthca_UNMAP_ICM_AUX(mdev, &status);
  522. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  523. }
  524. static int mthca_init_arbel(struct mthca_dev *mdev)
  525. {
  526. struct mthca_dev_lim dev_lim;
  527. struct mthca_profile profile;
  528. struct mthca_init_hca_param init_hca;
  529. u64 icm_size;
  530. u8 status;
  531. int err;
  532. err = mthca_QUERY_FW(mdev, &status);
  533. if (err) {
  534. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  535. return err;
  536. }
  537. if (status) {
  538. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  539. "aborting.\n", status);
  540. return -EINVAL;
  541. }
  542. err = mthca_ENABLE_LAM(mdev, &status);
  543. if (err) {
  544. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  545. return err;
  546. }
  547. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  548. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  549. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  550. } else if (status) {
  551. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  552. "aborting.\n", status);
  553. return -EINVAL;
  554. }
  555. err = mthca_load_fw(mdev);
  556. if (err) {
  557. mthca_err(mdev, "Failed to start FW, aborting.\n");
  558. goto err_disable;
  559. }
  560. err = mthca_dev_lim(mdev, &dev_lim);
  561. if (err) {
  562. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  563. goto err_stop_fw;
  564. }
  565. profile = hca_profile;
  566. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  567. profile.num_udav = 0;
  568. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  569. profile.num_srq = dev_lim.max_srqs;
  570. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  571. if ((int) icm_size < 0) {
  572. err = icm_size;
  573. goto err_stop_fw;
  574. }
  575. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  576. if (err)
  577. goto err_stop_fw;
  578. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  579. if (err) {
  580. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  581. goto err_free_icm;
  582. }
  583. if (status) {
  584. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  585. "aborting.\n", status);
  586. err = -EINVAL;
  587. goto err_free_icm;
  588. }
  589. return 0;
  590. err_free_icm:
  591. mthca_free_icms(mdev);
  592. err_stop_fw:
  593. mthca_UNMAP_FA(mdev, &status);
  594. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  595. err_disable:
  596. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  597. mthca_DISABLE_LAM(mdev, &status);
  598. return err;
  599. }
  600. static void mthca_close_hca(struct mthca_dev *mdev)
  601. {
  602. u8 status;
  603. mthca_CLOSE_HCA(mdev, 0, &status);
  604. if (mthca_is_memfree(mdev)) {
  605. mthca_free_icms(mdev);
  606. mthca_UNMAP_FA(mdev, &status);
  607. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  608. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  609. mthca_DISABLE_LAM(mdev, &status);
  610. } else
  611. mthca_SYS_DIS(mdev, &status);
  612. }
  613. static int mthca_init_hca(struct mthca_dev *mdev)
  614. {
  615. u8 status;
  616. int err;
  617. struct mthca_adapter adapter;
  618. if (mthca_is_memfree(mdev))
  619. err = mthca_init_arbel(mdev);
  620. else
  621. err = mthca_init_tavor(mdev);
  622. if (err)
  623. return err;
  624. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  625. if (err) {
  626. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  627. goto err_close;
  628. }
  629. if (status) {
  630. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  631. "aborting.\n", status);
  632. err = -EINVAL;
  633. goto err_close;
  634. }
  635. mdev->eq_table.inta_pin = adapter.inta_pin;
  636. mdev->rev_id = adapter.revision_id;
  637. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  638. return 0;
  639. err_close:
  640. mthca_close_hca(mdev);
  641. return err;
  642. }
  643. static int mthca_setup_hca(struct mthca_dev *dev)
  644. {
  645. int err;
  646. u8 status;
  647. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  648. err = mthca_init_uar_table(dev);
  649. if (err) {
  650. mthca_err(dev, "Failed to initialize "
  651. "user access region table, aborting.\n");
  652. return err;
  653. }
  654. err = mthca_uar_alloc(dev, &dev->driver_uar);
  655. if (err) {
  656. mthca_err(dev, "Failed to allocate driver access region, "
  657. "aborting.\n");
  658. goto err_uar_table_free;
  659. }
  660. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  661. if (!dev->kar) {
  662. mthca_err(dev, "Couldn't map kernel access region, "
  663. "aborting.\n");
  664. err = -ENOMEM;
  665. goto err_uar_free;
  666. }
  667. err = mthca_init_pd_table(dev);
  668. if (err) {
  669. mthca_err(dev, "Failed to initialize "
  670. "protection domain table, aborting.\n");
  671. goto err_kar_unmap;
  672. }
  673. err = mthca_init_mr_table(dev);
  674. if (err) {
  675. mthca_err(dev, "Failed to initialize "
  676. "memory region table, aborting.\n");
  677. goto err_pd_table_free;
  678. }
  679. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  680. if (err) {
  681. mthca_err(dev, "Failed to create driver PD, "
  682. "aborting.\n");
  683. goto err_mr_table_free;
  684. }
  685. err = mthca_init_eq_table(dev);
  686. if (err) {
  687. mthca_err(dev, "Failed to initialize "
  688. "event queue table, aborting.\n");
  689. goto err_pd_free;
  690. }
  691. err = mthca_cmd_use_events(dev);
  692. if (err) {
  693. mthca_err(dev, "Failed to switch to event-driven "
  694. "firmware commands, aborting.\n");
  695. goto err_eq_table_free;
  696. }
  697. err = mthca_NOP(dev, &status);
  698. if (err || status) {
  699. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  700. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  701. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  702. dev->pdev->irq);
  703. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  704. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  705. else
  706. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  707. goto err_cmd_poll;
  708. }
  709. mthca_dbg(dev, "NOP command IRQ test passed\n");
  710. err = mthca_init_cq_table(dev);
  711. if (err) {
  712. mthca_err(dev, "Failed to initialize "
  713. "completion queue table, aborting.\n");
  714. goto err_cmd_poll;
  715. }
  716. err = mthca_init_srq_table(dev);
  717. if (err) {
  718. mthca_err(dev, "Failed to initialize "
  719. "shared receive queue table, aborting.\n");
  720. goto err_cq_table_free;
  721. }
  722. err = mthca_init_qp_table(dev);
  723. if (err) {
  724. mthca_err(dev, "Failed to initialize "
  725. "queue pair table, aborting.\n");
  726. goto err_srq_table_free;
  727. }
  728. err = mthca_init_av_table(dev);
  729. if (err) {
  730. mthca_err(dev, "Failed to initialize "
  731. "address vector table, aborting.\n");
  732. goto err_qp_table_free;
  733. }
  734. err = mthca_init_mcg_table(dev);
  735. if (err) {
  736. mthca_err(dev, "Failed to initialize "
  737. "multicast group table, aborting.\n");
  738. goto err_av_table_free;
  739. }
  740. return 0;
  741. err_av_table_free:
  742. mthca_cleanup_av_table(dev);
  743. err_qp_table_free:
  744. mthca_cleanup_qp_table(dev);
  745. err_srq_table_free:
  746. mthca_cleanup_srq_table(dev);
  747. err_cq_table_free:
  748. mthca_cleanup_cq_table(dev);
  749. err_cmd_poll:
  750. mthca_cmd_use_polling(dev);
  751. err_eq_table_free:
  752. mthca_cleanup_eq_table(dev);
  753. err_pd_free:
  754. mthca_pd_free(dev, &dev->driver_pd);
  755. err_mr_table_free:
  756. mthca_cleanup_mr_table(dev);
  757. err_pd_table_free:
  758. mthca_cleanup_pd_table(dev);
  759. err_kar_unmap:
  760. iounmap(dev->kar);
  761. err_uar_free:
  762. mthca_uar_free(dev, &dev->driver_uar);
  763. err_uar_table_free:
  764. mthca_cleanup_uar_table(dev);
  765. return err;
  766. }
  767. static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
  768. {
  769. int err;
  770. /*
  771. * We can't just use pci_request_regions() because the MSI-X
  772. * table is right in the middle of the first BAR. If we did
  773. * pci_request_region and grab all of the first BAR, then
  774. * setting up MSI-X would fail, since the PCI core wants to do
  775. * request_mem_region on the MSI-X vector table.
  776. *
  777. * So just request what we need right now, and request any
  778. * other regions we need when setting up EQs.
  779. */
  780. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  781. MTHCA_HCR_SIZE, DRV_NAME))
  782. return -EBUSY;
  783. err = pci_request_region(pdev, 2, DRV_NAME);
  784. if (err)
  785. goto err_bar2_failed;
  786. if (!ddr_hidden) {
  787. err = pci_request_region(pdev, 4, DRV_NAME);
  788. if (err)
  789. goto err_bar4_failed;
  790. }
  791. return 0;
  792. err_bar4_failed:
  793. pci_release_region(pdev, 2);
  794. err_bar2_failed:
  795. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  796. MTHCA_HCR_SIZE);
  797. return err;
  798. }
  799. static void mthca_release_regions(struct pci_dev *pdev,
  800. int ddr_hidden)
  801. {
  802. if (!ddr_hidden)
  803. pci_release_region(pdev, 4);
  804. pci_release_region(pdev, 2);
  805. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  806. MTHCA_HCR_SIZE);
  807. }
  808. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  809. {
  810. struct msix_entry entries[3];
  811. int err;
  812. entries[0].entry = 0;
  813. entries[1].entry = 1;
  814. entries[2].entry = 2;
  815. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  816. if (err) {
  817. if (err > 0)
  818. mthca_info(mdev, "Only %d MSI-X vectors available, "
  819. "not using MSI-X\n", err);
  820. return err;
  821. }
  822. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  823. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  824. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  825. return 0;
  826. }
  827. /* Types of supported HCA */
  828. enum {
  829. TAVOR, /* MT23108 */
  830. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  831. ARBEL_NATIVE, /* MT25208 with extended features */
  832. SINAI /* MT25204 */
  833. };
  834. #define MTHCA_FW_VER(major, minor, subminor) \
  835. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  836. static struct {
  837. u64 latest_fw;
  838. u32 flags;
  839. } mthca_hca_table[] = {
  840. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 4, 0),
  841. .flags = 0 },
  842. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 600),
  843. .flags = MTHCA_FLAG_PCIE },
  844. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 400),
  845. .flags = MTHCA_FLAG_MEMFREE |
  846. MTHCA_FLAG_PCIE },
  847. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 1, 0),
  848. .flags = MTHCA_FLAG_MEMFREE |
  849. MTHCA_FLAG_PCIE |
  850. MTHCA_FLAG_SINAI_OPT }
  851. };
  852. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  853. {
  854. int ddr_hidden = 0;
  855. int err;
  856. struct mthca_dev *mdev;
  857. printk(KERN_INFO PFX "Initializing %s\n",
  858. pci_name(pdev));
  859. err = pci_enable_device(pdev);
  860. if (err) {
  861. dev_err(&pdev->dev, "Cannot enable PCI device, "
  862. "aborting.\n");
  863. return err;
  864. }
  865. /*
  866. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  867. * be present)
  868. */
  869. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  870. pci_resource_len(pdev, 0) != 1 << 20) {
  871. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  872. err = -ENODEV;
  873. goto err_disable_pdev;
  874. }
  875. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  876. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  877. err = -ENODEV;
  878. goto err_disable_pdev;
  879. }
  880. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  881. ddr_hidden = 1;
  882. err = mthca_request_regions(pdev, ddr_hidden);
  883. if (err) {
  884. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  885. "aborting.\n");
  886. goto err_disable_pdev;
  887. }
  888. pci_set_master(pdev);
  889. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  890. if (err) {
  891. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  892. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  893. if (err) {
  894. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  895. goto err_free_res;
  896. }
  897. }
  898. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  899. if (err) {
  900. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  901. "consistent PCI DMA mask.\n");
  902. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  903. if (err) {
  904. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  905. "aborting.\n");
  906. goto err_free_res;
  907. }
  908. }
  909. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  910. if (!mdev) {
  911. dev_err(&pdev->dev, "Device struct alloc failed, "
  912. "aborting.\n");
  913. err = -ENOMEM;
  914. goto err_free_res;
  915. }
  916. mdev->pdev = pdev;
  917. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  918. if (ddr_hidden)
  919. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  920. /*
  921. * Now reset the HCA before we touch the PCI capabilities or
  922. * attempt a firmware command, since a boot ROM may have left
  923. * the HCA in an undefined state.
  924. */
  925. err = mthca_reset(mdev);
  926. if (err) {
  927. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  928. goto err_free_dev;
  929. }
  930. if (msi_x && !mthca_enable_msi_x(mdev))
  931. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  932. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  933. !pci_enable_msi(pdev))
  934. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  935. if (mthca_cmd_init(mdev)) {
  936. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  937. goto err_free_dev;
  938. }
  939. err = mthca_tune_pci(mdev);
  940. if (err)
  941. goto err_cmd;
  942. err = mthca_init_hca(mdev);
  943. if (err)
  944. goto err_cmd;
  945. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  946. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  947. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  948. (int) (mdev->fw_ver & 0xffff),
  949. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  950. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  951. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  952. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  953. }
  954. err = mthca_setup_hca(mdev);
  955. if (err)
  956. goto err_close;
  957. err = mthca_register_device(mdev);
  958. if (err)
  959. goto err_cleanup;
  960. err = mthca_create_agents(mdev);
  961. if (err)
  962. goto err_unregister;
  963. pci_set_drvdata(pdev, mdev);
  964. mdev->hca_type = hca_type;
  965. return 0;
  966. err_unregister:
  967. mthca_unregister_device(mdev);
  968. err_cleanup:
  969. mthca_cleanup_mcg_table(mdev);
  970. mthca_cleanup_av_table(mdev);
  971. mthca_cleanup_qp_table(mdev);
  972. mthca_cleanup_srq_table(mdev);
  973. mthca_cleanup_cq_table(mdev);
  974. mthca_cmd_use_polling(mdev);
  975. mthca_cleanup_eq_table(mdev);
  976. mthca_pd_free(mdev, &mdev->driver_pd);
  977. mthca_cleanup_mr_table(mdev);
  978. mthca_cleanup_pd_table(mdev);
  979. mthca_cleanup_uar_table(mdev);
  980. err_close:
  981. mthca_close_hca(mdev);
  982. err_cmd:
  983. mthca_cmd_cleanup(mdev);
  984. err_free_dev:
  985. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  986. pci_disable_msix(pdev);
  987. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  988. pci_disable_msi(pdev);
  989. ib_dealloc_device(&mdev->ib_dev);
  990. err_free_res:
  991. mthca_release_regions(pdev, ddr_hidden);
  992. err_disable_pdev:
  993. pci_disable_device(pdev);
  994. pci_set_drvdata(pdev, NULL);
  995. return err;
  996. }
  997. static void __mthca_remove_one(struct pci_dev *pdev)
  998. {
  999. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  1000. u8 status;
  1001. int p;
  1002. if (mdev) {
  1003. mthca_free_agents(mdev);
  1004. mthca_unregister_device(mdev);
  1005. for (p = 1; p <= mdev->limits.num_ports; ++p)
  1006. mthca_CLOSE_IB(mdev, p, &status);
  1007. mthca_cleanup_mcg_table(mdev);
  1008. mthca_cleanup_av_table(mdev);
  1009. mthca_cleanup_qp_table(mdev);
  1010. mthca_cleanup_srq_table(mdev);
  1011. mthca_cleanup_cq_table(mdev);
  1012. mthca_cmd_use_polling(mdev);
  1013. mthca_cleanup_eq_table(mdev);
  1014. mthca_pd_free(mdev, &mdev->driver_pd);
  1015. mthca_cleanup_mr_table(mdev);
  1016. mthca_cleanup_pd_table(mdev);
  1017. iounmap(mdev->kar);
  1018. mthca_uar_free(mdev, &mdev->driver_uar);
  1019. mthca_cleanup_uar_table(mdev);
  1020. mthca_close_hca(mdev);
  1021. mthca_cmd_cleanup(mdev);
  1022. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1023. pci_disable_msix(pdev);
  1024. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  1025. pci_disable_msi(pdev);
  1026. ib_dealloc_device(&mdev->ib_dev);
  1027. mthca_release_regions(pdev, mdev->mthca_flags &
  1028. MTHCA_FLAG_DDR_HIDDEN);
  1029. pci_disable_device(pdev);
  1030. pci_set_drvdata(pdev, NULL);
  1031. }
  1032. }
  1033. int __mthca_restart_one(struct pci_dev *pdev)
  1034. {
  1035. struct mthca_dev *mdev;
  1036. mdev = pci_get_drvdata(pdev);
  1037. if (!mdev)
  1038. return -ENODEV;
  1039. __mthca_remove_one(pdev);
  1040. return __mthca_init_one(pdev, mdev->hca_type);
  1041. }
  1042. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1043. const struct pci_device_id *id)
  1044. {
  1045. static int mthca_version_printed = 0;
  1046. int ret;
  1047. mutex_lock(&mthca_device_mutex);
  1048. if (!mthca_version_printed) {
  1049. printk(KERN_INFO "%s", mthca_version);
  1050. ++mthca_version_printed;
  1051. }
  1052. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1053. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1054. pci_name(pdev), id->driver_data);
  1055. mutex_unlock(&mthca_device_mutex);
  1056. return -ENODEV;
  1057. }
  1058. ret = __mthca_init_one(pdev, id->driver_data);
  1059. mutex_unlock(&mthca_device_mutex);
  1060. return ret;
  1061. }
  1062. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1063. {
  1064. mutex_lock(&mthca_device_mutex);
  1065. __mthca_remove_one(pdev);
  1066. mutex_unlock(&mthca_device_mutex);
  1067. }
  1068. static struct pci_device_id mthca_pci_table[] = {
  1069. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1070. .driver_data = TAVOR },
  1071. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1072. .driver_data = TAVOR },
  1073. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1074. .driver_data = ARBEL_COMPAT },
  1075. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1076. .driver_data = ARBEL_COMPAT },
  1077. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1078. .driver_data = ARBEL_NATIVE },
  1079. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1080. .driver_data = ARBEL_NATIVE },
  1081. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1082. .driver_data = SINAI },
  1083. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1084. .driver_data = SINAI },
  1085. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1086. .driver_data = SINAI },
  1087. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1088. .driver_data = SINAI },
  1089. { 0, }
  1090. };
  1091. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1092. static struct pci_driver mthca_driver = {
  1093. .name = DRV_NAME,
  1094. .id_table = mthca_pci_table,
  1095. .probe = mthca_init_one,
  1096. .remove = __devexit_p(mthca_remove_one)
  1097. };
  1098. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1099. int pval_default)
  1100. {
  1101. /* value must be positive and power of 2 */
  1102. int old_pval = *pval;
  1103. if (old_pval <= 0)
  1104. *pval = pval_default;
  1105. else
  1106. *pval = roundup_pow_of_two(old_pval);
  1107. if (old_pval != *pval) {
  1108. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1109. old_pval, name);
  1110. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1111. }
  1112. }
  1113. #define mthca_check_profile_val(name, default) \
  1114. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1115. static void __init mthca_validate_profile(void)
  1116. {
  1117. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1118. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1119. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1120. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1121. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1122. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1123. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1124. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1125. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1126. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1127. hca_profile.fmr_reserved_mtts);
  1128. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1129. hca_profile.num_mtt);
  1130. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1131. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1132. hca_profile.fmr_reserved_mtts);
  1133. }
  1134. }
  1135. static int __init mthca_init(void)
  1136. {
  1137. int ret;
  1138. mthca_validate_profile();
  1139. ret = mthca_catas_init();
  1140. if (ret)
  1141. return ret;
  1142. ret = pci_register_driver(&mthca_driver);
  1143. if (ret < 0) {
  1144. mthca_catas_cleanup();
  1145. return ret;
  1146. }
  1147. return 0;
  1148. }
  1149. static void __exit mthca_cleanup(void)
  1150. {
  1151. pci_unregister_driver(&mthca_driver);
  1152. mthca_catas_cleanup();
  1153. }
  1154. module_init(mthca_init);
  1155. module_exit(mthca_cleanup);