registers.h 353 KB

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  1. /*
  2. * ARIZONA register definitions
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef _ARIZONA_REGISTERS_H
  13. #define _ARIZONA_REGISTERS_H
  14. /*
  15. * Register values.
  16. */
  17. #define ARIZONA_SOFTWARE_RESET 0x00
  18. #define ARIZONA_DEVICE_REVISION 0x01
  19. #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
  20. #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
  21. #define ARIZONA_CTRL_IF_STATUS_1 0x0D
  22. #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
  23. #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
  24. #define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18
  25. #define ARIZONA_WRITE_SEQUENCER_PROM 0x1A
  26. #define ARIZONA_TONE_GENERATOR_1 0x20
  27. #define ARIZONA_TONE_GENERATOR_2 0x21
  28. #define ARIZONA_TONE_GENERATOR_3 0x22
  29. #define ARIZONA_TONE_GENERATOR_4 0x23
  30. #define ARIZONA_TONE_GENERATOR_5 0x24
  31. #define ARIZONA_PWM_DRIVE_1 0x30
  32. #define ARIZONA_PWM_DRIVE_2 0x31
  33. #define ARIZONA_PWM_DRIVE_3 0x32
  34. #define ARIZONA_WAKE_CONTROL 0x40
  35. #define ARIZONA_SEQUENCE_CONTROL 0x41
  36. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61
  37. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62
  38. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63
  39. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64
  40. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68
  41. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69
  42. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A
  43. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B
  44. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C
  45. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D
  46. #define ARIZONA_COMFORT_NOISE_GENERATOR 0x70
  47. #define ARIZONA_HAPTICS_CONTROL_1 0x90
  48. #define ARIZONA_HAPTICS_CONTROL_2 0x91
  49. #define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92
  50. #define ARIZONA_HAPTICS_PHASE_1_DURATION 0x93
  51. #define ARIZONA_HAPTICS_PHASE_2_INTENSITY 0x94
  52. #define ARIZONA_HAPTICS_PHASE_2_DURATION 0x95
  53. #define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96
  54. #define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97
  55. #define ARIZONA_HAPTICS_STATUS 0x98
  56. #define ARIZONA_CLOCK_32K_1 0x100
  57. #define ARIZONA_SYSTEM_CLOCK_1 0x101
  58. #define ARIZONA_SAMPLE_RATE_1 0x102
  59. #define ARIZONA_SAMPLE_RATE_2 0x103
  60. #define ARIZONA_SAMPLE_RATE_3 0x104
  61. #define ARIZONA_SAMPLE_RATE_1_STATUS 0x10A
  62. #define ARIZONA_SAMPLE_RATE_2_STATUS 0x10B
  63. #define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C
  64. #define ARIZONA_ASYNC_CLOCK_1 0x112
  65. #define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113
  66. #define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B
  67. #define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149
  68. #define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A
  69. #define ARIZONA_RATE_ESTIMATOR_1 0x152
  70. #define ARIZONA_RATE_ESTIMATOR_2 0x153
  71. #define ARIZONA_RATE_ESTIMATOR_3 0x154
  72. #define ARIZONA_RATE_ESTIMATOR_4 0x155
  73. #define ARIZONA_RATE_ESTIMATOR_5 0x156
  74. #define ARIZONA_FLL1_CONTROL_1 0x171
  75. #define ARIZONA_FLL1_CONTROL_2 0x172
  76. #define ARIZONA_FLL1_CONTROL_3 0x173
  77. #define ARIZONA_FLL1_CONTROL_4 0x174
  78. #define ARIZONA_FLL1_CONTROL_5 0x175
  79. #define ARIZONA_FLL1_CONTROL_6 0x176
  80. #define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177
  81. #define ARIZONA_FLL1_SYNCHRONISER_1 0x181
  82. #define ARIZONA_FLL1_SYNCHRONISER_2 0x182
  83. #define ARIZONA_FLL1_SYNCHRONISER_3 0x183
  84. #define ARIZONA_FLL1_SYNCHRONISER_4 0x184
  85. #define ARIZONA_FLL1_SYNCHRONISER_5 0x185
  86. #define ARIZONA_FLL1_SYNCHRONISER_6 0x186
  87. #define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189
  88. #define ARIZONA_FLL1_GPIO_CLOCK 0x18A
  89. #define ARIZONA_FLL2_CONTROL_1 0x191
  90. #define ARIZONA_FLL2_CONTROL_2 0x192
  91. #define ARIZONA_FLL2_CONTROL_3 0x193
  92. #define ARIZONA_FLL2_CONTROL_4 0x194
  93. #define ARIZONA_FLL2_CONTROL_5 0x195
  94. #define ARIZONA_FLL2_CONTROL_6 0x196
  95. #define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197
  96. #define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1
  97. #define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2
  98. #define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3
  99. #define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4
  100. #define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5
  101. #define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6
  102. #define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9
  103. #define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
  104. #define ARIZONA_MIC_CHARGE_PUMP_1 0x200
  105. #define ARIZONA_LDO1_CONTROL_1 0x210
  106. #define ARIZONA_LDO2_CONTROL_1 0x213
  107. #define ARIZONA_MIC_BIAS_CTRL_1 0x218
  108. #define ARIZONA_MIC_BIAS_CTRL_2 0x219
  109. #define ARIZONA_MIC_BIAS_CTRL_3 0x21A
  110. #define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293
  111. #define ARIZONA_HEADPHONE_DETECT_1 0x29B
  112. #define ARIZONA_HEADPHONE_DETECT_2 0x29C
  113. #define ARIZONA_MIC_DETECT_1 0x2A3
  114. #define ARIZONA_MIC_DETECT_2 0x2A4
  115. #define ARIZONA_MIC_DETECT_3 0x2A5
  116. #define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
  117. #define ARIZONA_ISOLATION_CONTROL 0x2CB
  118. #define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
  119. #define ARIZONA_INPUT_ENABLES 0x300
  120. #define ARIZONA_INPUT_RATE 0x308
  121. #define ARIZONA_INPUT_VOLUME_RAMP 0x309
  122. #define ARIZONA_IN1L_CONTROL 0x310
  123. #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311
  124. #define ARIZONA_DMIC1L_CONTROL 0x312
  125. #define ARIZONA_IN1R_CONTROL 0x314
  126. #define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315
  127. #define ARIZONA_DMIC1R_CONTROL 0x316
  128. #define ARIZONA_IN2L_CONTROL 0x318
  129. #define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319
  130. #define ARIZONA_DMIC2L_CONTROL 0x31A
  131. #define ARIZONA_IN2R_CONTROL 0x31C
  132. #define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D
  133. #define ARIZONA_DMIC2R_CONTROL 0x31E
  134. #define ARIZONA_IN3L_CONTROL 0x320
  135. #define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321
  136. #define ARIZONA_DMIC3L_CONTROL 0x322
  137. #define ARIZONA_IN3R_CONTROL 0x324
  138. #define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325
  139. #define ARIZONA_DMIC3R_CONTROL 0x326
  140. #define ARIZONA_OUTPUT_ENABLES_1 0x400
  141. #define ARIZONA_OUTPUT_STATUS_1 0x401
  142. #define ARIZONA_OUTPUT_RATE_1 0x408
  143. #define ARIZONA_OUTPUT_VOLUME_RAMP 0x409
  144. #define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410
  145. #define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411
  146. #define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412
  147. #define ARIZONA_NOISE_GATE_SELECT_1L 0x413
  148. #define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414
  149. #define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415
  150. #define ARIZONA_DAC_VOLUME_LIMIT_1R 0x416
  151. #define ARIZONA_NOISE_GATE_SELECT_1R 0x417
  152. #define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418
  153. #define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419
  154. #define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A
  155. #define ARIZONA_NOISE_GATE_SELECT_2L 0x41B
  156. #define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C
  157. #define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D
  158. #define ARIZONA_DAC_VOLUME_LIMIT_2R 0x41E
  159. #define ARIZONA_NOISE_GATE_SELECT_2R 0x41F
  160. #define ARIZONA_OUTPUT_PATH_CONFIG_3L 0x420
  161. #define ARIZONA_DAC_DIGITAL_VOLUME_3L 0x421
  162. #define ARIZONA_DAC_VOLUME_LIMIT_3L 0x422
  163. #define ARIZONA_NOISE_GATE_SELECT_3L 0x423
  164. #define ARIZONA_OUTPUT_PATH_CONFIG_3R 0x424
  165. #define ARIZONA_DAC_DIGITAL_VOLUME_3R 0x425
  166. #define ARIZONA_DAC_VOLUME_LIMIT_3R 0x426
  167. #define ARIZONA_OUTPUT_PATH_CONFIG_4L 0x428
  168. #define ARIZONA_DAC_DIGITAL_VOLUME_4L 0x429
  169. #define ARIZONA_OUT_VOLUME_4L 0x42A
  170. #define ARIZONA_NOISE_GATE_SELECT_4L 0x42B
  171. #define ARIZONA_OUTPUT_PATH_CONFIG_4R 0x42C
  172. #define ARIZONA_DAC_DIGITAL_VOLUME_4R 0x42D
  173. #define ARIZONA_OUT_VOLUME_4R 0x42E
  174. #define ARIZONA_NOISE_GATE_SELECT_4R 0x42F
  175. #define ARIZONA_OUTPUT_PATH_CONFIG_5L 0x430
  176. #define ARIZONA_DAC_DIGITAL_VOLUME_5L 0x431
  177. #define ARIZONA_DAC_VOLUME_LIMIT_5L 0x432
  178. #define ARIZONA_NOISE_GATE_SELECT_5L 0x433
  179. #define ARIZONA_OUTPUT_PATH_CONFIG_5R 0x434
  180. #define ARIZONA_DAC_DIGITAL_VOLUME_5R 0x435
  181. #define ARIZONA_DAC_VOLUME_LIMIT_5R 0x436
  182. #define ARIZONA_NOISE_GATE_SELECT_5R 0x437
  183. #define ARIZONA_DAC_AEC_CONTROL_1 0x450
  184. #define ARIZONA_NOISE_GATE_CONTROL 0x458
  185. #define ARIZONA_PDM_SPK1_CTRL_1 0x490
  186. #define ARIZONA_PDM_SPK1_CTRL_2 0x491
  187. #define ARIZONA_DAC_COMP_1 0x4DC
  188. #define ARIZONA_DAC_COMP_2 0x4DD
  189. #define ARIZONA_DAC_COMP_3 0x4DE
  190. #define ARIZONA_DAC_COMP_4 0x4DF
  191. #define ARIZONA_AIF1_BCLK_CTRL 0x500
  192. #define ARIZONA_AIF1_TX_PIN_CTRL 0x501
  193. #define ARIZONA_AIF1_RX_PIN_CTRL 0x502
  194. #define ARIZONA_AIF1_RATE_CTRL 0x503
  195. #define ARIZONA_AIF1_FORMAT 0x504
  196. #define ARIZONA_AIF1_TX_BCLK_RATE 0x505
  197. #define ARIZONA_AIF1_RX_BCLK_RATE 0x506
  198. #define ARIZONA_AIF1_FRAME_CTRL_1 0x507
  199. #define ARIZONA_AIF1_FRAME_CTRL_2 0x508
  200. #define ARIZONA_AIF1_FRAME_CTRL_3 0x509
  201. #define ARIZONA_AIF1_FRAME_CTRL_4 0x50A
  202. #define ARIZONA_AIF1_FRAME_CTRL_5 0x50B
  203. #define ARIZONA_AIF1_FRAME_CTRL_6 0x50C
  204. #define ARIZONA_AIF1_FRAME_CTRL_7 0x50D
  205. #define ARIZONA_AIF1_FRAME_CTRL_8 0x50E
  206. #define ARIZONA_AIF1_FRAME_CTRL_9 0x50F
  207. #define ARIZONA_AIF1_FRAME_CTRL_10 0x510
  208. #define ARIZONA_AIF1_FRAME_CTRL_11 0x511
  209. #define ARIZONA_AIF1_FRAME_CTRL_12 0x512
  210. #define ARIZONA_AIF1_FRAME_CTRL_13 0x513
  211. #define ARIZONA_AIF1_FRAME_CTRL_14 0x514
  212. #define ARIZONA_AIF1_FRAME_CTRL_15 0x515
  213. #define ARIZONA_AIF1_FRAME_CTRL_16 0x516
  214. #define ARIZONA_AIF1_FRAME_CTRL_17 0x517
  215. #define ARIZONA_AIF1_FRAME_CTRL_18 0x518
  216. #define ARIZONA_AIF1_TX_ENABLES 0x519
  217. #define ARIZONA_AIF1_RX_ENABLES 0x51A
  218. #define ARIZONA_AIF1_FORCE_WRITE 0x51B
  219. #define ARIZONA_AIF2_BCLK_CTRL 0x540
  220. #define ARIZONA_AIF2_TX_PIN_CTRL 0x541
  221. #define ARIZONA_AIF2_RX_PIN_CTRL 0x542
  222. #define ARIZONA_AIF2_RATE_CTRL 0x543
  223. #define ARIZONA_AIF2_FORMAT 0x544
  224. #define ARIZONA_AIF2_TX_BCLK_RATE 0x545
  225. #define ARIZONA_AIF2_RX_BCLK_RATE 0x546
  226. #define ARIZONA_AIF2_FRAME_CTRL_1 0x547
  227. #define ARIZONA_AIF2_FRAME_CTRL_2 0x548
  228. #define ARIZONA_AIF2_FRAME_CTRL_3 0x549
  229. #define ARIZONA_AIF2_FRAME_CTRL_4 0x54A
  230. #define ARIZONA_AIF2_FRAME_CTRL_11 0x551
  231. #define ARIZONA_AIF2_FRAME_CTRL_12 0x552
  232. #define ARIZONA_AIF2_TX_ENABLES 0x559
  233. #define ARIZONA_AIF2_RX_ENABLES 0x55A
  234. #define ARIZONA_AIF2_FORCE_WRITE 0x55B
  235. #define ARIZONA_AIF3_BCLK_CTRL 0x580
  236. #define ARIZONA_AIF3_TX_PIN_CTRL 0x581
  237. #define ARIZONA_AIF3_RX_PIN_CTRL 0x582
  238. #define ARIZONA_AIF3_RATE_CTRL 0x583
  239. #define ARIZONA_AIF3_FORMAT 0x584
  240. #define ARIZONA_AIF3_TX_BCLK_RATE 0x585
  241. #define ARIZONA_AIF3_RX_BCLK_RATE 0x586
  242. #define ARIZONA_AIF3_FRAME_CTRL_1 0x587
  243. #define ARIZONA_AIF3_FRAME_CTRL_2 0x588
  244. #define ARIZONA_AIF3_FRAME_CTRL_3 0x589
  245. #define ARIZONA_AIF3_FRAME_CTRL_4 0x58A
  246. #define ARIZONA_AIF3_FRAME_CTRL_11 0x591
  247. #define ARIZONA_AIF3_FRAME_CTRL_12 0x592
  248. #define ARIZONA_AIF3_TX_ENABLES 0x599
  249. #define ARIZONA_AIF3_RX_ENABLES 0x59A
  250. #define ARIZONA_AIF3_FORCE_WRITE 0x59B
  251. #define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3
  252. #define ARIZONA_SLIMBUS_RATES_1 0x5E5
  253. #define ARIZONA_SLIMBUS_RATES_2 0x5E6
  254. #define ARIZONA_SLIMBUS_RATES_3 0x5E7
  255. #define ARIZONA_SLIMBUS_RATES_4 0x5E8
  256. #define ARIZONA_SLIMBUS_RATES_5 0x5E9
  257. #define ARIZONA_SLIMBUS_RATES_6 0x5EA
  258. #define ARIZONA_SLIMBUS_RATES_7 0x5EB
  259. #define ARIZONA_SLIMBUS_RATES_8 0x5EC
  260. #define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE 0x5F5
  261. #define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE 0x5F6
  262. #define ARIZONA_SLIMBUS_RX_PORT_STATUS 0x5F7
  263. #define ARIZONA_SLIMBUS_TX_PORT_STATUS 0x5F8
  264. #define ARIZONA_PWM1MIX_INPUT_1_SOURCE 0x640
  265. #define ARIZONA_PWM1MIX_INPUT_1_VOLUME 0x641
  266. #define ARIZONA_PWM1MIX_INPUT_2_SOURCE 0x642
  267. #define ARIZONA_PWM1MIX_INPUT_2_VOLUME 0x643
  268. #define ARIZONA_PWM1MIX_INPUT_3_SOURCE 0x644
  269. #define ARIZONA_PWM1MIX_INPUT_3_VOLUME 0x645
  270. #define ARIZONA_PWM1MIX_INPUT_4_SOURCE 0x646
  271. #define ARIZONA_PWM1MIX_INPUT_4_VOLUME 0x647
  272. #define ARIZONA_PWM2MIX_INPUT_1_SOURCE 0x648
  273. #define ARIZONA_PWM2MIX_INPUT_1_VOLUME 0x649
  274. #define ARIZONA_PWM2MIX_INPUT_2_SOURCE 0x64A
  275. #define ARIZONA_PWM2MIX_INPUT_2_VOLUME 0x64B
  276. #define ARIZONA_PWM2MIX_INPUT_3_SOURCE 0x64C
  277. #define ARIZONA_PWM2MIX_INPUT_3_VOLUME 0x64D
  278. #define ARIZONA_PWM2MIX_INPUT_4_SOURCE 0x64E
  279. #define ARIZONA_PWM2MIX_INPUT_4_VOLUME 0x64F
  280. #define ARIZONA_MICMIX_INPUT_1_SOURCE 0x660
  281. #define ARIZONA_MICMIX_INPUT_1_VOLUME 0x661
  282. #define ARIZONA_MICMIX_INPUT_2_SOURCE 0x662
  283. #define ARIZONA_MICMIX_INPUT_2_VOLUME 0x663
  284. #define ARIZONA_MICMIX_INPUT_3_SOURCE 0x664
  285. #define ARIZONA_MICMIX_INPUT_3_VOLUME 0x665
  286. #define ARIZONA_MICMIX_INPUT_4_SOURCE 0x666
  287. #define ARIZONA_MICMIX_INPUT_4_VOLUME 0x667
  288. #define ARIZONA_NOISEMIX_INPUT_1_SOURCE 0x668
  289. #define ARIZONA_NOISEMIX_INPUT_1_VOLUME 0x669
  290. #define ARIZONA_NOISEMIX_INPUT_2_SOURCE 0x66A
  291. #define ARIZONA_NOISEMIX_INPUT_2_VOLUME 0x66B
  292. #define ARIZONA_NOISEMIX_INPUT_3_SOURCE 0x66C
  293. #define ARIZONA_NOISEMIX_INPUT_3_VOLUME 0x66D
  294. #define ARIZONA_NOISEMIX_INPUT_4_SOURCE 0x66E
  295. #define ARIZONA_NOISEMIX_INPUT_4_VOLUME 0x66F
  296. #define ARIZONA_OUT1LMIX_INPUT_1_SOURCE 0x680
  297. #define ARIZONA_OUT1LMIX_INPUT_1_VOLUME 0x681
  298. #define ARIZONA_OUT1LMIX_INPUT_2_SOURCE 0x682
  299. #define ARIZONA_OUT1LMIX_INPUT_2_VOLUME 0x683
  300. #define ARIZONA_OUT1LMIX_INPUT_3_SOURCE 0x684
  301. #define ARIZONA_OUT1LMIX_INPUT_3_VOLUME 0x685
  302. #define ARIZONA_OUT1LMIX_INPUT_4_SOURCE 0x686
  303. #define ARIZONA_OUT1LMIX_INPUT_4_VOLUME 0x687
  304. #define ARIZONA_OUT1RMIX_INPUT_1_SOURCE 0x688
  305. #define ARIZONA_OUT1RMIX_INPUT_1_VOLUME 0x689
  306. #define ARIZONA_OUT1RMIX_INPUT_2_SOURCE 0x68A
  307. #define ARIZONA_OUT1RMIX_INPUT_2_VOLUME 0x68B
  308. #define ARIZONA_OUT1RMIX_INPUT_3_SOURCE 0x68C
  309. #define ARIZONA_OUT1RMIX_INPUT_3_VOLUME 0x68D
  310. #define ARIZONA_OUT1RMIX_INPUT_4_SOURCE 0x68E
  311. #define ARIZONA_OUT1RMIX_INPUT_4_VOLUME 0x68F
  312. #define ARIZONA_OUT2LMIX_INPUT_1_SOURCE 0x690
  313. #define ARIZONA_OUT2LMIX_INPUT_1_VOLUME 0x691
  314. #define ARIZONA_OUT2LMIX_INPUT_2_SOURCE 0x692
  315. #define ARIZONA_OUT2LMIX_INPUT_2_VOLUME 0x693
  316. #define ARIZONA_OUT2LMIX_INPUT_3_SOURCE 0x694
  317. #define ARIZONA_OUT2LMIX_INPUT_3_VOLUME 0x695
  318. #define ARIZONA_OUT2LMIX_INPUT_4_SOURCE 0x696
  319. #define ARIZONA_OUT2LMIX_INPUT_4_VOLUME 0x697
  320. #define ARIZONA_OUT2RMIX_INPUT_1_SOURCE 0x698
  321. #define ARIZONA_OUT2RMIX_INPUT_1_VOLUME 0x699
  322. #define ARIZONA_OUT2RMIX_INPUT_2_SOURCE 0x69A
  323. #define ARIZONA_OUT2RMIX_INPUT_2_VOLUME 0x69B
  324. #define ARIZONA_OUT2RMIX_INPUT_3_SOURCE 0x69C
  325. #define ARIZONA_OUT2RMIX_INPUT_3_VOLUME 0x69D
  326. #define ARIZONA_OUT2RMIX_INPUT_4_SOURCE 0x69E
  327. #define ARIZONA_OUT2RMIX_INPUT_4_VOLUME 0x69F
  328. #define ARIZONA_OUT3LMIX_INPUT_1_SOURCE 0x6A0
  329. #define ARIZONA_OUT3LMIX_INPUT_1_VOLUME 0x6A1
  330. #define ARIZONA_OUT3LMIX_INPUT_2_SOURCE 0x6A2
  331. #define ARIZONA_OUT3LMIX_INPUT_2_VOLUME 0x6A3
  332. #define ARIZONA_OUT3LMIX_INPUT_3_SOURCE 0x6A4
  333. #define ARIZONA_OUT3LMIX_INPUT_3_VOLUME 0x6A5
  334. #define ARIZONA_OUT3LMIX_INPUT_4_SOURCE 0x6A6
  335. #define ARIZONA_OUT3LMIX_INPUT_4_VOLUME 0x6A7
  336. #define ARIZONA_OUT4LMIX_INPUT_1_SOURCE 0x6B0
  337. #define ARIZONA_OUT4LMIX_INPUT_1_VOLUME 0x6B1
  338. #define ARIZONA_OUT4LMIX_INPUT_2_SOURCE 0x6B2
  339. #define ARIZONA_OUT4LMIX_INPUT_2_VOLUME 0x6B3
  340. #define ARIZONA_OUT4LMIX_INPUT_3_SOURCE 0x6B4
  341. #define ARIZONA_OUT4LMIX_INPUT_3_VOLUME 0x6B5
  342. #define ARIZONA_OUT4LMIX_INPUT_4_SOURCE 0x6B6
  343. #define ARIZONA_OUT4LMIX_INPUT_4_VOLUME 0x6B7
  344. #define ARIZONA_OUT4RMIX_INPUT_1_SOURCE 0x6B8
  345. #define ARIZONA_OUT4RMIX_INPUT_1_VOLUME 0x6B9
  346. #define ARIZONA_OUT4RMIX_INPUT_2_SOURCE 0x6BA
  347. #define ARIZONA_OUT4RMIX_INPUT_2_VOLUME 0x6BB
  348. #define ARIZONA_OUT4RMIX_INPUT_3_SOURCE 0x6BC
  349. #define ARIZONA_OUT4RMIX_INPUT_3_VOLUME 0x6BD
  350. #define ARIZONA_OUT4RMIX_INPUT_4_SOURCE 0x6BE
  351. #define ARIZONA_OUT4RMIX_INPUT_4_VOLUME 0x6BF
  352. #define ARIZONA_OUT5LMIX_INPUT_1_SOURCE 0x6C0
  353. #define ARIZONA_OUT5LMIX_INPUT_1_VOLUME 0x6C1
  354. #define ARIZONA_OUT5LMIX_INPUT_2_SOURCE 0x6C2
  355. #define ARIZONA_OUT5LMIX_INPUT_2_VOLUME 0x6C3
  356. #define ARIZONA_OUT5LMIX_INPUT_3_SOURCE 0x6C4
  357. #define ARIZONA_OUT5LMIX_INPUT_3_VOLUME 0x6C5
  358. #define ARIZONA_OUT5LMIX_INPUT_4_SOURCE 0x6C6
  359. #define ARIZONA_OUT5LMIX_INPUT_4_VOLUME 0x6C7
  360. #define ARIZONA_OUT5RMIX_INPUT_1_SOURCE 0x6C8
  361. #define ARIZONA_OUT5RMIX_INPUT_1_VOLUME 0x6C9
  362. #define ARIZONA_OUT5RMIX_INPUT_2_SOURCE 0x6CA
  363. #define ARIZONA_OUT5RMIX_INPUT_2_VOLUME 0x6CB
  364. #define ARIZONA_OUT5RMIX_INPUT_3_SOURCE 0x6CC
  365. #define ARIZONA_OUT5RMIX_INPUT_3_VOLUME 0x6CD
  366. #define ARIZONA_OUT5RMIX_INPUT_4_SOURCE 0x6CE
  367. #define ARIZONA_OUT5RMIX_INPUT_4_VOLUME 0x6CF
  368. #define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE 0x700
  369. #define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME 0x701
  370. #define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE 0x702
  371. #define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME 0x703
  372. #define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE 0x704
  373. #define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME 0x705
  374. #define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE 0x706
  375. #define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME 0x707
  376. #define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE 0x708
  377. #define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME 0x709
  378. #define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE 0x70A
  379. #define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME 0x70B
  380. #define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE 0x70C
  381. #define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME 0x70D
  382. #define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE 0x70E
  383. #define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME 0x70F
  384. #define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE 0x710
  385. #define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME 0x711
  386. #define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE 0x712
  387. #define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME 0x713
  388. #define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE 0x714
  389. #define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME 0x715
  390. #define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE 0x716
  391. #define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME 0x717
  392. #define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE 0x718
  393. #define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME 0x719
  394. #define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE 0x71A
  395. #define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME 0x71B
  396. #define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE 0x71C
  397. #define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME 0x71D
  398. #define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE 0x71E
  399. #define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME 0x71F
  400. #define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE 0x720
  401. #define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME 0x721
  402. #define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE 0x722
  403. #define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME 0x723
  404. #define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE 0x724
  405. #define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME 0x725
  406. #define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE 0x726
  407. #define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME 0x727
  408. #define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE 0x728
  409. #define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME 0x729
  410. #define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE 0x72A
  411. #define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME 0x72B
  412. #define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE 0x72C
  413. #define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME 0x72D
  414. #define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE 0x72E
  415. #define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME 0x72F
  416. #define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE 0x730
  417. #define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME 0x731
  418. #define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE 0x732
  419. #define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME 0x733
  420. #define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE 0x734
  421. #define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME 0x735
  422. #define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE 0x736
  423. #define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME 0x737
  424. #define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE 0x738
  425. #define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME 0x739
  426. #define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE 0x73A
  427. #define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME 0x73B
  428. #define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE 0x73C
  429. #define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME 0x73D
  430. #define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE 0x73E
  431. #define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME 0x73F
  432. #define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE 0x740
  433. #define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME 0x741
  434. #define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE 0x742
  435. #define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME 0x743
  436. #define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE 0x744
  437. #define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME 0x745
  438. #define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE 0x746
  439. #define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME 0x747
  440. #define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE 0x748
  441. #define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME 0x749
  442. #define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE 0x74A
  443. #define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME 0x74B
  444. #define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE 0x74C
  445. #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D
  446. #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E
  447. #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F
  448. #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780
  449. #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781
  450. #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782
  451. #define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME 0x783
  452. #define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE 0x784
  453. #define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME 0x785
  454. #define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE 0x786
  455. #define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME 0x787
  456. #define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE 0x788
  457. #define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME 0x789
  458. #define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE 0x78A
  459. #define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME 0x78B
  460. #define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE 0x78C
  461. #define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
  462. #define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
  463. #define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
  464. #define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0
  465. #define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1
  466. #define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2
  467. #define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME 0x7C3
  468. #define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE 0x7C4
  469. #define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME 0x7C5
  470. #define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE 0x7C6
  471. #define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME 0x7C7
  472. #define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE 0x7C8
  473. #define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME 0x7C9
  474. #define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE 0x7CA
  475. #define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME 0x7CB
  476. #define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE 0x7CC
  477. #define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME 0x7CD
  478. #define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE 0x7CE
  479. #define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME 0x7CF
  480. #define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE 0x7D0
  481. #define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME 0x7D1
  482. #define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE 0x7D2
  483. #define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME 0x7D3
  484. #define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE 0x7D4
  485. #define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME 0x7D5
  486. #define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE 0x7D6
  487. #define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME 0x7D7
  488. #define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE 0x7D8
  489. #define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME 0x7D9
  490. #define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE 0x7DA
  491. #define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME 0x7DB
  492. #define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE 0x7DC
  493. #define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME 0x7DD
  494. #define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE 0x7DE
  495. #define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME 0x7DF
  496. #define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE 0x7E0
  497. #define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME 0x7E1
  498. #define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE 0x7E2
  499. #define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME 0x7E3
  500. #define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE 0x7E4
  501. #define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME 0x7E5
  502. #define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE 0x7E6
  503. #define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME 0x7E7
  504. #define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE 0x7E8
  505. #define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME 0x7E9
  506. #define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE 0x7EA
  507. #define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME 0x7EB
  508. #define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE 0x7EC
  509. #define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME 0x7ED
  510. #define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE 0x7EE
  511. #define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME 0x7EF
  512. #define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE 0x7F0
  513. #define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME 0x7F1
  514. #define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE 0x7F2
  515. #define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME 0x7F3
  516. #define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE 0x7F4
  517. #define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME 0x7F5
  518. #define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE 0x7F6
  519. #define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME 0x7F7
  520. #define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE 0x7F8
  521. #define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME 0x7F9
  522. #define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE 0x7FA
  523. #define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME 0x7FB
  524. #define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE 0x7FC
  525. #define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD
  526. #define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE
  527. #define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF
  528. #define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880
  529. #define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881
  530. #define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882
  531. #define ARIZONA_EQ1MIX_INPUT_2_VOLUME 0x883
  532. #define ARIZONA_EQ1MIX_INPUT_3_SOURCE 0x884
  533. #define ARIZONA_EQ1MIX_INPUT_3_VOLUME 0x885
  534. #define ARIZONA_EQ1MIX_INPUT_4_SOURCE 0x886
  535. #define ARIZONA_EQ1MIX_INPUT_4_VOLUME 0x887
  536. #define ARIZONA_EQ2MIX_INPUT_1_SOURCE 0x888
  537. #define ARIZONA_EQ2MIX_INPUT_1_VOLUME 0x889
  538. #define ARIZONA_EQ2MIX_INPUT_2_SOURCE 0x88A
  539. #define ARIZONA_EQ2MIX_INPUT_2_VOLUME 0x88B
  540. #define ARIZONA_EQ2MIX_INPUT_3_SOURCE 0x88C
  541. #define ARIZONA_EQ2MIX_INPUT_3_VOLUME 0x88D
  542. #define ARIZONA_EQ2MIX_INPUT_4_SOURCE 0x88E
  543. #define ARIZONA_EQ2MIX_INPUT_4_VOLUME 0x88F
  544. #define ARIZONA_EQ3MIX_INPUT_1_SOURCE 0x890
  545. #define ARIZONA_EQ3MIX_INPUT_1_VOLUME 0x891
  546. #define ARIZONA_EQ3MIX_INPUT_2_SOURCE 0x892
  547. #define ARIZONA_EQ3MIX_INPUT_2_VOLUME 0x893
  548. #define ARIZONA_EQ3MIX_INPUT_3_SOURCE 0x894
  549. #define ARIZONA_EQ3MIX_INPUT_3_VOLUME 0x895
  550. #define ARIZONA_EQ3MIX_INPUT_4_SOURCE 0x896
  551. #define ARIZONA_EQ3MIX_INPUT_4_VOLUME 0x897
  552. #define ARIZONA_EQ4MIX_INPUT_1_SOURCE 0x898
  553. #define ARIZONA_EQ4MIX_INPUT_1_VOLUME 0x899
  554. #define ARIZONA_EQ4MIX_INPUT_2_SOURCE 0x89A
  555. #define ARIZONA_EQ4MIX_INPUT_2_VOLUME 0x89B
  556. #define ARIZONA_EQ4MIX_INPUT_3_SOURCE 0x89C
  557. #define ARIZONA_EQ4MIX_INPUT_3_VOLUME 0x89D
  558. #define ARIZONA_EQ4MIX_INPUT_4_SOURCE 0x89E
  559. #define ARIZONA_EQ4MIX_INPUT_4_VOLUME 0x89F
  560. #define ARIZONA_DRC1LMIX_INPUT_1_SOURCE 0x8C0
  561. #define ARIZONA_DRC1LMIX_INPUT_1_VOLUME 0x8C1
  562. #define ARIZONA_DRC1LMIX_INPUT_2_SOURCE 0x8C2
  563. #define ARIZONA_DRC1LMIX_INPUT_2_VOLUME 0x8C3
  564. #define ARIZONA_DRC1LMIX_INPUT_3_SOURCE 0x8C4
  565. #define ARIZONA_DRC1LMIX_INPUT_3_VOLUME 0x8C5
  566. #define ARIZONA_DRC1LMIX_INPUT_4_SOURCE 0x8C6
  567. #define ARIZONA_DRC1LMIX_INPUT_4_VOLUME 0x8C7
  568. #define ARIZONA_DRC1RMIX_INPUT_1_SOURCE 0x8C8
  569. #define ARIZONA_DRC1RMIX_INPUT_1_VOLUME 0x8C9
  570. #define ARIZONA_DRC1RMIX_INPUT_2_SOURCE 0x8CA
  571. #define ARIZONA_DRC1RMIX_INPUT_2_VOLUME 0x8CB
  572. #define ARIZONA_DRC1RMIX_INPUT_3_SOURCE 0x8CC
  573. #define ARIZONA_DRC1RMIX_INPUT_3_VOLUME 0x8CD
  574. #define ARIZONA_DRC1RMIX_INPUT_4_SOURCE 0x8CE
  575. #define ARIZONA_DRC1RMIX_INPUT_4_VOLUME 0x8CF
  576. #define ARIZONA_DRC2LMIX_INPUT_1_SOURCE 0x8D0
  577. #define ARIZONA_DRC2LMIX_INPUT_1_VOLUME 0x8D1
  578. #define ARIZONA_DRC2LMIX_INPUT_2_SOURCE 0x8D2
  579. #define ARIZONA_DRC2LMIX_INPUT_2_VOLUME 0x8D3
  580. #define ARIZONA_DRC2LMIX_INPUT_3_SOURCE 0x8D4
  581. #define ARIZONA_DRC2LMIX_INPUT_3_VOLUME 0x8D5
  582. #define ARIZONA_DRC2LMIX_INPUT_4_SOURCE 0x8D6
  583. #define ARIZONA_DRC2LMIX_INPUT_4_VOLUME 0x8D7
  584. #define ARIZONA_DRC2RMIX_INPUT_1_SOURCE 0x8D8
  585. #define ARIZONA_DRC2RMIX_INPUT_1_VOLUME 0x8D9
  586. #define ARIZONA_DRC2RMIX_INPUT_2_SOURCE 0x8DA
  587. #define ARIZONA_DRC2RMIX_INPUT_2_VOLUME 0x8DB
  588. #define ARIZONA_DRC2RMIX_INPUT_3_SOURCE 0x8DC
  589. #define ARIZONA_DRC2RMIX_INPUT_3_VOLUME 0x8DD
  590. #define ARIZONA_DRC2RMIX_INPUT_4_SOURCE 0x8DE
  591. #define ARIZONA_DRC2RMIX_INPUT_4_VOLUME 0x8DF
  592. #define ARIZONA_HPLP1MIX_INPUT_1_SOURCE 0x900
  593. #define ARIZONA_HPLP1MIX_INPUT_1_VOLUME 0x901
  594. #define ARIZONA_HPLP1MIX_INPUT_2_SOURCE 0x902
  595. #define ARIZONA_HPLP1MIX_INPUT_2_VOLUME 0x903
  596. #define ARIZONA_HPLP1MIX_INPUT_3_SOURCE 0x904
  597. #define ARIZONA_HPLP1MIX_INPUT_3_VOLUME 0x905
  598. #define ARIZONA_HPLP1MIX_INPUT_4_SOURCE 0x906
  599. #define ARIZONA_HPLP1MIX_INPUT_4_VOLUME 0x907
  600. #define ARIZONA_HPLP2MIX_INPUT_1_SOURCE 0x908
  601. #define ARIZONA_HPLP2MIX_INPUT_1_VOLUME 0x909
  602. #define ARIZONA_HPLP2MIX_INPUT_2_SOURCE 0x90A
  603. #define ARIZONA_HPLP2MIX_INPUT_2_VOLUME 0x90B
  604. #define ARIZONA_HPLP2MIX_INPUT_3_SOURCE 0x90C
  605. #define ARIZONA_HPLP2MIX_INPUT_3_VOLUME 0x90D
  606. #define ARIZONA_HPLP2MIX_INPUT_4_SOURCE 0x90E
  607. #define ARIZONA_HPLP2MIX_INPUT_4_VOLUME 0x90F
  608. #define ARIZONA_HPLP3MIX_INPUT_1_SOURCE 0x910
  609. #define ARIZONA_HPLP3MIX_INPUT_1_VOLUME 0x911
  610. #define ARIZONA_HPLP3MIX_INPUT_2_SOURCE 0x912
  611. #define ARIZONA_HPLP3MIX_INPUT_2_VOLUME 0x913
  612. #define ARIZONA_HPLP3MIX_INPUT_3_SOURCE 0x914
  613. #define ARIZONA_HPLP3MIX_INPUT_3_VOLUME 0x915
  614. #define ARIZONA_HPLP3MIX_INPUT_4_SOURCE 0x916
  615. #define ARIZONA_HPLP3MIX_INPUT_4_VOLUME 0x917
  616. #define ARIZONA_HPLP4MIX_INPUT_1_SOURCE 0x918
  617. #define ARIZONA_HPLP4MIX_INPUT_1_VOLUME 0x919
  618. #define ARIZONA_HPLP4MIX_INPUT_2_SOURCE 0x91A
  619. #define ARIZONA_HPLP4MIX_INPUT_2_VOLUME 0x91B
  620. #define ARIZONA_HPLP4MIX_INPUT_3_SOURCE 0x91C
  621. #define ARIZONA_HPLP4MIX_INPUT_3_VOLUME 0x91D
  622. #define ARIZONA_HPLP4MIX_INPUT_4_SOURCE 0x91E
  623. #define ARIZONA_HPLP4MIX_INPUT_4_VOLUME 0x91F
  624. #define ARIZONA_DSP1LMIX_INPUT_1_SOURCE 0x940
  625. #define ARIZONA_DSP1LMIX_INPUT_1_VOLUME 0x941
  626. #define ARIZONA_DSP1LMIX_INPUT_2_SOURCE 0x942
  627. #define ARIZONA_DSP1LMIX_INPUT_2_VOLUME 0x943
  628. #define ARIZONA_DSP1LMIX_INPUT_3_SOURCE 0x944
  629. #define ARIZONA_DSP1LMIX_INPUT_3_VOLUME 0x945
  630. #define ARIZONA_DSP1LMIX_INPUT_4_SOURCE 0x946
  631. #define ARIZONA_DSP1LMIX_INPUT_4_VOLUME 0x947
  632. #define ARIZONA_DSP1RMIX_INPUT_1_SOURCE 0x948
  633. #define ARIZONA_DSP1RMIX_INPUT_1_VOLUME 0x949
  634. #define ARIZONA_DSP1RMIX_INPUT_2_SOURCE 0x94A
  635. #define ARIZONA_DSP1RMIX_INPUT_2_VOLUME 0x94B
  636. #define ARIZONA_DSP1RMIX_INPUT_3_SOURCE 0x94C
  637. #define ARIZONA_DSP1RMIX_INPUT_3_VOLUME 0x94D
  638. #define ARIZONA_DSP1RMIX_INPUT_4_SOURCE 0x94E
  639. #define ARIZONA_DSP1RMIX_INPUT_4_VOLUME 0x94F
  640. #define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE 0x950
  641. #define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE 0x958
  642. #define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE 0x960
  643. #define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE 0x968
  644. #define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE 0x970
  645. #define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE 0x978
  646. #define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80
  647. #define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88
  648. #define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90
  649. #define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98
  650. #define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00
  651. #define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08
  652. #define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20
  653. #define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28
  654. #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
  655. #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
  656. #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
  657. #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
  658. #define ARIZONA_GPIO1_CTRL 0xC00
  659. #define ARIZONA_GPIO2_CTRL 0xC01
  660. #define ARIZONA_GPIO3_CTRL 0xC02
  661. #define ARIZONA_GPIO4_CTRL 0xC03
  662. #define ARIZONA_GPIO5_CTRL 0xC04
  663. #define ARIZONA_IRQ_CTRL_1 0xC0F
  664. #define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10
  665. #define ARIZONA_MISC_PAD_CTRL_1 0xC20
  666. #define ARIZONA_MISC_PAD_CTRL_2 0xC21
  667. #define ARIZONA_MISC_PAD_CTRL_3 0xC22
  668. #define ARIZONA_MISC_PAD_CTRL_4 0xC23
  669. #define ARIZONA_MISC_PAD_CTRL_5 0xC24
  670. #define ARIZONA_MISC_PAD_CTRL_6 0xC25
  671. #define ARIZONA_INTERRUPT_STATUS_1 0xD00
  672. #define ARIZONA_INTERRUPT_STATUS_2 0xD01
  673. #define ARIZONA_INTERRUPT_STATUS_3 0xD02
  674. #define ARIZONA_INTERRUPT_STATUS_4 0xD03
  675. #define ARIZONA_INTERRUPT_STATUS_5 0xD04
  676. #define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08
  677. #define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09
  678. #define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A
  679. #define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B
  680. #define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C
  681. #define ARIZONA_INTERRUPT_CONTROL 0xD0F
  682. #define ARIZONA_IRQ2_STATUS_1 0xD10
  683. #define ARIZONA_IRQ2_STATUS_2 0xD11
  684. #define ARIZONA_IRQ2_STATUS_3 0xD12
  685. #define ARIZONA_IRQ2_STATUS_4 0xD13
  686. #define ARIZONA_IRQ2_STATUS_5 0xD14
  687. #define ARIZONA_IRQ2_STATUS_1_MASK 0xD18
  688. #define ARIZONA_IRQ2_STATUS_2_MASK 0xD19
  689. #define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A
  690. #define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B
  691. #define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C
  692. #define ARIZONA_IRQ2_CONTROL 0xD1F
  693. #define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20
  694. #define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21
  695. #define ARIZONA_INTERRUPT_RAW_STATUS_4 0xD22
  696. #define ARIZONA_INTERRUPT_RAW_STATUS_5 0xD23
  697. #define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24
  698. #define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25
  699. #define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26
  700. #define ARIZONA_IRQ_PIN_STATUS 0xD40
  701. #define ARIZONA_ADSP2_IRQ0 0xD41
  702. #define ARIZONA_AOD_WKUP_AND_TRIG 0xD50
  703. #define ARIZONA_AOD_IRQ1 0xD51
  704. #define ARIZONA_AOD_IRQ2 0xD52
  705. #define ARIZONA_AOD_IRQ_MASK_IRQ1 0xD53
  706. #define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54
  707. #define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55
  708. #define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56
  709. #define ARIZONA_FX_CTRL1 0xE00
  710. #define ARIZONA_FX_CTRL2 0xE01
  711. #define ARIZONA_EQ1_1 0xE10
  712. #define ARIZONA_EQ1_2 0xE11
  713. #define ARIZONA_EQ1_3 0xE12
  714. #define ARIZONA_EQ1_4 0xE13
  715. #define ARIZONA_EQ1_5 0xE14
  716. #define ARIZONA_EQ1_6 0xE15
  717. #define ARIZONA_EQ1_7 0xE16
  718. #define ARIZONA_EQ1_8 0xE17
  719. #define ARIZONA_EQ1_9 0xE18
  720. #define ARIZONA_EQ1_10 0xE19
  721. #define ARIZONA_EQ1_11 0xE1A
  722. #define ARIZONA_EQ1_12 0xE1B
  723. #define ARIZONA_EQ1_13 0xE1C
  724. #define ARIZONA_EQ1_14 0xE1D
  725. #define ARIZONA_EQ1_15 0xE1E
  726. #define ARIZONA_EQ1_16 0xE1F
  727. #define ARIZONA_EQ1_17 0xE20
  728. #define ARIZONA_EQ1_18 0xE21
  729. #define ARIZONA_EQ1_19 0xE22
  730. #define ARIZONA_EQ1_20 0xE23
  731. #define ARIZONA_EQ1_21 0xE24
  732. #define ARIZONA_EQ2_1 0xE26
  733. #define ARIZONA_EQ2_2 0xE27
  734. #define ARIZONA_EQ2_3 0xE28
  735. #define ARIZONA_EQ2_4 0xE29
  736. #define ARIZONA_EQ2_5 0xE2A
  737. #define ARIZONA_EQ2_6 0xE2B
  738. #define ARIZONA_EQ2_7 0xE2C
  739. #define ARIZONA_EQ2_8 0xE2D
  740. #define ARIZONA_EQ2_9 0xE2E
  741. #define ARIZONA_EQ2_10 0xE2F
  742. #define ARIZONA_EQ2_11 0xE30
  743. #define ARIZONA_EQ2_12 0xE31
  744. #define ARIZONA_EQ2_13 0xE32
  745. #define ARIZONA_EQ2_14 0xE33
  746. #define ARIZONA_EQ2_15 0xE34
  747. #define ARIZONA_EQ2_16 0xE35
  748. #define ARIZONA_EQ2_17 0xE36
  749. #define ARIZONA_EQ2_18 0xE37
  750. #define ARIZONA_EQ2_19 0xE38
  751. #define ARIZONA_EQ2_20 0xE39
  752. #define ARIZONA_EQ2_21 0xE3A
  753. #define ARIZONA_EQ3_1 0xE3C
  754. #define ARIZONA_EQ3_2 0xE3D
  755. #define ARIZONA_EQ3_3 0xE3E
  756. #define ARIZONA_EQ3_4 0xE3F
  757. #define ARIZONA_EQ3_5 0xE40
  758. #define ARIZONA_EQ3_6 0xE41
  759. #define ARIZONA_EQ3_7 0xE42
  760. #define ARIZONA_EQ3_8 0xE43
  761. #define ARIZONA_EQ3_9 0xE44
  762. #define ARIZONA_EQ3_10 0xE45
  763. #define ARIZONA_EQ3_11 0xE46
  764. #define ARIZONA_EQ3_12 0xE47
  765. #define ARIZONA_EQ3_13 0xE48
  766. #define ARIZONA_EQ3_14 0xE49
  767. #define ARIZONA_EQ3_15 0xE4A
  768. #define ARIZONA_EQ3_16 0xE4B
  769. #define ARIZONA_EQ3_17 0xE4C
  770. #define ARIZONA_EQ3_18 0xE4D
  771. #define ARIZONA_EQ3_19 0xE4E
  772. #define ARIZONA_EQ3_20 0xE4F
  773. #define ARIZONA_EQ3_21 0xE50
  774. #define ARIZONA_EQ4_1 0xE52
  775. #define ARIZONA_EQ4_2 0xE53
  776. #define ARIZONA_EQ4_3 0xE54
  777. #define ARIZONA_EQ4_4 0xE55
  778. #define ARIZONA_EQ4_5 0xE56
  779. #define ARIZONA_EQ4_6 0xE57
  780. #define ARIZONA_EQ4_7 0xE58
  781. #define ARIZONA_EQ4_8 0xE59
  782. #define ARIZONA_EQ4_9 0xE5A
  783. #define ARIZONA_EQ4_10 0xE5B
  784. #define ARIZONA_EQ4_11 0xE5C
  785. #define ARIZONA_EQ4_12 0xE5D
  786. #define ARIZONA_EQ4_13 0xE5E
  787. #define ARIZONA_EQ4_14 0xE5F
  788. #define ARIZONA_EQ4_15 0xE60
  789. #define ARIZONA_EQ4_16 0xE61
  790. #define ARIZONA_EQ4_17 0xE62
  791. #define ARIZONA_EQ4_18 0xE63
  792. #define ARIZONA_EQ4_19 0xE64
  793. #define ARIZONA_EQ4_20 0xE65
  794. #define ARIZONA_EQ4_21 0xE66
  795. #define ARIZONA_DRC1_CTRL1 0xE80
  796. #define ARIZONA_DRC1_CTRL2 0xE81
  797. #define ARIZONA_DRC1_CTRL3 0xE82
  798. #define ARIZONA_DRC1_CTRL4 0xE83
  799. #define ARIZONA_DRC1_CTRL5 0xE84
  800. #define ARIZONA_DRC2_CTRL1 0xE89
  801. #define ARIZONA_DRC2_CTRL2 0xE8A
  802. #define ARIZONA_DRC2_CTRL3 0xE8B
  803. #define ARIZONA_DRC2_CTRL4 0xE8C
  804. #define ARIZONA_DRC2_CTRL5 0xE8D
  805. #define ARIZONA_HPLPF1_1 0xEC0
  806. #define ARIZONA_HPLPF1_2 0xEC1
  807. #define ARIZONA_HPLPF2_1 0xEC4
  808. #define ARIZONA_HPLPF2_2 0xEC5
  809. #define ARIZONA_HPLPF3_1 0xEC8
  810. #define ARIZONA_HPLPF3_2 0xEC9
  811. #define ARIZONA_HPLPF4_1 0xECC
  812. #define ARIZONA_HPLPF4_2 0xECD
  813. #define ARIZONA_ASRC_ENABLE 0xEE0
  814. #define ARIZONA_ASRC_RATE1 0xEE2
  815. #define ARIZONA_ASRC_RATE2 0xEE3
  816. #define ARIZONA_ISRC_1_CTRL_1 0xEF0
  817. #define ARIZONA_ISRC_1_CTRL_2 0xEF1
  818. #define ARIZONA_ISRC_1_CTRL_3 0xEF2
  819. #define ARIZONA_ISRC_2_CTRL_1 0xEF3
  820. #define ARIZONA_ISRC_2_CTRL_2 0xEF4
  821. #define ARIZONA_ISRC_2_CTRL_3 0xEF5
  822. #define ARIZONA_ISRC_3_CTRL_1 0xEF6
  823. #define ARIZONA_ISRC_3_CTRL_2 0xEF7
  824. #define ARIZONA_ISRC_3_CTRL_3 0xEF8
  825. #define ARIZONA_DSP1_CONTROL_1 0x1100
  826. #define ARIZONA_DSP1_CLOCKING_1 0x1101
  827. #define ARIZONA_DSP1_STATUS_1 0x1104
  828. #define ARIZONA_DSP1_STATUS_2 0x1105
  829. /*
  830. * Field Definitions.
  831. */
  832. /*
  833. * R0 (0x00) - software reset
  834. */
  835. #define ARIZONA_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
  836. #define ARIZONA_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
  837. #define ARIZONA_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
  838. /*
  839. * R1 (0x01) - Device Revision
  840. */
  841. #define ARIZONA_DEVICE_REVISION_MASK 0x00FF /* DEVICE_REVISION - [7:0] */
  842. #define ARIZONA_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [7:0] */
  843. #define ARIZONA_DEVICE_REVISION_WIDTH 8 /* DEVICE_REVISION - [7:0] */
  844. /*
  845. * R8 (0x08) - Ctrl IF SPI CFG 1
  846. */
  847. #define ARIZONA_SPI_CFG 0x0010 /* SPI_CFG */
  848. #define ARIZONA_SPI_CFG_MASK 0x0010 /* SPI_CFG */
  849. #define ARIZONA_SPI_CFG_SHIFT 4 /* SPI_CFG */
  850. #define ARIZONA_SPI_CFG_WIDTH 1 /* SPI_CFG */
  851. #define ARIZONA_SPI_4WIRE 0x0008 /* SPI_4WIRE */
  852. #define ARIZONA_SPI_4WIRE_MASK 0x0008 /* SPI_4WIRE */
  853. #define ARIZONA_SPI_4WIRE_SHIFT 3 /* SPI_4WIRE */
  854. #define ARIZONA_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
  855. #define ARIZONA_SPI_AUTO_INC_MASK 0x0003 /* SPI_AUTO_INC - [1:0] */
  856. #define ARIZONA_SPI_AUTO_INC_SHIFT 0 /* SPI_AUTO_INC - [1:0] */
  857. #define ARIZONA_SPI_AUTO_INC_WIDTH 2 /* SPI_AUTO_INC - [1:0] */
  858. /*
  859. * R9 (0x09) - Ctrl IF I2C1 CFG 1
  860. */
  861. #define ARIZONA_I2C1_AUTO_INC_MASK 0x0003 /* I2C1_AUTO_INC - [1:0] */
  862. #define ARIZONA_I2C1_AUTO_INC_SHIFT 0 /* I2C1_AUTO_INC - [1:0] */
  863. #define ARIZONA_I2C1_AUTO_INC_WIDTH 2 /* I2C1_AUTO_INC - [1:0] */
  864. /*
  865. * R13 (0x0D) - Ctrl IF Status 1
  866. */
  867. #define ARIZONA_I2C1_BUSY 0x0020 /* I2C1_BUSY */
  868. #define ARIZONA_I2C1_BUSY_MASK 0x0020 /* I2C1_BUSY */
  869. #define ARIZONA_I2C1_BUSY_SHIFT 5 /* I2C1_BUSY */
  870. #define ARIZONA_I2C1_BUSY_WIDTH 1 /* I2C1_BUSY */
  871. #define ARIZONA_SPI_BUSY 0x0010 /* SPI_BUSY */
  872. #define ARIZONA_SPI_BUSY_MASK 0x0010 /* SPI_BUSY */
  873. #define ARIZONA_SPI_BUSY_SHIFT 4 /* SPI_BUSY */
  874. #define ARIZONA_SPI_BUSY_WIDTH 1 /* SPI_BUSY */
  875. /*
  876. * R22 (0x16) - Write Sequencer Ctrl 0
  877. */
  878. #define ARIZONA_WSEQ_ABORT 0x0800 /* WSEQ_ABORT */
  879. #define ARIZONA_WSEQ_ABORT_MASK 0x0800 /* WSEQ_ABORT */
  880. #define ARIZONA_WSEQ_ABORT_SHIFT 11 /* WSEQ_ABORT */
  881. #define ARIZONA_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  882. #define ARIZONA_WSEQ_START 0x0400 /* WSEQ_START */
  883. #define ARIZONA_WSEQ_START_MASK 0x0400 /* WSEQ_START */
  884. #define ARIZONA_WSEQ_START_SHIFT 10 /* WSEQ_START */
  885. #define ARIZONA_WSEQ_START_WIDTH 1 /* WSEQ_START */
  886. #define ARIZONA_WSEQ_ENA 0x0200 /* WSEQ_ENA */
  887. #define ARIZONA_WSEQ_ENA_MASK 0x0200 /* WSEQ_ENA */
  888. #define ARIZONA_WSEQ_ENA_SHIFT 9 /* WSEQ_ENA */
  889. #define ARIZONA_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  890. #define ARIZONA_WSEQ_START_INDEX_MASK 0x01FF /* WSEQ_START_INDEX - [8:0] */
  891. #define ARIZONA_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [8:0] */
  892. #define ARIZONA_WSEQ_START_INDEX_WIDTH 9 /* WSEQ_START_INDEX - [8:0] */
  893. /*
  894. * R23 (0x17) - Write Sequencer Ctrl 1
  895. */
  896. #define ARIZONA_WSEQ_BUSY 0x0200 /* WSEQ_BUSY */
  897. #define ARIZONA_WSEQ_BUSY_MASK 0x0200 /* WSEQ_BUSY */
  898. #define ARIZONA_WSEQ_BUSY_SHIFT 9 /* WSEQ_BUSY */
  899. #define ARIZONA_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  900. #define ARIZONA_WSEQ_CURRENT_INDEX_MASK 0x01FF /* WSEQ_CURRENT_INDEX - [8:0] */
  901. #define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [8:0] */
  902. #define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH 9 /* WSEQ_CURRENT_INDEX - [8:0] */
  903. /*
  904. * R24 (0x18) - Write Sequencer Ctrl 2
  905. */
  906. #define ARIZONA_LOAD_DEFAULTS 0x0002 /* LOAD_DEFAULTS */
  907. #define ARIZONA_LOAD_DEFAULTS_MASK 0x0002 /* LOAD_DEFAULTS */
  908. #define ARIZONA_LOAD_DEFAULTS_SHIFT 1 /* LOAD_DEFAULTS */
  909. #define ARIZONA_LOAD_DEFAULTS_WIDTH 1 /* LOAD_DEFAULTS */
  910. #define ARIZONA_WSEQ_LOAD_MEM 0x0001 /* WSEQ_LOAD_MEM */
  911. #define ARIZONA_WSEQ_LOAD_MEM_MASK 0x0001 /* WSEQ_LOAD_MEM */
  912. #define ARIZONA_WSEQ_LOAD_MEM_SHIFT 0 /* WSEQ_LOAD_MEM */
  913. #define ARIZONA_WSEQ_LOAD_MEM_WIDTH 1 /* WSEQ_LOAD_MEM */
  914. /*
  915. * R26 (0x1A) - Write Sequencer PROM
  916. */
  917. #define ARIZONA_WSEQ_OTP_WRITE 0x0001 /* WSEQ_OTP_WRITE */
  918. #define ARIZONA_WSEQ_OTP_WRITE_MASK 0x0001 /* WSEQ_OTP_WRITE */
  919. #define ARIZONA_WSEQ_OTP_WRITE_SHIFT 0 /* WSEQ_OTP_WRITE */
  920. #define ARIZONA_WSEQ_OTP_WRITE_WIDTH 1 /* WSEQ_OTP_WRITE */
  921. /*
  922. * R32 (0x20) - Tone Generator 1
  923. */
  924. #define ARIZONA_TONE_RATE_MASK 0x7800 /* TONE_RATE - [14:11] */
  925. #define ARIZONA_TONE_RATE_SHIFT 11 /* TONE_RATE - [14:11] */
  926. #define ARIZONA_TONE_RATE_WIDTH 4 /* TONE_RATE - [14:11] */
  927. #define ARIZONA_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */
  928. #define ARIZONA_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */
  929. #define ARIZONA_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */
  930. #define ARIZONA_TONE2_OVD 0x0020 /* TONE2_OVD */
  931. #define ARIZONA_TONE2_OVD_MASK 0x0020 /* TONE2_OVD */
  932. #define ARIZONA_TONE2_OVD_SHIFT 5 /* TONE2_OVD */
  933. #define ARIZONA_TONE2_OVD_WIDTH 1 /* TONE2_OVD */
  934. #define ARIZONA_TONE1_OVD 0x0010 /* TONE1_OVD */
  935. #define ARIZONA_TONE1_OVD_MASK 0x0010 /* TONE1_OVD */
  936. #define ARIZONA_TONE1_OVD_SHIFT 4 /* TONE1_OVD */
  937. #define ARIZONA_TONE1_OVD_WIDTH 1 /* TONE1_OVD */
  938. #define ARIZONA_TONE2_ENA 0x0002 /* TONE2_ENA */
  939. #define ARIZONA_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */
  940. #define ARIZONA_TONE2_ENA_SHIFT 1 /* TONE2_ENA */
  941. #define ARIZONA_TONE2_ENA_WIDTH 1 /* TONE2_ENA */
  942. #define ARIZONA_TONE1_ENA 0x0001 /* TONE1_ENA */
  943. #define ARIZONA_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */
  944. #define ARIZONA_TONE1_ENA_SHIFT 0 /* TONE1_ENA */
  945. #define ARIZONA_TONE1_ENA_WIDTH 1 /* TONE1_ENA */
  946. /*
  947. * R33 (0x21) - Tone Generator 2
  948. */
  949. #define ARIZONA_TONE1_LVL_0_MASK 0xFFFF /* TONE1_LVL - [15:0] */
  950. #define ARIZONA_TONE1_LVL_0_SHIFT 0 /* TONE1_LVL - [15:0] */
  951. #define ARIZONA_TONE1_LVL_0_WIDTH 16 /* TONE1_LVL - [15:0] */
  952. /*
  953. * R34 (0x22) - Tone Generator 3
  954. */
  955. #define ARIZONA_TONE1_LVL_MASK 0x00FF /* TONE1_LVL - [7:0] */
  956. #define ARIZONA_TONE1_LVL_SHIFT 0 /* TONE1_LVL - [7:0] */
  957. #define ARIZONA_TONE1_LVL_WIDTH 8 /* TONE1_LVL - [7:0] */
  958. /*
  959. * R35 (0x23) - Tone Generator 4
  960. */
  961. #define ARIZONA_TONE2_LVL_0_MASK 0xFFFF /* TONE2_LVL - [15:0] */
  962. #define ARIZONA_TONE2_LVL_0_SHIFT 0 /* TONE2_LVL - [15:0] */
  963. #define ARIZONA_TONE2_LVL_0_WIDTH 16 /* TONE2_LVL - [15:0] */
  964. /*
  965. * R36 (0x24) - Tone Generator 5
  966. */
  967. #define ARIZONA_TONE2_LVL_MASK 0x00FF /* TONE2_LVL - [7:0] */
  968. #define ARIZONA_TONE2_LVL_SHIFT 0 /* TONE2_LVL - [7:0] */
  969. #define ARIZONA_TONE2_LVL_WIDTH 8 /* TONE2_LVL - [7:0] */
  970. /*
  971. * R48 (0x30) - PWM Drive 1
  972. */
  973. #define ARIZONA_PWM_RATE_MASK 0x7800 /* PWM_RATE - [14:11] */
  974. #define ARIZONA_PWM_RATE_SHIFT 11 /* PWM_RATE - [14:11] */
  975. #define ARIZONA_PWM_RATE_WIDTH 4 /* PWM_RATE - [14:11] */
  976. #define ARIZONA_PWM_CLK_SEL_MASK 0x0700 /* PWM_CLK_SEL - [10:8] */
  977. #define ARIZONA_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [10:8] */
  978. #define ARIZONA_PWM_CLK_SEL_WIDTH 3 /* PWM_CLK_SEL - [10:8] */
  979. #define ARIZONA_PWM2_OVD 0x0020 /* PWM2_OVD */
  980. #define ARIZONA_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */
  981. #define ARIZONA_PWM2_OVD_SHIFT 5 /* PWM2_OVD */
  982. #define ARIZONA_PWM2_OVD_WIDTH 1 /* PWM2_OVD */
  983. #define ARIZONA_PWM1_OVD 0x0010 /* PWM1_OVD */
  984. #define ARIZONA_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */
  985. #define ARIZONA_PWM1_OVD_SHIFT 4 /* PWM1_OVD */
  986. #define ARIZONA_PWM1_OVD_WIDTH 1 /* PWM1_OVD */
  987. #define ARIZONA_PWM2_ENA 0x0002 /* PWM2_ENA */
  988. #define ARIZONA_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */
  989. #define ARIZONA_PWM2_ENA_SHIFT 1 /* PWM2_ENA */
  990. #define ARIZONA_PWM2_ENA_WIDTH 1 /* PWM2_ENA */
  991. #define ARIZONA_PWM1_ENA 0x0001 /* PWM1_ENA */
  992. #define ARIZONA_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */
  993. #define ARIZONA_PWM1_ENA_SHIFT 0 /* PWM1_ENA */
  994. #define ARIZONA_PWM1_ENA_WIDTH 1 /* PWM1_ENA */
  995. /*
  996. * R49 (0x31) - PWM Drive 2
  997. */
  998. #define ARIZONA_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */
  999. #define ARIZONA_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */
  1000. #define ARIZONA_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */
  1001. /*
  1002. * R50 (0x32) - PWM Drive 3
  1003. */
  1004. #define ARIZONA_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */
  1005. #define ARIZONA_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */
  1006. #define ARIZONA_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */
  1007. /*
  1008. * R64 (0x40) - Wake control
  1009. */
  1010. #define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */
  1011. #define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */
  1012. #define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */
  1013. #define ARIZONA_WKUP_GP5_FALL_WIDTH 1 /* WKUP_GP5_FALL */
  1014. #define ARIZONA_WKUP_GP5_RISE 0x0010 /* WKUP_GP5_RISE */
  1015. #define ARIZONA_WKUP_GP5_RISE_MASK 0x0010 /* WKUP_GP5_RISE */
  1016. #define ARIZONA_WKUP_GP5_RISE_SHIFT 4 /* WKUP_GP5_RISE */
  1017. #define ARIZONA_WKUP_GP5_RISE_WIDTH 1 /* WKUP_GP5_RISE */
  1018. #define ARIZONA_WKUP_JD1_FALL 0x0008 /* WKUP_JD1_FALL */
  1019. #define ARIZONA_WKUP_JD1_FALL_MASK 0x0008 /* WKUP_JD1_FALL */
  1020. #define ARIZONA_WKUP_JD1_FALL_SHIFT 3 /* WKUP_JD1_FALL */
  1021. #define ARIZONA_WKUP_JD1_FALL_WIDTH 1 /* WKUP_JD1_FALL */
  1022. #define ARIZONA_WKUP_JD1_RISE 0x0004 /* WKUP_JD1_RISE */
  1023. #define ARIZONA_WKUP_JD1_RISE_MASK 0x0004 /* WKUP_JD1_RISE */
  1024. #define ARIZONA_WKUP_JD1_RISE_SHIFT 2 /* WKUP_JD1_RISE */
  1025. #define ARIZONA_WKUP_JD1_RISE_WIDTH 1 /* WKUP_JD1_RISE */
  1026. #define ARIZONA_WKUP_JD2_FALL 0x0002 /* WKUP_JD2_FALL */
  1027. #define ARIZONA_WKUP_JD2_FALL_MASK 0x0002 /* WKUP_JD2_FALL */
  1028. #define ARIZONA_WKUP_JD2_FALL_SHIFT 1 /* WKUP_JD2_FALL */
  1029. #define ARIZONA_WKUP_JD2_FALL_WIDTH 1 /* WKUP_JD2_FALL */
  1030. #define ARIZONA_WKUP_JD2_RISE 0x0001 /* WKUP_JD2_RISE */
  1031. #define ARIZONA_WKUP_JD2_RISE_MASK 0x0001 /* WKUP_JD2_RISE */
  1032. #define ARIZONA_WKUP_JD2_RISE_SHIFT 0 /* WKUP_JD2_RISE */
  1033. #define ARIZONA_WKUP_JD2_RISE_WIDTH 1 /* WKUP_JD2_RISE */
  1034. /*
  1035. * R65 (0x41) - Sequence control
  1036. */
  1037. #define ARIZONA_WSEQ_ENA_GP5_FALL 0x0020 /* WSEQ_ENA_GP5_FALL */
  1038. #define ARIZONA_WSEQ_ENA_GP5_FALL_MASK 0x0020 /* WSEQ_ENA_GP5_FALL */
  1039. #define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT 5 /* WSEQ_ENA_GP5_FALL */
  1040. #define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH 1 /* WSEQ_ENA_GP5_FALL */
  1041. #define ARIZONA_WSEQ_ENA_GP5_RISE 0x0010 /* WSEQ_ENA_GP5_RISE */
  1042. #define ARIZONA_WSEQ_ENA_GP5_RISE_MASK 0x0010 /* WSEQ_ENA_GP5_RISE */
  1043. #define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT 4 /* WSEQ_ENA_GP5_RISE */
  1044. #define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH 1 /* WSEQ_ENA_GP5_RISE */
  1045. #define ARIZONA_WSEQ_ENA_JD1_FALL 0x0008 /* WSEQ_ENA_JD1_FALL */
  1046. #define ARIZONA_WSEQ_ENA_JD1_FALL_MASK 0x0008 /* WSEQ_ENA_JD1_FALL */
  1047. #define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT 3 /* WSEQ_ENA_JD1_FALL */
  1048. #define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH 1 /* WSEQ_ENA_JD1_FALL */
  1049. #define ARIZONA_WSEQ_ENA_JD1_RISE 0x0004 /* WSEQ_ENA_JD1_RISE */
  1050. #define ARIZONA_WSEQ_ENA_JD1_RISE_MASK 0x0004 /* WSEQ_ENA_JD1_RISE */
  1051. #define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT 2 /* WSEQ_ENA_JD1_RISE */
  1052. #define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH 1 /* WSEQ_ENA_JD1_RISE */
  1053. #define ARIZONA_WSEQ_ENA_JD2_FALL 0x0002 /* WSEQ_ENA_JD2_FALL */
  1054. #define ARIZONA_WSEQ_ENA_JD2_FALL_MASK 0x0002 /* WSEQ_ENA_JD2_FALL */
  1055. #define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT 1 /* WSEQ_ENA_JD2_FALL */
  1056. #define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH 1 /* WSEQ_ENA_JD2_FALL */
  1057. #define ARIZONA_WSEQ_ENA_JD2_RISE 0x0001 /* WSEQ_ENA_JD2_RISE */
  1058. #define ARIZONA_WSEQ_ENA_JD2_RISE_MASK 0x0001 /* WSEQ_ENA_JD2_RISE */
  1059. #define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */
  1060. #define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */
  1061. /*
  1062. * R97 (0x61) - Sample Rate Sequence Select 1
  1063. */
  1064. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
  1065. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
  1066. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
  1067. /*
  1068. * R98 (0x62) - Sample Rate Sequence Select 2
  1069. */
  1070. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
  1071. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
  1072. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
  1073. /*
  1074. * R99 (0x63) - Sample Rate Sequence Select 3
  1075. */
  1076. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
  1077. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
  1078. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
  1079. /*
  1080. * R100 (0x64) - Sample Rate Sequence Select 4
  1081. */
  1082. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
  1083. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
  1084. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
  1085. /*
  1086. * R104 (0x68) - Always On Triggers Sequence Select 1
  1087. */
  1088. #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
  1089. #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
  1090. #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
  1091. /*
  1092. * R105 (0x69) - Always On Triggers Sequence Select 2
  1093. */
  1094. #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
  1095. #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
  1096. #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
  1097. /*
  1098. * R106 (0x6A) - Always On Triggers Sequence Select 3
  1099. */
  1100. #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
  1101. #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
  1102. #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
  1103. /*
  1104. * R107 (0x6B) - Always On Triggers Sequence Select 4
  1105. */
  1106. #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
  1107. #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
  1108. #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
  1109. /*
  1110. * R108 (0x6C) - Always On Triggers Sequence Select 5
  1111. */
  1112. #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
  1113. #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
  1114. #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
  1115. /*
  1116. * R109 (0x6D) - Always On Triggers Sequence Select 6
  1117. */
  1118. #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
  1119. #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
  1120. #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
  1121. /*
  1122. * R112 (0x70) - Comfort Noise Generator
  1123. */
  1124. #define ARIZONA_NOISE_GEN_RATE_MASK 0x7800 /* NOISE_GEN_RATE - [14:11] */
  1125. #define ARIZONA_NOISE_GEN_RATE_SHIFT 11 /* NOISE_GEN_RATE - [14:11] */
  1126. #define ARIZONA_NOISE_GEN_RATE_WIDTH 4 /* NOISE_GEN_RATE - [14:11] */
  1127. #define ARIZONA_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */
  1128. #define ARIZONA_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */
  1129. #define ARIZONA_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */
  1130. #define ARIZONA_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */
  1131. #define ARIZONA_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */
  1132. #define ARIZONA_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */
  1133. #define ARIZONA_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */
  1134. /*
  1135. * R144 (0x90) - Haptics Control 1
  1136. */
  1137. #define ARIZONA_HAP_RATE_MASK 0x7800 /* HAP_RATE - [14:11] */
  1138. #define ARIZONA_HAP_RATE_SHIFT 11 /* HAP_RATE - [14:11] */
  1139. #define ARIZONA_HAP_RATE_WIDTH 4 /* HAP_RATE - [14:11] */
  1140. #define ARIZONA_ONESHOT_TRIG 0x0010 /* ONESHOT_TRIG */
  1141. #define ARIZONA_ONESHOT_TRIG_MASK 0x0010 /* ONESHOT_TRIG */
  1142. #define ARIZONA_ONESHOT_TRIG_SHIFT 4 /* ONESHOT_TRIG */
  1143. #define ARIZONA_ONESHOT_TRIG_WIDTH 1 /* ONESHOT_TRIG */
  1144. #define ARIZONA_HAP_CTRL_MASK 0x000C /* HAP_CTRL - [3:2] */
  1145. #define ARIZONA_HAP_CTRL_SHIFT 2 /* HAP_CTRL - [3:2] */
  1146. #define ARIZONA_HAP_CTRL_WIDTH 2 /* HAP_CTRL - [3:2] */
  1147. #define ARIZONA_HAP_ACT 0x0002 /* HAP_ACT */
  1148. #define ARIZONA_HAP_ACT_MASK 0x0002 /* HAP_ACT */
  1149. #define ARIZONA_HAP_ACT_SHIFT 1 /* HAP_ACT */
  1150. #define ARIZONA_HAP_ACT_WIDTH 1 /* HAP_ACT */
  1151. /*
  1152. * R145 (0x91) - Haptics Control 2
  1153. */
  1154. #define ARIZONA_LRA_FREQ_MASK 0x7FFF /* LRA_FREQ - [14:0] */
  1155. #define ARIZONA_LRA_FREQ_SHIFT 0 /* LRA_FREQ - [14:0] */
  1156. #define ARIZONA_LRA_FREQ_WIDTH 15 /* LRA_FREQ - [14:0] */
  1157. /*
  1158. * R146 (0x92) - Haptics phase 1 intensity
  1159. */
  1160. #define ARIZONA_PHASE1_INTENSITY_MASK 0x00FF /* PHASE1_INTENSITY - [7:0] */
  1161. #define ARIZONA_PHASE1_INTENSITY_SHIFT 0 /* PHASE1_INTENSITY - [7:0] */
  1162. #define ARIZONA_PHASE1_INTENSITY_WIDTH 8 /* PHASE1_INTENSITY - [7:0] */
  1163. /*
  1164. * R147 (0x93) - Haptics phase 1 duration
  1165. */
  1166. #define ARIZONA_PHASE1_DURATION_MASK 0x01FF /* PHASE1_DURATION - [8:0] */
  1167. #define ARIZONA_PHASE1_DURATION_SHIFT 0 /* PHASE1_DURATION - [8:0] */
  1168. #define ARIZONA_PHASE1_DURATION_WIDTH 9 /* PHASE1_DURATION - [8:0] */
  1169. /*
  1170. * R148 (0x94) - Haptics phase 2 intensity
  1171. */
  1172. #define ARIZONA_PHASE2_INTENSITY_MASK 0x00FF /* PHASE2_INTENSITY - [7:0] */
  1173. #define ARIZONA_PHASE2_INTENSITY_SHIFT 0 /* PHASE2_INTENSITY - [7:0] */
  1174. #define ARIZONA_PHASE2_INTENSITY_WIDTH 8 /* PHASE2_INTENSITY - [7:0] */
  1175. /*
  1176. * R149 (0x95) - Haptics phase 2 duration
  1177. */
  1178. #define ARIZONA_PHASE2_DURATION_MASK 0x07FF /* PHASE2_DURATION - [10:0] */
  1179. #define ARIZONA_PHASE2_DURATION_SHIFT 0 /* PHASE2_DURATION - [10:0] */
  1180. #define ARIZONA_PHASE2_DURATION_WIDTH 11 /* PHASE2_DURATION - [10:0] */
  1181. /*
  1182. * R150 (0x96) - Haptics phase 3 intensity
  1183. */
  1184. #define ARIZONA_PHASE3_INTENSITY_MASK 0x00FF /* PHASE3_INTENSITY - [7:0] */
  1185. #define ARIZONA_PHASE3_INTENSITY_SHIFT 0 /* PHASE3_INTENSITY - [7:0] */
  1186. #define ARIZONA_PHASE3_INTENSITY_WIDTH 8 /* PHASE3_INTENSITY - [7:0] */
  1187. /*
  1188. * R151 (0x97) - Haptics phase 3 duration
  1189. */
  1190. #define ARIZONA_PHASE3_DURATION_MASK 0x01FF /* PHASE3_DURATION - [8:0] */
  1191. #define ARIZONA_PHASE3_DURATION_SHIFT 0 /* PHASE3_DURATION - [8:0] */
  1192. #define ARIZONA_PHASE3_DURATION_WIDTH 9 /* PHASE3_DURATION - [8:0] */
  1193. /*
  1194. * R152 (0x98) - Haptics Status
  1195. */
  1196. #define ARIZONA_ONESHOT_STS 0x0001 /* ONESHOT_STS */
  1197. #define ARIZONA_ONESHOT_STS_MASK 0x0001 /* ONESHOT_STS */
  1198. #define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */
  1199. #define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */
  1200. /*
  1201. * R256 (0x100) - Clock 32k 1
  1202. */
  1203. #define ARIZONA_CLK_32K_ENA 0x0040 /* CLK_32K_ENA */
  1204. #define ARIZONA_CLK_32K_ENA_MASK 0x0040 /* CLK_32K_ENA */
  1205. #define ARIZONA_CLK_32K_ENA_SHIFT 6 /* CLK_32K_ENA */
  1206. #define ARIZONA_CLK_32K_ENA_WIDTH 1 /* CLK_32K_ENA */
  1207. #define ARIZONA_CLK_32K_SRC_MASK 0x0003 /* CLK_32K_SRC - [1:0] */
  1208. #define ARIZONA_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [1:0] */
  1209. #define ARIZONA_CLK_32K_SRC_WIDTH 2 /* CLK_32K_SRC - [1:0] */
  1210. /*
  1211. * R257 (0x101) - System Clock 1
  1212. */
  1213. #define ARIZONA_SYSCLK_FRAC 0x8000 /* SYSCLK_FRAC */
  1214. #define ARIZONA_SYSCLK_FRAC_MASK 0x8000 /* SYSCLK_FRAC */
  1215. #define ARIZONA_SYSCLK_FRAC_SHIFT 15 /* SYSCLK_FRAC */
  1216. #define ARIZONA_SYSCLK_FRAC_WIDTH 1 /* SYSCLK_FRAC */
  1217. #define ARIZONA_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
  1218. #define ARIZONA_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
  1219. #define ARIZONA_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
  1220. #define ARIZONA_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
  1221. #define ARIZONA_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
  1222. #define ARIZONA_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
  1223. #define ARIZONA_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
  1224. #define ARIZONA_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
  1225. #define ARIZONA_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
  1226. #define ARIZONA_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
  1227. /*
  1228. * R258 (0x102) - Sample rate 1
  1229. */
  1230. #define ARIZONA_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
  1231. #define ARIZONA_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
  1232. #define ARIZONA_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
  1233. /*
  1234. * R259 (0x103) - Sample rate 2
  1235. */
  1236. #define ARIZONA_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */
  1237. #define ARIZONA_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */
  1238. #define ARIZONA_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */
  1239. /*
  1240. * R260 (0x104) - Sample rate 3
  1241. */
  1242. #define ARIZONA_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */
  1243. #define ARIZONA_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */
  1244. #define ARIZONA_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */
  1245. /*
  1246. * R266 (0x10A) - Sample rate 1 status
  1247. */
  1248. #define ARIZONA_SAMPLE_RATE_1_STS_MASK 0x001F /* SAMPLE_RATE_1_STS - [4:0] */
  1249. #define ARIZONA_SAMPLE_RATE_1_STS_SHIFT 0 /* SAMPLE_RATE_1_STS - [4:0] */
  1250. #define ARIZONA_SAMPLE_RATE_1_STS_WIDTH 5 /* SAMPLE_RATE_1_STS - [4:0] */
  1251. /*
  1252. * R267 (0x10B) - Sample rate 2 status
  1253. */
  1254. #define ARIZONA_SAMPLE_RATE_2_STS_MASK 0x001F /* SAMPLE_RATE_2_STS - [4:0] */
  1255. #define ARIZONA_SAMPLE_RATE_2_STS_SHIFT 0 /* SAMPLE_RATE_2_STS - [4:0] */
  1256. #define ARIZONA_SAMPLE_RATE_2_STS_WIDTH 5 /* SAMPLE_RATE_2_STS - [4:0] */
  1257. /*
  1258. * R268 (0x10C) - Sample rate 3 status
  1259. */
  1260. #define ARIZONA_SAMPLE_RATE_3_STS_MASK 0x001F /* SAMPLE_RATE_3_STS - [4:0] */
  1261. #define ARIZONA_SAMPLE_RATE_3_STS_SHIFT 0 /* SAMPLE_RATE_3_STS - [4:0] */
  1262. #define ARIZONA_SAMPLE_RATE_3_STS_WIDTH 5 /* SAMPLE_RATE_3_STS - [4:0] */
  1263. /*
  1264. * R274 (0x112) - Async clock 1
  1265. */
  1266. #define ARIZONA_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */
  1267. #define ARIZONA_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */
  1268. #define ARIZONA_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */
  1269. #define ARIZONA_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */
  1270. #define ARIZONA_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */
  1271. #define ARIZONA_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */
  1272. #define ARIZONA_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */
  1273. #define ARIZONA_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */
  1274. #define ARIZONA_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */
  1275. #define ARIZONA_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */
  1276. /*
  1277. * R275 (0x113) - Async sample rate 1
  1278. */
  1279. #define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */
  1280. #define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */
  1281. #define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */
  1282. /*
  1283. * R283 (0x11B) - Async sample rate 1 status
  1284. */
  1285. #define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */
  1286. #define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
  1287. #define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
  1288. /*
  1289. * R329 (0x149) - Output system clock
  1290. */
  1291. #define ARIZONA_OPCLK_ENA 0x8000 /* OPCLK_ENA */
  1292. #define ARIZONA_OPCLK_ENA_MASK 0x8000 /* OPCLK_ENA */
  1293. #define ARIZONA_OPCLK_ENA_SHIFT 15 /* OPCLK_ENA */
  1294. #define ARIZONA_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
  1295. #define ARIZONA_OPCLK_DIV_MASK 0x00F8 /* OPCLK_DIV - [7:3] */
  1296. #define ARIZONA_OPCLK_DIV_SHIFT 3 /* OPCLK_DIV - [7:3] */
  1297. #define ARIZONA_OPCLK_DIV_WIDTH 5 /* OPCLK_DIV - [7:3] */
  1298. #define ARIZONA_OPCLK_SEL_MASK 0x0007 /* OPCLK_SEL - [2:0] */
  1299. #define ARIZONA_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [2:0] */
  1300. #define ARIZONA_OPCLK_SEL_WIDTH 3 /* OPCLK_SEL - [2:0] */
  1301. /*
  1302. * R330 (0x14A) - Output async clock
  1303. */
  1304. #define ARIZONA_OPCLK_ASYNC_ENA 0x8000 /* OPCLK_ASYNC_ENA */
  1305. #define ARIZONA_OPCLK_ASYNC_ENA_MASK 0x8000 /* OPCLK_ASYNC_ENA */
  1306. #define ARIZONA_OPCLK_ASYNC_ENA_SHIFT 15 /* OPCLK_ASYNC_ENA */
  1307. #define ARIZONA_OPCLK_ASYNC_ENA_WIDTH 1 /* OPCLK_ASYNC_ENA */
  1308. #define ARIZONA_OPCLK_ASYNC_DIV_MASK 0x00F8 /* OPCLK_ASYNC_DIV - [7:3] */
  1309. #define ARIZONA_OPCLK_ASYNC_DIV_SHIFT 3 /* OPCLK_ASYNC_DIV - [7:3] */
  1310. #define ARIZONA_OPCLK_ASYNC_DIV_WIDTH 5 /* OPCLK_ASYNC_DIV - [7:3] */
  1311. #define ARIZONA_OPCLK_ASYNC_SEL_MASK 0x0007 /* OPCLK_ASYNC_SEL - [2:0] */
  1312. #define ARIZONA_OPCLK_ASYNC_SEL_SHIFT 0 /* OPCLK_ASYNC_SEL - [2:0] */
  1313. #define ARIZONA_OPCLK_ASYNC_SEL_WIDTH 3 /* OPCLK_ASYNC_SEL - [2:0] */
  1314. /*
  1315. * R338 (0x152) - Rate Estimator 1
  1316. */
  1317. #define ARIZONA_TRIG_ON_STARTUP 0x0010 /* TRIG_ON_STARTUP */
  1318. #define ARIZONA_TRIG_ON_STARTUP_MASK 0x0010 /* TRIG_ON_STARTUP */
  1319. #define ARIZONA_TRIG_ON_STARTUP_SHIFT 4 /* TRIG_ON_STARTUP */
  1320. #define ARIZONA_TRIG_ON_STARTUP_WIDTH 1 /* TRIG_ON_STARTUP */
  1321. #define ARIZONA_LRCLK_SRC_MASK 0x000E /* LRCLK_SRC - [3:1] */
  1322. #define ARIZONA_LRCLK_SRC_SHIFT 1 /* LRCLK_SRC - [3:1] */
  1323. #define ARIZONA_LRCLK_SRC_WIDTH 3 /* LRCLK_SRC - [3:1] */
  1324. #define ARIZONA_RATE_EST_ENA 0x0001 /* RATE_EST_ENA */
  1325. #define ARIZONA_RATE_EST_ENA_MASK 0x0001 /* RATE_EST_ENA */
  1326. #define ARIZONA_RATE_EST_ENA_SHIFT 0 /* RATE_EST_ENA */
  1327. #define ARIZONA_RATE_EST_ENA_WIDTH 1 /* RATE_EST_ENA */
  1328. /*
  1329. * R339 (0x153) - Rate Estimator 2
  1330. */
  1331. #define ARIZONA_SAMPLE_RATE_DETECT_A_MASK 0x001F /* SAMPLE_RATE_DETECT_A - [4:0] */
  1332. #define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT 0 /* SAMPLE_RATE_DETECT_A - [4:0] */
  1333. #define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH 5 /* SAMPLE_RATE_DETECT_A - [4:0] */
  1334. /*
  1335. * R340 (0x154) - Rate Estimator 3
  1336. */
  1337. #define ARIZONA_SAMPLE_RATE_DETECT_B_MASK 0x001F /* SAMPLE_RATE_DETECT_B - [4:0] */
  1338. #define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT 0 /* SAMPLE_RATE_DETECT_B - [4:0] */
  1339. #define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH 5 /* SAMPLE_RATE_DETECT_B - [4:0] */
  1340. /*
  1341. * R341 (0x155) - Rate Estimator 4
  1342. */
  1343. #define ARIZONA_SAMPLE_RATE_DETECT_C_MASK 0x001F /* SAMPLE_RATE_DETECT_C - [4:0] */
  1344. #define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT 0 /* SAMPLE_RATE_DETECT_C - [4:0] */
  1345. #define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH 5 /* SAMPLE_RATE_DETECT_C - [4:0] */
  1346. /*
  1347. * R342 (0x156) - Rate Estimator 5
  1348. */
  1349. #define ARIZONA_SAMPLE_RATE_DETECT_D_MASK 0x001F /* SAMPLE_RATE_DETECT_D - [4:0] */
  1350. #define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT 0 /* SAMPLE_RATE_DETECT_D - [4:0] */
  1351. #define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */
  1352. /*
  1353. * R369 (0x171) - FLL1 Control 1
  1354. */
  1355. #define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */
  1356. #define ARIZONA_FLL1_FREERUN_MASK 0x0002 /* FLL1_FREERUN */
  1357. #define ARIZONA_FLL1_FREERUN_SHIFT 1 /* FLL1_FREERUN */
  1358. #define ARIZONA_FLL1_FREERUN_WIDTH 1 /* FLL1_FREERUN */
  1359. #define ARIZONA_FLL1_ENA 0x0001 /* FLL1_ENA */
  1360. #define ARIZONA_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
  1361. #define ARIZONA_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
  1362. #define ARIZONA_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
  1363. /*
  1364. * R370 (0x172) - FLL1 Control 2
  1365. */
  1366. #define ARIZONA_FLL1_CTRL_UPD 0x8000 /* FLL1_CTRL_UPD */
  1367. #define ARIZONA_FLL1_CTRL_UPD_MASK 0x8000 /* FLL1_CTRL_UPD */
  1368. #define ARIZONA_FLL1_CTRL_UPD_SHIFT 15 /* FLL1_CTRL_UPD */
  1369. #define ARIZONA_FLL1_CTRL_UPD_WIDTH 1 /* FLL1_CTRL_UPD */
  1370. #define ARIZONA_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */
  1371. #define ARIZONA_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */
  1372. #define ARIZONA_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */
  1373. /*
  1374. * R371 (0x173) - FLL1 Control 3
  1375. */
  1376. #define ARIZONA_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
  1377. #define ARIZONA_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
  1378. #define ARIZONA_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
  1379. /*
  1380. * R372 (0x174) - FLL1 Control 4
  1381. */
  1382. #define ARIZONA_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
  1383. #define ARIZONA_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
  1384. #define ARIZONA_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
  1385. /*
  1386. * R373 (0x175) - FLL1 Control 5
  1387. */
  1388. #define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */
  1389. #define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */
  1390. #define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */
  1391. #define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */
  1392. #define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */
  1393. #define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */
  1394. /*
  1395. * R374 (0x176) - FLL1 Control 6
  1396. */
  1397. #define ARIZONA_FLL1_CLK_REF_DIV_MASK 0x00C0 /* FLL1_CLK_REF_DIV - [7:6] */
  1398. #define ARIZONA_FLL1_CLK_REF_DIV_SHIFT 6 /* FLL1_CLK_REF_DIV - [7:6] */
  1399. #define ARIZONA_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [7:6] */
  1400. #define ARIZONA_FLL1_CLK_REF_SRC_MASK 0x000F /* FLL1_CLK_REF_SRC - [3:0] */
  1401. #define ARIZONA_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [3:0] */
  1402. #define ARIZONA_FLL1_CLK_REF_SRC_WIDTH 4 /* FLL1_CLK_REF_SRC - [3:0] */
  1403. /*
  1404. * R375 (0x177) - FLL1 Loop Filter Test 1
  1405. */
  1406. #define ARIZONA_FLL1_FRC_INTEG_UPD 0x8000 /* FLL1_FRC_INTEG_UPD */
  1407. #define ARIZONA_FLL1_FRC_INTEG_UPD_MASK 0x8000 /* FLL1_FRC_INTEG_UPD */
  1408. #define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT 15 /* FLL1_FRC_INTEG_UPD */
  1409. #define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH 1 /* FLL1_FRC_INTEG_UPD */
  1410. #define ARIZONA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF /* FLL1_FRC_INTEG_VAL - [11:0] */
  1411. #define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */
  1412. #define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */
  1413. /*
  1414. * R385 (0x181) - FLL1 Synchroniser 1
  1415. */
  1416. #define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */
  1417. #define ARIZONA_FLL1_SYNC_ENA_MASK 0x0001 /* FLL1_SYNC_ENA */
  1418. #define ARIZONA_FLL1_SYNC_ENA_SHIFT 0 /* FLL1_SYNC_ENA */
  1419. #define ARIZONA_FLL1_SYNC_ENA_WIDTH 1 /* FLL1_SYNC_ENA */
  1420. /*
  1421. * R386 (0x182) - FLL1 Synchroniser 2
  1422. */
  1423. #define ARIZONA_FLL1_SYNC_N_MASK 0x03FF /* FLL1_SYNC_N - [9:0] */
  1424. #define ARIZONA_FLL1_SYNC_N_SHIFT 0 /* FLL1_SYNC_N - [9:0] */
  1425. #define ARIZONA_FLL1_SYNC_N_WIDTH 10 /* FLL1_SYNC_N - [9:0] */
  1426. /*
  1427. * R387 (0x183) - FLL1 Synchroniser 3
  1428. */
  1429. #define ARIZONA_FLL1_SYNC_THETA_MASK 0xFFFF /* FLL1_SYNC_THETA - [15:0] */
  1430. #define ARIZONA_FLL1_SYNC_THETA_SHIFT 0 /* FLL1_SYNC_THETA - [15:0] */
  1431. #define ARIZONA_FLL1_SYNC_THETA_WIDTH 16 /* FLL1_SYNC_THETA - [15:0] */
  1432. /*
  1433. * R388 (0x184) - FLL1 Synchroniser 4
  1434. */
  1435. #define ARIZONA_FLL1_SYNC_LAMBDA_MASK 0xFFFF /* FLL1_SYNC_LAMBDA - [15:0] */
  1436. #define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT 0 /* FLL1_SYNC_LAMBDA - [15:0] */
  1437. #define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH 16 /* FLL1_SYNC_LAMBDA - [15:0] */
  1438. /*
  1439. * R389 (0x185) - FLL1 Synchroniser 5
  1440. */
  1441. #define ARIZONA_FLL1_SYNC_FRATIO_MASK 0x0700 /* FLL1_SYNC_FRATIO - [10:8] */
  1442. #define ARIZONA_FLL1_SYNC_FRATIO_SHIFT 8 /* FLL1_SYNC_FRATIO - [10:8] */
  1443. #define ARIZONA_FLL1_SYNC_FRATIO_WIDTH 3 /* FLL1_SYNC_FRATIO - [10:8] */
  1444. /*
  1445. * R390 (0x186) - FLL1 Synchroniser 6
  1446. */
  1447. #define ARIZONA_FLL1_CLK_SYNC_DIV_MASK 0x00C0 /* FLL1_CLK_SYNC_DIV - [7:6] */
  1448. #define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT 6 /* FLL1_CLK_SYNC_DIV - [7:6] */
  1449. #define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH 2 /* FLL1_CLK_SYNC_DIV - [7:6] */
  1450. #define ARIZONA_FLL1_CLK_SYNC_SRC_MASK 0x000F /* FLL1_CLK_SYNC_SRC - [3:0] */
  1451. #define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */
  1452. #define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */
  1453. /*
  1454. * R393 (0x189) - FLL1 Spread Spectrum
  1455. */
  1456. #define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */
  1457. #define ARIZONA_FLL1_SS_AMPL_SHIFT 4 /* FLL1_SS_AMPL - [5:4] */
  1458. #define ARIZONA_FLL1_SS_AMPL_WIDTH 2 /* FLL1_SS_AMPL - [5:4] */
  1459. #define ARIZONA_FLL1_SS_FREQ_MASK 0x000C /* FLL1_SS_FREQ - [3:2] */
  1460. #define ARIZONA_FLL1_SS_FREQ_SHIFT 2 /* FLL1_SS_FREQ - [3:2] */
  1461. #define ARIZONA_FLL1_SS_FREQ_WIDTH 2 /* FLL1_SS_FREQ - [3:2] */
  1462. #define ARIZONA_FLL1_SS_SEL_MASK 0x0003 /* FLL1_SS_SEL - [1:0] */
  1463. #define ARIZONA_FLL1_SS_SEL_SHIFT 0 /* FLL1_SS_SEL - [1:0] */
  1464. #define ARIZONA_FLL1_SS_SEL_WIDTH 2 /* FLL1_SS_SEL - [1:0] */
  1465. /*
  1466. * R394 (0x18A) - FLL1 GPIO Clock
  1467. */
  1468. #define ARIZONA_FLL1_GPDIV_MASK 0x00FE /* FLL1_GPDIV - [7:1] */
  1469. #define ARIZONA_FLL1_GPDIV_SHIFT 1 /* FLL1_GPDIV - [7:1] */
  1470. #define ARIZONA_FLL1_GPDIV_WIDTH 7 /* FLL1_GPDIV - [7:1] */
  1471. #define ARIZONA_FLL1_GPDIV_ENA 0x0001 /* FLL1_GPDIV_ENA */
  1472. #define ARIZONA_FLL1_GPDIV_ENA_MASK 0x0001 /* FLL1_GPDIV_ENA */
  1473. #define ARIZONA_FLL1_GPDIV_ENA_SHIFT 0 /* FLL1_GPDIV_ENA */
  1474. #define ARIZONA_FLL1_GPDIV_ENA_WIDTH 1 /* FLL1_GPDIV_ENA */
  1475. /*
  1476. * R401 (0x191) - FLL2 Control 1
  1477. */
  1478. #define ARIZONA_FLL2_FREERUN 0x0002 /* FLL2_FREERUN */
  1479. #define ARIZONA_FLL2_FREERUN_MASK 0x0002 /* FLL2_FREERUN */
  1480. #define ARIZONA_FLL2_FREERUN_SHIFT 1 /* FLL2_FREERUN */
  1481. #define ARIZONA_FLL2_FREERUN_WIDTH 1 /* FLL2_FREERUN */
  1482. #define ARIZONA_FLL2_ENA 0x0001 /* FLL2_ENA */
  1483. #define ARIZONA_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
  1484. #define ARIZONA_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
  1485. #define ARIZONA_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
  1486. /*
  1487. * R402 (0x192) - FLL2 Control 2
  1488. */
  1489. #define ARIZONA_FLL2_CTRL_UPD 0x8000 /* FLL2_CTRL_UPD */
  1490. #define ARIZONA_FLL2_CTRL_UPD_MASK 0x8000 /* FLL2_CTRL_UPD */
  1491. #define ARIZONA_FLL2_CTRL_UPD_SHIFT 15 /* FLL2_CTRL_UPD */
  1492. #define ARIZONA_FLL2_CTRL_UPD_WIDTH 1 /* FLL2_CTRL_UPD */
  1493. #define ARIZONA_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */
  1494. #define ARIZONA_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */
  1495. #define ARIZONA_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */
  1496. /*
  1497. * R403 (0x193) - FLL2 Control 3
  1498. */
  1499. #define ARIZONA_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
  1500. #define ARIZONA_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
  1501. #define ARIZONA_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
  1502. /*
  1503. * R404 (0x194) - FLL2 Control 4
  1504. */
  1505. #define ARIZONA_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
  1506. #define ARIZONA_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
  1507. #define ARIZONA_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
  1508. /*
  1509. * R405 (0x195) - FLL2 Control 5
  1510. */
  1511. #define ARIZONA_FLL2_FRATIO_MASK 0x0700 /* FLL2_FRATIO - [10:8] */
  1512. #define ARIZONA_FLL2_FRATIO_SHIFT 8 /* FLL2_FRATIO - [10:8] */
  1513. #define ARIZONA_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [10:8] */
  1514. #define ARIZONA_FLL2_OUTDIV_MASK 0x000E /* FLL2_OUTDIV - [3:1] */
  1515. #define ARIZONA_FLL2_OUTDIV_SHIFT 1 /* FLL2_OUTDIV - [3:1] */
  1516. #define ARIZONA_FLL2_OUTDIV_WIDTH 3 /* FLL2_OUTDIV - [3:1] */
  1517. /*
  1518. * R406 (0x196) - FLL2 Control 6
  1519. */
  1520. #define ARIZONA_FLL2_CLK_REF_DIV_MASK 0x00C0 /* FLL2_CLK_REF_DIV - [7:6] */
  1521. #define ARIZONA_FLL2_CLK_REF_DIV_SHIFT 6 /* FLL2_CLK_REF_DIV - [7:6] */
  1522. #define ARIZONA_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [7:6] */
  1523. #define ARIZONA_FLL2_CLK_REF_SRC_MASK 0x000F /* FLL2_CLK_REF_SRC - [3:0] */
  1524. #define ARIZONA_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [3:0] */
  1525. #define ARIZONA_FLL2_CLK_REF_SRC_WIDTH 4 /* FLL2_CLK_REF_SRC - [3:0] */
  1526. /*
  1527. * R407 (0x197) - FLL2 Loop Filter Test 1
  1528. */
  1529. #define ARIZONA_FLL2_FRC_INTEG_UPD 0x8000 /* FLL2_FRC_INTEG_UPD */
  1530. #define ARIZONA_FLL2_FRC_INTEG_UPD_MASK 0x8000 /* FLL2_FRC_INTEG_UPD */
  1531. #define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT 15 /* FLL2_FRC_INTEG_UPD */
  1532. #define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH 1 /* FLL2_FRC_INTEG_UPD */
  1533. #define ARIZONA_FLL2_FRC_INTEG_VAL_MASK 0x0FFF /* FLL2_FRC_INTEG_VAL - [11:0] */
  1534. #define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */
  1535. #define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */
  1536. /*
  1537. * R417 (0x1A1) - FLL2 Synchroniser 1
  1538. */
  1539. #define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */
  1540. #define ARIZONA_FLL2_SYNC_ENA_MASK 0x0001 /* FLL2_SYNC_ENA */
  1541. #define ARIZONA_FLL2_SYNC_ENA_SHIFT 0 /* FLL2_SYNC_ENA */
  1542. #define ARIZONA_FLL2_SYNC_ENA_WIDTH 1 /* FLL2_SYNC_ENA */
  1543. /*
  1544. * R418 (0x1A2) - FLL2 Synchroniser 2
  1545. */
  1546. #define ARIZONA_FLL2_SYNC_N_MASK 0x03FF /* FLL2_SYNC_N - [9:0] */
  1547. #define ARIZONA_FLL2_SYNC_N_SHIFT 0 /* FLL2_SYNC_N - [9:0] */
  1548. #define ARIZONA_FLL2_SYNC_N_WIDTH 10 /* FLL2_SYNC_N - [9:0] */
  1549. /*
  1550. * R419 (0x1A3) - FLL2 Synchroniser 3
  1551. */
  1552. #define ARIZONA_FLL2_SYNC_THETA_MASK 0xFFFF /* FLL2_SYNC_THETA - [15:0] */
  1553. #define ARIZONA_FLL2_SYNC_THETA_SHIFT 0 /* FLL2_SYNC_THETA - [15:0] */
  1554. #define ARIZONA_FLL2_SYNC_THETA_WIDTH 16 /* FLL2_SYNC_THETA - [15:0] */
  1555. /*
  1556. * R420 (0x1A4) - FLL2 Synchroniser 4
  1557. */
  1558. #define ARIZONA_FLL2_SYNC_LAMBDA_MASK 0xFFFF /* FLL2_SYNC_LAMBDA - [15:0] */
  1559. #define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT 0 /* FLL2_SYNC_LAMBDA - [15:0] */
  1560. #define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH 16 /* FLL2_SYNC_LAMBDA - [15:0] */
  1561. /*
  1562. * R421 (0x1A5) - FLL2 Synchroniser 5
  1563. */
  1564. #define ARIZONA_FLL2_SYNC_FRATIO_MASK 0x0700 /* FLL2_SYNC_FRATIO - [10:8] */
  1565. #define ARIZONA_FLL2_SYNC_FRATIO_SHIFT 8 /* FLL2_SYNC_FRATIO - [10:8] */
  1566. #define ARIZONA_FLL2_SYNC_FRATIO_WIDTH 3 /* FLL2_SYNC_FRATIO - [10:8] */
  1567. /*
  1568. * R422 (0x1A6) - FLL2 Synchroniser 6
  1569. */
  1570. #define ARIZONA_FLL2_CLK_SYNC_DIV_MASK 0x00C0 /* FLL2_CLK_SYNC_DIV - [7:6] */
  1571. #define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT 6 /* FLL2_CLK_SYNC_DIV - [7:6] */
  1572. #define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH 2 /* FLL2_CLK_SYNC_DIV - [7:6] */
  1573. #define ARIZONA_FLL2_CLK_SYNC_SRC_MASK 0x000F /* FLL2_CLK_SYNC_SRC - [3:0] */
  1574. #define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */
  1575. #define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */
  1576. /*
  1577. * R425 (0x1A9) - FLL2 Spread Spectrum
  1578. */
  1579. #define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */
  1580. #define ARIZONA_FLL2_SS_AMPL_SHIFT 4 /* FLL2_SS_AMPL - [5:4] */
  1581. #define ARIZONA_FLL2_SS_AMPL_WIDTH 2 /* FLL2_SS_AMPL - [5:4] */
  1582. #define ARIZONA_FLL2_SS_FREQ_MASK 0x000C /* FLL2_SS_FREQ - [3:2] */
  1583. #define ARIZONA_FLL2_SS_FREQ_SHIFT 2 /* FLL2_SS_FREQ - [3:2] */
  1584. #define ARIZONA_FLL2_SS_FREQ_WIDTH 2 /* FLL2_SS_FREQ - [3:2] */
  1585. #define ARIZONA_FLL2_SS_SEL_MASK 0x0003 /* FLL2_SS_SEL - [1:0] */
  1586. #define ARIZONA_FLL2_SS_SEL_SHIFT 0 /* FLL2_SS_SEL - [1:0] */
  1587. #define ARIZONA_FLL2_SS_SEL_WIDTH 2 /* FLL2_SS_SEL - [1:0] */
  1588. /*
  1589. * R426 (0x1AA) - FLL2 GPIO Clock
  1590. */
  1591. #define ARIZONA_FLL2_GPDIV_MASK 0x00FE /* FLL2_GPDIV - [7:1] */
  1592. #define ARIZONA_FLL2_GPDIV_SHIFT 1 /* FLL2_GPDIV - [7:1] */
  1593. #define ARIZONA_FLL2_GPDIV_WIDTH 7 /* FLL2_GPDIV - [7:1] */
  1594. #define ARIZONA_FLL2_GPDIV_ENA 0x0001 /* FLL2_GPDIV_ENA */
  1595. #define ARIZONA_FLL2_GPDIV_ENA_MASK 0x0001 /* FLL2_GPDIV_ENA */
  1596. #define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */
  1597. #define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */
  1598. /*
  1599. * R512 (0x200) - Mic Charge Pump 1
  1600. */
  1601. #define ARIZONA_CPMIC_DISCH 0x0004 /* CPMIC_DISCH */
  1602. #define ARIZONA_CPMIC_DISCH_MASK 0x0004 /* CPMIC_DISCH */
  1603. #define ARIZONA_CPMIC_DISCH_SHIFT 2 /* CPMIC_DISCH */
  1604. #define ARIZONA_CPMIC_DISCH_WIDTH 1 /* CPMIC_DISCH */
  1605. #define ARIZONA_CPMIC_BYPASS 0x0002 /* CPMIC_BYPASS */
  1606. #define ARIZONA_CPMIC_BYPASS_MASK 0x0002 /* CPMIC_BYPASS */
  1607. #define ARIZONA_CPMIC_BYPASS_SHIFT 1 /* CPMIC_BYPASS */
  1608. #define ARIZONA_CPMIC_BYPASS_WIDTH 1 /* CPMIC_BYPASS */
  1609. #define ARIZONA_CPMIC_ENA 0x0001 /* CPMIC_ENA */
  1610. #define ARIZONA_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
  1611. #define ARIZONA_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
  1612. #define ARIZONA_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */
  1613. /*
  1614. * R528 (0x210) - LDO1 Control 1
  1615. */
  1616. #define ARIZONA_LDO1_VSEL_MASK 0x07E0 /* LDO1_VSEL - [10:5] */
  1617. #define ARIZONA_LDO1_VSEL_SHIFT 5 /* LDO1_VSEL - [10:5] */
  1618. #define ARIZONA_LDO1_VSEL_WIDTH 6 /* LDO1_VSEL - [10:5] */
  1619. #define ARIZONA_LDO1_FAST 0x0010 /* LDO1_FAST */
  1620. #define ARIZONA_LDO1_FAST_MASK 0x0010 /* LDO1_FAST */
  1621. #define ARIZONA_LDO1_FAST_SHIFT 4 /* LDO1_FAST */
  1622. #define ARIZONA_LDO1_FAST_WIDTH 1 /* LDO1_FAST */
  1623. #define ARIZONA_LDO1_DISCH 0x0004 /* LDO1_DISCH */
  1624. #define ARIZONA_LDO1_DISCH_MASK 0x0004 /* LDO1_DISCH */
  1625. #define ARIZONA_LDO1_DISCH_SHIFT 2 /* LDO1_DISCH */
  1626. #define ARIZONA_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
  1627. #define ARIZONA_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */
  1628. #define ARIZONA_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */
  1629. #define ARIZONA_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */
  1630. #define ARIZONA_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */
  1631. #define ARIZONA_LDO1_ENA 0x0001 /* LDO1_ENA */
  1632. #define ARIZONA_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
  1633. #define ARIZONA_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
  1634. #define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
  1635. /*
  1636. * R531 (0x213) - LDO2 Control 1
  1637. */
  1638. #define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */
  1639. #define ARIZONA_LDO2_VSEL_SHIFT 5 /* LDO2_VSEL - [10:5] */
  1640. #define ARIZONA_LDO2_VSEL_WIDTH 6 /* LDO2_VSEL - [10:5] */
  1641. #define ARIZONA_LDO2_FAST 0x0010 /* LDO2_FAST */
  1642. #define ARIZONA_LDO2_FAST_MASK 0x0010 /* LDO2_FAST */
  1643. #define ARIZONA_LDO2_FAST_SHIFT 4 /* LDO2_FAST */
  1644. #define ARIZONA_LDO2_FAST_WIDTH 1 /* LDO2_FAST */
  1645. #define ARIZONA_LDO2_DISCH 0x0004 /* LDO2_DISCH */
  1646. #define ARIZONA_LDO2_DISCH_MASK 0x0004 /* LDO2_DISCH */
  1647. #define ARIZONA_LDO2_DISCH_SHIFT 2 /* LDO2_DISCH */
  1648. #define ARIZONA_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
  1649. #define ARIZONA_LDO2_BYPASS 0x0002 /* LDO2_BYPASS */
  1650. #define ARIZONA_LDO2_BYPASS_MASK 0x0002 /* LDO2_BYPASS */
  1651. #define ARIZONA_LDO2_BYPASS_SHIFT 1 /* LDO2_BYPASS */
  1652. #define ARIZONA_LDO2_BYPASS_WIDTH 1 /* LDO2_BYPASS */
  1653. #define ARIZONA_LDO2_ENA 0x0001 /* LDO2_ENA */
  1654. #define ARIZONA_LDO2_ENA_MASK 0x0001 /* LDO2_ENA */
  1655. #define ARIZONA_LDO2_ENA_SHIFT 0 /* LDO2_ENA */
  1656. #define ARIZONA_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
  1657. /*
  1658. * R536 (0x218) - Mic Bias Ctrl 1
  1659. */
  1660. #define ARIZONA_MICB1_EXT_CAP 0x8000 /* MICB1_EXT_CAP */
  1661. #define ARIZONA_MICB1_EXT_CAP_MASK 0x8000 /* MICB1_EXT_CAP */
  1662. #define ARIZONA_MICB1_EXT_CAP_SHIFT 15 /* MICB1_EXT_CAP */
  1663. #define ARIZONA_MICB1_EXT_CAP_WIDTH 1 /* MICB1_EXT_CAP */
  1664. #define ARIZONA_MICB1_LVL_MASK 0x01E0 /* MICB1_LVL - [8:5] */
  1665. #define ARIZONA_MICB1_LVL_SHIFT 5 /* MICB1_LVL - [8:5] */
  1666. #define ARIZONA_MICB1_LVL_WIDTH 4 /* MICB1_LVL - [8:5] */
  1667. #define ARIZONA_MICB1_FAST 0x0010 /* MICB1_FAST */
  1668. #define ARIZONA_MICB1_FAST_MASK 0x0010 /* MICB1_FAST */
  1669. #define ARIZONA_MICB1_FAST_SHIFT 4 /* MICB1_FAST */
  1670. #define ARIZONA_MICB1_FAST_WIDTH 1 /* MICB1_FAST */
  1671. #define ARIZONA_MICB1_RATE 0x0008 /* MICB1_RATE */
  1672. #define ARIZONA_MICB1_RATE_MASK 0x0008 /* MICB1_RATE */
  1673. #define ARIZONA_MICB1_RATE_SHIFT 3 /* MICB1_RATE */
  1674. #define ARIZONA_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
  1675. #define ARIZONA_MICB1_DISCH 0x0004 /* MICB1_DISCH */
  1676. #define ARIZONA_MICB1_DISCH_MASK 0x0004 /* MICB1_DISCH */
  1677. #define ARIZONA_MICB1_DISCH_SHIFT 2 /* MICB1_DISCH */
  1678. #define ARIZONA_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
  1679. #define ARIZONA_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */
  1680. #define ARIZONA_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */
  1681. #define ARIZONA_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */
  1682. #define ARIZONA_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */
  1683. #define ARIZONA_MICB1_ENA 0x0001 /* MICB1_ENA */
  1684. #define ARIZONA_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
  1685. #define ARIZONA_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
  1686. #define ARIZONA_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
  1687. /*
  1688. * R537 (0x219) - Mic Bias Ctrl 2
  1689. */
  1690. #define ARIZONA_MICB2_EXT_CAP 0x8000 /* MICB2_EXT_CAP */
  1691. #define ARIZONA_MICB2_EXT_CAP_MASK 0x8000 /* MICB2_EXT_CAP */
  1692. #define ARIZONA_MICB2_EXT_CAP_SHIFT 15 /* MICB2_EXT_CAP */
  1693. #define ARIZONA_MICB2_EXT_CAP_WIDTH 1 /* MICB2_EXT_CAP */
  1694. #define ARIZONA_MICB2_LVL_MASK 0x01E0 /* MICB2_LVL - [8:5] */
  1695. #define ARIZONA_MICB2_LVL_SHIFT 5 /* MICB2_LVL - [8:5] */
  1696. #define ARIZONA_MICB2_LVL_WIDTH 4 /* MICB2_LVL - [8:5] */
  1697. #define ARIZONA_MICB2_FAST 0x0010 /* MICB2_FAST */
  1698. #define ARIZONA_MICB2_FAST_MASK 0x0010 /* MICB2_FAST */
  1699. #define ARIZONA_MICB2_FAST_SHIFT 4 /* MICB2_FAST */
  1700. #define ARIZONA_MICB2_FAST_WIDTH 1 /* MICB2_FAST */
  1701. #define ARIZONA_MICB2_RATE 0x0008 /* MICB2_RATE */
  1702. #define ARIZONA_MICB2_RATE_MASK 0x0008 /* MICB2_RATE */
  1703. #define ARIZONA_MICB2_RATE_SHIFT 3 /* MICB2_RATE */
  1704. #define ARIZONA_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
  1705. #define ARIZONA_MICB2_DISCH 0x0004 /* MICB2_DISCH */
  1706. #define ARIZONA_MICB2_DISCH_MASK 0x0004 /* MICB2_DISCH */
  1707. #define ARIZONA_MICB2_DISCH_SHIFT 2 /* MICB2_DISCH */
  1708. #define ARIZONA_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
  1709. #define ARIZONA_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */
  1710. #define ARIZONA_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */
  1711. #define ARIZONA_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */
  1712. #define ARIZONA_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */
  1713. #define ARIZONA_MICB2_ENA 0x0001 /* MICB2_ENA */
  1714. #define ARIZONA_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
  1715. #define ARIZONA_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
  1716. #define ARIZONA_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
  1717. /*
  1718. * R538 (0x21A) - Mic Bias Ctrl 3
  1719. */
  1720. #define ARIZONA_MICB3_EXT_CAP 0x8000 /* MICB3_EXT_CAP */
  1721. #define ARIZONA_MICB3_EXT_CAP_MASK 0x8000 /* MICB3_EXT_CAP */
  1722. #define ARIZONA_MICB3_EXT_CAP_SHIFT 15 /* MICB3_EXT_CAP */
  1723. #define ARIZONA_MICB3_EXT_CAP_WIDTH 1 /* MICB3_EXT_CAP */
  1724. #define ARIZONA_MICB3_LVL_MASK 0x01E0 /* MICB3_LVL - [8:5] */
  1725. #define ARIZONA_MICB3_LVL_SHIFT 5 /* MICB3_LVL - [8:5] */
  1726. #define ARIZONA_MICB3_LVL_WIDTH 4 /* MICB3_LVL - [8:5] */
  1727. #define ARIZONA_MICB3_FAST 0x0010 /* MICB3_FAST */
  1728. #define ARIZONA_MICB3_FAST_MASK 0x0010 /* MICB3_FAST */
  1729. #define ARIZONA_MICB3_FAST_SHIFT 4 /* MICB3_FAST */
  1730. #define ARIZONA_MICB3_FAST_WIDTH 1 /* MICB3_FAST */
  1731. #define ARIZONA_MICB3_RATE 0x0008 /* MICB3_RATE */
  1732. #define ARIZONA_MICB3_RATE_MASK 0x0008 /* MICB3_RATE */
  1733. #define ARIZONA_MICB3_RATE_SHIFT 3 /* MICB3_RATE */
  1734. #define ARIZONA_MICB3_RATE_WIDTH 1 /* MICB3_RATE */
  1735. #define ARIZONA_MICB3_DISCH 0x0004 /* MICB3_DISCH */
  1736. #define ARIZONA_MICB3_DISCH_MASK 0x0004 /* MICB3_DISCH */
  1737. #define ARIZONA_MICB3_DISCH_SHIFT 2 /* MICB3_DISCH */
  1738. #define ARIZONA_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */
  1739. #define ARIZONA_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */
  1740. #define ARIZONA_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */
  1741. #define ARIZONA_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */
  1742. #define ARIZONA_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */
  1743. #define ARIZONA_MICB3_ENA 0x0001 /* MICB3_ENA */
  1744. #define ARIZONA_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */
  1745. #define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */
  1746. #define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */
  1747. /*
  1748. * R659 (0x293) - Accessory Detect Mode 1
  1749. */
  1750. #define ARIZONA_ACCDET_SRC 0x2000 /* ACCDET_SRC */
  1751. #define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
  1752. #define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */
  1753. #define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */
  1754. #define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */
  1755. #define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */
  1756. #define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */
  1757. /*
  1758. * R667 (0x29B) - Headphone Detect 1
  1759. */
  1760. #define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */
  1761. #define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */
  1762. #define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */
  1763. #define ARIZONA_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
  1764. #define ARIZONA_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
  1765. #define ARIZONA_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
  1766. #define ARIZONA_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
  1767. #define ARIZONA_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
  1768. #define ARIZONA_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
  1769. #define ARIZONA_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
  1770. #define ARIZONA_HP_IDAC_STEER 0x0004 /* HP_IDAC_STEER */
  1771. #define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */
  1772. #define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */
  1773. #define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */
  1774. #define ARIZONA_HP_RATE 0x0002 /* HP_RATE */
  1775. #define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */
  1776. #define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */
  1777. #define ARIZONA_HP_RATE_WIDTH 1 /* HP_RATE */
  1778. #define ARIZONA_HP_POLL 0x0001 /* HP_POLL */
  1779. #define ARIZONA_HP_POLL_MASK 0x0001 /* HP_POLL */
  1780. #define ARIZONA_HP_POLL_SHIFT 0 /* HP_POLL */
  1781. #define ARIZONA_HP_POLL_WIDTH 1 /* HP_POLL */
  1782. /*
  1783. * R668 (0x29C) - Headphone Detect 2
  1784. */
  1785. #define ARIZONA_HP_DONE 0x0080 /* HP_DONE */
  1786. #define ARIZONA_HP_DONE_MASK 0x0080 /* HP_DONE */
  1787. #define ARIZONA_HP_DONE_SHIFT 7 /* HP_DONE */
  1788. #define ARIZONA_HP_DONE_WIDTH 1 /* HP_DONE */
  1789. #define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
  1790. #define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
  1791. #define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
  1792. /*
  1793. * R675 (0x2A3) - Mic Detect 1
  1794. */
  1795. #define ARIZONA_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
  1796. #define ARIZONA_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
  1797. #define ARIZONA_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
  1798. #define ARIZONA_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
  1799. #define ARIZONA_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
  1800. #define ARIZONA_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
  1801. #define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */
  1802. #define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */
  1803. #define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */
  1804. #define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */
  1805. #define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
  1806. #define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
  1807. #define ARIZONA_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
  1808. #define ARIZONA_MICD_ENA 0x0001 /* MICD_ENA */
  1809. #define ARIZONA_MICD_ENA_MASK 0x0001 /* MICD_ENA */
  1810. #define ARIZONA_MICD_ENA_SHIFT 0 /* MICD_ENA */
  1811. #define ARIZONA_MICD_ENA_WIDTH 1 /* MICD_ENA */
  1812. /*
  1813. * R676 (0x2A4) - Mic Detect 2
  1814. */
  1815. #define ARIZONA_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
  1816. #define ARIZONA_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
  1817. #define ARIZONA_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
  1818. /*
  1819. * R677 (0x2A5) - Mic Detect 3
  1820. */
  1821. #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
  1822. #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
  1823. #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
  1824. #define ARIZONA_MICD_VALID 0x0002 /* MICD_VALID */
  1825. #define ARIZONA_MICD_VALID_MASK 0x0002 /* MICD_VALID */
  1826. #define ARIZONA_MICD_VALID_SHIFT 1 /* MICD_VALID */
  1827. #define ARIZONA_MICD_VALID_WIDTH 1 /* MICD_VALID */
  1828. #define ARIZONA_MICD_STS 0x0001 /* MICD_STS */
  1829. #define ARIZONA_MICD_STS_MASK 0x0001 /* MICD_STS */
  1830. #define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */
  1831. #define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */
  1832. /*
  1833. * R707 (0x2C3) - Mic noise mix control 1
  1834. */
  1835. #define ARIZONA_MICMUTE_RATE_MASK 0x7800 /* MICMUTE_RATE - [14:11] */
  1836. #define ARIZONA_MICMUTE_RATE_SHIFT 11 /* MICMUTE_RATE - [14:11] */
  1837. #define ARIZONA_MICMUTE_RATE_WIDTH 4 /* MICMUTE_RATE - [14:11] */
  1838. #define ARIZONA_MICMUTE_MIX_ENA 0x0040 /* MICMUTE_MIX_ENA */
  1839. #define ARIZONA_MICMUTE_MIX_ENA_MASK 0x0040 /* MICMUTE_MIX_ENA */
  1840. #define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */
  1841. #define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */
  1842. /*
  1843. * R715 (0x2CB) - Isolation control
  1844. */
  1845. #define ARIZONA_ISOLATE_DCVDD1 0x0001 /* ISOLATE_DCVDD1 */
  1846. #define ARIZONA_ISOLATE_DCVDD1_MASK 0x0001 /* ISOLATE_DCVDD1 */
  1847. #define ARIZONA_ISOLATE_DCVDD1_SHIFT 0 /* ISOLATE_DCVDD1 */
  1848. #define ARIZONA_ISOLATE_DCVDD1_WIDTH 1 /* ISOLATE_DCVDD1 */
  1849. /*
  1850. * R723 (0x2D3) - Jack detect analogue
  1851. */
  1852. #define ARIZONA_JD2_ENA 0x0002 /* JD2_ENA */
  1853. #define ARIZONA_JD2_ENA_MASK 0x0002 /* JD2_ENA */
  1854. #define ARIZONA_JD2_ENA_SHIFT 1 /* JD2_ENA */
  1855. #define ARIZONA_JD2_ENA_WIDTH 1 /* JD2_ENA */
  1856. #define ARIZONA_JD1_ENA 0x0001 /* JD1_ENA */
  1857. #define ARIZONA_JD1_ENA_MASK 0x0001 /* JD1_ENA */
  1858. #define ARIZONA_JD1_ENA_SHIFT 0 /* JD1_ENA */
  1859. #define ARIZONA_JD1_ENA_WIDTH 1 /* JD1_ENA */
  1860. /*
  1861. * R768 (0x300) - Input Enables
  1862. */
  1863. #define ARIZONA_IN3L_ENA 0x0020 /* IN3L_ENA */
  1864. #define ARIZONA_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
  1865. #define ARIZONA_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
  1866. #define ARIZONA_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
  1867. #define ARIZONA_IN3R_ENA 0x0010 /* IN3R_ENA */
  1868. #define ARIZONA_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
  1869. #define ARIZONA_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
  1870. #define ARIZONA_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
  1871. #define ARIZONA_IN2L_ENA 0x0008 /* IN2L_ENA */
  1872. #define ARIZONA_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
  1873. #define ARIZONA_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
  1874. #define ARIZONA_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
  1875. #define ARIZONA_IN2R_ENA 0x0004 /* IN2R_ENA */
  1876. #define ARIZONA_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
  1877. #define ARIZONA_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
  1878. #define ARIZONA_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
  1879. #define ARIZONA_IN1L_ENA 0x0002 /* IN1L_ENA */
  1880. #define ARIZONA_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
  1881. #define ARIZONA_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
  1882. #define ARIZONA_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
  1883. #define ARIZONA_IN1R_ENA 0x0001 /* IN1R_ENA */
  1884. #define ARIZONA_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
  1885. #define ARIZONA_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
  1886. #define ARIZONA_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
  1887. /*
  1888. * R776 (0x308) - Input Rate
  1889. */
  1890. #define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */
  1891. #define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */
  1892. #define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */
  1893. /*
  1894. * R777 (0x309) - Input Volume Ramp
  1895. */
  1896. #define ARIZONA_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
  1897. #define ARIZONA_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
  1898. #define ARIZONA_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
  1899. #define ARIZONA_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
  1900. #define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
  1901. #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
  1902. /*
  1903. * R784 (0x310) - IN1L Control
  1904. */
  1905. #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */
  1906. #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */
  1907. #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */
  1908. #define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
  1909. #define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
  1910. #define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
  1911. #define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
  1912. #define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
  1913. #define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
  1914. #define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
  1915. #define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
  1916. #define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
  1917. /*
  1918. * R785 (0x311) - ADC Digital Volume 1L
  1919. */
  1920. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  1921. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  1922. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  1923. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  1924. #define ARIZONA_IN1L_MUTE 0x0100 /* IN1L_MUTE */
  1925. #define ARIZONA_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
  1926. #define ARIZONA_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
  1927. #define ARIZONA_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
  1928. #define ARIZONA_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
  1929. #define ARIZONA_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
  1930. #define ARIZONA_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
  1931. /*
  1932. * R786 (0x312) - DMIC1L Control
  1933. */
  1934. #define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */
  1935. #define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */
  1936. #define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */
  1937. /*
  1938. * R788 (0x314) - IN1R Control
  1939. */
  1940. #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
  1941. #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
  1942. #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
  1943. /*
  1944. * R789 (0x315) - ADC Digital Volume 1R
  1945. */
  1946. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  1947. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  1948. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  1949. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  1950. #define ARIZONA_IN1R_MUTE 0x0100 /* IN1R_MUTE */
  1951. #define ARIZONA_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
  1952. #define ARIZONA_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
  1953. #define ARIZONA_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
  1954. #define ARIZONA_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
  1955. #define ARIZONA_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
  1956. #define ARIZONA_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
  1957. /*
  1958. * R790 (0x316) - DMIC1R Control
  1959. */
  1960. #define ARIZONA_IN1_DMICR_DLY_MASK 0x003F /* IN1_DMICR_DLY - [5:0] */
  1961. #define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */
  1962. #define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */
  1963. /*
  1964. * R792 (0x318) - IN2L Control
  1965. */
  1966. #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */
  1967. #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */
  1968. #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */
  1969. #define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
  1970. #define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
  1971. #define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
  1972. #define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
  1973. #define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
  1974. #define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
  1975. #define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
  1976. #define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
  1977. #define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
  1978. /*
  1979. * R793 (0x319) - ADC Digital Volume 2L
  1980. */
  1981. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  1982. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  1983. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  1984. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  1985. #define ARIZONA_IN2L_MUTE 0x0100 /* IN2L_MUTE */
  1986. #define ARIZONA_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
  1987. #define ARIZONA_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
  1988. #define ARIZONA_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
  1989. #define ARIZONA_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
  1990. #define ARIZONA_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
  1991. #define ARIZONA_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
  1992. /*
  1993. * R794 (0x31A) - DMIC2L Control
  1994. */
  1995. #define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */
  1996. #define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */
  1997. #define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */
  1998. /*
  1999. * R796 (0x31C) - IN2R Control
  2000. */
  2001. #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
  2002. #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
  2003. #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
  2004. /*
  2005. * R797 (0x31D) - ADC Digital Volume 2R
  2006. */
  2007. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2008. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2009. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2010. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2011. #define ARIZONA_IN2R_MUTE 0x0100 /* IN2R_MUTE */
  2012. #define ARIZONA_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
  2013. #define ARIZONA_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
  2014. #define ARIZONA_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
  2015. #define ARIZONA_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
  2016. #define ARIZONA_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
  2017. #define ARIZONA_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
  2018. /*
  2019. * R798 (0x31E) - DMIC2R Control
  2020. */
  2021. #define ARIZONA_IN2_DMICR_DLY_MASK 0x003F /* IN2_DMICR_DLY - [5:0] */
  2022. #define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */
  2023. #define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */
  2024. /*
  2025. * R800 (0x320) - IN3L Control
  2026. */
  2027. #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */
  2028. #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */
  2029. #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */
  2030. #define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
  2031. #define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
  2032. #define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
  2033. #define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
  2034. #define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
  2035. #define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
  2036. #define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
  2037. #define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
  2038. #define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
  2039. /*
  2040. * R801 (0x321) - ADC Digital Volume 3L
  2041. */
  2042. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2043. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2044. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2045. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2046. #define ARIZONA_IN3L_MUTE 0x0100 /* IN3L_MUTE */
  2047. #define ARIZONA_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
  2048. #define ARIZONA_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
  2049. #define ARIZONA_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
  2050. #define ARIZONA_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
  2051. #define ARIZONA_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
  2052. #define ARIZONA_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
  2053. /*
  2054. * R802 (0x322) - DMIC3L Control
  2055. */
  2056. #define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */
  2057. #define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */
  2058. #define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */
  2059. /*
  2060. * R804 (0x324) - IN3R Control
  2061. */
  2062. #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
  2063. #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
  2064. #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
  2065. /*
  2066. * R805 (0x325) - ADC Digital Volume 3R
  2067. */
  2068. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2069. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2070. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2071. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2072. #define ARIZONA_IN3R_MUTE 0x0100 /* IN3R_MUTE */
  2073. #define ARIZONA_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
  2074. #define ARIZONA_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
  2075. #define ARIZONA_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
  2076. #define ARIZONA_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
  2077. #define ARIZONA_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
  2078. #define ARIZONA_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
  2079. /*
  2080. * R806 (0x326) - DMIC3R Control
  2081. */
  2082. #define ARIZONA_IN3_DMICR_DLY_MASK 0x003F /* IN3_DMICR_DLY - [5:0] */
  2083. #define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */
  2084. #define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */
  2085. /*
  2086. * R1024 (0x400) - Output Enables 1
  2087. */
  2088. #define ARIZONA_OUT5L_ENA 0x0200 /* OUT5L_ENA */
  2089. #define ARIZONA_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */
  2090. #define ARIZONA_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */
  2091. #define ARIZONA_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */
  2092. #define ARIZONA_OUT5R_ENA 0x0100 /* OUT5R_ENA */
  2093. #define ARIZONA_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */
  2094. #define ARIZONA_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */
  2095. #define ARIZONA_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */
  2096. #define ARIZONA_OUT4L_ENA 0x0080 /* OUT4L_ENA */
  2097. #define ARIZONA_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */
  2098. #define ARIZONA_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */
  2099. #define ARIZONA_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */
  2100. #define ARIZONA_OUT4R_ENA 0x0040 /* OUT4R_ENA */
  2101. #define ARIZONA_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */
  2102. #define ARIZONA_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */
  2103. #define ARIZONA_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */
  2104. #define ARIZONA_OUT3L_ENA 0x0020 /* OUT3L_ENA */
  2105. #define ARIZONA_OUT3L_ENA_MASK 0x0020 /* OUT3L_ENA */
  2106. #define ARIZONA_OUT3L_ENA_SHIFT 5 /* OUT3L_ENA */
  2107. #define ARIZONA_OUT3L_ENA_WIDTH 1 /* OUT3L_ENA */
  2108. #define ARIZONA_OUT3R_ENA 0x0010 /* OUT3R_ENA */
  2109. #define ARIZONA_OUT3R_ENA_MASK 0x0010 /* OUT3R_ENA */
  2110. #define ARIZONA_OUT3R_ENA_SHIFT 4 /* OUT3R_ENA */
  2111. #define ARIZONA_OUT3R_ENA_WIDTH 1 /* OUT3R_ENA */
  2112. #define ARIZONA_OUT2L_ENA 0x0008 /* OUT2L_ENA */
  2113. #define ARIZONA_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
  2114. #define ARIZONA_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */
  2115. #define ARIZONA_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */
  2116. #define ARIZONA_OUT2R_ENA 0x0004 /* OUT2R_ENA */
  2117. #define ARIZONA_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
  2118. #define ARIZONA_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */
  2119. #define ARIZONA_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */
  2120. #define ARIZONA_OUT1L_ENA 0x0002 /* OUT1L_ENA */
  2121. #define ARIZONA_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
  2122. #define ARIZONA_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */
  2123. #define ARIZONA_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */
  2124. #define ARIZONA_OUT1R_ENA 0x0001 /* OUT1R_ENA */
  2125. #define ARIZONA_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
  2126. #define ARIZONA_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
  2127. #define ARIZONA_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */
  2128. /*
  2129. * R1025 (0x401) - Output Status 1
  2130. */
  2131. #define ARIZONA_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */
  2132. #define ARIZONA_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */
  2133. #define ARIZONA_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */
  2134. #define ARIZONA_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */
  2135. #define ARIZONA_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */
  2136. #define ARIZONA_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */
  2137. #define ARIZONA_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */
  2138. #define ARIZONA_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */
  2139. #define ARIZONA_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */
  2140. #define ARIZONA_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */
  2141. #define ARIZONA_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */
  2142. #define ARIZONA_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */
  2143. #define ARIZONA_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */
  2144. #define ARIZONA_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */
  2145. #define ARIZONA_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */
  2146. #define ARIZONA_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */
  2147. #define ARIZONA_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */
  2148. #define ARIZONA_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */
  2149. #define ARIZONA_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */
  2150. #define ARIZONA_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */
  2151. #define ARIZONA_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */
  2152. #define ARIZONA_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */
  2153. #define ARIZONA_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */
  2154. #define ARIZONA_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */
  2155. /*
  2156. * R1032 (0x408) - Output Rate 1
  2157. */
  2158. #define ARIZONA_OUT_RATE_MASK 0x7800 /* OUT_RATE - [14:11] */
  2159. #define ARIZONA_OUT_RATE_SHIFT 11 /* OUT_RATE - [14:11] */
  2160. #define ARIZONA_OUT_RATE_WIDTH 4 /* OUT_RATE - [14:11] */
  2161. /*
  2162. * R1033 (0x409) - Output Volume Ramp
  2163. */
  2164. #define ARIZONA_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
  2165. #define ARIZONA_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
  2166. #define ARIZONA_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
  2167. #define ARIZONA_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
  2168. #define ARIZONA_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
  2169. #define ARIZONA_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
  2170. /*
  2171. * R1040 (0x410) - Output Path Config 1L
  2172. */
  2173. #define ARIZONA_OUT1_LP_MODE 0x8000 /* OUT1_LP_MODE */
  2174. #define ARIZONA_OUT1_LP_MODE_MASK 0x8000 /* OUT1_LP_MODE */
  2175. #define ARIZONA_OUT1_LP_MODE_SHIFT 15 /* OUT1_LP_MODE */
  2176. #define ARIZONA_OUT1_LP_MODE_WIDTH 1 /* OUT1_LP_MODE */
  2177. #define ARIZONA_OUT1_OSR 0x2000 /* OUT1_OSR */
  2178. #define ARIZONA_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
  2179. #define ARIZONA_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
  2180. #define ARIZONA_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
  2181. #define ARIZONA_OUT1_MONO 0x1000 /* OUT1_MONO */
  2182. #define ARIZONA_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */
  2183. #define ARIZONA_OUT1_MONO_SHIFT 12 /* OUT1_MONO */
  2184. #define ARIZONA_OUT1_MONO_WIDTH 1 /* OUT1_MONO */
  2185. #define ARIZONA_OUT1L_ANC_SRC_MASK 0x0C00 /* OUT1L_ANC_SRC - [11:10] */
  2186. #define ARIZONA_OUT1L_ANC_SRC_SHIFT 10 /* OUT1L_ANC_SRC - [11:10] */
  2187. #define ARIZONA_OUT1L_ANC_SRC_WIDTH 2 /* OUT1L_ANC_SRC - [11:10] */
  2188. #define ARIZONA_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
  2189. #define ARIZONA_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
  2190. #define ARIZONA_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
  2191. /*
  2192. * R1041 (0x411) - DAC Digital Volume 1L
  2193. */
  2194. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2195. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2196. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2197. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2198. #define ARIZONA_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
  2199. #define ARIZONA_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
  2200. #define ARIZONA_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
  2201. #define ARIZONA_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
  2202. #define ARIZONA_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
  2203. #define ARIZONA_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
  2204. #define ARIZONA_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
  2205. /*
  2206. * R1042 (0x412) - DAC Volume Limit 1L
  2207. */
  2208. #define ARIZONA_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */
  2209. #define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */
  2210. #define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */
  2211. /*
  2212. * R1043 (0x413) - Noise Gate Select 1L
  2213. */
  2214. #define ARIZONA_OUT1L_NGATE_SRC_MASK 0x0FFF /* OUT1L_NGATE_SRC - [11:0] */
  2215. #define ARIZONA_OUT1L_NGATE_SRC_SHIFT 0 /* OUT1L_NGATE_SRC - [11:0] */
  2216. #define ARIZONA_OUT1L_NGATE_SRC_WIDTH 12 /* OUT1L_NGATE_SRC - [11:0] */
  2217. /*
  2218. * R1044 (0x414) - Output Path Config 1R
  2219. */
  2220. #define ARIZONA_OUT1R_ANC_SRC_MASK 0x0C00 /* OUT1R_ANC_SRC - [11:10] */
  2221. #define ARIZONA_OUT1R_ANC_SRC_SHIFT 10 /* OUT1R_ANC_SRC - [11:10] */
  2222. #define ARIZONA_OUT1R_ANC_SRC_WIDTH 2 /* OUT1R_ANC_SRC - [11:10] */
  2223. #define ARIZONA_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
  2224. #define ARIZONA_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
  2225. #define ARIZONA_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
  2226. /*
  2227. * R1045 (0x415) - DAC Digital Volume 1R
  2228. */
  2229. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2230. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2231. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2232. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2233. #define ARIZONA_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
  2234. #define ARIZONA_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
  2235. #define ARIZONA_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
  2236. #define ARIZONA_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
  2237. #define ARIZONA_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
  2238. #define ARIZONA_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
  2239. #define ARIZONA_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
  2240. /*
  2241. * R1046 (0x416) - DAC Volume Limit 1R
  2242. */
  2243. #define ARIZONA_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */
  2244. #define ARIZONA_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */
  2245. #define ARIZONA_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */
  2246. /*
  2247. * R1047 (0x417) - Noise Gate Select 1R
  2248. */
  2249. #define ARIZONA_OUT1R_NGATE_SRC_MASK 0x0FFF /* OUT1R_NGATE_SRC - [11:0] */
  2250. #define ARIZONA_OUT1R_NGATE_SRC_SHIFT 0 /* OUT1R_NGATE_SRC - [11:0] */
  2251. #define ARIZONA_OUT1R_NGATE_SRC_WIDTH 12 /* OUT1R_NGATE_SRC - [11:0] */
  2252. /*
  2253. * R1048 (0x418) - Output Path Config 2L
  2254. */
  2255. #define ARIZONA_OUT2_LP_MODE 0x8000 /* OUT2_LP_MODE */
  2256. #define ARIZONA_OUT2_LP_MODE_MASK 0x8000 /* OUT2_LP_MODE */
  2257. #define ARIZONA_OUT2_LP_MODE_SHIFT 15 /* OUT2_LP_MODE */
  2258. #define ARIZONA_OUT2_LP_MODE_WIDTH 1 /* OUT2_LP_MODE */
  2259. #define ARIZONA_OUT2_OSR 0x2000 /* OUT2_OSR */
  2260. #define ARIZONA_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
  2261. #define ARIZONA_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
  2262. #define ARIZONA_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
  2263. #define ARIZONA_OUT2_MONO 0x1000 /* OUT2_MONO */
  2264. #define ARIZONA_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */
  2265. #define ARIZONA_OUT2_MONO_SHIFT 12 /* OUT2_MONO */
  2266. #define ARIZONA_OUT2_MONO_WIDTH 1 /* OUT2_MONO */
  2267. #define ARIZONA_OUT2L_ANC_SRC_MASK 0x0C00 /* OUT2L_ANC_SRC - [11:10] */
  2268. #define ARIZONA_OUT2L_ANC_SRC_SHIFT 10 /* OUT2L_ANC_SRC - [11:10] */
  2269. #define ARIZONA_OUT2L_ANC_SRC_WIDTH 2 /* OUT2L_ANC_SRC - [11:10] */
  2270. #define ARIZONA_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */
  2271. #define ARIZONA_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */
  2272. #define ARIZONA_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */
  2273. /*
  2274. * R1049 (0x419) - DAC Digital Volume 2L
  2275. */
  2276. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2277. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2278. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2279. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2280. #define ARIZONA_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
  2281. #define ARIZONA_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
  2282. #define ARIZONA_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
  2283. #define ARIZONA_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
  2284. #define ARIZONA_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
  2285. #define ARIZONA_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
  2286. #define ARIZONA_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
  2287. /*
  2288. * R1050 (0x41A) - DAC Volume Limit 2L
  2289. */
  2290. #define ARIZONA_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */
  2291. #define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */
  2292. #define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */
  2293. /*
  2294. * R1051 (0x41B) - Noise Gate Select 2L
  2295. */
  2296. #define ARIZONA_OUT2L_NGATE_SRC_MASK 0x0FFF /* OUT2L_NGATE_SRC - [11:0] */
  2297. #define ARIZONA_OUT2L_NGATE_SRC_SHIFT 0 /* OUT2L_NGATE_SRC - [11:0] */
  2298. #define ARIZONA_OUT2L_NGATE_SRC_WIDTH 12 /* OUT2L_NGATE_SRC - [11:0] */
  2299. /*
  2300. * R1052 (0x41C) - Output Path Config 2R
  2301. */
  2302. #define ARIZONA_OUT2R_ANC_SRC_MASK 0x0C00 /* OUT2R_ANC_SRC - [11:10] */
  2303. #define ARIZONA_OUT2R_ANC_SRC_SHIFT 10 /* OUT2R_ANC_SRC - [11:10] */
  2304. #define ARIZONA_OUT2R_ANC_SRC_WIDTH 2 /* OUT2R_ANC_SRC - [11:10] */
  2305. #define ARIZONA_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */
  2306. #define ARIZONA_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */
  2307. #define ARIZONA_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */
  2308. /*
  2309. * R1053 (0x41D) - DAC Digital Volume 2R
  2310. */
  2311. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2312. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2313. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2314. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2315. #define ARIZONA_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
  2316. #define ARIZONA_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
  2317. #define ARIZONA_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
  2318. #define ARIZONA_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
  2319. #define ARIZONA_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
  2320. #define ARIZONA_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
  2321. #define ARIZONA_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
  2322. /*
  2323. * R1054 (0x41E) - DAC Volume Limit 2R
  2324. */
  2325. #define ARIZONA_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */
  2326. #define ARIZONA_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */
  2327. #define ARIZONA_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */
  2328. /*
  2329. * R1055 (0x41F) - Noise Gate Select 2R
  2330. */
  2331. #define ARIZONA_OUT2R_NGATE_SRC_MASK 0x0FFF /* OUT2R_NGATE_SRC - [11:0] */
  2332. #define ARIZONA_OUT2R_NGATE_SRC_SHIFT 0 /* OUT2R_NGATE_SRC - [11:0] */
  2333. #define ARIZONA_OUT2R_NGATE_SRC_WIDTH 12 /* OUT2R_NGATE_SRC - [11:0] */
  2334. /*
  2335. * R1056 (0x420) - Output Path Config 3L
  2336. */
  2337. #define ARIZONA_OUT3_LP_MODE 0x8000 /* OUT3_LP_MODE */
  2338. #define ARIZONA_OUT3_LP_MODE_MASK 0x8000 /* OUT3_LP_MODE */
  2339. #define ARIZONA_OUT3_LP_MODE_SHIFT 15 /* OUT3_LP_MODE */
  2340. #define ARIZONA_OUT3_LP_MODE_WIDTH 1 /* OUT3_LP_MODE */
  2341. #define ARIZONA_OUT3_OSR 0x2000 /* OUT3_OSR */
  2342. #define ARIZONA_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
  2343. #define ARIZONA_OUT3_OSR_SHIFT 13 /* OUT3_OSR */
  2344. #define ARIZONA_OUT3_OSR_WIDTH 1 /* OUT3_OSR */
  2345. #define ARIZONA_OUT3_MONO 0x1000 /* OUT3_MONO */
  2346. #define ARIZONA_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */
  2347. #define ARIZONA_OUT3_MONO_SHIFT 12 /* OUT3_MONO */
  2348. #define ARIZONA_OUT3_MONO_WIDTH 1 /* OUT3_MONO */
  2349. #define ARIZONA_OUT3L_ANC_SRC_MASK 0x0C00 /* OUT3L_ANC_SRC - [11:10] */
  2350. #define ARIZONA_OUT3L_ANC_SRC_SHIFT 10 /* OUT3L_ANC_SRC - [11:10] */
  2351. #define ARIZONA_OUT3L_ANC_SRC_WIDTH 2 /* OUT3L_ANC_SRC - [11:10] */
  2352. #define ARIZONA_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */
  2353. #define ARIZONA_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */
  2354. #define ARIZONA_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */
  2355. /*
  2356. * R1057 (0x421) - DAC Digital Volume 3L
  2357. */
  2358. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2359. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2360. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2361. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2362. #define ARIZONA_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */
  2363. #define ARIZONA_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */
  2364. #define ARIZONA_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */
  2365. #define ARIZONA_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */
  2366. #define ARIZONA_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */
  2367. #define ARIZONA_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */
  2368. #define ARIZONA_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */
  2369. /*
  2370. * R1058 (0x422) - DAC Volume Limit 3L
  2371. */
  2372. #define ARIZONA_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */
  2373. #define ARIZONA_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */
  2374. #define ARIZONA_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */
  2375. /*
  2376. * R1059 (0x423) - Noise Gate Select 3L
  2377. */
  2378. #define ARIZONA_OUT3_NGATE_SRC_MASK 0x0FFF /* OUT3_NGATE_SRC - [11:0] */
  2379. #define ARIZONA_OUT3_NGATE_SRC_SHIFT 0 /* OUT3_NGATE_SRC - [11:0] */
  2380. #define ARIZONA_OUT3_NGATE_SRC_WIDTH 12 /* OUT3_NGATE_SRC - [11:0] */
  2381. /*
  2382. * R1060 (0x424) - Output Path Config 3R
  2383. */
  2384. #define ARIZONA_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */
  2385. #define ARIZONA_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */
  2386. #define ARIZONA_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */
  2387. /*
  2388. * R1061 (0x425) - DAC Digital Volume 3R
  2389. */
  2390. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2391. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2392. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2393. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2394. #define ARIZONA_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */
  2395. #define ARIZONA_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */
  2396. #define ARIZONA_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */
  2397. #define ARIZONA_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */
  2398. #define ARIZONA_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */
  2399. #define ARIZONA_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */
  2400. #define ARIZONA_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */
  2401. /*
  2402. * R1062 (0x426) - DAC Volume Limit 3R
  2403. */
  2404. #define ARIZONA_OUT3R_ANC_SRC_MASK 0x0C00 /* OUT3R_ANC_SRC - [11:10] */
  2405. #define ARIZONA_OUT3R_ANC_SRC_SHIFT 10 /* OUT3R_ANC_SRC - [11:10] */
  2406. #define ARIZONA_OUT3R_ANC_SRC_WIDTH 2 /* OUT3R_ANC_SRC - [11:10] */
  2407. #define ARIZONA_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */
  2408. #define ARIZONA_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */
  2409. #define ARIZONA_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */
  2410. /*
  2411. * R1064 (0x428) - Output Path Config 4L
  2412. */
  2413. #define ARIZONA_OUT4_OSR 0x2000 /* OUT4_OSR */
  2414. #define ARIZONA_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
  2415. #define ARIZONA_OUT4_OSR_SHIFT 13 /* OUT4_OSR */
  2416. #define ARIZONA_OUT4_OSR_WIDTH 1 /* OUT4_OSR */
  2417. #define ARIZONA_OUT4L_ANC_SRC_MASK 0x0C00 /* OUT4L_ANC_SRC - [11:10] */
  2418. #define ARIZONA_OUT4L_ANC_SRC_SHIFT 10 /* OUT4L_ANC_SRC - [11:10] */
  2419. #define ARIZONA_OUT4L_ANC_SRC_WIDTH 2 /* OUT4L_ANC_SRC - [11:10] */
  2420. /*
  2421. * R1065 (0x429) - DAC Digital Volume 4L
  2422. */
  2423. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2424. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2425. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2426. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2427. #define ARIZONA_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */
  2428. #define ARIZONA_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */
  2429. #define ARIZONA_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */
  2430. #define ARIZONA_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */
  2431. #define ARIZONA_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */
  2432. #define ARIZONA_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */
  2433. #define ARIZONA_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */
  2434. /*
  2435. * R1066 (0x42A) - Out Volume 4L
  2436. */
  2437. #define ARIZONA_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */
  2438. #define ARIZONA_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */
  2439. #define ARIZONA_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */
  2440. /*
  2441. * R1067 (0x42B) - Noise Gate Select 4L
  2442. */
  2443. #define ARIZONA_OUT4L_NGATE_SRC_MASK 0x0FFF /* OUT4L_NGATE_SRC - [11:0] */
  2444. #define ARIZONA_OUT4L_NGATE_SRC_SHIFT 0 /* OUT4L_NGATE_SRC - [11:0] */
  2445. #define ARIZONA_OUT4L_NGATE_SRC_WIDTH 12 /* OUT4L_NGATE_SRC - [11:0] */
  2446. /*
  2447. * R1068 (0x42C) - Output Path Config 4R
  2448. */
  2449. #define ARIZONA_OUT4R_ANC_SRC_MASK 0x0C00 /* OUT4R_ANC_SRC - [11:10] */
  2450. #define ARIZONA_OUT4R_ANC_SRC_SHIFT 10 /* OUT4R_ANC_SRC - [11:10] */
  2451. #define ARIZONA_OUT4R_ANC_SRC_WIDTH 2 /* OUT4R_ANC_SRC - [11:10] */
  2452. /*
  2453. * R1069 (0x42D) - DAC Digital Volume 4R
  2454. */
  2455. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2456. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2457. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2458. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2459. #define ARIZONA_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */
  2460. #define ARIZONA_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */
  2461. #define ARIZONA_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */
  2462. #define ARIZONA_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */
  2463. #define ARIZONA_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */
  2464. #define ARIZONA_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */
  2465. #define ARIZONA_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */
  2466. /*
  2467. * R1070 (0x42E) - Out Volume 4R
  2468. */
  2469. #define ARIZONA_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */
  2470. #define ARIZONA_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */
  2471. #define ARIZONA_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */
  2472. /*
  2473. * R1071 (0x42F) - Noise Gate Select 4R
  2474. */
  2475. #define ARIZONA_OUT4R_NGATE_SRC_MASK 0x0FFF /* OUT4R_NGATE_SRC - [11:0] */
  2476. #define ARIZONA_OUT4R_NGATE_SRC_SHIFT 0 /* OUT4R_NGATE_SRC - [11:0] */
  2477. #define ARIZONA_OUT4R_NGATE_SRC_WIDTH 12 /* OUT4R_NGATE_SRC - [11:0] */
  2478. /*
  2479. * R1072 (0x430) - Output Path Config 5L
  2480. */
  2481. #define ARIZONA_OUT5_OSR 0x2000 /* OUT5_OSR */
  2482. #define ARIZONA_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
  2483. #define ARIZONA_OUT5_OSR_SHIFT 13 /* OUT5_OSR */
  2484. #define ARIZONA_OUT5_OSR_WIDTH 1 /* OUT5_OSR */
  2485. #define ARIZONA_OUT5L_ANC_SRC_MASK 0x0C00 /* OUT5L_ANC_SRC - [11:10] */
  2486. #define ARIZONA_OUT5L_ANC_SRC_SHIFT 10 /* OUT5L_ANC_SRC - [11:10] */
  2487. #define ARIZONA_OUT5L_ANC_SRC_WIDTH 2 /* OUT5L_ANC_SRC - [11:10] */
  2488. /*
  2489. * R1073 (0x431) - DAC Digital Volume 5L
  2490. */
  2491. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2492. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2493. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2494. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2495. #define ARIZONA_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */
  2496. #define ARIZONA_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */
  2497. #define ARIZONA_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */
  2498. #define ARIZONA_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */
  2499. #define ARIZONA_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */
  2500. #define ARIZONA_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */
  2501. #define ARIZONA_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */
  2502. /*
  2503. * R1074 (0x432) - DAC Volume Limit 5L
  2504. */
  2505. #define ARIZONA_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */
  2506. #define ARIZONA_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */
  2507. #define ARIZONA_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */
  2508. /*
  2509. * R1075 (0x433) - Noise Gate Select 5L
  2510. */
  2511. #define ARIZONA_OUT5L_NGATE_SRC_MASK 0x0FFF /* OUT5L_NGATE_SRC - [11:0] */
  2512. #define ARIZONA_OUT5L_NGATE_SRC_SHIFT 0 /* OUT5L_NGATE_SRC - [11:0] */
  2513. #define ARIZONA_OUT5L_NGATE_SRC_WIDTH 12 /* OUT5L_NGATE_SRC - [11:0] */
  2514. /*
  2515. * R1076 (0x434) - Output Path Config 5R
  2516. */
  2517. #define ARIZONA_OUT5R_ANC_SRC_MASK 0x0C00 /* OUT5R_ANC_SRC - [11:10] */
  2518. #define ARIZONA_OUT5R_ANC_SRC_SHIFT 10 /* OUT5R_ANC_SRC - [11:10] */
  2519. #define ARIZONA_OUT5R_ANC_SRC_WIDTH 2 /* OUT5R_ANC_SRC - [11:10] */
  2520. /*
  2521. * R1077 (0x435) - DAC Digital Volume 5R
  2522. */
  2523. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2524. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2525. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2526. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2527. #define ARIZONA_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */
  2528. #define ARIZONA_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */
  2529. #define ARIZONA_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */
  2530. #define ARIZONA_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */
  2531. #define ARIZONA_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */
  2532. #define ARIZONA_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */
  2533. #define ARIZONA_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */
  2534. /*
  2535. * R1078 (0x436) - DAC Volume Limit 5R
  2536. */
  2537. #define ARIZONA_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */
  2538. #define ARIZONA_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */
  2539. #define ARIZONA_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */
  2540. /*
  2541. * R1079 (0x437) - Noise Gate Select 5R
  2542. */
  2543. #define ARIZONA_OUT5R_NGATE_SRC_MASK 0x0FFF /* OUT5R_NGATE_SRC - [11:0] */
  2544. #define ARIZONA_OUT5R_NGATE_SRC_SHIFT 0 /* OUT5R_NGATE_SRC - [11:0] */
  2545. #define ARIZONA_OUT5R_NGATE_SRC_WIDTH 12 /* OUT5R_NGATE_SRC - [11:0] */
  2546. /*
  2547. * R1104 (0x450) - DAC AEC Control 1
  2548. */
  2549. #define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
  2550. #define ARIZONA_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */
  2551. #define ARIZONA_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */
  2552. #define ARIZONA_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */
  2553. #define ARIZONA_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */
  2554. #define ARIZONA_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */
  2555. #define ARIZONA_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */
  2556. #define ARIZONA_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */
  2557. #define ARIZONA_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */
  2558. #define ARIZONA_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */
  2559. #define ARIZONA_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
  2560. /*
  2561. * R1112 (0x458) - Noise Gate Control
  2562. */
  2563. #define ARIZONA_NGATE_HOLD_MASK 0x0030 /* NGATE_HOLD - [5:4] */
  2564. #define ARIZONA_NGATE_HOLD_SHIFT 4 /* NGATE_HOLD - [5:4] */
  2565. #define ARIZONA_NGATE_HOLD_WIDTH 2 /* NGATE_HOLD - [5:4] */
  2566. #define ARIZONA_NGATE_THR_MASK 0x000E /* NGATE_THR - [3:1] */
  2567. #define ARIZONA_NGATE_THR_SHIFT 1 /* NGATE_THR - [3:1] */
  2568. #define ARIZONA_NGATE_THR_WIDTH 3 /* NGATE_THR - [3:1] */
  2569. #define ARIZONA_NGATE_ENA 0x0001 /* NGATE_ENA */
  2570. #define ARIZONA_NGATE_ENA_MASK 0x0001 /* NGATE_ENA */
  2571. #define ARIZONA_NGATE_ENA_SHIFT 0 /* NGATE_ENA */
  2572. #define ARIZONA_NGATE_ENA_WIDTH 1 /* NGATE_ENA */
  2573. /*
  2574. * R1168 (0x490) - PDM SPK1 CTRL 1
  2575. */
  2576. #define ARIZONA_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
  2577. #define ARIZONA_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
  2578. #define ARIZONA_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
  2579. #define ARIZONA_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
  2580. #define ARIZONA_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
  2581. #define ARIZONA_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
  2582. #define ARIZONA_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
  2583. #define ARIZONA_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
  2584. #define ARIZONA_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
  2585. #define ARIZONA_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
  2586. #define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
  2587. #define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
  2588. #define ARIZONA_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
  2589. #define ARIZONA_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
  2590. #define ARIZONA_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
  2591. /*
  2592. * R1169 (0x491) - PDM SPK1 CTRL 2
  2593. */
  2594. #define ARIZONA_SPK1_FMT 0x0001 /* SPK1_FMT */
  2595. #define ARIZONA_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
  2596. #define ARIZONA_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
  2597. #define ARIZONA_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
  2598. /*
  2599. * R1244 (0x4DC) - DAC comp 1
  2600. */
  2601. #define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */
  2602. #define ARIZONA_OUT_COMP_COEFF_SHIFT 0 /* OUT_COMP_COEFF - [15:0] */
  2603. #define ARIZONA_OUT_COMP_COEFF_WIDTH 16 /* OUT_COMP_COEFF - [15:0] */
  2604. /*
  2605. * R1245 (0x4DD) - DAC comp 2
  2606. */
  2607. #define ARIZONA_OUT_COMP_COEFF_1 0x0002 /* OUT_COMP_COEFF */
  2608. #define ARIZONA_OUT_COMP_COEFF_1_MASK 0x0002 /* OUT_COMP_COEFF */
  2609. #define ARIZONA_OUT_COMP_COEFF_1_SHIFT 1 /* OUT_COMP_COEFF */
  2610. #define ARIZONA_OUT_COMP_COEFF_1_WIDTH 1 /* OUT_COMP_COEFF */
  2611. #define ARIZONA_OUT_COMP_COEFF_SEL 0x0001 /* OUT_COMP_COEFF_SEL */
  2612. #define ARIZONA_OUT_COMP_COEFF_SEL_MASK 0x0001 /* OUT_COMP_COEFF_SEL */
  2613. #define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT 0 /* OUT_COMP_COEFF_SEL */
  2614. #define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH 1 /* OUT_COMP_COEFF_SEL */
  2615. /*
  2616. * R1246 (0x4DE) - DAC comp 3
  2617. */
  2618. #define ARIZONA_AEC_COMP_COEFF_MASK 0xFFFF /* AEC_COMP_COEFF - [15:0] */
  2619. #define ARIZONA_AEC_COMP_COEFF_SHIFT 0 /* AEC_COMP_COEFF - [15:0] */
  2620. #define ARIZONA_AEC_COMP_COEFF_WIDTH 16 /* AEC_COMP_COEFF - [15:0] */
  2621. /*
  2622. * R1247 (0x4DF) - DAC comp 4
  2623. */
  2624. #define ARIZONA_AEC_COMP_COEFF_1 0x0002 /* AEC_COMP_COEFF */
  2625. #define ARIZONA_AEC_COMP_COEFF_1_MASK 0x0002 /* AEC_COMP_COEFF */
  2626. #define ARIZONA_AEC_COMP_COEFF_1_SHIFT 1 /* AEC_COMP_COEFF */
  2627. #define ARIZONA_AEC_COMP_COEFF_1_WIDTH 1 /* AEC_COMP_COEFF */
  2628. #define ARIZONA_AEC_COMP_COEFF_SEL 0x0001 /* AEC_COMP_COEFF_SEL */
  2629. #define ARIZONA_AEC_COMP_COEFF_SEL_MASK 0x0001 /* AEC_COMP_COEFF_SEL */
  2630. #define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT 0 /* AEC_COMP_COEFF_SEL */
  2631. #define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH 1 /* AEC_COMP_COEFF_SEL */
  2632. /*
  2633. * R1280 (0x500) - AIF1 BCLK Ctrl
  2634. */
  2635. #define ARIZONA_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */
  2636. #define ARIZONA_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */
  2637. #define ARIZONA_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */
  2638. #define ARIZONA_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
  2639. #define ARIZONA_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */
  2640. #define ARIZONA_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */
  2641. #define ARIZONA_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */
  2642. #define ARIZONA_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
  2643. #define ARIZONA_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */
  2644. #define ARIZONA_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */
  2645. #define ARIZONA_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */
  2646. #define ARIZONA_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
  2647. #define ARIZONA_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */
  2648. #define ARIZONA_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */
  2649. #define ARIZONA_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */
  2650. /*
  2651. * R1281 (0x501) - AIF1 Tx Pin Ctrl
  2652. */
  2653. #define ARIZONA_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
  2654. #define ARIZONA_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
  2655. #define ARIZONA_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
  2656. #define ARIZONA_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
  2657. #define ARIZONA_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
  2658. #define ARIZONA_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
  2659. #define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
  2660. #define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
  2661. #define ARIZONA_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
  2662. #define ARIZONA_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
  2663. #define ARIZONA_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
  2664. #define ARIZONA_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
  2665. #define ARIZONA_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
  2666. #define ARIZONA_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
  2667. #define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
  2668. #define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
  2669. #define ARIZONA_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
  2670. #define ARIZONA_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
  2671. #define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
  2672. #define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
  2673. /*
  2674. * R1282 (0x502) - AIF1 Rx Pin Ctrl
  2675. */
  2676. #define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
  2677. #define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
  2678. #define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
  2679. #define ARIZONA_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
  2680. #define ARIZONA_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
  2681. #define ARIZONA_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
  2682. #define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
  2683. #define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
  2684. #define ARIZONA_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
  2685. #define ARIZONA_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
  2686. #define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
  2687. #define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
  2688. /*
  2689. * R1283 (0x503) - AIF1 Rate Ctrl
  2690. */
  2691. #define ARIZONA_AIF1_RATE_MASK 0x7800 /* AIF1_RATE - [14:11] */
  2692. #define ARIZONA_AIF1_RATE_SHIFT 11 /* AIF1_RATE - [14:11] */
  2693. #define ARIZONA_AIF1_RATE_WIDTH 4 /* AIF1_RATE - [14:11] */
  2694. #define ARIZONA_AIF1_TRI 0x0040 /* AIF1_TRI */
  2695. #define ARIZONA_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
  2696. #define ARIZONA_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
  2697. #define ARIZONA_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
  2698. /*
  2699. * R1284 (0x504) - AIF1 Format
  2700. */
  2701. #define ARIZONA_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
  2702. #define ARIZONA_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
  2703. #define ARIZONA_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
  2704. /*
  2705. * R1285 (0x505) - AIF1 Tx BCLK Rate
  2706. */
  2707. #define ARIZONA_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */
  2708. #define ARIZONA_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */
  2709. #define ARIZONA_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */
  2710. /*
  2711. * R1286 (0x506) - AIF1 Rx BCLK Rate
  2712. */
  2713. #define ARIZONA_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */
  2714. #define ARIZONA_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */
  2715. #define ARIZONA_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */
  2716. /*
  2717. * R1287 (0x507) - AIF1 Frame Ctrl 1
  2718. */
  2719. #define ARIZONA_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
  2720. #define ARIZONA_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
  2721. #define ARIZONA_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
  2722. #define ARIZONA_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
  2723. #define ARIZONA_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
  2724. #define ARIZONA_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
  2725. /*
  2726. * R1288 (0x508) - AIF1 Frame Ctrl 2
  2727. */
  2728. #define ARIZONA_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
  2729. #define ARIZONA_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
  2730. #define ARIZONA_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
  2731. #define ARIZONA_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
  2732. #define ARIZONA_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
  2733. #define ARIZONA_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
  2734. /*
  2735. * R1289 (0x509) - AIF1 Frame Ctrl 3
  2736. */
  2737. #define ARIZONA_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
  2738. #define ARIZONA_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
  2739. #define ARIZONA_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
  2740. /*
  2741. * R1290 (0x50A) - AIF1 Frame Ctrl 4
  2742. */
  2743. #define ARIZONA_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
  2744. #define ARIZONA_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
  2745. #define ARIZONA_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
  2746. /*
  2747. * R1291 (0x50B) - AIF1 Frame Ctrl 5
  2748. */
  2749. #define ARIZONA_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
  2750. #define ARIZONA_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
  2751. #define ARIZONA_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
  2752. /*
  2753. * R1292 (0x50C) - AIF1 Frame Ctrl 6
  2754. */
  2755. #define ARIZONA_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
  2756. #define ARIZONA_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
  2757. #define ARIZONA_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
  2758. /*
  2759. * R1293 (0x50D) - AIF1 Frame Ctrl 7
  2760. */
  2761. #define ARIZONA_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
  2762. #define ARIZONA_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
  2763. #define ARIZONA_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
  2764. /*
  2765. * R1294 (0x50E) - AIF1 Frame Ctrl 8
  2766. */
  2767. #define ARIZONA_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
  2768. #define ARIZONA_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
  2769. #define ARIZONA_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
  2770. /*
  2771. * R1295 (0x50F) - AIF1 Frame Ctrl 9
  2772. */
  2773. #define ARIZONA_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */
  2774. #define ARIZONA_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */
  2775. #define ARIZONA_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */
  2776. /*
  2777. * R1296 (0x510) - AIF1 Frame Ctrl 10
  2778. */
  2779. #define ARIZONA_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */
  2780. #define ARIZONA_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */
  2781. #define ARIZONA_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */
  2782. /*
  2783. * R1297 (0x511) - AIF1 Frame Ctrl 11
  2784. */
  2785. #define ARIZONA_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
  2786. #define ARIZONA_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
  2787. #define ARIZONA_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
  2788. /*
  2789. * R1298 (0x512) - AIF1 Frame Ctrl 12
  2790. */
  2791. #define ARIZONA_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
  2792. #define ARIZONA_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
  2793. #define ARIZONA_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
  2794. /*
  2795. * R1299 (0x513) - AIF1 Frame Ctrl 13
  2796. */
  2797. #define ARIZONA_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
  2798. #define ARIZONA_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
  2799. #define ARIZONA_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
  2800. /*
  2801. * R1300 (0x514) - AIF1 Frame Ctrl 14
  2802. */
  2803. #define ARIZONA_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
  2804. #define ARIZONA_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
  2805. #define ARIZONA_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
  2806. /*
  2807. * R1301 (0x515) - AIF1 Frame Ctrl 15
  2808. */
  2809. #define ARIZONA_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
  2810. #define ARIZONA_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
  2811. #define ARIZONA_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
  2812. /*
  2813. * R1302 (0x516) - AIF1 Frame Ctrl 16
  2814. */
  2815. #define ARIZONA_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
  2816. #define ARIZONA_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
  2817. #define ARIZONA_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
  2818. /*
  2819. * R1303 (0x517) - AIF1 Frame Ctrl 17
  2820. */
  2821. #define ARIZONA_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */
  2822. #define ARIZONA_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */
  2823. #define ARIZONA_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */
  2824. /*
  2825. * R1304 (0x518) - AIF1 Frame Ctrl 18
  2826. */
  2827. #define ARIZONA_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */
  2828. #define ARIZONA_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */
  2829. #define ARIZONA_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */
  2830. /*
  2831. * R1305 (0x519) - AIF1 Tx Enables
  2832. */
  2833. #define ARIZONA_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */
  2834. #define ARIZONA_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */
  2835. #define ARIZONA_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */
  2836. #define ARIZONA_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */
  2837. #define ARIZONA_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */
  2838. #define ARIZONA_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */
  2839. #define ARIZONA_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */
  2840. #define ARIZONA_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */
  2841. #define ARIZONA_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
  2842. #define ARIZONA_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
  2843. #define ARIZONA_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
  2844. #define ARIZONA_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
  2845. #define ARIZONA_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
  2846. #define ARIZONA_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
  2847. #define ARIZONA_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
  2848. #define ARIZONA_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
  2849. #define ARIZONA_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
  2850. #define ARIZONA_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
  2851. #define ARIZONA_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
  2852. #define ARIZONA_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
  2853. #define ARIZONA_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
  2854. #define ARIZONA_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
  2855. #define ARIZONA_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
  2856. #define ARIZONA_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
  2857. #define ARIZONA_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
  2858. #define ARIZONA_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
  2859. #define ARIZONA_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
  2860. #define ARIZONA_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
  2861. #define ARIZONA_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
  2862. #define ARIZONA_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
  2863. #define ARIZONA_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
  2864. #define ARIZONA_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
  2865. /*
  2866. * R1306 (0x51A) - AIF1 Rx Enables
  2867. */
  2868. #define ARIZONA_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */
  2869. #define ARIZONA_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */
  2870. #define ARIZONA_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */
  2871. #define ARIZONA_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */
  2872. #define ARIZONA_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */
  2873. #define ARIZONA_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */
  2874. #define ARIZONA_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */
  2875. #define ARIZONA_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */
  2876. #define ARIZONA_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */
  2877. #define ARIZONA_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */
  2878. #define ARIZONA_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */
  2879. #define ARIZONA_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
  2880. #define ARIZONA_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */
  2881. #define ARIZONA_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */
  2882. #define ARIZONA_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */
  2883. #define ARIZONA_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
  2884. #define ARIZONA_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */
  2885. #define ARIZONA_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */
  2886. #define ARIZONA_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */
  2887. #define ARIZONA_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
  2888. #define ARIZONA_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */
  2889. #define ARIZONA_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */
  2890. #define ARIZONA_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */
  2891. #define ARIZONA_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
  2892. #define ARIZONA_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */
  2893. #define ARIZONA_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */
  2894. #define ARIZONA_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */
  2895. #define ARIZONA_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
  2896. #define ARIZONA_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */
  2897. #define ARIZONA_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */
  2898. #define ARIZONA_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */
  2899. #define ARIZONA_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
  2900. /*
  2901. * R1307 (0x51B) - AIF1 Force Write
  2902. */
  2903. #define ARIZONA_AIF1_FRC_WR 0x0001 /* AIF1_FRC_WR */
  2904. #define ARIZONA_AIF1_FRC_WR_MASK 0x0001 /* AIF1_FRC_WR */
  2905. #define ARIZONA_AIF1_FRC_WR_SHIFT 0 /* AIF1_FRC_WR */
  2906. #define ARIZONA_AIF1_FRC_WR_WIDTH 1 /* AIF1_FRC_WR */
  2907. /*
  2908. * R1344 (0x540) - AIF2 BCLK Ctrl
  2909. */
  2910. #define ARIZONA_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */
  2911. #define ARIZONA_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */
  2912. #define ARIZONA_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */
  2913. #define ARIZONA_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
  2914. #define ARIZONA_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */
  2915. #define ARIZONA_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */
  2916. #define ARIZONA_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */
  2917. #define ARIZONA_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
  2918. #define ARIZONA_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */
  2919. #define ARIZONA_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */
  2920. #define ARIZONA_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */
  2921. #define ARIZONA_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
  2922. #define ARIZONA_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */
  2923. #define ARIZONA_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */
  2924. #define ARIZONA_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */
  2925. /*
  2926. * R1345 (0x541) - AIF2 Tx Pin Ctrl
  2927. */
  2928. #define ARIZONA_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */
  2929. #define ARIZONA_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */
  2930. #define ARIZONA_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */
  2931. #define ARIZONA_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
  2932. #define ARIZONA_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */
  2933. #define ARIZONA_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */
  2934. #define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */
  2935. #define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */
  2936. #define ARIZONA_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
  2937. #define ARIZONA_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
  2938. #define ARIZONA_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
  2939. #define ARIZONA_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
  2940. #define ARIZONA_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
  2941. #define ARIZONA_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
  2942. #define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
  2943. #define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
  2944. #define ARIZONA_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
  2945. #define ARIZONA_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
  2946. #define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
  2947. #define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
  2948. /*
  2949. * R1346 (0x542) - AIF2 Rx Pin Ctrl
  2950. */
  2951. #define ARIZONA_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
  2952. #define ARIZONA_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
  2953. #define ARIZONA_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
  2954. #define ARIZONA_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
  2955. #define ARIZONA_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
  2956. #define ARIZONA_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
  2957. #define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
  2958. #define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
  2959. #define ARIZONA_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
  2960. #define ARIZONA_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
  2961. #define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
  2962. #define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
  2963. /*
  2964. * R1347 (0x543) - AIF2 Rate Ctrl
  2965. */
  2966. #define ARIZONA_AIF2_RATE_MASK 0x7800 /* AIF2_RATE - [14:11] */
  2967. #define ARIZONA_AIF2_RATE_SHIFT 11 /* AIF2_RATE - [14:11] */
  2968. #define ARIZONA_AIF2_RATE_WIDTH 4 /* AIF2_RATE - [14:11] */
  2969. #define ARIZONA_AIF2_TRI 0x0040 /* AIF2_TRI */
  2970. #define ARIZONA_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */
  2971. #define ARIZONA_AIF2_TRI_SHIFT 6 /* AIF2_TRI */
  2972. #define ARIZONA_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
  2973. /*
  2974. * R1348 (0x544) - AIF2 Format
  2975. */
  2976. #define ARIZONA_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */
  2977. #define ARIZONA_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */
  2978. #define ARIZONA_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */
  2979. /*
  2980. * R1349 (0x545) - AIF2 Tx BCLK Rate
  2981. */
  2982. #define ARIZONA_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */
  2983. #define ARIZONA_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */
  2984. #define ARIZONA_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */
  2985. /*
  2986. * R1350 (0x546) - AIF2 Rx BCLK Rate
  2987. */
  2988. #define ARIZONA_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */
  2989. #define ARIZONA_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */
  2990. #define ARIZONA_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */
  2991. /*
  2992. * R1351 (0x547) - AIF2 Frame Ctrl 1
  2993. */
  2994. #define ARIZONA_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */
  2995. #define ARIZONA_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */
  2996. #define ARIZONA_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */
  2997. #define ARIZONA_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
  2998. #define ARIZONA_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
  2999. #define ARIZONA_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
  3000. /*
  3001. * R1352 (0x548) - AIF2 Frame Ctrl 2
  3002. */
  3003. #define ARIZONA_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */
  3004. #define ARIZONA_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */
  3005. #define ARIZONA_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */
  3006. #define ARIZONA_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
  3007. #define ARIZONA_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
  3008. #define ARIZONA_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
  3009. /*
  3010. * R1353 (0x549) - AIF2 Frame Ctrl 3
  3011. */
  3012. #define ARIZONA_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */
  3013. #define ARIZONA_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */
  3014. #define ARIZONA_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */
  3015. /*
  3016. * R1354 (0x54A) - AIF2 Frame Ctrl 4
  3017. */
  3018. #define ARIZONA_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */
  3019. #define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */
  3020. #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */
  3021. /*
  3022. * R1361 (0x551) - AIF2 Frame Ctrl 11
  3023. */
  3024. #define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */
  3025. #define ARIZONA_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */
  3026. #define ARIZONA_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */
  3027. /*
  3028. * R1362 (0x552) - AIF2 Frame Ctrl 12
  3029. */
  3030. #define ARIZONA_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */
  3031. #define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */
  3032. #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */
  3033. /*
  3034. * R1369 (0x559) - AIF2 Tx Enables
  3035. */
  3036. #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */
  3037. #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */
  3038. #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */
  3039. #define ARIZONA_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */
  3040. #define ARIZONA_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */
  3041. #define ARIZONA_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */
  3042. #define ARIZONA_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */
  3043. #define ARIZONA_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */
  3044. /*
  3045. * R1370 (0x55A) - AIF2 Rx Enables
  3046. */
  3047. #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */
  3048. #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */
  3049. #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */
  3050. #define ARIZONA_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */
  3051. #define ARIZONA_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */
  3052. #define ARIZONA_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */
  3053. #define ARIZONA_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */
  3054. #define ARIZONA_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */
  3055. /*
  3056. * R1371 (0x55B) - AIF2 Force Write
  3057. */
  3058. #define ARIZONA_AIF2_FRC_WR 0x0001 /* AIF2_FRC_WR */
  3059. #define ARIZONA_AIF2_FRC_WR_MASK 0x0001 /* AIF2_FRC_WR */
  3060. #define ARIZONA_AIF2_FRC_WR_SHIFT 0 /* AIF2_FRC_WR */
  3061. #define ARIZONA_AIF2_FRC_WR_WIDTH 1 /* AIF2_FRC_WR */
  3062. /*
  3063. * R1408 (0x580) - AIF3 BCLK Ctrl
  3064. */
  3065. #define ARIZONA_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */
  3066. #define ARIZONA_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */
  3067. #define ARIZONA_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */
  3068. #define ARIZONA_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */
  3069. #define ARIZONA_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */
  3070. #define ARIZONA_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */
  3071. #define ARIZONA_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */
  3072. #define ARIZONA_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */
  3073. #define ARIZONA_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */
  3074. #define ARIZONA_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */
  3075. #define ARIZONA_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */
  3076. #define ARIZONA_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */
  3077. #define ARIZONA_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */
  3078. #define ARIZONA_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */
  3079. #define ARIZONA_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */
  3080. /*
  3081. * R1409 (0x581) - AIF3 Tx Pin Ctrl
  3082. */
  3083. #define ARIZONA_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */
  3084. #define ARIZONA_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */
  3085. #define ARIZONA_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */
  3086. #define ARIZONA_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */
  3087. #define ARIZONA_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */
  3088. #define ARIZONA_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */
  3089. #define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */
  3090. #define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */
  3091. #define ARIZONA_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */
  3092. #define ARIZONA_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */
  3093. #define ARIZONA_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */
  3094. #define ARIZONA_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */
  3095. #define ARIZONA_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */
  3096. #define ARIZONA_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */
  3097. #define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */
  3098. #define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */
  3099. #define ARIZONA_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */
  3100. #define ARIZONA_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */
  3101. #define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */
  3102. #define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */
  3103. /*
  3104. * R1410 (0x582) - AIF3 Rx Pin Ctrl
  3105. */
  3106. #define ARIZONA_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */
  3107. #define ARIZONA_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */
  3108. #define ARIZONA_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */
  3109. #define ARIZONA_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */
  3110. #define ARIZONA_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */
  3111. #define ARIZONA_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */
  3112. #define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */
  3113. #define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */
  3114. #define ARIZONA_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */
  3115. #define ARIZONA_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */
  3116. #define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */
  3117. #define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */
  3118. /*
  3119. * R1411 (0x583) - AIF3 Rate Ctrl
  3120. */
  3121. #define ARIZONA_AIF3_RATE_MASK 0x7800 /* AIF3_RATE - [14:11] */
  3122. #define ARIZONA_AIF3_RATE_SHIFT 11 /* AIF3_RATE - [14:11] */
  3123. #define ARIZONA_AIF3_RATE_WIDTH 4 /* AIF3_RATE - [14:11] */
  3124. #define ARIZONA_AIF3_TRI 0x0040 /* AIF3_TRI */
  3125. #define ARIZONA_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */
  3126. #define ARIZONA_AIF3_TRI_SHIFT 6 /* AIF3_TRI */
  3127. #define ARIZONA_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
  3128. /*
  3129. * R1412 (0x584) - AIF3 Format
  3130. */
  3131. #define ARIZONA_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */
  3132. #define ARIZONA_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */
  3133. #define ARIZONA_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */
  3134. /*
  3135. * R1413 (0x585) - AIF3 Tx BCLK Rate
  3136. */
  3137. #define ARIZONA_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */
  3138. #define ARIZONA_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */
  3139. #define ARIZONA_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */
  3140. /*
  3141. * R1414 (0x586) - AIF3 Rx BCLK Rate
  3142. */
  3143. #define ARIZONA_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */
  3144. #define ARIZONA_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */
  3145. #define ARIZONA_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */
  3146. /*
  3147. * R1415 (0x587) - AIF3 Frame Ctrl 1
  3148. */
  3149. #define ARIZONA_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */
  3150. #define ARIZONA_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */
  3151. #define ARIZONA_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */
  3152. #define ARIZONA_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */
  3153. #define ARIZONA_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */
  3154. #define ARIZONA_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */
  3155. /*
  3156. * R1416 (0x588) - AIF3 Frame Ctrl 2
  3157. */
  3158. #define ARIZONA_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */
  3159. #define ARIZONA_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */
  3160. #define ARIZONA_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */
  3161. #define ARIZONA_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */
  3162. #define ARIZONA_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */
  3163. #define ARIZONA_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */
  3164. /*
  3165. * R1417 (0x589) - AIF3 Frame Ctrl 3
  3166. */
  3167. #define ARIZONA_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */
  3168. #define ARIZONA_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */
  3169. #define ARIZONA_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */
  3170. /*
  3171. * R1418 (0x58A) - AIF3 Frame Ctrl 4
  3172. */
  3173. #define ARIZONA_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */
  3174. #define ARIZONA_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */
  3175. #define ARIZONA_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */
  3176. /*
  3177. * R1425 (0x591) - AIF3 Frame Ctrl 11
  3178. */
  3179. #define ARIZONA_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */
  3180. #define ARIZONA_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */
  3181. #define ARIZONA_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */
  3182. /*
  3183. * R1426 (0x592) - AIF3 Frame Ctrl 12
  3184. */
  3185. #define ARIZONA_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */
  3186. #define ARIZONA_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */
  3187. #define ARIZONA_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */
  3188. /*
  3189. * R1433 (0x599) - AIF3 Tx Enables
  3190. */
  3191. #define ARIZONA_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */
  3192. #define ARIZONA_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */
  3193. #define ARIZONA_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */
  3194. #define ARIZONA_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */
  3195. #define ARIZONA_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */
  3196. #define ARIZONA_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */
  3197. #define ARIZONA_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */
  3198. #define ARIZONA_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */
  3199. /*
  3200. * R1434 (0x59A) - AIF3 Rx Enables
  3201. */
  3202. #define ARIZONA_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */
  3203. #define ARIZONA_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */
  3204. #define ARIZONA_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */
  3205. #define ARIZONA_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */
  3206. #define ARIZONA_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */
  3207. #define ARIZONA_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */
  3208. #define ARIZONA_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */
  3209. #define ARIZONA_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */
  3210. /*
  3211. * R1435 (0x59B) - AIF3 Force Write
  3212. */
  3213. #define ARIZONA_AIF3_FRC_WR 0x0001 /* AIF3_FRC_WR */
  3214. #define ARIZONA_AIF3_FRC_WR_MASK 0x0001 /* AIF3_FRC_WR */
  3215. #define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */
  3216. #define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */
  3217. /*
  3218. * R1507 (0x5E3) - SLIMbus Framer Ref Gear
  3219. */
  3220. #define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */
  3221. #define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */
  3222. #define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */
  3223. #define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */
  3224. #define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */
  3225. #define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */
  3226. #define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */
  3227. /*
  3228. * R1509 (0x5E5) - SLIMbus Rates 1
  3229. */
  3230. #define ARIZONA_SLIMRX2_RATE_MASK 0x7800 /* SLIMRX2_RATE - [14:11] */
  3231. #define ARIZONA_SLIMRX2_RATE_SHIFT 11 /* SLIMRX2_RATE - [14:11] */
  3232. #define ARIZONA_SLIMRX2_RATE_WIDTH 4 /* SLIMRX2_RATE - [14:11] */
  3233. #define ARIZONA_SLIMRX1_RATE_MASK 0x0078 /* SLIMRX1_RATE - [6:3] */
  3234. #define ARIZONA_SLIMRX1_RATE_SHIFT 3 /* SLIMRX1_RATE - [6:3] */
  3235. #define ARIZONA_SLIMRX1_RATE_WIDTH 4 /* SLIMRX1_RATE - [6:3] */
  3236. /*
  3237. * R1510 (0x5E6) - SLIMbus Rates 2
  3238. */
  3239. #define ARIZONA_SLIMRX4_RATE_MASK 0x7800 /* SLIMRX4_RATE - [14:11] */
  3240. #define ARIZONA_SLIMRX4_RATE_SHIFT 11 /* SLIMRX4_RATE - [14:11] */
  3241. #define ARIZONA_SLIMRX4_RATE_WIDTH 4 /* SLIMRX4_RATE - [14:11] */
  3242. #define ARIZONA_SLIMRX3_RATE_MASK 0x0078 /* SLIMRX3_RATE - [6:3] */
  3243. #define ARIZONA_SLIMRX3_RATE_SHIFT 3 /* SLIMRX3_RATE - [6:3] */
  3244. #define ARIZONA_SLIMRX3_RATE_WIDTH 4 /* SLIMRX3_RATE - [6:3] */
  3245. /*
  3246. * R1511 (0x5E7) - SLIMbus Rates 3
  3247. */
  3248. #define ARIZONA_SLIMRX6_RATE_MASK 0x7800 /* SLIMRX6_RATE - [14:11] */
  3249. #define ARIZONA_SLIMRX6_RATE_SHIFT 11 /* SLIMRX6_RATE - [14:11] */
  3250. #define ARIZONA_SLIMRX6_RATE_WIDTH 4 /* SLIMRX6_RATE - [14:11] */
  3251. #define ARIZONA_SLIMRX5_RATE_MASK 0x0078 /* SLIMRX5_RATE - [6:3] */
  3252. #define ARIZONA_SLIMRX5_RATE_SHIFT 3 /* SLIMRX5_RATE - [6:3] */
  3253. #define ARIZONA_SLIMRX5_RATE_WIDTH 4 /* SLIMRX5_RATE - [6:3] */
  3254. /*
  3255. * R1512 (0x5E8) - SLIMbus Rates 4
  3256. */
  3257. #define ARIZONA_SLIMRX8_RATE_MASK 0x7800 /* SLIMRX8_RATE - [14:11] */
  3258. #define ARIZONA_SLIMRX8_RATE_SHIFT 11 /* SLIMRX8_RATE - [14:11] */
  3259. #define ARIZONA_SLIMRX8_RATE_WIDTH 4 /* SLIMRX8_RATE - [14:11] */
  3260. #define ARIZONA_SLIMRX7_RATE_MASK 0x0078 /* SLIMRX7_RATE - [6:3] */
  3261. #define ARIZONA_SLIMRX7_RATE_SHIFT 3 /* SLIMRX7_RATE - [6:3] */
  3262. #define ARIZONA_SLIMRX7_RATE_WIDTH 4 /* SLIMRX7_RATE - [6:3] */
  3263. /*
  3264. * R1513 (0x5E9) - SLIMbus Rates 5
  3265. */
  3266. #define ARIZONA_SLIMTX2_RATE_MASK 0x7800 /* SLIMTX2_RATE - [14:11] */
  3267. #define ARIZONA_SLIMTX2_RATE_SHIFT 11 /* SLIMTX2_RATE - [14:11] */
  3268. #define ARIZONA_SLIMTX2_RATE_WIDTH 4 /* SLIMTX2_RATE - [14:11] */
  3269. #define ARIZONA_SLIMTX1_RATE_MASK 0x0078 /* SLIMTX1_RATE - [6:3] */
  3270. #define ARIZONA_SLIMTX1_RATE_SHIFT 3 /* SLIMTX1_RATE - [6:3] */
  3271. #define ARIZONA_SLIMTX1_RATE_WIDTH 4 /* SLIMTX1_RATE - [6:3] */
  3272. /*
  3273. * R1514 (0x5EA) - SLIMbus Rates 6
  3274. */
  3275. #define ARIZONA_SLIMTX4_RATE_MASK 0x7800 /* SLIMTX4_RATE - [14:11] */
  3276. #define ARIZONA_SLIMTX4_RATE_SHIFT 11 /* SLIMTX4_RATE - [14:11] */
  3277. #define ARIZONA_SLIMTX4_RATE_WIDTH 4 /* SLIMTX4_RATE - [14:11] */
  3278. #define ARIZONA_SLIMTX3_RATE_MASK 0x0078 /* SLIMTX3_RATE - [6:3] */
  3279. #define ARIZONA_SLIMTX3_RATE_SHIFT 3 /* SLIMTX3_RATE - [6:3] */
  3280. #define ARIZONA_SLIMTX3_RATE_WIDTH 4 /* SLIMTX3_RATE - [6:3] */
  3281. /*
  3282. * R1515 (0x5EB) - SLIMbus Rates 7
  3283. */
  3284. #define ARIZONA_SLIMTX6_RATE_MASK 0x7800 /* SLIMTX6_RATE - [14:11] */
  3285. #define ARIZONA_SLIMTX6_RATE_SHIFT 11 /* SLIMTX6_RATE - [14:11] */
  3286. #define ARIZONA_SLIMTX6_RATE_WIDTH 4 /* SLIMTX6_RATE - [14:11] */
  3287. #define ARIZONA_SLIMTX5_RATE_MASK 0x0078 /* SLIMTX5_RATE - [6:3] */
  3288. #define ARIZONA_SLIMTX5_RATE_SHIFT 3 /* SLIMTX5_RATE - [6:3] */
  3289. #define ARIZONA_SLIMTX5_RATE_WIDTH 4 /* SLIMTX5_RATE - [6:3] */
  3290. /*
  3291. * R1516 (0x5EC) - SLIMbus Rates 8
  3292. */
  3293. #define ARIZONA_SLIMTX8_RATE_MASK 0x7800 /* SLIMTX8_RATE - [14:11] */
  3294. #define ARIZONA_SLIMTX8_RATE_SHIFT 11 /* SLIMTX8_RATE - [14:11] */
  3295. #define ARIZONA_SLIMTX8_RATE_WIDTH 4 /* SLIMTX8_RATE - [14:11] */
  3296. #define ARIZONA_SLIMTX7_RATE_MASK 0x0078 /* SLIMTX7_RATE - [6:3] */
  3297. #define ARIZONA_SLIMTX7_RATE_SHIFT 3 /* SLIMTX7_RATE - [6:3] */
  3298. #define ARIZONA_SLIMTX7_RATE_WIDTH 4 /* SLIMTX7_RATE - [6:3] */
  3299. /*
  3300. * R1525 (0x5F5) - SLIMbus RX Channel Enable
  3301. */
  3302. #define ARIZONA_SLIMRX8_ENA 0x0080 /* SLIMRX8_ENA */
  3303. #define ARIZONA_SLIMRX8_ENA_MASK 0x0080 /* SLIMRX8_ENA */
  3304. #define ARIZONA_SLIMRX8_ENA_SHIFT 7 /* SLIMRX8_ENA */
  3305. #define ARIZONA_SLIMRX8_ENA_WIDTH 1 /* SLIMRX8_ENA */
  3306. #define ARIZONA_SLIMRX7_ENA 0x0040 /* SLIMRX7_ENA */
  3307. #define ARIZONA_SLIMRX7_ENA_MASK 0x0040 /* SLIMRX7_ENA */
  3308. #define ARIZONA_SLIMRX7_ENA_SHIFT 6 /* SLIMRX7_ENA */
  3309. #define ARIZONA_SLIMRX7_ENA_WIDTH 1 /* SLIMRX7_ENA */
  3310. #define ARIZONA_SLIMRX6_ENA 0x0020 /* SLIMRX6_ENA */
  3311. #define ARIZONA_SLIMRX6_ENA_MASK 0x0020 /* SLIMRX6_ENA */
  3312. #define ARIZONA_SLIMRX6_ENA_SHIFT 5 /* SLIMRX6_ENA */
  3313. #define ARIZONA_SLIMRX6_ENA_WIDTH 1 /* SLIMRX6_ENA */
  3314. #define ARIZONA_SLIMRX5_ENA 0x0010 /* SLIMRX5_ENA */
  3315. #define ARIZONA_SLIMRX5_ENA_MASK 0x0010 /* SLIMRX5_ENA */
  3316. #define ARIZONA_SLIMRX5_ENA_SHIFT 4 /* SLIMRX5_ENA */
  3317. #define ARIZONA_SLIMRX5_ENA_WIDTH 1 /* SLIMRX5_ENA */
  3318. #define ARIZONA_SLIMRX4_ENA 0x0008 /* SLIMRX4_ENA */
  3319. #define ARIZONA_SLIMRX4_ENA_MASK 0x0008 /* SLIMRX4_ENA */
  3320. #define ARIZONA_SLIMRX4_ENA_SHIFT 3 /* SLIMRX4_ENA */
  3321. #define ARIZONA_SLIMRX4_ENA_WIDTH 1 /* SLIMRX4_ENA */
  3322. #define ARIZONA_SLIMRX3_ENA 0x0004 /* SLIMRX3_ENA */
  3323. #define ARIZONA_SLIMRX3_ENA_MASK 0x0004 /* SLIMRX3_ENA */
  3324. #define ARIZONA_SLIMRX3_ENA_SHIFT 2 /* SLIMRX3_ENA */
  3325. #define ARIZONA_SLIMRX3_ENA_WIDTH 1 /* SLIMRX3_ENA */
  3326. #define ARIZONA_SLIMRX2_ENA 0x0002 /* SLIMRX2_ENA */
  3327. #define ARIZONA_SLIMRX2_ENA_MASK 0x0002 /* SLIMRX2_ENA */
  3328. #define ARIZONA_SLIMRX2_ENA_SHIFT 1 /* SLIMRX2_ENA */
  3329. #define ARIZONA_SLIMRX2_ENA_WIDTH 1 /* SLIMRX2_ENA */
  3330. #define ARIZONA_SLIMRX1_ENA 0x0001 /* SLIMRX1_ENA */
  3331. #define ARIZONA_SLIMRX1_ENA_MASK 0x0001 /* SLIMRX1_ENA */
  3332. #define ARIZONA_SLIMRX1_ENA_SHIFT 0 /* SLIMRX1_ENA */
  3333. #define ARIZONA_SLIMRX1_ENA_WIDTH 1 /* SLIMRX1_ENA */
  3334. /*
  3335. * R1526 (0x5F6) - SLIMbus TX Channel Enable
  3336. */
  3337. #define ARIZONA_SLIMTX8_ENA 0x0080 /* SLIMTX8_ENA */
  3338. #define ARIZONA_SLIMTX8_ENA_MASK 0x0080 /* SLIMTX8_ENA */
  3339. #define ARIZONA_SLIMTX8_ENA_SHIFT 7 /* SLIMTX8_ENA */
  3340. #define ARIZONA_SLIMTX8_ENA_WIDTH 1 /* SLIMTX8_ENA */
  3341. #define ARIZONA_SLIMTX7_ENA 0x0040 /* SLIMTX7_ENA */
  3342. #define ARIZONA_SLIMTX7_ENA_MASK 0x0040 /* SLIMTX7_ENA */
  3343. #define ARIZONA_SLIMTX7_ENA_SHIFT 6 /* SLIMTX7_ENA */
  3344. #define ARIZONA_SLIMTX7_ENA_WIDTH 1 /* SLIMTX7_ENA */
  3345. #define ARIZONA_SLIMTX6_ENA 0x0020 /* SLIMTX6_ENA */
  3346. #define ARIZONA_SLIMTX6_ENA_MASK 0x0020 /* SLIMTX6_ENA */
  3347. #define ARIZONA_SLIMTX6_ENA_SHIFT 5 /* SLIMTX6_ENA */
  3348. #define ARIZONA_SLIMTX6_ENA_WIDTH 1 /* SLIMTX6_ENA */
  3349. #define ARIZONA_SLIMTX5_ENA 0x0010 /* SLIMTX5_ENA */
  3350. #define ARIZONA_SLIMTX5_ENA_MASK 0x0010 /* SLIMTX5_ENA */
  3351. #define ARIZONA_SLIMTX5_ENA_SHIFT 4 /* SLIMTX5_ENA */
  3352. #define ARIZONA_SLIMTX5_ENA_WIDTH 1 /* SLIMTX5_ENA */
  3353. #define ARIZONA_SLIMTX4_ENA 0x0008 /* SLIMTX4_ENA */
  3354. #define ARIZONA_SLIMTX4_ENA_MASK 0x0008 /* SLIMTX4_ENA */
  3355. #define ARIZONA_SLIMTX4_ENA_SHIFT 3 /* SLIMTX4_ENA */
  3356. #define ARIZONA_SLIMTX4_ENA_WIDTH 1 /* SLIMTX4_ENA */
  3357. #define ARIZONA_SLIMTX3_ENA 0x0004 /* SLIMTX3_ENA */
  3358. #define ARIZONA_SLIMTX3_ENA_MASK 0x0004 /* SLIMTX3_ENA */
  3359. #define ARIZONA_SLIMTX3_ENA_SHIFT 2 /* SLIMTX3_ENA */
  3360. #define ARIZONA_SLIMTX3_ENA_WIDTH 1 /* SLIMTX3_ENA */
  3361. #define ARIZONA_SLIMTX2_ENA 0x0002 /* SLIMTX2_ENA */
  3362. #define ARIZONA_SLIMTX2_ENA_MASK 0x0002 /* SLIMTX2_ENA */
  3363. #define ARIZONA_SLIMTX2_ENA_SHIFT 1 /* SLIMTX2_ENA */
  3364. #define ARIZONA_SLIMTX2_ENA_WIDTH 1 /* SLIMTX2_ENA */
  3365. #define ARIZONA_SLIMTX1_ENA 0x0001 /* SLIMTX1_ENA */
  3366. #define ARIZONA_SLIMTX1_ENA_MASK 0x0001 /* SLIMTX1_ENA */
  3367. #define ARIZONA_SLIMTX1_ENA_SHIFT 0 /* SLIMTX1_ENA */
  3368. #define ARIZONA_SLIMTX1_ENA_WIDTH 1 /* SLIMTX1_ENA */
  3369. /*
  3370. * R1527 (0x5F7) - SLIMbus RX Port Status
  3371. */
  3372. #define ARIZONA_SLIMRX8_PORT_STS 0x0080 /* SLIMRX8_PORT_STS */
  3373. #define ARIZONA_SLIMRX8_PORT_STS_MASK 0x0080 /* SLIMRX8_PORT_STS */
  3374. #define ARIZONA_SLIMRX8_PORT_STS_SHIFT 7 /* SLIMRX8_PORT_STS */
  3375. #define ARIZONA_SLIMRX8_PORT_STS_WIDTH 1 /* SLIMRX8_PORT_STS */
  3376. #define ARIZONA_SLIMRX7_PORT_STS 0x0040 /* SLIMRX7_PORT_STS */
  3377. #define ARIZONA_SLIMRX7_PORT_STS_MASK 0x0040 /* SLIMRX7_PORT_STS */
  3378. #define ARIZONA_SLIMRX7_PORT_STS_SHIFT 6 /* SLIMRX7_PORT_STS */
  3379. #define ARIZONA_SLIMRX7_PORT_STS_WIDTH 1 /* SLIMRX7_PORT_STS */
  3380. #define ARIZONA_SLIMRX6_PORT_STS 0x0020 /* SLIMRX6_PORT_STS */
  3381. #define ARIZONA_SLIMRX6_PORT_STS_MASK 0x0020 /* SLIMRX6_PORT_STS */
  3382. #define ARIZONA_SLIMRX6_PORT_STS_SHIFT 5 /* SLIMRX6_PORT_STS */
  3383. #define ARIZONA_SLIMRX6_PORT_STS_WIDTH 1 /* SLIMRX6_PORT_STS */
  3384. #define ARIZONA_SLIMRX5_PORT_STS 0x0010 /* SLIMRX5_PORT_STS */
  3385. #define ARIZONA_SLIMRX5_PORT_STS_MASK 0x0010 /* SLIMRX5_PORT_STS */
  3386. #define ARIZONA_SLIMRX5_PORT_STS_SHIFT 4 /* SLIMRX5_PORT_STS */
  3387. #define ARIZONA_SLIMRX5_PORT_STS_WIDTH 1 /* SLIMRX5_PORT_STS */
  3388. #define ARIZONA_SLIMRX4_PORT_STS 0x0008 /* SLIMRX4_PORT_STS */
  3389. #define ARIZONA_SLIMRX4_PORT_STS_MASK 0x0008 /* SLIMRX4_PORT_STS */
  3390. #define ARIZONA_SLIMRX4_PORT_STS_SHIFT 3 /* SLIMRX4_PORT_STS */
  3391. #define ARIZONA_SLIMRX4_PORT_STS_WIDTH 1 /* SLIMRX4_PORT_STS */
  3392. #define ARIZONA_SLIMRX3_PORT_STS 0x0004 /* SLIMRX3_PORT_STS */
  3393. #define ARIZONA_SLIMRX3_PORT_STS_MASK 0x0004 /* SLIMRX3_PORT_STS */
  3394. #define ARIZONA_SLIMRX3_PORT_STS_SHIFT 2 /* SLIMRX3_PORT_STS */
  3395. #define ARIZONA_SLIMRX3_PORT_STS_WIDTH 1 /* SLIMRX3_PORT_STS */
  3396. #define ARIZONA_SLIMRX2_PORT_STS 0x0002 /* SLIMRX2_PORT_STS */
  3397. #define ARIZONA_SLIMRX2_PORT_STS_MASK 0x0002 /* SLIMRX2_PORT_STS */
  3398. #define ARIZONA_SLIMRX2_PORT_STS_SHIFT 1 /* SLIMRX2_PORT_STS */
  3399. #define ARIZONA_SLIMRX2_PORT_STS_WIDTH 1 /* SLIMRX2_PORT_STS */
  3400. #define ARIZONA_SLIMRX1_PORT_STS 0x0001 /* SLIMRX1_PORT_STS */
  3401. #define ARIZONA_SLIMRX1_PORT_STS_MASK 0x0001 /* SLIMRX1_PORT_STS */
  3402. #define ARIZONA_SLIMRX1_PORT_STS_SHIFT 0 /* SLIMRX1_PORT_STS */
  3403. #define ARIZONA_SLIMRX1_PORT_STS_WIDTH 1 /* SLIMRX1_PORT_STS */
  3404. /*
  3405. * R1528 (0x5F8) - SLIMbus TX Port Status
  3406. */
  3407. #define ARIZONA_SLIMTX8_PORT_STS 0x0080 /* SLIMTX8_PORT_STS */
  3408. #define ARIZONA_SLIMTX8_PORT_STS_MASK 0x0080 /* SLIMTX8_PORT_STS */
  3409. #define ARIZONA_SLIMTX8_PORT_STS_SHIFT 7 /* SLIMTX8_PORT_STS */
  3410. #define ARIZONA_SLIMTX8_PORT_STS_WIDTH 1 /* SLIMTX8_PORT_STS */
  3411. #define ARIZONA_SLIMTX7_PORT_STS 0x0040 /* SLIMTX7_PORT_STS */
  3412. #define ARIZONA_SLIMTX7_PORT_STS_MASK 0x0040 /* SLIMTX7_PORT_STS */
  3413. #define ARIZONA_SLIMTX7_PORT_STS_SHIFT 6 /* SLIMTX7_PORT_STS */
  3414. #define ARIZONA_SLIMTX7_PORT_STS_WIDTH 1 /* SLIMTX7_PORT_STS */
  3415. #define ARIZONA_SLIMTX6_PORT_STS 0x0020 /* SLIMTX6_PORT_STS */
  3416. #define ARIZONA_SLIMTX6_PORT_STS_MASK 0x0020 /* SLIMTX6_PORT_STS */
  3417. #define ARIZONA_SLIMTX6_PORT_STS_SHIFT 5 /* SLIMTX6_PORT_STS */
  3418. #define ARIZONA_SLIMTX6_PORT_STS_WIDTH 1 /* SLIMTX6_PORT_STS */
  3419. #define ARIZONA_SLIMTX5_PORT_STS 0x0010 /* SLIMTX5_PORT_STS */
  3420. #define ARIZONA_SLIMTX5_PORT_STS_MASK 0x0010 /* SLIMTX5_PORT_STS */
  3421. #define ARIZONA_SLIMTX5_PORT_STS_SHIFT 4 /* SLIMTX5_PORT_STS */
  3422. #define ARIZONA_SLIMTX5_PORT_STS_WIDTH 1 /* SLIMTX5_PORT_STS */
  3423. #define ARIZONA_SLIMTX4_PORT_STS 0x0008 /* SLIMTX4_PORT_STS */
  3424. #define ARIZONA_SLIMTX4_PORT_STS_MASK 0x0008 /* SLIMTX4_PORT_STS */
  3425. #define ARIZONA_SLIMTX4_PORT_STS_SHIFT 3 /* SLIMTX4_PORT_STS */
  3426. #define ARIZONA_SLIMTX4_PORT_STS_WIDTH 1 /* SLIMTX4_PORT_STS */
  3427. #define ARIZONA_SLIMTX3_PORT_STS 0x0004 /* SLIMTX3_PORT_STS */
  3428. #define ARIZONA_SLIMTX3_PORT_STS_MASK 0x0004 /* SLIMTX3_PORT_STS */
  3429. #define ARIZONA_SLIMTX3_PORT_STS_SHIFT 2 /* SLIMTX3_PORT_STS */
  3430. #define ARIZONA_SLIMTX3_PORT_STS_WIDTH 1 /* SLIMTX3_PORT_STS */
  3431. #define ARIZONA_SLIMTX2_PORT_STS 0x0002 /* SLIMTX2_PORT_STS */
  3432. #define ARIZONA_SLIMTX2_PORT_STS_MASK 0x0002 /* SLIMTX2_PORT_STS */
  3433. #define ARIZONA_SLIMTX2_PORT_STS_SHIFT 1 /* SLIMTX2_PORT_STS */
  3434. #define ARIZONA_SLIMTX2_PORT_STS_WIDTH 1 /* SLIMTX2_PORT_STS */
  3435. #define ARIZONA_SLIMTX1_PORT_STS 0x0001 /* SLIMTX1_PORT_STS */
  3436. #define ARIZONA_SLIMTX1_PORT_STS_MASK 0x0001 /* SLIMTX1_PORT_STS */
  3437. #define ARIZONA_SLIMTX1_PORT_STS_SHIFT 0 /* SLIMTX1_PORT_STS */
  3438. #define ARIZONA_SLIMTX1_PORT_STS_WIDTH 1 /* SLIMTX1_PORT_STS */
  3439. /*
  3440. * R3087 (0xC0F) - IRQ CTRL 1
  3441. */
  3442. #define ARIZONA_IRQ_POL 0x0400 /* IRQ_POL */
  3443. #define ARIZONA_IRQ_POL_MASK 0x0400 /* IRQ_POL */
  3444. #define ARIZONA_IRQ_POL_SHIFT 10 /* IRQ_POL */
  3445. #define ARIZONA_IRQ_POL_WIDTH 1 /* IRQ_POL */
  3446. #define ARIZONA_IRQ_OP_CFG 0x0200 /* IRQ_OP_CFG */
  3447. #define ARIZONA_IRQ_OP_CFG_MASK 0x0200 /* IRQ_OP_CFG */
  3448. #define ARIZONA_IRQ_OP_CFG_SHIFT 9 /* IRQ_OP_CFG */
  3449. #define ARIZONA_IRQ_OP_CFG_WIDTH 1 /* IRQ_OP_CFG */
  3450. /*
  3451. * R3088 (0xC10) - GPIO Debounce Config
  3452. */
  3453. #define ARIZONA_GP_DBTIME_MASK 0xF000 /* GP_DBTIME - [15:12] */
  3454. #define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */
  3455. #define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */
  3456. /*
  3457. * R3104 (0xC20) - Misc Pad Ctrl 1
  3458. */
  3459. #define ARIZONA_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
  3460. #define ARIZONA_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
  3461. #define ARIZONA_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
  3462. #define ARIZONA_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
  3463. #define ARIZONA_MCLK2_PD 0x2000 /* MCLK2_PD */
  3464. #define ARIZONA_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
  3465. #define ARIZONA_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
  3466. #define ARIZONA_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
  3467. #define ARIZONA_RSTB_PU 0x0002 /* RSTB_PU */
  3468. #define ARIZONA_RSTB_PU_MASK 0x0002 /* RSTB_PU */
  3469. #define ARIZONA_RSTB_PU_SHIFT 1 /* RSTB_PU */
  3470. #define ARIZONA_RSTB_PU_WIDTH 1 /* RSTB_PU */
  3471. /*
  3472. * R3105 (0xC21) - Misc Pad Ctrl 2
  3473. */
  3474. #define ARIZONA_MCLK1_PD 0x1000 /* MCLK1_PD */
  3475. #define ARIZONA_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
  3476. #define ARIZONA_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
  3477. #define ARIZONA_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
  3478. #define ARIZONA_MICD_PD 0x0100 /* MICD_PD */
  3479. #define ARIZONA_MICD_PD_MASK 0x0100 /* MICD_PD */
  3480. #define ARIZONA_MICD_PD_SHIFT 8 /* MICD_PD */
  3481. #define ARIZONA_MICD_PD_WIDTH 1 /* MICD_PD */
  3482. #define ARIZONA_ADDR_PD 0x0001 /* ADDR_PD */
  3483. #define ARIZONA_ADDR_PD_MASK 0x0001 /* ADDR_PD */
  3484. #define ARIZONA_ADDR_PD_SHIFT 0 /* ADDR_PD */
  3485. #define ARIZONA_ADDR_PD_WIDTH 1 /* ADDR_PD */
  3486. /*
  3487. * R3106 (0xC22) - Misc Pad Ctrl 3
  3488. */
  3489. #define ARIZONA_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */
  3490. #define ARIZONA_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */
  3491. #define ARIZONA_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */
  3492. #define ARIZONA_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */
  3493. #define ARIZONA_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */
  3494. #define ARIZONA_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */
  3495. #define ARIZONA_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */
  3496. #define ARIZONA_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
  3497. #define ARIZONA_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */
  3498. #define ARIZONA_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */
  3499. #define ARIZONA_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */
  3500. #define ARIZONA_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
  3501. #define ARIZONA_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */
  3502. #define ARIZONA_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */
  3503. #define ARIZONA_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */
  3504. #define ARIZONA_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
  3505. /*
  3506. * R3107 (0xC23) - Misc Pad Ctrl 4
  3507. */
  3508. #define ARIZONA_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */
  3509. #define ARIZONA_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */
  3510. #define ARIZONA_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */
  3511. #define ARIZONA_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */
  3512. #define ARIZONA_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */
  3513. #define ARIZONA_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */
  3514. #define ARIZONA_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */
  3515. #define ARIZONA_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */
  3516. #define ARIZONA_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */
  3517. #define ARIZONA_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */
  3518. #define ARIZONA_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */
  3519. #define ARIZONA_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */
  3520. #define ARIZONA_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */
  3521. #define ARIZONA_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */
  3522. #define ARIZONA_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */
  3523. #define ARIZONA_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */
  3524. #define ARIZONA_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */
  3525. #define ARIZONA_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */
  3526. #define ARIZONA_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */
  3527. #define ARIZONA_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */
  3528. #define ARIZONA_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */
  3529. #define ARIZONA_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */
  3530. #define ARIZONA_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */
  3531. #define ARIZONA_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */
  3532. /*
  3533. * R3108 (0xC24) - Misc Pad Ctrl 5
  3534. */
  3535. #define ARIZONA_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */
  3536. #define ARIZONA_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */
  3537. #define ARIZONA_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */
  3538. #define ARIZONA_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */
  3539. #define ARIZONA_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */
  3540. #define ARIZONA_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */
  3541. #define ARIZONA_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */
  3542. #define ARIZONA_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */
  3543. #define ARIZONA_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */
  3544. #define ARIZONA_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */
  3545. #define ARIZONA_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */
  3546. #define ARIZONA_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */
  3547. #define ARIZONA_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */
  3548. #define ARIZONA_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */
  3549. #define ARIZONA_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */
  3550. #define ARIZONA_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */
  3551. #define ARIZONA_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */
  3552. #define ARIZONA_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */
  3553. #define ARIZONA_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */
  3554. #define ARIZONA_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */
  3555. #define ARIZONA_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */
  3556. #define ARIZONA_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */
  3557. #define ARIZONA_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */
  3558. #define ARIZONA_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */
  3559. /*
  3560. * R3109 (0xC25) - Misc Pad Ctrl 6
  3561. */
  3562. #define ARIZONA_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */
  3563. #define ARIZONA_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */
  3564. #define ARIZONA_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */
  3565. #define ARIZONA_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */
  3566. #define ARIZONA_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */
  3567. #define ARIZONA_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */
  3568. #define ARIZONA_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */
  3569. #define ARIZONA_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */
  3570. #define ARIZONA_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */
  3571. #define ARIZONA_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */
  3572. #define ARIZONA_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */
  3573. #define ARIZONA_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */
  3574. #define ARIZONA_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */
  3575. #define ARIZONA_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */
  3576. #define ARIZONA_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */
  3577. #define ARIZONA_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */
  3578. #define ARIZONA_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */
  3579. #define ARIZONA_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */
  3580. #define ARIZONA_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */
  3581. #define ARIZONA_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */
  3582. #define ARIZONA_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */
  3583. #define ARIZONA_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */
  3584. #define ARIZONA_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */
  3585. #define ARIZONA_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */
  3586. /*
  3587. * R3328 (0xD00) - Interrupt Status 1
  3588. */
  3589. #define ARIZONA_GP4_EINT1 0x0008 /* GP4_EINT1 */
  3590. #define ARIZONA_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */
  3591. #define ARIZONA_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */
  3592. #define ARIZONA_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */
  3593. #define ARIZONA_GP3_EINT1 0x0004 /* GP3_EINT1 */
  3594. #define ARIZONA_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */
  3595. #define ARIZONA_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */
  3596. #define ARIZONA_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */
  3597. #define ARIZONA_GP2_EINT1 0x0002 /* GP2_EINT1 */
  3598. #define ARIZONA_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */
  3599. #define ARIZONA_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */
  3600. #define ARIZONA_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */
  3601. #define ARIZONA_GP1_EINT1 0x0001 /* GP1_EINT1 */
  3602. #define ARIZONA_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */
  3603. #define ARIZONA_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */
  3604. #define ARIZONA_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */
  3605. /*
  3606. * R3329 (0xD01) - Interrupt Status 2
  3607. */
  3608. #define ARIZONA_DSP1_RAM_RDY_EINT1 0x0100 /* DSP1_RAM_RDY_EINT1 */
  3609. #define ARIZONA_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* DSP1_RAM_RDY_EINT1 */
  3610. #define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT 8 /* DSP1_RAM_RDY_EINT1 */
  3611. #define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH 1 /* DSP1_RAM_RDY_EINT1 */
  3612. #define ARIZONA_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */
  3613. #define ARIZONA_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */
  3614. #define ARIZONA_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */
  3615. #define ARIZONA_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */
  3616. #define ARIZONA_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */
  3617. #define ARIZONA_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */
  3618. #define ARIZONA_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */
  3619. #define ARIZONA_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */
  3620. /*
  3621. * R3330 (0xD02) - Interrupt Status 3
  3622. */
  3623. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
  3624. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
  3625. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */
  3626. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */
  3627. #define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */
  3628. #define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */
  3629. #define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */
  3630. #define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */
  3631. #define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */
  3632. #define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */
  3633. #define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */
  3634. #define ARIZONA_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */
  3635. #define ARIZONA_MICDET_EINT1 0x1000 /* MICDET_EINT1 */
  3636. #define ARIZONA_MICDET_EINT1_MASK 0x1000 /* MICDET_EINT1 */
  3637. #define ARIZONA_MICDET_EINT1_SHIFT 12 /* MICDET_EINT1 */
  3638. #define ARIZONA_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */
  3639. #define ARIZONA_WSEQ_DONE_EINT1 0x0800 /* WSEQ_DONE_EINT1 */
  3640. #define ARIZONA_WSEQ_DONE_EINT1_MASK 0x0800 /* WSEQ_DONE_EINT1 */
  3641. #define ARIZONA_WSEQ_DONE_EINT1_SHIFT 11 /* WSEQ_DONE_EINT1 */
  3642. #define ARIZONA_WSEQ_DONE_EINT1_WIDTH 1 /* WSEQ_DONE_EINT1 */
  3643. #define ARIZONA_DRC2_SIG_DET_EINT1 0x0400 /* DRC2_SIG_DET_EINT1 */
  3644. #define ARIZONA_DRC2_SIG_DET_EINT1_MASK 0x0400 /* DRC2_SIG_DET_EINT1 */
  3645. #define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT 10 /* DRC2_SIG_DET_EINT1 */
  3646. #define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */
  3647. #define ARIZONA_DRC1_SIG_DET_EINT1 0x0200 /* DRC1_SIG_DET_EINT1 */
  3648. #define ARIZONA_DRC1_SIG_DET_EINT1_MASK 0x0200 /* DRC1_SIG_DET_EINT1 */
  3649. #define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT 9 /* DRC1_SIG_DET_EINT1 */
  3650. #define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */
  3651. #define ARIZONA_ASRC2_LOCK_EINT1 0x0100 /* ASRC2_LOCK_EINT1 */
  3652. #define ARIZONA_ASRC2_LOCK_EINT1_MASK 0x0100 /* ASRC2_LOCK_EINT1 */
  3653. #define ARIZONA_ASRC2_LOCK_EINT1_SHIFT 8 /* ASRC2_LOCK_EINT1 */
  3654. #define ARIZONA_ASRC2_LOCK_EINT1_WIDTH 1 /* ASRC2_LOCK_EINT1 */
  3655. #define ARIZONA_ASRC1_LOCK_EINT1 0x0080 /* ASRC1_LOCK_EINT1 */
  3656. #define ARIZONA_ASRC1_LOCK_EINT1_MASK 0x0080 /* ASRC1_LOCK_EINT1 */
  3657. #define ARIZONA_ASRC1_LOCK_EINT1_SHIFT 7 /* ASRC1_LOCK_EINT1 */
  3658. #define ARIZONA_ASRC1_LOCK_EINT1_WIDTH 1 /* ASRC1_LOCK_EINT1 */
  3659. #define ARIZONA_UNDERCLOCKED_EINT1 0x0040 /* UNDERCLOCKED_EINT1 */
  3660. #define ARIZONA_UNDERCLOCKED_EINT1_MASK 0x0040 /* UNDERCLOCKED_EINT1 */
  3661. #define ARIZONA_UNDERCLOCKED_EINT1_SHIFT 6 /* UNDERCLOCKED_EINT1 */
  3662. #define ARIZONA_UNDERCLOCKED_EINT1_WIDTH 1 /* UNDERCLOCKED_EINT1 */
  3663. #define ARIZONA_OVERCLOCKED_EINT1 0x0020 /* OVERCLOCKED_EINT1 */
  3664. #define ARIZONA_OVERCLOCKED_EINT1_MASK 0x0020 /* OVERCLOCKED_EINT1 */
  3665. #define ARIZONA_OVERCLOCKED_EINT1_SHIFT 5 /* OVERCLOCKED_EINT1 */
  3666. #define ARIZONA_OVERCLOCKED_EINT1_WIDTH 1 /* OVERCLOCKED_EINT1 */
  3667. #define ARIZONA_FLL2_LOCK_EINT1 0x0008 /* FLL2_LOCK_EINT1 */
  3668. #define ARIZONA_FLL2_LOCK_EINT1_MASK 0x0008 /* FLL2_LOCK_EINT1 */
  3669. #define ARIZONA_FLL2_LOCK_EINT1_SHIFT 3 /* FLL2_LOCK_EINT1 */
  3670. #define ARIZONA_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */
  3671. #define ARIZONA_FLL1_LOCK_EINT1 0x0004 /* FLL1_LOCK_EINT1 */
  3672. #define ARIZONA_FLL1_LOCK_EINT1_MASK 0x0004 /* FLL1_LOCK_EINT1 */
  3673. #define ARIZONA_FLL1_LOCK_EINT1_SHIFT 2 /* FLL1_LOCK_EINT1 */
  3674. #define ARIZONA_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */
  3675. #define ARIZONA_CLKGEN_ERR_EINT1 0x0002 /* CLKGEN_ERR_EINT1 */
  3676. #define ARIZONA_CLKGEN_ERR_EINT1_MASK 0x0002 /* CLKGEN_ERR_EINT1 */
  3677. #define ARIZONA_CLKGEN_ERR_EINT1_SHIFT 1 /* CLKGEN_ERR_EINT1 */
  3678. #define ARIZONA_CLKGEN_ERR_EINT1_WIDTH 1 /* CLKGEN_ERR_EINT1 */
  3679. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
  3680. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
  3681. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT1 */
  3682. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT1 */
  3683. /*
  3684. * R3331 (0xD03) - Interrupt Status 4
  3685. */
  3686. #define ARIZONA_ASRC_CFG_ERR_EINT1 0x8000 /* ASRC_CFG_ERR_EINT1 */
  3687. #define ARIZONA_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* ASRC_CFG_ERR_EINT1 */
  3688. #define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT 15 /* ASRC_CFG_ERR_EINT1 */
  3689. #define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */
  3690. #define ARIZONA_AIF3_ERR_EINT1 0x4000 /* AIF3_ERR_EINT1 */
  3691. #define ARIZONA_AIF3_ERR_EINT1_MASK 0x4000 /* AIF3_ERR_EINT1 */
  3692. #define ARIZONA_AIF3_ERR_EINT1_SHIFT 14 /* AIF3_ERR_EINT1 */
  3693. #define ARIZONA_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */
  3694. #define ARIZONA_AIF2_ERR_EINT1 0x2000 /* AIF2_ERR_EINT1 */
  3695. #define ARIZONA_AIF2_ERR_EINT1_MASK 0x2000 /* AIF2_ERR_EINT1 */
  3696. #define ARIZONA_AIF2_ERR_EINT1_SHIFT 13 /* AIF2_ERR_EINT1 */
  3697. #define ARIZONA_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */
  3698. #define ARIZONA_AIF1_ERR_EINT1 0x1000 /* AIF1_ERR_EINT1 */
  3699. #define ARIZONA_AIF1_ERR_EINT1_MASK 0x1000 /* AIF1_ERR_EINT1 */
  3700. #define ARIZONA_AIF1_ERR_EINT1_SHIFT 12 /* AIF1_ERR_EINT1 */
  3701. #define ARIZONA_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */
  3702. #define ARIZONA_CTRLIF_ERR_EINT1 0x0800 /* CTRLIF_ERR_EINT1 */
  3703. #define ARIZONA_CTRLIF_ERR_EINT1_MASK 0x0800 /* CTRLIF_ERR_EINT1 */
  3704. #define ARIZONA_CTRLIF_ERR_EINT1_SHIFT 11 /* CTRLIF_ERR_EINT1 */
  3705. #define ARIZONA_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */
  3706. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
  3707. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
  3708. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT1 */
  3709. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */
  3710. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
  3711. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
  3712. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT1 */
  3713. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */
  3714. #define ARIZONA_SYSCLK_ENA_LOW_EINT1 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
  3715. #define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
  3716. #define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* SYSCLK_ENA_LOW_EINT1 */
  3717. #define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */
  3718. #define ARIZONA_ISRC1_CFG_ERR_EINT1 0x0080 /* ISRC1_CFG_ERR_EINT1 */
  3719. #define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* ISRC1_CFG_ERR_EINT1 */
  3720. #define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* ISRC1_CFG_ERR_EINT1 */
  3721. #define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */
  3722. #define ARIZONA_ISRC2_CFG_ERR_EINT1 0x0040 /* ISRC2_CFG_ERR_EINT1 */
  3723. #define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */
  3724. #define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */
  3725. #define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */
  3726. /*
  3727. * R3332 (0xD04) - Interrupt Status 5
  3728. */
  3729. #define ARIZONA_BOOT_DONE_EINT1 0x0100 /* BOOT_DONE_EINT1 */
  3730. #define ARIZONA_BOOT_DONE_EINT1_MASK 0x0100 /* BOOT_DONE_EINT1 */
  3731. #define ARIZONA_BOOT_DONE_EINT1_SHIFT 8 /* BOOT_DONE_EINT1 */
  3732. #define ARIZONA_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */
  3733. #define ARIZONA_DCS_DAC_DONE_EINT1 0x0080 /* DCS_DAC_DONE_EINT1 */
  3734. #define ARIZONA_DCS_DAC_DONE_EINT1_MASK 0x0080 /* DCS_DAC_DONE_EINT1 */
  3735. #define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT 7 /* DCS_DAC_DONE_EINT1 */
  3736. #define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH 1 /* DCS_DAC_DONE_EINT1 */
  3737. #define ARIZONA_DCS_HP_DONE_EINT1 0x0040 /* DCS_HP_DONE_EINT1 */
  3738. #define ARIZONA_DCS_HP_DONE_EINT1_MASK 0x0040 /* DCS_HP_DONE_EINT1 */
  3739. #define ARIZONA_DCS_HP_DONE_EINT1_SHIFT 6 /* DCS_HP_DONE_EINT1 */
  3740. #define ARIZONA_DCS_HP_DONE_EINT1_WIDTH 1 /* DCS_HP_DONE_EINT1 */
  3741. #define ARIZONA_FLL2_CLOCK_OK_EINT1 0x0002 /* FLL2_CLOCK_OK_EINT1 */
  3742. #define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* FLL2_CLOCK_OK_EINT1 */
  3743. #define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* FLL2_CLOCK_OK_EINT1 */
  3744. #define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* FLL2_CLOCK_OK_EINT1 */
  3745. #define ARIZONA_FLL1_CLOCK_OK_EINT1 0x0001 /* FLL1_CLOCK_OK_EINT1 */
  3746. #define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* FLL1_CLOCK_OK_EINT1 */
  3747. #define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */
  3748. #define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */
  3749. /*
  3750. * R3336 (0xD08) - Interrupt Status 1 Mask
  3751. */
  3752. #define ARIZONA_IM_GP4_EINT1 0x0008 /* IM_GP4_EINT1 */
  3753. #define ARIZONA_IM_GP4_EINT1_MASK 0x0008 /* IM_GP4_EINT1 */
  3754. #define ARIZONA_IM_GP4_EINT1_SHIFT 3 /* IM_GP4_EINT1 */
  3755. #define ARIZONA_IM_GP4_EINT1_WIDTH 1 /* IM_GP4_EINT1 */
  3756. #define ARIZONA_IM_GP3_EINT1 0x0004 /* IM_GP3_EINT1 */
  3757. #define ARIZONA_IM_GP3_EINT1_MASK 0x0004 /* IM_GP3_EINT1 */
  3758. #define ARIZONA_IM_GP3_EINT1_SHIFT 2 /* IM_GP3_EINT1 */
  3759. #define ARIZONA_IM_GP3_EINT1_WIDTH 1 /* IM_GP3_EINT1 */
  3760. #define ARIZONA_IM_GP2_EINT1 0x0002 /* IM_GP2_EINT1 */
  3761. #define ARIZONA_IM_GP2_EINT1_MASK 0x0002 /* IM_GP2_EINT1 */
  3762. #define ARIZONA_IM_GP2_EINT1_SHIFT 1 /* IM_GP2_EINT1 */
  3763. #define ARIZONA_IM_GP2_EINT1_WIDTH 1 /* IM_GP2_EINT1 */
  3764. #define ARIZONA_IM_GP1_EINT1 0x0001 /* IM_GP1_EINT1 */
  3765. #define ARIZONA_IM_GP1_EINT1_MASK 0x0001 /* IM_GP1_EINT1 */
  3766. #define ARIZONA_IM_GP1_EINT1_SHIFT 0 /* IM_GP1_EINT1 */
  3767. #define ARIZONA_IM_GP1_EINT1_WIDTH 1 /* IM_GP1_EINT1 */
  3768. /*
  3769. * R3337 (0xD09) - Interrupt Status 2 Mask
  3770. */
  3771. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
  3772. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
  3773. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT1 */
  3774. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT1 */
  3775. #define ARIZONA_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */
  3776. #define ARIZONA_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */
  3777. #define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */
  3778. #define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */
  3779. #define ARIZONA_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */
  3780. #define ARIZONA_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */
  3781. #define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */
  3782. #define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */
  3783. /*
  3784. * R3338 (0xD0A) - Interrupt Status 3 Mask
  3785. */
  3786. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  3787. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  3788. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  3789. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  3790. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
  3791. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
  3792. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */
  3793. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */
  3794. #define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */
  3795. #define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */
  3796. #define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */
  3797. #define ARIZONA_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */
  3798. #define ARIZONA_IM_MICDET_EINT1 0x1000 /* IM_MICDET_EINT1 */
  3799. #define ARIZONA_IM_MICDET_EINT1_MASK 0x1000 /* IM_MICDET_EINT1 */
  3800. #define ARIZONA_IM_MICDET_EINT1_SHIFT 12 /* IM_MICDET_EINT1 */
  3801. #define ARIZONA_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */
  3802. #define ARIZONA_IM_WSEQ_DONE_EINT1 0x0800 /* IM_WSEQ_DONE_EINT1 */
  3803. #define ARIZONA_IM_WSEQ_DONE_EINT1_MASK 0x0800 /* IM_WSEQ_DONE_EINT1 */
  3804. #define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT 11 /* IM_WSEQ_DONE_EINT1 */
  3805. #define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH 1 /* IM_WSEQ_DONE_EINT1 */
  3806. #define ARIZONA_IM_DRC2_SIG_DET_EINT1 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
  3807. #define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
  3808. #define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT 10 /* IM_DRC2_SIG_DET_EINT1 */
  3809. #define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */
  3810. #define ARIZONA_IM_DRC1_SIG_DET_EINT1 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
  3811. #define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
  3812. #define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT 9 /* IM_DRC1_SIG_DET_EINT1 */
  3813. #define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */
  3814. #define ARIZONA_IM_ASRC2_LOCK_EINT1 0x0100 /* IM_ASRC2_LOCK_EINT1 */
  3815. #define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK 0x0100 /* IM_ASRC2_LOCK_EINT1 */
  3816. #define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT 8 /* IM_ASRC2_LOCK_EINT1 */
  3817. #define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_LOCK_EINT1 */
  3818. #define ARIZONA_IM_ASRC1_LOCK_EINT1 0x0080 /* IM_ASRC1_LOCK_EINT1 */
  3819. #define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK 0x0080 /* IM_ASRC1_LOCK_EINT1 */
  3820. #define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT 7 /* IM_ASRC1_LOCK_EINT1 */
  3821. #define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_LOCK_EINT1 */
  3822. #define ARIZONA_IM_UNDERCLOCKED_EINT1 0x0040 /* IM_UNDERCLOCKED_EINT1 */
  3823. #define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK 0x0040 /* IM_UNDERCLOCKED_EINT1 */
  3824. #define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT 6 /* IM_UNDERCLOCKED_EINT1 */
  3825. #define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH 1 /* IM_UNDERCLOCKED_EINT1 */
  3826. #define ARIZONA_IM_OVERCLOCKED_EINT1 0x0020 /* IM_OVERCLOCKED_EINT1 */
  3827. #define ARIZONA_IM_OVERCLOCKED_EINT1_MASK 0x0020 /* IM_OVERCLOCKED_EINT1 */
  3828. #define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT 5 /* IM_OVERCLOCKED_EINT1 */
  3829. #define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH 1 /* IM_OVERCLOCKED_EINT1 */
  3830. #define ARIZONA_IM_FLL2_LOCK_EINT1 0x0008 /* IM_FLL2_LOCK_EINT1 */
  3831. #define ARIZONA_IM_FLL2_LOCK_EINT1_MASK 0x0008 /* IM_FLL2_LOCK_EINT1 */
  3832. #define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT 3 /* IM_FLL2_LOCK_EINT1 */
  3833. #define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */
  3834. #define ARIZONA_IM_FLL1_LOCK_EINT1 0x0004 /* IM_FLL1_LOCK_EINT1 */
  3835. #define ARIZONA_IM_FLL1_LOCK_EINT1_MASK 0x0004 /* IM_FLL1_LOCK_EINT1 */
  3836. #define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT 2 /* IM_FLL1_LOCK_EINT1 */
  3837. #define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */
  3838. #define ARIZONA_IM_CLKGEN_ERR_EINT1 0x0002 /* IM_CLKGEN_ERR_EINT1 */
  3839. #define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK 0x0002 /* IM_CLKGEN_ERR_EINT1 */
  3840. #define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT 1 /* IM_CLKGEN_ERR_EINT1 */
  3841. #define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_EINT1 */
  3842. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  3843. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  3844. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  3845. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  3846. /*
  3847. * R3339 (0xD0B) - Interrupt Status 4 Mask
  3848. */
  3849. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
  3850. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
  3851. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */
  3852. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */
  3853. #define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */
  3854. #define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */
  3855. #define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */
  3856. #define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */
  3857. #define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */
  3858. #define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */
  3859. #define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */
  3860. #define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */
  3861. #define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */
  3862. #define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */
  3863. #define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */
  3864. #define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */
  3865. #define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */
  3866. #define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */
  3867. #define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */
  3868. #define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */
  3869. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  3870. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  3871. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  3872. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  3873. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  3874. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  3875. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  3876. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  3877. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
  3878. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
  3879. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */
  3880. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */
  3881. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
  3882. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
  3883. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */
  3884. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */
  3885. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
  3886. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
  3887. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */
  3888. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */
  3889. /*
  3890. * R3340 (0xD0C) - Interrupt Status 5 Mask
  3891. */
  3892. #define ARIZONA_IM_BOOT_DONE_EINT1 0x0100 /* IM_BOOT_DONE_EINT1 */
  3893. #define ARIZONA_IM_BOOT_DONE_EINT1_MASK 0x0100 /* IM_BOOT_DONE_EINT1 */
  3894. #define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT 8 /* IM_BOOT_DONE_EINT1 */
  3895. #define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */
  3896. #define ARIZONA_IM_DCS_DAC_DONE_EINT1 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
  3897. #define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
  3898. #define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT 7 /* IM_DCS_DAC_DONE_EINT1 */
  3899. #define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH 1 /* IM_DCS_DAC_DONE_EINT1 */
  3900. #define ARIZONA_IM_DCS_HP_DONE_EINT1 0x0040 /* IM_DCS_HP_DONE_EINT1 */
  3901. #define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK 0x0040 /* IM_DCS_HP_DONE_EINT1 */
  3902. #define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT 6 /* IM_DCS_HP_DONE_EINT1 */
  3903. #define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH 1 /* IM_DCS_HP_DONE_EINT1 */
  3904. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
  3905. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
  3906. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT1 */
  3907. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT1 */
  3908. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
  3909. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
  3910. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */
  3911. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */
  3912. /*
  3913. * R3343 (0xD0F) - Interrupt Control
  3914. */
  3915. #define ARIZONA_IM_IRQ1 0x0001 /* IM_IRQ1 */
  3916. #define ARIZONA_IM_IRQ1_MASK 0x0001 /* IM_IRQ1 */
  3917. #define ARIZONA_IM_IRQ1_SHIFT 0 /* IM_IRQ1 */
  3918. #define ARIZONA_IM_IRQ1_WIDTH 1 /* IM_IRQ1 */
  3919. /*
  3920. * R3344 (0xD10) - IRQ2 Status 1
  3921. */
  3922. #define ARIZONA_GP4_EINT2 0x0008 /* GP4_EINT2 */
  3923. #define ARIZONA_GP4_EINT2_MASK 0x0008 /* GP4_EINT2 */
  3924. #define ARIZONA_GP4_EINT2_SHIFT 3 /* GP4_EINT2 */
  3925. #define ARIZONA_GP4_EINT2_WIDTH 1 /* GP4_EINT2 */
  3926. #define ARIZONA_GP3_EINT2 0x0004 /* GP3_EINT2 */
  3927. #define ARIZONA_GP3_EINT2_MASK 0x0004 /* GP3_EINT2 */
  3928. #define ARIZONA_GP3_EINT2_SHIFT 2 /* GP3_EINT2 */
  3929. #define ARIZONA_GP3_EINT2_WIDTH 1 /* GP3_EINT2 */
  3930. #define ARIZONA_GP2_EINT2 0x0002 /* GP2_EINT2 */
  3931. #define ARIZONA_GP2_EINT2_MASK 0x0002 /* GP2_EINT2 */
  3932. #define ARIZONA_GP2_EINT2_SHIFT 1 /* GP2_EINT2 */
  3933. #define ARIZONA_GP2_EINT2_WIDTH 1 /* GP2_EINT2 */
  3934. #define ARIZONA_GP1_EINT2 0x0001 /* GP1_EINT2 */
  3935. #define ARIZONA_GP1_EINT2_MASK 0x0001 /* GP1_EINT2 */
  3936. #define ARIZONA_GP1_EINT2_SHIFT 0 /* GP1_EINT2 */
  3937. #define ARIZONA_GP1_EINT2_WIDTH 1 /* GP1_EINT2 */
  3938. /*
  3939. * R3345 (0xD11) - IRQ2 Status 2
  3940. */
  3941. #define ARIZONA_DSP1_RAM_RDY_EINT2 0x0100 /* DSP1_RAM_RDY_EINT2 */
  3942. #define ARIZONA_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* DSP1_RAM_RDY_EINT2 */
  3943. #define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT 8 /* DSP1_RAM_RDY_EINT2 */
  3944. #define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH 1 /* DSP1_RAM_RDY_EINT2 */
  3945. #define ARIZONA_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */
  3946. #define ARIZONA_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */
  3947. #define ARIZONA_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */
  3948. #define ARIZONA_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */
  3949. #define ARIZONA_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */
  3950. #define ARIZONA_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */
  3951. #define ARIZONA_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */
  3952. #define ARIZONA_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */
  3953. /*
  3954. * R3346 (0xD12) - IRQ2 Status 3
  3955. */
  3956. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
  3957. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
  3958. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */
  3959. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */
  3960. #define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */
  3961. #define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */
  3962. #define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */
  3963. #define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */
  3964. #define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */
  3965. #define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */
  3966. #define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */
  3967. #define ARIZONA_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */
  3968. #define ARIZONA_MICDET_EINT2 0x1000 /* MICDET_EINT2 */
  3969. #define ARIZONA_MICDET_EINT2_MASK 0x1000 /* MICDET_EINT2 */
  3970. #define ARIZONA_MICDET_EINT2_SHIFT 12 /* MICDET_EINT2 */
  3971. #define ARIZONA_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */
  3972. #define ARIZONA_WSEQ_DONE_EINT2 0x0800 /* WSEQ_DONE_EINT2 */
  3973. #define ARIZONA_WSEQ_DONE_EINT2_MASK 0x0800 /* WSEQ_DONE_EINT2 */
  3974. #define ARIZONA_WSEQ_DONE_EINT2_SHIFT 11 /* WSEQ_DONE_EINT2 */
  3975. #define ARIZONA_WSEQ_DONE_EINT2_WIDTH 1 /* WSEQ_DONE_EINT2 */
  3976. #define ARIZONA_DRC2_SIG_DET_EINT2 0x0400 /* DRC2_SIG_DET_EINT2 */
  3977. #define ARIZONA_DRC2_SIG_DET_EINT2_MASK 0x0400 /* DRC2_SIG_DET_EINT2 */
  3978. #define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT 10 /* DRC2_SIG_DET_EINT2 */
  3979. #define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */
  3980. #define ARIZONA_DRC1_SIG_DET_EINT2 0x0200 /* DRC1_SIG_DET_EINT2 */
  3981. #define ARIZONA_DRC1_SIG_DET_EINT2_MASK 0x0200 /* DRC1_SIG_DET_EINT2 */
  3982. #define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT 9 /* DRC1_SIG_DET_EINT2 */
  3983. #define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */
  3984. #define ARIZONA_ASRC2_LOCK_EINT2 0x0100 /* ASRC2_LOCK_EINT2 */
  3985. #define ARIZONA_ASRC2_LOCK_EINT2_MASK 0x0100 /* ASRC2_LOCK_EINT2 */
  3986. #define ARIZONA_ASRC2_LOCK_EINT2_SHIFT 8 /* ASRC2_LOCK_EINT2 */
  3987. #define ARIZONA_ASRC2_LOCK_EINT2_WIDTH 1 /* ASRC2_LOCK_EINT2 */
  3988. #define ARIZONA_ASRC1_LOCK_EINT2 0x0080 /* ASRC1_LOCK_EINT2 */
  3989. #define ARIZONA_ASRC1_LOCK_EINT2_MASK 0x0080 /* ASRC1_LOCK_EINT2 */
  3990. #define ARIZONA_ASRC1_LOCK_EINT2_SHIFT 7 /* ASRC1_LOCK_EINT2 */
  3991. #define ARIZONA_ASRC1_LOCK_EINT2_WIDTH 1 /* ASRC1_LOCK_EINT2 */
  3992. #define ARIZONA_UNDERCLOCKED_EINT2 0x0040 /* UNDERCLOCKED_EINT2 */
  3993. #define ARIZONA_UNDERCLOCKED_EINT2_MASK 0x0040 /* UNDERCLOCKED_EINT2 */
  3994. #define ARIZONA_UNDERCLOCKED_EINT2_SHIFT 6 /* UNDERCLOCKED_EINT2 */
  3995. #define ARIZONA_UNDERCLOCKED_EINT2_WIDTH 1 /* UNDERCLOCKED_EINT2 */
  3996. #define ARIZONA_OVERCLOCKED_EINT2 0x0020 /* OVERCLOCKED_EINT2 */
  3997. #define ARIZONA_OVERCLOCKED_EINT2_MASK 0x0020 /* OVERCLOCKED_EINT2 */
  3998. #define ARIZONA_OVERCLOCKED_EINT2_SHIFT 5 /* OVERCLOCKED_EINT2 */
  3999. #define ARIZONA_OVERCLOCKED_EINT2_WIDTH 1 /* OVERCLOCKED_EINT2 */
  4000. #define ARIZONA_FLL2_LOCK_EINT2 0x0008 /* FLL2_LOCK_EINT2 */
  4001. #define ARIZONA_FLL2_LOCK_EINT2_MASK 0x0008 /* FLL2_LOCK_EINT2 */
  4002. #define ARIZONA_FLL2_LOCK_EINT2_SHIFT 3 /* FLL2_LOCK_EINT2 */
  4003. #define ARIZONA_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */
  4004. #define ARIZONA_FLL1_LOCK_EINT2 0x0004 /* FLL1_LOCK_EINT2 */
  4005. #define ARIZONA_FLL1_LOCK_EINT2_MASK 0x0004 /* FLL1_LOCK_EINT2 */
  4006. #define ARIZONA_FLL1_LOCK_EINT2_SHIFT 2 /* FLL1_LOCK_EINT2 */
  4007. #define ARIZONA_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */
  4008. #define ARIZONA_CLKGEN_ERR_EINT2 0x0002 /* CLKGEN_ERR_EINT2 */
  4009. #define ARIZONA_CLKGEN_ERR_EINT2_MASK 0x0002 /* CLKGEN_ERR_EINT2 */
  4010. #define ARIZONA_CLKGEN_ERR_EINT2_SHIFT 1 /* CLKGEN_ERR_EINT2 */
  4011. #define ARIZONA_CLKGEN_ERR_EINT2_WIDTH 1 /* CLKGEN_ERR_EINT2 */
  4012. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
  4013. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
  4014. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT2 */
  4015. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT2 */
  4016. /*
  4017. * R3347 (0xD13) - IRQ2 Status 4
  4018. */
  4019. #define ARIZONA_ASRC_CFG_ERR_EINT2 0x8000 /* ASRC_CFG_ERR_EINT2 */
  4020. #define ARIZONA_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* ASRC_CFG_ERR_EINT2 */
  4021. #define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT 15 /* ASRC_CFG_ERR_EINT2 */
  4022. #define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */
  4023. #define ARIZONA_AIF3_ERR_EINT2 0x4000 /* AIF3_ERR_EINT2 */
  4024. #define ARIZONA_AIF3_ERR_EINT2_MASK 0x4000 /* AIF3_ERR_EINT2 */
  4025. #define ARIZONA_AIF3_ERR_EINT2_SHIFT 14 /* AIF3_ERR_EINT2 */
  4026. #define ARIZONA_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */
  4027. #define ARIZONA_AIF2_ERR_EINT2 0x2000 /* AIF2_ERR_EINT2 */
  4028. #define ARIZONA_AIF2_ERR_EINT2_MASK 0x2000 /* AIF2_ERR_EINT2 */
  4029. #define ARIZONA_AIF2_ERR_EINT2_SHIFT 13 /* AIF2_ERR_EINT2 */
  4030. #define ARIZONA_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */
  4031. #define ARIZONA_AIF1_ERR_EINT2 0x1000 /* AIF1_ERR_EINT2 */
  4032. #define ARIZONA_AIF1_ERR_EINT2_MASK 0x1000 /* AIF1_ERR_EINT2 */
  4033. #define ARIZONA_AIF1_ERR_EINT2_SHIFT 12 /* AIF1_ERR_EINT2 */
  4034. #define ARIZONA_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */
  4035. #define ARIZONA_CTRLIF_ERR_EINT2 0x0800 /* CTRLIF_ERR_EINT2 */
  4036. #define ARIZONA_CTRLIF_ERR_EINT2_MASK 0x0800 /* CTRLIF_ERR_EINT2 */
  4037. #define ARIZONA_CTRLIF_ERR_EINT2_SHIFT 11 /* CTRLIF_ERR_EINT2 */
  4038. #define ARIZONA_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */
  4039. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4040. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4041. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4042. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4043. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4044. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4045. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4046. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4047. #define ARIZONA_SYSCLK_ENA_LOW_EINT2 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
  4048. #define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
  4049. #define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* SYSCLK_ENA_LOW_EINT2 */
  4050. #define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */
  4051. #define ARIZONA_ISRC1_CFG_ERR_EINT2 0x0080 /* ISRC1_CFG_ERR_EINT2 */
  4052. #define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* ISRC1_CFG_ERR_EINT2 */
  4053. #define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* ISRC1_CFG_ERR_EINT2 */
  4054. #define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */
  4055. #define ARIZONA_ISRC2_CFG_ERR_EINT2 0x0040 /* ISRC2_CFG_ERR_EINT2 */
  4056. #define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */
  4057. #define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */
  4058. #define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */
  4059. /*
  4060. * R3348 (0xD14) - IRQ2 Status 5
  4061. */
  4062. #define ARIZONA_BOOT_DONE_EINT2 0x0100 /* BOOT_DONE_EINT2 */
  4063. #define ARIZONA_BOOT_DONE_EINT2_MASK 0x0100 /* BOOT_DONE_EINT2 */
  4064. #define ARIZONA_BOOT_DONE_EINT2_SHIFT 8 /* BOOT_DONE_EINT2 */
  4065. #define ARIZONA_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */
  4066. #define ARIZONA_DCS_DAC_DONE_EINT2 0x0080 /* DCS_DAC_DONE_EINT2 */
  4067. #define ARIZONA_DCS_DAC_DONE_EINT2_MASK 0x0080 /* DCS_DAC_DONE_EINT2 */
  4068. #define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT 7 /* DCS_DAC_DONE_EINT2 */
  4069. #define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH 1 /* DCS_DAC_DONE_EINT2 */
  4070. #define ARIZONA_DCS_HP_DONE_EINT2 0x0040 /* DCS_HP_DONE_EINT2 */
  4071. #define ARIZONA_DCS_HP_DONE_EINT2_MASK 0x0040 /* DCS_HP_DONE_EINT2 */
  4072. #define ARIZONA_DCS_HP_DONE_EINT2_SHIFT 6 /* DCS_HP_DONE_EINT2 */
  4073. #define ARIZONA_DCS_HP_DONE_EINT2_WIDTH 1 /* DCS_HP_DONE_EINT2 */
  4074. #define ARIZONA_FLL2_CLOCK_OK_EINT2 0x0002 /* FLL2_CLOCK_OK_EINT2 */
  4075. #define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* FLL2_CLOCK_OK_EINT2 */
  4076. #define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* FLL2_CLOCK_OK_EINT2 */
  4077. #define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* FLL2_CLOCK_OK_EINT2 */
  4078. #define ARIZONA_FLL1_CLOCK_OK_EINT2 0x0001 /* FLL1_CLOCK_OK_EINT2 */
  4079. #define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* FLL1_CLOCK_OK_EINT2 */
  4080. #define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */
  4081. #define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */
  4082. /*
  4083. * R3352 (0xD18) - IRQ2 Status 1 Mask
  4084. */
  4085. #define ARIZONA_IM_GP4_EINT2 0x0008 /* IM_GP4_EINT2 */
  4086. #define ARIZONA_IM_GP4_EINT2_MASK 0x0008 /* IM_GP4_EINT2 */
  4087. #define ARIZONA_IM_GP4_EINT2_SHIFT 3 /* IM_GP4_EINT2 */
  4088. #define ARIZONA_IM_GP4_EINT2_WIDTH 1 /* IM_GP4_EINT2 */
  4089. #define ARIZONA_IM_GP3_EINT2 0x0004 /* IM_GP3_EINT2 */
  4090. #define ARIZONA_IM_GP3_EINT2_MASK 0x0004 /* IM_GP3_EINT2 */
  4091. #define ARIZONA_IM_GP3_EINT2_SHIFT 2 /* IM_GP3_EINT2 */
  4092. #define ARIZONA_IM_GP3_EINT2_WIDTH 1 /* IM_GP3_EINT2 */
  4093. #define ARIZONA_IM_GP2_EINT2 0x0002 /* IM_GP2_EINT2 */
  4094. #define ARIZONA_IM_GP2_EINT2_MASK 0x0002 /* IM_GP2_EINT2 */
  4095. #define ARIZONA_IM_GP2_EINT2_SHIFT 1 /* IM_GP2_EINT2 */
  4096. #define ARIZONA_IM_GP2_EINT2_WIDTH 1 /* IM_GP2_EINT2 */
  4097. #define ARIZONA_IM_GP1_EINT2 0x0001 /* IM_GP1_EINT2 */
  4098. #define ARIZONA_IM_GP1_EINT2_MASK 0x0001 /* IM_GP1_EINT2 */
  4099. #define ARIZONA_IM_GP1_EINT2_SHIFT 0 /* IM_GP1_EINT2 */
  4100. #define ARIZONA_IM_GP1_EINT2_WIDTH 1 /* IM_GP1_EINT2 */
  4101. /*
  4102. * R3353 (0xD19) - IRQ2 Status 2 Mask
  4103. */
  4104. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
  4105. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
  4106. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT2 */
  4107. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT2 */
  4108. #define ARIZONA_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */
  4109. #define ARIZONA_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */
  4110. #define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */
  4111. #define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */
  4112. #define ARIZONA_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */
  4113. #define ARIZONA_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */
  4114. #define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */
  4115. #define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */
  4116. /*
  4117. * R3354 (0xD1A) - IRQ2 Status 3 Mask
  4118. */
  4119. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4120. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4121. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4122. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4123. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
  4124. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
  4125. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */
  4126. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */
  4127. #define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */
  4128. #define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */
  4129. #define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */
  4130. #define ARIZONA_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */
  4131. #define ARIZONA_IM_MICDET_EINT2 0x1000 /* IM_MICDET_EINT2 */
  4132. #define ARIZONA_IM_MICDET_EINT2_MASK 0x1000 /* IM_MICDET_EINT2 */
  4133. #define ARIZONA_IM_MICDET_EINT2_SHIFT 12 /* IM_MICDET_EINT2 */
  4134. #define ARIZONA_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */
  4135. #define ARIZONA_IM_WSEQ_DONE_EINT2 0x0800 /* IM_WSEQ_DONE_EINT2 */
  4136. #define ARIZONA_IM_WSEQ_DONE_EINT2_MASK 0x0800 /* IM_WSEQ_DONE_EINT2 */
  4137. #define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT 11 /* IM_WSEQ_DONE_EINT2 */
  4138. #define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH 1 /* IM_WSEQ_DONE_EINT2 */
  4139. #define ARIZONA_IM_DRC2_SIG_DET_EINT2 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
  4140. #define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
  4141. #define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT 10 /* IM_DRC2_SIG_DET_EINT2 */
  4142. #define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */
  4143. #define ARIZONA_IM_DRC1_SIG_DET_EINT2 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
  4144. #define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
  4145. #define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT 9 /* IM_DRC1_SIG_DET_EINT2 */
  4146. #define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */
  4147. #define ARIZONA_IM_ASRC2_LOCK_EINT2 0x0100 /* IM_ASRC2_LOCK_EINT2 */
  4148. #define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK 0x0100 /* IM_ASRC2_LOCK_EINT2 */
  4149. #define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT 8 /* IM_ASRC2_LOCK_EINT2 */
  4150. #define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_LOCK_EINT2 */
  4151. #define ARIZONA_IM_ASRC1_LOCK_EINT2 0x0080 /* IM_ASRC1_LOCK_EINT2 */
  4152. #define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK 0x0080 /* IM_ASRC1_LOCK_EINT2 */
  4153. #define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT 7 /* IM_ASRC1_LOCK_EINT2 */
  4154. #define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_LOCK_EINT2 */
  4155. #define ARIZONA_IM_UNDERCLOCKED_EINT2 0x0040 /* IM_UNDERCLOCKED_EINT2 */
  4156. #define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK 0x0040 /* IM_UNDERCLOCKED_EINT2 */
  4157. #define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT 6 /* IM_UNDERCLOCKED_EINT2 */
  4158. #define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH 1 /* IM_UNDERCLOCKED_EINT2 */
  4159. #define ARIZONA_IM_OVERCLOCKED_EINT2 0x0020 /* IM_OVERCLOCKED_EINT2 */
  4160. #define ARIZONA_IM_OVERCLOCKED_EINT2_MASK 0x0020 /* IM_OVERCLOCKED_EINT2 */
  4161. #define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT 5 /* IM_OVERCLOCKED_EINT2 */
  4162. #define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH 1 /* IM_OVERCLOCKED_EINT2 */
  4163. #define ARIZONA_IM_FLL2_LOCK_EINT2 0x0008 /* IM_FLL2_LOCK_EINT2 */
  4164. #define ARIZONA_IM_FLL2_LOCK_EINT2_MASK 0x0008 /* IM_FLL2_LOCK_EINT2 */
  4165. #define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT 3 /* IM_FLL2_LOCK_EINT2 */
  4166. #define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */
  4167. #define ARIZONA_IM_FLL1_LOCK_EINT2 0x0004 /* IM_FLL1_LOCK_EINT2 */
  4168. #define ARIZONA_IM_FLL1_LOCK_EINT2_MASK 0x0004 /* IM_FLL1_LOCK_EINT2 */
  4169. #define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT 2 /* IM_FLL1_LOCK_EINT2 */
  4170. #define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */
  4171. #define ARIZONA_IM_CLKGEN_ERR_EINT2 0x0002 /* IM_CLKGEN_ERR_EINT2 */
  4172. #define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK 0x0002 /* IM_CLKGEN_ERR_EINT2 */
  4173. #define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT 1 /* IM_CLKGEN_ERR_EINT2 */
  4174. #define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_EINT2 */
  4175. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4176. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4177. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4178. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4179. /*
  4180. * R3355 (0xD1B) - IRQ2 Status 4 Mask
  4181. */
  4182. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
  4183. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
  4184. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */
  4185. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */
  4186. #define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */
  4187. #define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */
  4188. #define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */
  4189. #define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */
  4190. #define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */
  4191. #define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */
  4192. #define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */
  4193. #define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */
  4194. #define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */
  4195. #define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */
  4196. #define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */
  4197. #define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */
  4198. #define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */
  4199. #define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */
  4200. #define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */
  4201. #define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */
  4202. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4203. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4204. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4205. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4206. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4207. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4208. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4209. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4210. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4211. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4212. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4213. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4214. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
  4215. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
  4216. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */
  4217. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */
  4218. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
  4219. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
  4220. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */
  4221. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */
  4222. /*
  4223. * R3356 (0xD1C) - IRQ2 Status 5 Mask
  4224. */
  4225. #define ARIZONA_IM_BOOT_DONE_EINT2 0x0100 /* IM_BOOT_DONE_EINT2 */
  4226. #define ARIZONA_IM_BOOT_DONE_EINT2_MASK 0x0100 /* IM_BOOT_DONE_EINT2 */
  4227. #define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT 8 /* IM_BOOT_DONE_EINT2 */
  4228. #define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */
  4229. #define ARIZONA_IM_DCS_DAC_DONE_EINT2 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
  4230. #define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
  4231. #define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT 7 /* IM_DCS_DAC_DONE_EINT2 */
  4232. #define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH 1 /* IM_DCS_DAC_DONE_EINT2 */
  4233. #define ARIZONA_IM_DCS_HP_DONE_EINT2 0x0040 /* IM_DCS_HP_DONE_EINT2 */
  4234. #define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK 0x0040 /* IM_DCS_HP_DONE_EINT2 */
  4235. #define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT 6 /* IM_DCS_HP_DONE_EINT2 */
  4236. #define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH 1 /* IM_DCS_HP_DONE_EINT2 */
  4237. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
  4238. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
  4239. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT2 */
  4240. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT2 */
  4241. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
  4242. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
  4243. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */
  4244. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */
  4245. /*
  4246. * R3359 (0xD1F) - IRQ2 Control
  4247. */
  4248. #define ARIZONA_IM_IRQ2 0x0001 /* IM_IRQ2 */
  4249. #define ARIZONA_IM_IRQ2_MASK 0x0001 /* IM_IRQ2 */
  4250. #define ARIZONA_IM_IRQ2_SHIFT 0 /* IM_IRQ2 */
  4251. #define ARIZONA_IM_IRQ2_WIDTH 1 /* IM_IRQ2 */
  4252. /*
  4253. * R3360 (0xD20) - Interrupt Raw Status 2
  4254. */
  4255. #define ARIZONA_DSP1_RAM_RDY_STS 0x0100 /* DSP1_RAM_RDY_STS */
  4256. #define ARIZONA_DSP1_RAM_RDY_STS_MASK 0x0100 /* DSP1_RAM_RDY_STS */
  4257. #define ARIZONA_DSP1_RAM_RDY_STS_SHIFT 8 /* DSP1_RAM_RDY_STS */
  4258. #define ARIZONA_DSP1_RAM_RDY_STS_WIDTH 1 /* DSP1_RAM_RDY_STS */
  4259. #define ARIZONA_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */
  4260. #define ARIZONA_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */
  4261. #define ARIZONA_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */
  4262. #define ARIZONA_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */
  4263. #define ARIZONA_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */
  4264. #define ARIZONA_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */
  4265. #define ARIZONA_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */
  4266. #define ARIZONA_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */
  4267. /*
  4268. * R3361 (0xD21) - Interrupt Raw Status 3
  4269. */
  4270. #define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
  4271. #define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
  4272. #define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
  4273. #define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
  4274. #define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
  4275. #define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
  4276. #define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
  4277. #define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
  4278. #define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */
  4279. #define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */
  4280. #define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */
  4281. #define ARIZONA_HPDET_STS_WIDTH 1 /* HPDET_STS */
  4282. #define ARIZONA_MICDET_STS 0x1000 /* MICDET_STS */
  4283. #define ARIZONA_MICDET_STS_MASK 0x1000 /* MICDET_STS */
  4284. #define ARIZONA_MICDET_STS_SHIFT 12 /* MICDET_STS */
  4285. #define ARIZONA_MICDET_STS_WIDTH 1 /* MICDET_STS */
  4286. #define ARIZONA_WSEQ_DONE_STS 0x0800 /* WSEQ_DONE_STS */
  4287. #define ARIZONA_WSEQ_DONE_STS_MASK 0x0800 /* WSEQ_DONE_STS */
  4288. #define ARIZONA_WSEQ_DONE_STS_SHIFT 11 /* WSEQ_DONE_STS */
  4289. #define ARIZONA_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
  4290. #define ARIZONA_DRC2_SIG_DET_STS 0x0400 /* DRC2_SIG_DET_STS */
  4291. #define ARIZONA_DRC2_SIG_DET_STS_MASK 0x0400 /* DRC2_SIG_DET_STS */
  4292. #define ARIZONA_DRC2_SIG_DET_STS_SHIFT 10 /* DRC2_SIG_DET_STS */
  4293. #define ARIZONA_DRC2_SIG_DET_STS_WIDTH 1 /* DRC2_SIG_DET_STS */
  4294. #define ARIZONA_DRC1_SIG_DET_STS 0x0200 /* DRC1_SIG_DET_STS */
  4295. #define ARIZONA_DRC1_SIG_DET_STS_MASK 0x0200 /* DRC1_SIG_DET_STS */
  4296. #define ARIZONA_DRC1_SIG_DET_STS_SHIFT 9 /* DRC1_SIG_DET_STS */
  4297. #define ARIZONA_DRC1_SIG_DET_STS_WIDTH 1 /* DRC1_SIG_DET_STS */
  4298. #define ARIZONA_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */
  4299. #define ARIZONA_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */
  4300. #define ARIZONA_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */
  4301. #define ARIZONA_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */
  4302. #define ARIZONA_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */
  4303. #define ARIZONA_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */
  4304. #define ARIZONA_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */
  4305. #define ARIZONA_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */
  4306. #define ARIZONA_UNDERCLOCKED_STS 0x0040 /* UNDERCLOCKED_STS */
  4307. #define ARIZONA_UNDERCLOCKED_STS_MASK 0x0040 /* UNDERCLOCKED_STS */
  4308. #define ARIZONA_UNDERCLOCKED_STS_SHIFT 6 /* UNDERCLOCKED_STS */
  4309. #define ARIZONA_UNDERCLOCKED_STS_WIDTH 1 /* UNDERCLOCKED_STS */
  4310. #define ARIZONA_OVERCLOCKED_STS 0x0020 /* OVERCLOCKED_STS */
  4311. #define ARIZONA_OVERCLOCKED_STS_MASK 0x0020 /* OVERCLOCKED_STS */
  4312. #define ARIZONA_OVERCLOCKED_STS_SHIFT 5 /* OVERCLOCKED_STS */
  4313. #define ARIZONA_OVERCLOCKED_STS_WIDTH 1 /* OVERCLOCKED_STS */
  4314. #define ARIZONA_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
  4315. #define ARIZONA_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
  4316. #define ARIZONA_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
  4317. #define ARIZONA_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
  4318. #define ARIZONA_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
  4319. #define ARIZONA_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
  4320. #define ARIZONA_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
  4321. #define ARIZONA_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
  4322. #define ARIZONA_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */
  4323. #define ARIZONA_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */
  4324. #define ARIZONA_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */
  4325. #define ARIZONA_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */
  4326. #define ARIZONA_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */
  4327. #define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */
  4328. #define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */
  4329. #define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */
  4330. /*
  4331. * R3362 (0xD22) - Interrupt Raw Status 4
  4332. */
  4333. #define ARIZONA_ASRC_CFG_ERR_STS 0x8000 /* ASRC_CFG_ERR_STS */
  4334. #define ARIZONA_ASRC_CFG_ERR_STS_MASK 0x8000 /* ASRC_CFG_ERR_STS */
  4335. #define ARIZONA_ASRC_CFG_ERR_STS_SHIFT 15 /* ASRC_CFG_ERR_STS */
  4336. #define ARIZONA_ASRC_CFG_ERR_STS_WIDTH 1 /* ASRC_CFG_ERR_STS */
  4337. #define ARIZONA_AIF3_ERR_STS 0x4000 /* AIF3_ERR_STS */
  4338. #define ARIZONA_AIF3_ERR_STS_MASK 0x4000 /* AIF3_ERR_STS */
  4339. #define ARIZONA_AIF3_ERR_STS_SHIFT 14 /* AIF3_ERR_STS */
  4340. #define ARIZONA_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */
  4341. #define ARIZONA_AIF2_ERR_STS 0x2000 /* AIF2_ERR_STS */
  4342. #define ARIZONA_AIF2_ERR_STS_MASK 0x2000 /* AIF2_ERR_STS */
  4343. #define ARIZONA_AIF2_ERR_STS_SHIFT 13 /* AIF2_ERR_STS */
  4344. #define ARIZONA_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */
  4345. #define ARIZONA_AIF1_ERR_STS 0x1000 /* AIF1_ERR_STS */
  4346. #define ARIZONA_AIF1_ERR_STS_MASK 0x1000 /* AIF1_ERR_STS */
  4347. #define ARIZONA_AIF1_ERR_STS_SHIFT 12 /* AIF1_ERR_STS */
  4348. #define ARIZONA_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */
  4349. #define ARIZONA_CTRLIF_ERR_STS 0x0800 /* CTRLIF_ERR_STS */
  4350. #define ARIZONA_CTRLIF_ERR_STS_MASK 0x0800 /* CTRLIF_ERR_STS */
  4351. #define ARIZONA_CTRLIF_ERR_STS_SHIFT 11 /* CTRLIF_ERR_STS */
  4352. #define ARIZONA_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */
  4353. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
  4354. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
  4355. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT 10 /* MIXER_DROPPED_SAMPLE_STS */
  4356. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH 1 /* MIXER_DROPPED_SAMPLE_STS */
  4357. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
  4358. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
  4359. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT 9 /* ASYNC_CLK_ENA_LOW_STS */
  4360. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH 1 /* ASYNC_CLK_ENA_LOW_STS */
  4361. #define ARIZONA_SYSCLK_ENA_LOW_STS 0x0100 /* SYSCLK_ENA_LOW_STS */
  4362. #define ARIZONA_SYSCLK_ENA_LOW_STS_MASK 0x0100 /* SYSCLK_ENA_LOW_STS */
  4363. #define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT 8 /* SYSCLK_ENA_LOW_STS */
  4364. #define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH 1 /* SYSCLK_ENA_LOW_STS */
  4365. #define ARIZONA_ISRC1_CFG_ERR_STS 0x0080 /* ISRC1_CFG_ERR_STS */
  4366. #define ARIZONA_ISRC1_CFG_ERR_STS_MASK 0x0080 /* ISRC1_CFG_ERR_STS */
  4367. #define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT 7 /* ISRC1_CFG_ERR_STS */
  4368. #define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH 1 /* ISRC1_CFG_ERR_STS */
  4369. #define ARIZONA_ISRC2_CFG_ERR_STS 0x0040 /* ISRC2_CFG_ERR_STS */
  4370. #define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */
  4371. #define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */
  4372. #define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */
  4373. /*
  4374. * R3363 (0xD23) - Interrupt Raw Status 5
  4375. */
  4376. #define ARIZONA_BOOT_DONE_STS 0x0100 /* BOOT_DONE_STS */
  4377. #define ARIZONA_BOOT_DONE_STS_MASK 0x0100 /* BOOT_DONE_STS */
  4378. #define ARIZONA_BOOT_DONE_STS_SHIFT 8 /* BOOT_DONE_STS */
  4379. #define ARIZONA_BOOT_DONE_STS_WIDTH 1 /* BOOT_DONE_STS */
  4380. #define ARIZONA_DCS_DAC_DONE_STS 0x0080 /* DCS_DAC_DONE_STS */
  4381. #define ARIZONA_DCS_DAC_DONE_STS_MASK 0x0080 /* DCS_DAC_DONE_STS */
  4382. #define ARIZONA_DCS_DAC_DONE_STS_SHIFT 7 /* DCS_DAC_DONE_STS */
  4383. #define ARIZONA_DCS_DAC_DONE_STS_WIDTH 1 /* DCS_DAC_DONE_STS */
  4384. #define ARIZONA_DCS_HP_DONE_STS 0x0040 /* DCS_HP_DONE_STS */
  4385. #define ARIZONA_DCS_HP_DONE_STS_MASK 0x0040 /* DCS_HP_DONE_STS */
  4386. #define ARIZONA_DCS_HP_DONE_STS_SHIFT 6 /* DCS_HP_DONE_STS */
  4387. #define ARIZONA_DCS_HP_DONE_STS_WIDTH 1 /* DCS_HP_DONE_STS */
  4388. #define ARIZONA_FLL2_CLOCK_OK_STS 0x0002 /* FLL2_CLOCK_OK_STS */
  4389. #define ARIZONA_FLL2_CLOCK_OK_STS_MASK 0x0002 /* FLL2_CLOCK_OK_STS */
  4390. #define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT 1 /* FLL2_CLOCK_OK_STS */
  4391. #define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH 1 /* FLL2_CLOCK_OK_STS */
  4392. #define ARIZONA_FLL1_CLOCK_OK_STS 0x0001 /* FLL1_CLOCK_OK_STS */
  4393. #define ARIZONA_FLL1_CLOCK_OK_STS_MASK 0x0001 /* FLL1_CLOCK_OK_STS */
  4394. #define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT 0 /* FLL1_CLOCK_OK_STS */
  4395. #define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH 1 /* FLL1_CLOCK_OK_STS */
  4396. /*
  4397. * R3364 (0xD24) - Interrupt Raw Status 6
  4398. */
  4399. #define ARIZONA_PWM_OVERCLOCKED_STS 0x2000 /* PWM_OVERCLOCKED_STS */
  4400. #define ARIZONA_PWM_OVERCLOCKED_STS_MASK 0x2000 /* PWM_OVERCLOCKED_STS */
  4401. #define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT 13 /* PWM_OVERCLOCKED_STS */
  4402. #define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH 1 /* PWM_OVERCLOCKED_STS */
  4403. #define ARIZONA_FX_CORE_OVERCLOCKED_STS 0x1000 /* FX_CORE_OVERCLOCKED_STS */
  4404. #define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK 0x1000 /* FX_CORE_OVERCLOCKED_STS */
  4405. #define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT 12 /* FX_CORE_OVERCLOCKED_STS */
  4406. #define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH 1 /* FX_CORE_OVERCLOCKED_STS */
  4407. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
  4408. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
  4409. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT 10 /* DAC_SYS_OVERCLOCKED_STS */
  4410. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH 1 /* DAC_SYS_OVERCLOCKED_STS */
  4411. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
  4412. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
  4413. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT 9 /* DAC_WARP_OVERCLOCKED_STS */
  4414. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH 1 /* DAC_WARP_OVERCLOCKED_STS */
  4415. #define ARIZONA_ADC_OVERCLOCKED_STS 0x0100 /* ADC_OVERCLOCKED_STS */
  4416. #define ARIZONA_ADC_OVERCLOCKED_STS_MASK 0x0100 /* ADC_OVERCLOCKED_STS */
  4417. #define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT 8 /* ADC_OVERCLOCKED_STS */
  4418. #define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH 1 /* ADC_OVERCLOCKED_STS */
  4419. #define ARIZONA_MIXER_OVERCLOCKED_STS 0x0080 /* MIXER_OVERCLOCKED_STS */
  4420. #define ARIZONA_MIXER_OVERCLOCKED_STS_MASK 0x0080 /* MIXER_OVERCLOCKED_STS */
  4421. #define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT 7 /* MIXER_OVERCLOCKED_STS */
  4422. #define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH 1 /* MIXER_OVERCLOCKED_STS */
  4423. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4424. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4425. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT 6 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4426. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4427. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4428. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4429. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT 5 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4430. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4431. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4432. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4433. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT 4 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4434. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4435. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
  4436. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
  4437. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT 3 /* AIF3_SYNC_OVERCLOCKED_STS */
  4438. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_SYNC_OVERCLOCKED_STS */
  4439. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
  4440. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
  4441. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT 2 /* AIF2_SYNC_OVERCLOCKED_STS */
  4442. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_SYNC_OVERCLOCKED_STS */
  4443. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
  4444. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
  4445. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT 1 /* AIF1_SYNC_OVERCLOCKED_STS */
  4446. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_SYNC_OVERCLOCKED_STS */
  4447. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
  4448. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
  4449. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT 0 /* PAD_CTRL_OVERCLOCKED_STS */
  4450. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH 1 /* PAD_CTRL_OVERCLOCKED_STS */
  4451. /*
  4452. * R3365 (0xD25) - Interrupt Raw Status 7
  4453. */
  4454. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4455. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4456. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4457. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4458. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4459. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4460. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4461. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4462. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4463. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4464. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4465. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4466. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4467. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4468. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4469. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4470. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4471. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4472. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4473. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4474. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4475. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4476. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4477. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4478. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4479. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4480. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4481. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4482. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
  4483. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
  4484. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */
  4485. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */
  4486. #define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */
  4487. #define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */
  4488. #define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */
  4489. #define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */
  4490. #define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */
  4491. #define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */
  4492. #define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */
  4493. #define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */
  4494. /*
  4495. * R3366 (0xD26) - Interrupt Raw Status 8
  4496. */
  4497. #define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */
  4498. #define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */
  4499. #define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */
  4500. #define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */
  4501. #define ARIZONA_AIF2_UNDERCLOCKED_STS 0x0200 /* AIF2_UNDERCLOCKED_STS */
  4502. #define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK 0x0200 /* AIF2_UNDERCLOCKED_STS */
  4503. #define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT 9 /* AIF2_UNDERCLOCKED_STS */
  4504. #define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */
  4505. #define ARIZONA_AIF1_UNDERCLOCKED_STS 0x0100 /* AIF1_UNDERCLOCKED_STS */
  4506. #define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */
  4507. #define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */
  4508. #define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
  4509. #define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */
  4510. #define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */
  4511. #define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */
  4512. #define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */
  4513. #define ARIZONA_ISRC1_UNDERCLOCKED_STS 0x0020 /* ISRC1_UNDERCLOCKED_STS */
  4514. #define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK 0x0020 /* ISRC1_UNDERCLOCKED_STS */
  4515. #define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT 5 /* ISRC1_UNDERCLOCKED_STS */
  4516. #define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */
  4517. #define ARIZONA_FX_UNDERCLOCKED_STS 0x0010 /* FX_UNDERCLOCKED_STS */
  4518. #define ARIZONA_FX_UNDERCLOCKED_STS_MASK 0x0010 /* FX_UNDERCLOCKED_STS */
  4519. #define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT 4 /* FX_UNDERCLOCKED_STS */
  4520. #define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */
  4521. #define ARIZONA_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */
  4522. #define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */
  4523. #define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */
  4524. #define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */
  4525. #define ARIZONA_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */
  4526. #define ARIZONA_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */
  4527. #define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */
  4528. #define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */
  4529. #define ARIZONA_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */
  4530. #define ARIZONA_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */
  4531. #define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */
  4532. #define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */
  4533. #define ARIZONA_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */
  4534. #define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */
  4535. #define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
  4536. #define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
  4537. /*
  4538. * R3392 (0xD40) - IRQ Pin Status
  4539. */
  4540. #define ARIZONA_IRQ2_STS 0x0002 /* IRQ2_STS */
  4541. #define ARIZONA_IRQ2_STS_MASK 0x0002 /* IRQ2_STS */
  4542. #define ARIZONA_IRQ2_STS_SHIFT 1 /* IRQ2_STS */
  4543. #define ARIZONA_IRQ2_STS_WIDTH 1 /* IRQ2_STS */
  4544. #define ARIZONA_IRQ1_STS 0x0001 /* IRQ1_STS */
  4545. #define ARIZONA_IRQ1_STS_MASK 0x0001 /* IRQ1_STS */
  4546. #define ARIZONA_IRQ1_STS_SHIFT 0 /* IRQ1_STS */
  4547. #define ARIZONA_IRQ1_STS_WIDTH 1 /* IRQ1_STS */
  4548. /*
  4549. * R3393 (0xD41) - ADSP2 IRQ0
  4550. */
  4551. #define ARIZONA_DSP_IRQ2 0x0002 /* DSP_IRQ2 */
  4552. #define ARIZONA_DSP_IRQ2_MASK 0x0002 /* DSP_IRQ2 */
  4553. #define ARIZONA_DSP_IRQ2_SHIFT 1 /* DSP_IRQ2 */
  4554. #define ARIZONA_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */
  4555. #define ARIZONA_DSP_IRQ1 0x0001 /* DSP_IRQ1 */
  4556. #define ARIZONA_DSP_IRQ1_MASK 0x0001 /* DSP_IRQ1 */
  4557. #define ARIZONA_DSP_IRQ1_SHIFT 0 /* DSP_IRQ1 */
  4558. #define ARIZONA_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */
  4559. /*
  4560. * R3408 (0xD50) - AOD wkup and trig
  4561. */
  4562. #define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */
  4563. #define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */
  4564. #define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */
  4565. #define ARIZONA_GP5_FALL_TRIG_STS_WIDTH 1 /* GP5_FALL_TRIG_STS */
  4566. #define ARIZONA_GP5_RISE_TRIG_STS 0x0010 /* GP5_RISE_TRIG_STS */
  4567. #define ARIZONA_GP5_RISE_TRIG_STS_MASK 0x0010 /* GP5_RISE_TRIG_STS */
  4568. #define ARIZONA_GP5_RISE_TRIG_STS_SHIFT 4 /* GP5_RISE_TRIG_STS */
  4569. #define ARIZONA_GP5_RISE_TRIG_STS_WIDTH 1 /* GP5_RISE_TRIG_STS */
  4570. #define ARIZONA_JD1_FALL_TRIG_STS 0x0008 /* JD1_FALL_TRIG_STS */
  4571. #define ARIZONA_JD1_FALL_TRIG_STS_MASK 0x0008 /* JD1_FALL_TRIG_STS */
  4572. #define ARIZONA_JD1_FALL_TRIG_STS_SHIFT 3 /* JD1_FALL_TRIG_STS */
  4573. #define ARIZONA_JD1_FALL_TRIG_STS_WIDTH 1 /* JD1_FALL_TRIG_STS */
  4574. #define ARIZONA_JD1_RISE_TRIG_STS 0x0004 /* JD1_RISE_TRIG_STS */
  4575. #define ARIZONA_JD1_RISE_TRIG_STS_MASK 0x0004 /* JD1_RISE_TRIG_STS */
  4576. #define ARIZONA_JD1_RISE_TRIG_STS_SHIFT 2 /* JD1_RISE_TRIG_STS */
  4577. #define ARIZONA_JD1_RISE_TRIG_STS_WIDTH 1 /* JD1_RISE_TRIG_STS */
  4578. #define ARIZONA_JD2_FALL_TRIG_STS 0x0002 /* JD2_FALL_TRIG_STS */
  4579. #define ARIZONA_JD2_FALL_TRIG_STS_MASK 0x0002 /* JD2_FALL_TRIG_STS */
  4580. #define ARIZONA_JD2_FALL_TRIG_STS_SHIFT 1 /* JD2_FALL_TRIG_STS */
  4581. #define ARIZONA_JD2_FALL_TRIG_STS_WIDTH 1 /* JD2_FALL_TRIG_STS */
  4582. #define ARIZONA_JD2_RISE_TRIG_STS 0x0001 /* JD2_RISE_TRIG_STS */
  4583. #define ARIZONA_JD2_RISE_TRIG_STS_MASK 0x0001 /* JD2_RISE_TRIG_STS */
  4584. #define ARIZONA_JD2_RISE_TRIG_STS_SHIFT 0 /* JD2_RISE_TRIG_STS */
  4585. #define ARIZONA_JD2_RISE_TRIG_STS_WIDTH 1 /* JD2_RISE_TRIG_STS */
  4586. /*
  4587. * R3409 (0xD51) - AOD IRQ1
  4588. */
  4589. #define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */
  4590. #define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */
  4591. #define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */
  4592. #define ARIZONA_GP5_FALL_EINT1_WIDTH 1 /* GP5_FALL_EINT1 */
  4593. #define ARIZONA_GP5_RISE_EINT1 0x0010 /* GP5_RISE_EINT1 */
  4594. #define ARIZONA_GP5_RISE_EINT1_MASK 0x0010 /* GP5_RISE_EINT1 */
  4595. #define ARIZONA_GP5_RISE_EINT1_SHIFT 4 /* GP5_RISE_EINT1 */
  4596. #define ARIZONA_GP5_RISE_EINT1_WIDTH 1 /* GP5_RISE_EINT1 */
  4597. #define ARIZONA_JD1_FALL_EINT1 0x0008 /* JD1_FALL_EINT1 */
  4598. #define ARIZONA_JD1_FALL_EINT1_MASK 0x0008 /* JD1_FALL_EINT1 */
  4599. #define ARIZONA_JD1_FALL_EINT1_SHIFT 3 /* JD1_FALL_EINT1 */
  4600. #define ARIZONA_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */
  4601. #define ARIZONA_JD1_RISE_EINT1 0x0004 /* JD1_RISE_EINT1 */
  4602. #define ARIZONA_JD1_RISE_EINT1_MASK 0x0004 /* JD1_RISE_EINT1 */
  4603. #define ARIZONA_JD1_RISE_EINT1_SHIFT 2 /* JD1_RISE_EINT1 */
  4604. #define ARIZONA_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */
  4605. #define ARIZONA_JD2_FALL_EINT1 0x0002 /* JD2_FALL_EINT1 */
  4606. #define ARIZONA_JD2_FALL_EINT1_MASK 0x0002 /* JD2_FALL_EINT1 */
  4607. #define ARIZONA_JD2_FALL_EINT1_SHIFT 1 /* JD2_FALL_EINT1 */
  4608. #define ARIZONA_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */
  4609. #define ARIZONA_JD2_RISE_EINT1 0x0001 /* JD2_RISE_EINT1 */
  4610. #define ARIZONA_JD2_RISE_EINT1_MASK 0x0001 /* JD2_RISE_EINT1 */
  4611. #define ARIZONA_JD2_RISE_EINT1_SHIFT 0 /* JD2_RISE_EINT1 */
  4612. #define ARIZONA_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */
  4613. /*
  4614. * R3410 (0xD52) - AOD IRQ2
  4615. */
  4616. #define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */
  4617. #define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */
  4618. #define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */
  4619. #define ARIZONA_GP5_FALL_EINT2_WIDTH 1 /* GP5_FALL_EINT2 */
  4620. #define ARIZONA_GP5_RISE_EINT2 0x0010 /* GP5_RISE_EINT2 */
  4621. #define ARIZONA_GP5_RISE_EINT2_MASK 0x0010 /* GP5_RISE_EINT2 */
  4622. #define ARIZONA_GP5_RISE_EINT2_SHIFT 4 /* GP5_RISE_EINT2 */
  4623. #define ARIZONA_GP5_RISE_EINT2_WIDTH 1 /* GP5_RISE_EINT2 */
  4624. #define ARIZONA_JD1_FALL_EINT2 0x0008 /* JD1_FALL_EINT2 */
  4625. #define ARIZONA_JD1_FALL_EINT2_MASK 0x0008 /* JD1_FALL_EINT2 */
  4626. #define ARIZONA_JD1_FALL_EINT2_SHIFT 3 /* JD1_FALL_EINT2 */
  4627. #define ARIZONA_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */
  4628. #define ARIZONA_JD1_RISE_EINT2 0x0004 /* JD1_RISE_EINT2 */
  4629. #define ARIZONA_JD1_RISE_EINT2_MASK 0x0004 /* JD1_RISE_EINT2 */
  4630. #define ARIZONA_JD1_RISE_EINT2_SHIFT 2 /* JD1_RISE_EINT2 */
  4631. #define ARIZONA_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */
  4632. #define ARIZONA_JD2_FALL_EINT2 0x0002 /* JD2_FALL_EINT2 */
  4633. #define ARIZONA_JD2_FALL_EINT2_MASK 0x0002 /* JD2_FALL_EINT2 */
  4634. #define ARIZONA_JD2_FALL_EINT2_SHIFT 1 /* JD2_FALL_EINT2 */
  4635. #define ARIZONA_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */
  4636. #define ARIZONA_JD2_RISE_EINT2 0x0001 /* JD2_RISE_EINT2 */
  4637. #define ARIZONA_JD2_RISE_EINT2_MASK 0x0001 /* JD2_RISE_EINT2 */
  4638. #define ARIZONA_JD2_RISE_EINT2_SHIFT 0 /* JD2_RISE_EINT2 */
  4639. #define ARIZONA_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */
  4640. /*
  4641. * R3411 (0xD53) - AOD IRQ Mask IRQ1
  4642. */
  4643. #define ARIZONA_IM_GP5_FALL_EINT1 0x0020 /* IM_GP5_FALL_EINT1 */
  4644. #define ARIZONA_IM_GP5_FALL_EINT1_MASK 0x0020 /* IM_GP5_FALL_EINT1 */
  4645. #define ARIZONA_IM_GP5_FALL_EINT1_SHIFT 5 /* IM_GP5_FALL_EINT1 */
  4646. #define ARIZONA_IM_GP5_FALL_EINT1_WIDTH 1 /* IM_GP5_FALL_EINT1 */
  4647. #define ARIZONA_IM_GP5_RISE_EINT1 0x0010 /* IM_GP5_RISE_EINT1 */
  4648. #define ARIZONA_IM_GP5_RISE_EINT1_MASK 0x0010 /* IM_GP5_RISE_EINT1 */
  4649. #define ARIZONA_IM_GP5_RISE_EINT1_SHIFT 4 /* IM_GP5_RISE_EINT1 */
  4650. #define ARIZONA_IM_GP5_RISE_EINT1_WIDTH 1 /* IM_GP5_RISE_EINT1 */
  4651. #define ARIZONA_IM_JD1_FALL_EINT1 0x0008 /* IM_JD1_FALL_EINT1 */
  4652. #define ARIZONA_IM_JD1_FALL_EINT1_MASK 0x0008 /* IM_JD1_FALL_EINT1 */
  4653. #define ARIZONA_IM_JD1_FALL_EINT1_SHIFT 3 /* IM_JD1_FALL_EINT1 */
  4654. #define ARIZONA_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */
  4655. #define ARIZONA_IM_JD1_RISE_EINT1 0x0004 /* IM_JD1_RISE_EINT1 */
  4656. #define ARIZONA_IM_JD1_RISE_EINT1_MASK 0x0004 /* IM_JD1_RISE_EINT1 */
  4657. #define ARIZONA_IM_JD1_RISE_EINT1_SHIFT 2 /* IM_JD1_RISE_EINT1 */
  4658. #define ARIZONA_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */
  4659. #define ARIZONA_IM_JD2_FALL_EINT1 0x0002 /* IM_JD2_FALL_EINT1 */
  4660. #define ARIZONA_IM_JD2_FALL_EINT1_MASK 0x0002 /* IM_JD2_FALL_EINT1 */
  4661. #define ARIZONA_IM_JD2_FALL_EINT1_SHIFT 1 /* IM_JD2_FALL_EINT1 */
  4662. #define ARIZONA_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */
  4663. #define ARIZONA_IM_JD2_RISE_EINT1 0x0001 /* IM_JD2_RISE_EINT1 */
  4664. #define ARIZONA_IM_JD2_RISE_EINT1_MASK 0x0001 /* IM_JD2_RISE_EINT1 */
  4665. #define ARIZONA_IM_JD2_RISE_EINT1_SHIFT 0 /* IM_JD2_RISE_EINT1 */
  4666. #define ARIZONA_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */
  4667. /*
  4668. * R3412 (0xD54) - AOD IRQ Mask IRQ2
  4669. */
  4670. #define ARIZONA_IM_GP5_FALL_EINT2 0x0020 /* IM_GP5_FALL_EINT2 */
  4671. #define ARIZONA_IM_GP5_FALL_EINT2_MASK 0x0020 /* IM_GP5_FALL_EINT2 */
  4672. #define ARIZONA_IM_GP5_FALL_EINT2_SHIFT 5 /* IM_GP5_FALL_EINT2 */
  4673. #define ARIZONA_IM_GP5_FALL_EINT2_WIDTH 1 /* IM_GP5_FALL_EINT2 */
  4674. #define ARIZONA_IM_GP5_RISE_EINT2 0x0010 /* IM_GP5_RISE_EINT2 */
  4675. #define ARIZONA_IM_GP5_RISE_EINT2_MASK 0x0010 /* IM_GP5_RISE_EINT2 */
  4676. #define ARIZONA_IM_GP5_RISE_EINT2_SHIFT 4 /* IM_GP5_RISE_EINT2 */
  4677. #define ARIZONA_IM_GP5_RISE_EINT2_WIDTH 1 /* IM_GP5_RISE_EINT2 */
  4678. #define ARIZONA_IM_JD1_FALL_EINT2 0x0008 /* IM_JD1_FALL_EINT2 */
  4679. #define ARIZONA_IM_JD1_FALL_EINT2_MASK 0x0008 /* IM_JD1_FALL_EINT2 */
  4680. #define ARIZONA_IM_JD1_FALL_EINT2_SHIFT 3 /* IM_JD1_FALL_EINT2 */
  4681. #define ARIZONA_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */
  4682. #define ARIZONA_IM_JD1_RISE_EINT2 0x0004 /* IM_JD1_RISE_EINT2 */
  4683. #define ARIZONA_IM_JD1_RISE_EINT2_MASK 0x0004 /* IM_JD1_RISE_EINT2 */
  4684. #define ARIZONA_IM_JD1_RISE_EINT2_SHIFT 2 /* IM_JD1_RISE_EINT2 */
  4685. #define ARIZONA_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */
  4686. #define ARIZONA_IM_JD2_FALL_EINT2 0x0002 /* IM_JD2_FALL_EINT2 */
  4687. #define ARIZONA_IM_JD2_FALL_EINT2_MASK 0x0002 /* IM_JD2_FALL_EINT2 */
  4688. #define ARIZONA_IM_JD2_FALL_EINT2_SHIFT 1 /* IM_JD2_FALL_EINT2 */
  4689. #define ARIZONA_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */
  4690. #define ARIZONA_IM_JD2_RISE_EINT2 0x0001 /* IM_JD2_RISE_EINT2 */
  4691. #define ARIZONA_IM_JD2_RISE_EINT2_MASK 0x0001 /* IM_JD2_RISE_EINT2 */
  4692. #define ARIZONA_IM_JD2_RISE_EINT2_SHIFT 0 /* IM_JD2_RISE_EINT2 */
  4693. #define ARIZONA_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */
  4694. /*
  4695. * R3413 (0xD55) - AOD IRQ Raw Status
  4696. */
  4697. #define ARIZONA_GP5_STS 0x0004 /* GP5_STS */
  4698. #define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */
  4699. #define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */
  4700. #define ARIZONA_GP5_STS_WIDTH 1 /* GP5_STS */
  4701. #define ARIZONA_JD2_STS 0x0002 /* JD2_STS */
  4702. #define ARIZONA_JD2_STS_MASK 0x0002 /* JD2_STS */
  4703. #define ARIZONA_JD2_STS_SHIFT 1 /* JD2_STS */
  4704. #define ARIZONA_JD2_STS_WIDTH 1 /* JD2_STS */
  4705. #define ARIZONA_JD1_STS 0x0001 /* JD1_STS */
  4706. #define ARIZONA_JD1_STS_MASK 0x0001 /* JD1_STS */
  4707. #define ARIZONA_JD1_STS_SHIFT 0 /* JD1_STS */
  4708. #define ARIZONA_JD1_STS_WIDTH 1 /* JD1_STS */
  4709. /*
  4710. * R3414 (0xD56) - Jack detect debounce
  4711. */
  4712. #define ARIZONA_JD2_DB 0x0002 /* JD2_DB */
  4713. #define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */
  4714. #define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */
  4715. #define ARIZONA_JD2_DB_WIDTH 1 /* JD2_DB */
  4716. #define ARIZONA_JD1_DB 0x0001 /* JD1_DB */
  4717. #define ARIZONA_JD1_DB_MASK 0x0001 /* JD1_DB */
  4718. #define ARIZONA_JD1_DB_SHIFT 0 /* JD1_DB */
  4719. #define ARIZONA_JD1_DB_WIDTH 1 /* JD1_DB */
  4720. /*
  4721. * R3584 (0xE00) - FX_Ctrl1
  4722. */
  4723. #define ARIZONA_FX_RATE_MASK 0x7800 /* FX_RATE - [14:11] */
  4724. #define ARIZONA_FX_RATE_SHIFT 11 /* FX_RATE - [14:11] */
  4725. #define ARIZONA_FX_RATE_WIDTH 4 /* FX_RATE - [14:11] */
  4726. /*
  4727. * R3585 (0xE01) - FX_Ctrl2
  4728. */
  4729. #define ARIZONA_FX_STS_MASK 0xFFF0 /* FX_STS - [15:4] */
  4730. #define ARIZONA_FX_STS_SHIFT 4 /* FX_STS - [15:4] */
  4731. #define ARIZONA_FX_STS_WIDTH 12 /* FX_STS - [15:4] */
  4732. /*
  4733. * R3600 (0xE10) - EQ1_1
  4734. */
  4735. #define ARIZONA_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
  4736. #define ARIZONA_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
  4737. #define ARIZONA_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
  4738. #define ARIZONA_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */
  4739. #define ARIZONA_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */
  4740. #define ARIZONA_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */
  4741. #define ARIZONA_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */
  4742. #define ARIZONA_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */
  4743. #define ARIZONA_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */
  4744. #define ARIZONA_EQ1_ENA 0x0001 /* EQ1_ENA */
  4745. #define ARIZONA_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */
  4746. #define ARIZONA_EQ1_ENA_SHIFT 0 /* EQ1_ENA */
  4747. #define ARIZONA_EQ1_ENA_WIDTH 1 /* EQ1_ENA */
  4748. /*
  4749. * R3601 (0xE11) - EQ1_2
  4750. */
  4751. #define ARIZONA_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
  4752. #define ARIZONA_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
  4753. #define ARIZONA_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
  4754. #define ARIZONA_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */
  4755. #define ARIZONA_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */
  4756. #define ARIZONA_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */
  4757. #define ARIZONA_EQ1_B1_MODE 0x0001 /* EQ1_B1_MODE */
  4758. #define ARIZONA_EQ1_B1_MODE_MASK 0x0001 /* EQ1_B1_MODE */
  4759. #define ARIZONA_EQ1_B1_MODE_SHIFT 0 /* EQ1_B1_MODE */
  4760. #define ARIZONA_EQ1_B1_MODE_WIDTH 1 /* EQ1_B1_MODE */
  4761. /*
  4762. * R3602 (0xE12) - EQ1_3
  4763. */
  4764. #define ARIZONA_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
  4765. #define ARIZONA_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
  4766. #define ARIZONA_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
  4767. /*
  4768. * R3603 (0xE13) - EQ1_4
  4769. */
  4770. #define ARIZONA_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
  4771. #define ARIZONA_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
  4772. #define ARIZONA_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
  4773. /*
  4774. * R3604 (0xE14) - EQ1_5
  4775. */
  4776. #define ARIZONA_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
  4777. #define ARIZONA_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
  4778. #define ARIZONA_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
  4779. /*
  4780. * R3605 (0xE15) - EQ1_6
  4781. */
  4782. #define ARIZONA_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
  4783. #define ARIZONA_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
  4784. #define ARIZONA_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
  4785. /*
  4786. * R3606 (0xE16) - EQ1_7
  4787. */
  4788. #define ARIZONA_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
  4789. #define ARIZONA_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
  4790. #define ARIZONA_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
  4791. /*
  4792. * R3607 (0xE17) - EQ1_8
  4793. */
  4794. #define ARIZONA_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
  4795. #define ARIZONA_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
  4796. #define ARIZONA_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
  4797. /*
  4798. * R3608 (0xE18) - EQ1_9
  4799. */
  4800. #define ARIZONA_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
  4801. #define ARIZONA_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
  4802. #define ARIZONA_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
  4803. /*
  4804. * R3609 (0xE19) - EQ1_10
  4805. */
  4806. #define ARIZONA_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
  4807. #define ARIZONA_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
  4808. #define ARIZONA_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
  4809. /*
  4810. * R3610 (0xE1A) - EQ1_11
  4811. */
  4812. #define ARIZONA_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
  4813. #define ARIZONA_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
  4814. #define ARIZONA_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
  4815. /*
  4816. * R3611 (0xE1B) - EQ1_12
  4817. */
  4818. #define ARIZONA_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
  4819. #define ARIZONA_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
  4820. #define ARIZONA_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
  4821. /*
  4822. * R3612 (0xE1C) - EQ1_13
  4823. */
  4824. #define ARIZONA_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
  4825. #define ARIZONA_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
  4826. #define ARIZONA_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
  4827. /*
  4828. * R3613 (0xE1D) - EQ1_14
  4829. */
  4830. #define ARIZONA_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
  4831. #define ARIZONA_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
  4832. #define ARIZONA_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
  4833. /*
  4834. * R3614 (0xE1E) - EQ1_15
  4835. */
  4836. #define ARIZONA_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
  4837. #define ARIZONA_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
  4838. #define ARIZONA_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
  4839. /*
  4840. * R3615 (0xE1F) - EQ1_16
  4841. */
  4842. #define ARIZONA_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
  4843. #define ARIZONA_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
  4844. #define ARIZONA_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
  4845. /*
  4846. * R3616 (0xE20) - EQ1_17
  4847. */
  4848. #define ARIZONA_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
  4849. #define ARIZONA_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
  4850. #define ARIZONA_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
  4851. /*
  4852. * R3617 (0xE21) - EQ1_18
  4853. */
  4854. #define ARIZONA_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
  4855. #define ARIZONA_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
  4856. #define ARIZONA_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
  4857. /*
  4858. * R3618 (0xE22) - EQ1_19
  4859. */
  4860. #define ARIZONA_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
  4861. #define ARIZONA_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
  4862. #define ARIZONA_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
  4863. /*
  4864. * R3619 (0xE23) - EQ1_20
  4865. */
  4866. #define ARIZONA_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
  4867. #define ARIZONA_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
  4868. #define ARIZONA_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
  4869. /*
  4870. * R3620 (0xE24) - EQ1_21
  4871. */
  4872. #define ARIZONA_EQ1_B1_C_MASK 0xFFFF /* EQ1_B1_C - [15:0] */
  4873. #define ARIZONA_EQ1_B1_C_SHIFT 0 /* EQ1_B1_C - [15:0] */
  4874. #define ARIZONA_EQ1_B1_C_WIDTH 16 /* EQ1_B1_C - [15:0] */
  4875. /*
  4876. * R3622 (0xE26) - EQ2_1
  4877. */
  4878. #define ARIZONA_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
  4879. #define ARIZONA_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
  4880. #define ARIZONA_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
  4881. #define ARIZONA_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */
  4882. #define ARIZONA_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */
  4883. #define ARIZONA_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */
  4884. #define ARIZONA_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */
  4885. #define ARIZONA_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */
  4886. #define ARIZONA_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */
  4887. #define ARIZONA_EQ2_ENA 0x0001 /* EQ2_ENA */
  4888. #define ARIZONA_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */
  4889. #define ARIZONA_EQ2_ENA_SHIFT 0 /* EQ2_ENA */
  4890. #define ARIZONA_EQ2_ENA_WIDTH 1 /* EQ2_ENA */
  4891. /*
  4892. * R3623 (0xE27) - EQ2_2
  4893. */
  4894. #define ARIZONA_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
  4895. #define ARIZONA_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
  4896. #define ARIZONA_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
  4897. #define ARIZONA_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */
  4898. #define ARIZONA_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */
  4899. #define ARIZONA_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */
  4900. #define ARIZONA_EQ2_B1_MODE 0x0001 /* EQ2_B1_MODE */
  4901. #define ARIZONA_EQ2_B1_MODE_MASK 0x0001 /* EQ2_B1_MODE */
  4902. #define ARIZONA_EQ2_B1_MODE_SHIFT 0 /* EQ2_B1_MODE */
  4903. #define ARIZONA_EQ2_B1_MODE_WIDTH 1 /* EQ2_B1_MODE */
  4904. /*
  4905. * R3624 (0xE28) - EQ2_3
  4906. */
  4907. #define ARIZONA_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
  4908. #define ARIZONA_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
  4909. #define ARIZONA_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
  4910. /*
  4911. * R3625 (0xE29) - EQ2_4
  4912. */
  4913. #define ARIZONA_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
  4914. #define ARIZONA_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
  4915. #define ARIZONA_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
  4916. /*
  4917. * R3626 (0xE2A) - EQ2_5
  4918. */
  4919. #define ARIZONA_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
  4920. #define ARIZONA_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
  4921. #define ARIZONA_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
  4922. /*
  4923. * R3627 (0xE2B) - EQ2_6
  4924. */
  4925. #define ARIZONA_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
  4926. #define ARIZONA_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
  4927. #define ARIZONA_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
  4928. /*
  4929. * R3628 (0xE2C) - EQ2_7
  4930. */
  4931. #define ARIZONA_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
  4932. #define ARIZONA_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
  4933. #define ARIZONA_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
  4934. /*
  4935. * R3629 (0xE2D) - EQ2_8
  4936. */
  4937. #define ARIZONA_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
  4938. #define ARIZONA_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
  4939. #define ARIZONA_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
  4940. /*
  4941. * R3630 (0xE2E) - EQ2_9
  4942. */
  4943. #define ARIZONA_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
  4944. #define ARIZONA_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
  4945. #define ARIZONA_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
  4946. /*
  4947. * R3631 (0xE2F) - EQ2_10
  4948. */
  4949. #define ARIZONA_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
  4950. #define ARIZONA_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
  4951. #define ARIZONA_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
  4952. /*
  4953. * R3632 (0xE30) - EQ2_11
  4954. */
  4955. #define ARIZONA_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
  4956. #define ARIZONA_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
  4957. #define ARIZONA_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
  4958. /*
  4959. * R3633 (0xE31) - EQ2_12
  4960. */
  4961. #define ARIZONA_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
  4962. #define ARIZONA_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
  4963. #define ARIZONA_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
  4964. /*
  4965. * R3634 (0xE32) - EQ2_13
  4966. */
  4967. #define ARIZONA_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
  4968. #define ARIZONA_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
  4969. #define ARIZONA_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
  4970. /*
  4971. * R3635 (0xE33) - EQ2_14
  4972. */
  4973. #define ARIZONA_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
  4974. #define ARIZONA_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
  4975. #define ARIZONA_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
  4976. /*
  4977. * R3636 (0xE34) - EQ2_15
  4978. */
  4979. #define ARIZONA_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
  4980. #define ARIZONA_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
  4981. #define ARIZONA_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
  4982. /*
  4983. * R3637 (0xE35) - EQ2_16
  4984. */
  4985. #define ARIZONA_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
  4986. #define ARIZONA_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
  4987. #define ARIZONA_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
  4988. /*
  4989. * R3638 (0xE36) - EQ2_17
  4990. */
  4991. #define ARIZONA_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
  4992. #define ARIZONA_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
  4993. #define ARIZONA_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
  4994. /*
  4995. * R3639 (0xE37) - EQ2_18
  4996. */
  4997. #define ARIZONA_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
  4998. #define ARIZONA_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
  4999. #define ARIZONA_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
  5000. /*
  5001. * R3640 (0xE38) - EQ2_19
  5002. */
  5003. #define ARIZONA_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
  5004. #define ARIZONA_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
  5005. #define ARIZONA_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
  5006. /*
  5007. * R3641 (0xE39) - EQ2_20
  5008. */
  5009. #define ARIZONA_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
  5010. #define ARIZONA_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
  5011. #define ARIZONA_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
  5012. /*
  5013. * R3642 (0xE3A) - EQ2_21
  5014. */
  5015. #define ARIZONA_EQ2_B1_C_MASK 0xFFFF /* EQ2_B1_C - [15:0] */
  5016. #define ARIZONA_EQ2_B1_C_SHIFT 0 /* EQ2_B1_C - [15:0] */
  5017. #define ARIZONA_EQ2_B1_C_WIDTH 16 /* EQ2_B1_C - [15:0] */
  5018. /*
  5019. * R3644 (0xE3C) - EQ3_1
  5020. */
  5021. #define ARIZONA_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
  5022. #define ARIZONA_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
  5023. #define ARIZONA_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
  5024. #define ARIZONA_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */
  5025. #define ARIZONA_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */
  5026. #define ARIZONA_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */
  5027. #define ARIZONA_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */
  5028. #define ARIZONA_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */
  5029. #define ARIZONA_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */
  5030. #define ARIZONA_EQ3_ENA 0x0001 /* EQ3_ENA */
  5031. #define ARIZONA_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */
  5032. #define ARIZONA_EQ3_ENA_SHIFT 0 /* EQ3_ENA */
  5033. #define ARIZONA_EQ3_ENA_WIDTH 1 /* EQ3_ENA */
  5034. /*
  5035. * R3645 (0xE3D) - EQ3_2
  5036. */
  5037. #define ARIZONA_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
  5038. #define ARIZONA_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
  5039. #define ARIZONA_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
  5040. #define ARIZONA_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */
  5041. #define ARIZONA_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */
  5042. #define ARIZONA_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */
  5043. #define ARIZONA_EQ3_B1_MODE 0x0001 /* EQ3_B1_MODE */
  5044. #define ARIZONA_EQ3_B1_MODE_MASK 0x0001 /* EQ3_B1_MODE */
  5045. #define ARIZONA_EQ3_B1_MODE_SHIFT 0 /* EQ3_B1_MODE */
  5046. #define ARIZONA_EQ3_B1_MODE_WIDTH 1 /* EQ3_B1_MODE */
  5047. /*
  5048. * R3646 (0xE3E) - EQ3_3
  5049. */
  5050. #define ARIZONA_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
  5051. #define ARIZONA_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
  5052. #define ARIZONA_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
  5053. /*
  5054. * R3647 (0xE3F) - EQ3_4
  5055. */
  5056. #define ARIZONA_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
  5057. #define ARIZONA_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
  5058. #define ARIZONA_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
  5059. /*
  5060. * R3648 (0xE40) - EQ3_5
  5061. */
  5062. #define ARIZONA_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
  5063. #define ARIZONA_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
  5064. #define ARIZONA_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
  5065. /*
  5066. * R3649 (0xE41) - EQ3_6
  5067. */
  5068. #define ARIZONA_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
  5069. #define ARIZONA_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
  5070. #define ARIZONA_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
  5071. /*
  5072. * R3650 (0xE42) - EQ3_7
  5073. */
  5074. #define ARIZONA_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
  5075. #define ARIZONA_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
  5076. #define ARIZONA_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
  5077. /*
  5078. * R3651 (0xE43) - EQ3_8
  5079. */
  5080. #define ARIZONA_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
  5081. #define ARIZONA_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
  5082. #define ARIZONA_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
  5083. /*
  5084. * R3652 (0xE44) - EQ3_9
  5085. */
  5086. #define ARIZONA_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
  5087. #define ARIZONA_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
  5088. #define ARIZONA_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
  5089. /*
  5090. * R3653 (0xE45) - EQ3_10
  5091. */
  5092. #define ARIZONA_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
  5093. #define ARIZONA_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
  5094. #define ARIZONA_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
  5095. /*
  5096. * R3654 (0xE46) - EQ3_11
  5097. */
  5098. #define ARIZONA_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
  5099. #define ARIZONA_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
  5100. #define ARIZONA_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
  5101. /*
  5102. * R3655 (0xE47) - EQ3_12
  5103. */
  5104. #define ARIZONA_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
  5105. #define ARIZONA_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
  5106. #define ARIZONA_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
  5107. /*
  5108. * R3656 (0xE48) - EQ3_13
  5109. */
  5110. #define ARIZONA_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
  5111. #define ARIZONA_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
  5112. #define ARIZONA_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
  5113. /*
  5114. * R3657 (0xE49) - EQ3_14
  5115. */
  5116. #define ARIZONA_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
  5117. #define ARIZONA_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
  5118. #define ARIZONA_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
  5119. /*
  5120. * R3658 (0xE4A) - EQ3_15
  5121. */
  5122. #define ARIZONA_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
  5123. #define ARIZONA_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
  5124. #define ARIZONA_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
  5125. /*
  5126. * R3659 (0xE4B) - EQ3_16
  5127. */
  5128. #define ARIZONA_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
  5129. #define ARIZONA_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
  5130. #define ARIZONA_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
  5131. /*
  5132. * R3660 (0xE4C) - EQ3_17
  5133. */
  5134. #define ARIZONA_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
  5135. #define ARIZONA_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
  5136. #define ARIZONA_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
  5137. /*
  5138. * R3661 (0xE4D) - EQ3_18
  5139. */
  5140. #define ARIZONA_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
  5141. #define ARIZONA_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
  5142. #define ARIZONA_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
  5143. /*
  5144. * R3662 (0xE4E) - EQ3_19
  5145. */
  5146. #define ARIZONA_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
  5147. #define ARIZONA_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
  5148. #define ARIZONA_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
  5149. /*
  5150. * R3663 (0xE4F) - EQ3_20
  5151. */
  5152. #define ARIZONA_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
  5153. #define ARIZONA_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
  5154. #define ARIZONA_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
  5155. /*
  5156. * R3664 (0xE50) - EQ3_21
  5157. */
  5158. #define ARIZONA_EQ3_B1_C_MASK 0xFFFF /* EQ3_B1_C - [15:0] */
  5159. #define ARIZONA_EQ3_B1_C_SHIFT 0 /* EQ3_B1_C - [15:0] */
  5160. #define ARIZONA_EQ3_B1_C_WIDTH 16 /* EQ3_B1_C - [15:0] */
  5161. /*
  5162. * R3666 (0xE52) - EQ4_1
  5163. */
  5164. #define ARIZONA_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
  5165. #define ARIZONA_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
  5166. #define ARIZONA_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
  5167. #define ARIZONA_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */
  5168. #define ARIZONA_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */
  5169. #define ARIZONA_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */
  5170. #define ARIZONA_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */
  5171. #define ARIZONA_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */
  5172. #define ARIZONA_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */
  5173. #define ARIZONA_EQ4_ENA 0x0001 /* EQ4_ENA */
  5174. #define ARIZONA_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */
  5175. #define ARIZONA_EQ4_ENA_SHIFT 0 /* EQ4_ENA */
  5176. #define ARIZONA_EQ4_ENA_WIDTH 1 /* EQ4_ENA */
  5177. /*
  5178. * R3667 (0xE53) - EQ4_2
  5179. */
  5180. #define ARIZONA_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
  5181. #define ARIZONA_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
  5182. #define ARIZONA_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
  5183. #define ARIZONA_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */
  5184. #define ARIZONA_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */
  5185. #define ARIZONA_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */
  5186. #define ARIZONA_EQ4_B1_MODE 0x0001 /* EQ4_B1_MODE */
  5187. #define ARIZONA_EQ4_B1_MODE_MASK 0x0001 /* EQ4_B1_MODE */
  5188. #define ARIZONA_EQ4_B1_MODE_SHIFT 0 /* EQ4_B1_MODE */
  5189. #define ARIZONA_EQ4_B1_MODE_WIDTH 1 /* EQ4_B1_MODE */
  5190. /*
  5191. * R3668 (0xE54) - EQ4_3
  5192. */
  5193. #define ARIZONA_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
  5194. #define ARIZONA_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
  5195. #define ARIZONA_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
  5196. /*
  5197. * R3669 (0xE55) - EQ4_4
  5198. */
  5199. #define ARIZONA_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
  5200. #define ARIZONA_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
  5201. #define ARIZONA_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
  5202. /*
  5203. * R3670 (0xE56) - EQ4_5
  5204. */
  5205. #define ARIZONA_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
  5206. #define ARIZONA_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
  5207. #define ARIZONA_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
  5208. /*
  5209. * R3671 (0xE57) - EQ4_6
  5210. */
  5211. #define ARIZONA_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
  5212. #define ARIZONA_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
  5213. #define ARIZONA_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
  5214. /*
  5215. * R3672 (0xE58) - EQ4_7
  5216. */
  5217. #define ARIZONA_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
  5218. #define ARIZONA_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
  5219. #define ARIZONA_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
  5220. /*
  5221. * R3673 (0xE59) - EQ4_8
  5222. */
  5223. #define ARIZONA_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
  5224. #define ARIZONA_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
  5225. #define ARIZONA_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
  5226. /*
  5227. * R3674 (0xE5A) - EQ4_9
  5228. */
  5229. #define ARIZONA_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
  5230. #define ARIZONA_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
  5231. #define ARIZONA_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
  5232. /*
  5233. * R3675 (0xE5B) - EQ4_10
  5234. */
  5235. #define ARIZONA_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
  5236. #define ARIZONA_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
  5237. #define ARIZONA_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
  5238. /*
  5239. * R3676 (0xE5C) - EQ4_11
  5240. */
  5241. #define ARIZONA_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
  5242. #define ARIZONA_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
  5243. #define ARIZONA_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
  5244. /*
  5245. * R3677 (0xE5D) - EQ4_12
  5246. */
  5247. #define ARIZONA_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
  5248. #define ARIZONA_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
  5249. #define ARIZONA_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
  5250. /*
  5251. * R3678 (0xE5E) - EQ4_13
  5252. */
  5253. #define ARIZONA_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
  5254. #define ARIZONA_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
  5255. #define ARIZONA_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
  5256. /*
  5257. * R3679 (0xE5F) - EQ4_14
  5258. */
  5259. #define ARIZONA_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
  5260. #define ARIZONA_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
  5261. #define ARIZONA_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
  5262. /*
  5263. * R3680 (0xE60) - EQ4_15
  5264. */
  5265. #define ARIZONA_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
  5266. #define ARIZONA_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
  5267. #define ARIZONA_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
  5268. /*
  5269. * R3681 (0xE61) - EQ4_16
  5270. */
  5271. #define ARIZONA_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
  5272. #define ARIZONA_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
  5273. #define ARIZONA_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
  5274. /*
  5275. * R3682 (0xE62) - EQ4_17
  5276. */
  5277. #define ARIZONA_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
  5278. #define ARIZONA_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
  5279. #define ARIZONA_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
  5280. /*
  5281. * R3683 (0xE63) - EQ4_18
  5282. */
  5283. #define ARIZONA_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
  5284. #define ARIZONA_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
  5285. #define ARIZONA_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
  5286. /*
  5287. * R3684 (0xE64) - EQ4_19
  5288. */
  5289. #define ARIZONA_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
  5290. #define ARIZONA_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
  5291. #define ARIZONA_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
  5292. /*
  5293. * R3685 (0xE65) - EQ4_20
  5294. */
  5295. #define ARIZONA_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
  5296. #define ARIZONA_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
  5297. #define ARIZONA_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
  5298. /*
  5299. * R3686 (0xE66) - EQ4_21
  5300. */
  5301. #define ARIZONA_EQ4_B1_C_MASK 0xFFFF /* EQ4_B1_C - [15:0] */
  5302. #define ARIZONA_EQ4_B1_C_SHIFT 0 /* EQ4_B1_C - [15:0] */
  5303. #define ARIZONA_EQ4_B1_C_WIDTH 16 /* EQ4_B1_C - [15:0] */
  5304. /*
  5305. * R3712 (0xE80) - DRC1 ctrl1
  5306. */
  5307. #define ARIZONA_DRC1_SIG_DET_RMS_MASK 0xF800 /* DRC1_SIG_DET_RMS - [15:11] */
  5308. #define ARIZONA_DRC1_SIG_DET_RMS_SHIFT 11 /* DRC1_SIG_DET_RMS - [15:11] */
  5309. #define ARIZONA_DRC1_SIG_DET_RMS_WIDTH 5 /* DRC1_SIG_DET_RMS - [15:11] */
  5310. #define ARIZONA_DRC1_SIG_DET_PK_MASK 0x0600 /* DRC1_SIG_DET_PK - [10:9] */
  5311. #define ARIZONA_DRC1_SIG_DET_PK_SHIFT 9 /* DRC1_SIG_DET_PK - [10:9] */
  5312. #define ARIZONA_DRC1_SIG_DET_PK_WIDTH 2 /* DRC1_SIG_DET_PK - [10:9] */
  5313. #define ARIZONA_DRC1_NG_ENA 0x0100 /* DRC1_NG_ENA */
  5314. #define ARIZONA_DRC1_NG_ENA_MASK 0x0100 /* DRC1_NG_ENA */
  5315. #define ARIZONA_DRC1_NG_ENA_SHIFT 8 /* DRC1_NG_ENA */
  5316. #define ARIZONA_DRC1_NG_ENA_WIDTH 1 /* DRC1_NG_ENA */
  5317. #define ARIZONA_DRC1_SIG_DET_MODE 0x0080 /* DRC1_SIG_DET_MODE */
  5318. #define ARIZONA_DRC1_SIG_DET_MODE_MASK 0x0080 /* DRC1_SIG_DET_MODE */
  5319. #define ARIZONA_DRC1_SIG_DET_MODE_SHIFT 7 /* DRC1_SIG_DET_MODE */
  5320. #define ARIZONA_DRC1_SIG_DET_MODE_WIDTH 1 /* DRC1_SIG_DET_MODE */
  5321. #define ARIZONA_DRC1_SIG_DET 0x0040 /* DRC1_SIG_DET */
  5322. #define ARIZONA_DRC1_SIG_DET_MASK 0x0040 /* DRC1_SIG_DET */
  5323. #define ARIZONA_DRC1_SIG_DET_SHIFT 6 /* DRC1_SIG_DET */
  5324. #define ARIZONA_DRC1_SIG_DET_WIDTH 1 /* DRC1_SIG_DET */
  5325. #define ARIZONA_DRC1_KNEE2_OP_ENA 0x0020 /* DRC1_KNEE2_OP_ENA */
  5326. #define ARIZONA_DRC1_KNEE2_OP_ENA_MASK 0x0020 /* DRC1_KNEE2_OP_ENA */
  5327. #define ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT 5 /* DRC1_KNEE2_OP_ENA */
  5328. #define ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH 1 /* DRC1_KNEE2_OP_ENA */
  5329. #define ARIZONA_DRC1_QR 0x0010 /* DRC1_QR */
  5330. #define ARIZONA_DRC1_QR_MASK 0x0010 /* DRC1_QR */
  5331. #define ARIZONA_DRC1_QR_SHIFT 4 /* DRC1_QR */
  5332. #define ARIZONA_DRC1_QR_WIDTH 1 /* DRC1_QR */
  5333. #define ARIZONA_DRC1_ANTICLIP 0x0008 /* DRC1_ANTICLIP */
  5334. #define ARIZONA_DRC1_ANTICLIP_MASK 0x0008 /* DRC1_ANTICLIP */
  5335. #define ARIZONA_DRC1_ANTICLIP_SHIFT 3 /* DRC1_ANTICLIP */
  5336. #define ARIZONA_DRC1_ANTICLIP_WIDTH 1 /* DRC1_ANTICLIP */
  5337. #define ARIZONA_DRC1L_ENA 0x0002 /* DRC1L_ENA */
  5338. #define ARIZONA_DRC1L_ENA_MASK 0x0002 /* DRC1L_ENA */
  5339. #define ARIZONA_DRC1L_ENA_SHIFT 1 /* DRC1L_ENA */
  5340. #define ARIZONA_DRC1L_ENA_WIDTH 1 /* DRC1L_ENA */
  5341. #define ARIZONA_DRC1R_ENA 0x0001 /* DRC1R_ENA */
  5342. #define ARIZONA_DRC1R_ENA_MASK 0x0001 /* DRC1R_ENA */
  5343. #define ARIZONA_DRC1R_ENA_SHIFT 0 /* DRC1R_ENA */
  5344. #define ARIZONA_DRC1R_ENA_WIDTH 1 /* DRC1R_ENA */
  5345. /*
  5346. * R3713 (0xE81) - DRC1 ctrl2
  5347. */
  5348. #define ARIZONA_DRC1_ATK_MASK 0x1E00 /* DRC1_ATK - [12:9] */
  5349. #define ARIZONA_DRC1_ATK_SHIFT 9 /* DRC1_ATK - [12:9] */
  5350. #define ARIZONA_DRC1_ATK_WIDTH 4 /* DRC1_ATK - [12:9] */
  5351. #define ARIZONA_DRC1_DCY_MASK 0x01E0 /* DRC1_DCY - [8:5] */
  5352. #define ARIZONA_DRC1_DCY_SHIFT 5 /* DRC1_DCY - [8:5] */
  5353. #define ARIZONA_DRC1_DCY_WIDTH 4 /* DRC1_DCY - [8:5] */
  5354. #define ARIZONA_DRC1_MINGAIN_MASK 0x001C /* DRC1_MINGAIN - [4:2] */
  5355. #define ARIZONA_DRC1_MINGAIN_SHIFT 2 /* DRC1_MINGAIN - [4:2] */
  5356. #define ARIZONA_DRC1_MINGAIN_WIDTH 3 /* DRC1_MINGAIN - [4:2] */
  5357. #define ARIZONA_DRC1_MAXGAIN_MASK 0x0003 /* DRC1_MAXGAIN - [1:0] */
  5358. #define ARIZONA_DRC1_MAXGAIN_SHIFT 0 /* DRC1_MAXGAIN - [1:0] */
  5359. #define ARIZONA_DRC1_MAXGAIN_WIDTH 2 /* DRC1_MAXGAIN - [1:0] */
  5360. /*
  5361. * R3714 (0xE82) - DRC1 ctrl3
  5362. */
  5363. #define ARIZONA_DRC1_NG_MINGAIN_MASK 0xF000 /* DRC1_NG_MINGAIN - [15:12] */
  5364. #define ARIZONA_DRC1_NG_MINGAIN_SHIFT 12 /* DRC1_NG_MINGAIN - [15:12] */
  5365. #define ARIZONA_DRC1_NG_MINGAIN_WIDTH 4 /* DRC1_NG_MINGAIN - [15:12] */
  5366. #define ARIZONA_DRC1_NG_EXP_MASK 0x0C00 /* DRC1_NG_EXP - [11:10] */
  5367. #define ARIZONA_DRC1_NG_EXP_SHIFT 10 /* DRC1_NG_EXP - [11:10] */
  5368. #define ARIZONA_DRC1_NG_EXP_WIDTH 2 /* DRC1_NG_EXP - [11:10] */
  5369. #define ARIZONA_DRC1_QR_THR_MASK 0x0300 /* DRC1_QR_THR - [9:8] */
  5370. #define ARIZONA_DRC1_QR_THR_SHIFT 8 /* DRC1_QR_THR - [9:8] */
  5371. #define ARIZONA_DRC1_QR_THR_WIDTH 2 /* DRC1_QR_THR - [9:8] */
  5372. #define ARIZONA_DRC1_QR_DCY_MASK 0x00C0 /* DRC1_QR_DCY - [7:6] */
  5373. #define ARIZONA_DRC1_QR_DCY_SHIFT 6 /* DRC1_QR_DCY - [7:6] */
  5374. #define ARIZONA_DRC1_QR_DCY_WIDTH 2 /* DRC1_QR_DCY - [7:6] */
  5375. #define ARIZONA_DRC1_HI_COMP_MASK 0x0038 /* DRC1_HI_COMP - [5:3] */
  5376. #define ARIZONA_DRC1_HI_COMP_SHIFT 3 /* DRC1_HI_COMP - [5:3] */
  5377. #define ARIZONA_DRC1_HI_COMP_WIDTH 3 /* DRC1_HI_COMP - [5:3] */
  5378. #define ARIZONA_DRC1_LO_COMP_MASK 0x0007 /* DRC1_LO_COMP - [2:0] */
  5379. #define ARIZONA_DRC1_LO_COMP_SHIFT 0 /* DRC1_LO_COMP - [2:0] */
  5380. #define ARIZONA_DRC1_LO_COMP_WIDTH 3 /* DRC1_LO_COMP - [2:0] */
  5381. /*
  5382. * R3715 (0xE83) - DRC1 ctrl4
  5383. */
  5384. #define ARIZONA_DRC1_KNEE_IP_MASK 0x07E0 /* DRC1_KNEE_IP - [10:5] */
  5385. #define ARIZONA_DRC1_KNEE_IP_SHIFT 5 /* DRC1_KNEE_IP - [10:5] */
  5386. #define ARIZONA_DRC1_KNEE_IP_WIDTH 6 /* DRC1_KNEE_IP - [10:5] */
  5387. #define ARIZONA_DRC1_KNEE_OP_MASK 0x001F /* DRC1_KNEE_OP - [4:0] */
  5388. #define ARIZONA_DRC1_KNEE_OP_SHIFT 0 /* DRC1_KNEE_OP - [4:0] */
  5389. #define ARIZONA_DRC1_KNEE_OP_WIDTH 5 /* DRC1_KNEE_OP - [4:0] */
  5390. /*
  5391. * R3716 (0xE84) - DRC1 ctrl5
  5392. */
  5393. #define ARIZONA_DRC1_KNEE2_IP_MASK 0x03E0 /* DRC1_KNEE2_IP - [9:5] */
  5394. #define ARIZONA_DRC1_KNEE2_IP_SHIFT 5 /* DRC1_KNEE2_IP - [9:5] */
  5395. #define ARIZONA_DRC1_KNEE2_IP_WIDTH 5 /* DRC1_KNEE2_IP - [9:5] */
  5396. #define ARIZONA_DRC1_KNEE2_OP_MASK 0x001F /* DRC1_KNEE2_OP - [4:0] */
  5397. #define ARIZONA_DRC1_KNEE2_OP_SHIFT 0 /* DRC1_KNEE2_OP - [4:0] */
  5398. #define ARIZONA_DRC1_KNEE2_OP_WIDTH 5 /* DRC1_KNEE2_OP - [4:0] */
  5399. /*
  5400. * R3721 (0xE89) - DRC2 ctrl1
  5401. */
  5402. #define ARIZONA_DRC2_SIG_DET_RMS_MASK 0xF800 /* DRC2_SIG_DET_RMS - [15:11] */
  5403. #define ARIZONA_DRC2_SIG_DET_RMS_SHIFT 11 /* DRC2_SIG_DET_RMS - [15:11] */
  5404. #define ARIZONA_DRC2_SIG_DET_RMS_WIDTH 5 /* DRC2_SIG_DET_RMS - [15:11] */
  5405. #define ARIZONA_DRC2_SIG_DET_PK_MASK 0x0600 /* DRC2_SIG_DET_PK - [10:9] */
  5406. #define ARIZONA_DRC2_SIG_DET_PK_SHIFT 9 /* DRC2_SIG_DET_PK - [10:9] */
  5407. #define ARIZONA_DRC2_SIG_DET_PK_WIDTH 2 /* DRC2_SIG_DET_PK - [10:9] */
  5408. #define ARIZONA_DRC2_NG_ENA 0x0100 /* DRC2_NG_ENA */
  5409. #define ARIZONA_DRC2_NG_ENA_MASK 0x0100 /* DRC2_NG_ENA */
  5410. #define ARIZONA_DRC2_NG_ENA_SHIFT 8 /* DRC2_NG_ENA */
  5411. #define ARIZONA_DRC2_NG_ENA_WIDTH 1 /* DRC2_NG_ENA */
  5412. #define ARIZONA_DRC2_SIG_DET_MODE 0x0080 /* DRC2_SIG_DET_MODE */
  5413. #define ARIZONA_DRC2_SIG_DET_MODE_MASK 0x0080 /* DRC2_SIG_DET_MODE */
  5414. #define ARIZONA_DRC2_SIG_DET_MODE_SHIFT 7 /* DRC2_SIG_DET_MODE */
  5415. #define ARIZONA_DRC2_SIG_DET_MODE_WIDTH 1 /* DRC2_SIG_DET_MODE */
  5416. #define ARIZONA_DRC2_SIG_DET 0x0040 /* DRC2_SIG_DET */
  5417. #define ARIZONA_DRC2_SIG_DET_MASK 0x0040 /* DRC2_SIG_DET */
  5418. #define ARIZONA_DRC2_SIG_DET_SHIFT 6 /* DRC2_SIG_DET */
  5419. #define ARIZONA_DRC2_SIG_DET_WIDTH 1 /* DRC2_SIG_DET */
  5420. #define ARIZONA_DRC2_KNEE2_OP_ENA 0x0020 /* DRC2_KNEE2_OP_ENA */
  5421. #define ARIZONA_DRC2_KNEE2_OP_ENA_MASK 0x0020 /* DRC2_KNEE2_OP_ENA */
  5422. #define ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT 5 /* DRC2_KNEE2_OP_ENA */
  5423. #define ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH 1 /* DRC2_KNEE2_OP_ENA */
  5424. #define ARIZONA_DRC2_QR 0x0010 /* DRC2_QR */
  5425. #define ARIZONA_DRC2_QR_MASK 0x0010 /* DRC2_QR */
  5426. #define ARIZONA_DRC2_QR_SHIFT 4 /* DRC2_QR */
  5427. #define ARIZONA_DRC2_QR_WIDTH 1 /* DRC2_QR */
  5428. #define ARIZONA_DRC2_ANTICLIP 0x0008 /* DRC2_ANTICLIP */
  5429. #define ARIZONA_DRC2_ANTICLIP_MASK 0x0008 /* DRC2_ANTICLIP */
  5430. #define ARIZONA_DRC2_ANTICLIP_SHIFT 3 /* DRC2_ANTICLIP */
  5431. #define ARIZONA_DRC2_ANTICLIP_WIDTH 1 /* DRC2_ANTICLIP */
  5432. #define ARIZONA_DRC2L_ENA 0x0002 /* DRC2L_ENA */
  5433. #define ARIZONA_DRC2L_ENA_MASK 0x0002 /* DRC2L_ENA */
  5434. #define ARIZONA_DRC2L_ENA_SHIFT 1 /* DRC2L_ENA */
  5435. #define ARIZONA_DRC2L_ENA_WIDTH 1 /* DRC2L_ENA */
  5436. #define ARIZONA_DRC2R_ENA 0x0001 /* DRC2R_ENA */
  5437. #define ARIZONA_DRC2R_ENA_MASK 0x0001 /* DRC2R_ENA */
  5438. #define ARIZONA_DRC2R_ENA_SHIFT 0 /* DRC2R_ENA */
  5439. #define ARIZONA_DRC2R_ENA_WIDTH 1 /* DRC2R_ENA */
  5440. /*
  5441. * R3722 (0xE8A) - DRC2 ctrl2
  5442. */
  5443. #define ARIZONA_DRC2_ATK_MASK 0x1E00 /* DRC2_ATK - [12:9] */
  5444. #define ARIZONA_DRC2_ATK_SHIFT 9 /* DRC2_ATK - [12:9] */
  5445. #define ARIZONA_DRC2_ATK_WIDTH 4 /* DRC2_ATK - [12:9] */
  5446. #define ARIZONA_DRC2_DCY_MASK 0x01E0 /* DRC2_DCY - [8:5] */
  5447. #define ARIZONA_DRC2_DCY_SHIFT 5 /* DRC2_DCY - [8:5] */
  5448. #define ARIZONA_DRC2_DCY_WIDTH 4 /* DRC2_DCY - [8:5] */
  5449. #define ARIZONA_DRC2_MINGAIN_MASK 0x001C /* DRC2_MINGAIN - [4:2] */
  5450. #define ARIZONA_DRC2_MINGAIN_SHIFT 2 /* DRC2_MINGAIN - [4:2] */
  5451. #define ARIZONA_DRC2_MINGAIN_WIDTH 3 /* DRC2_MINGAIN - [4:2] */
  5452. #define ARIZONA_DRC2_MAXGAIN_MASK 0x0003 /* DRC2_MAXGAIN - [1:0] */
  5453. #define ARIZONA_DRC2_MAXGAIN_SHIFT 0 /* DRC2_MAXGAIN - [1:0] */
  5454. #define ARIZONA_DRC2_MAXGAIN_WIDTH 2 /* DRC2_MAXGAIN - [1:0] */
  5455. /*
  5456. * R3723 (0xE8B) - DRC2 ctrl3
  5457. */
  5458. #define ARIZONA_DRC2_NG_MINGAIN_MASK 0xF000 /* DRC2_NG_MINGAIN - [15:12] */
  5459. #define ARIZONA_DRC2_NG_MINGAIN_SHIFT 12 /* DRC2_NG_MINGAIN - [15:12] */
  5460. #define ARIZONA_DRC2_NG_MINGAIN_WIDTH 4 /* DRC2_NG_MINGAIN - [15:12] */
  5461. #define ARIZONA_DRC2_NG_EXP_MASK 0x0C00 /* DRC2_NG_EXP - [11:10] */
  5462. #define ARIZONA_DRC2_NG_EXP_SHIFT 10 /* DRC2_NG_EXP - [11:10] */
  5463. #define ARIZONA_DRC2_NG_EXP_WIDTH 2 /* DRC2_NG_EXP - [11:10] */
  5464. #define ARIZONA_DRC2_QR_THR_MASK 0x0300 /* DRC2_QR_THR - [9:8] */
  5465. #define ARIZONA_DRC2_QR_THR_SHIFT 8 /* DRC2_QR_THR - [9:8] */
  5466. #define ARIZONA_DRC2_QR_THR_WIDTH 2 /* DRC2_QR_THR - [9:8] */
  5467. #define ARIZONA_DRC2_QR_DCY_MASK 0x00C0 /* DRC2_QR_DCY - [7:6] */
  5468. #define ARIZONA_DRC2_QR_DCY_SHIFT 6 /* DRC2_QR_DCY - [7:6] */
  5469. #define ARIZONA_DRC2_QR_DCY_WIDTH 2 /* DRC2_QR_DCY - [7:6] */
  5470. #define ARIZONA_DRC2_HI_COMP_MASK 0x0038 /* DRC2_HI_COMP - [5:3] */
  5471. #define ARIZONA_DRC2_HI_COMP_SHIFT 3 /* DRC2_HI_COMP - [5:3] */
  5472. #define ARIZONA_DRC2_HI_COMP_WIDTH 3 /* DRC2_HI_COMP - [5:3] */
  5473. #define ARIZONA_DRC2_LO_COMP_MASK 0x0007 /* DRC2_LO_COMP - [2:0] */
  5474. #define ARIZONA_DRC2_LO_COMP_SHIFT 0 /* DRC2_LO_COMP - [2:0] */
  5475. #define ARIZONA_DRC2_LO_COMP_WIDTH 3 /* DRC2_LO_COMP - [2:0] */
  5476. /*
  5477. * R3724 (0xE8C) - DRC2 ctrl4
  5478. */
  5479. #define ARIZONA_DRC2_KNEE_IP_MASK 0x07E0 /* DRC2_KNEE_IP - [10:5] */
  5480. #define ARIZONA_DRC2_KNEE_IP_SHIFT 5 /* DRC2_KNEE_IP - [10:5] */
  5481. #define ARIZONA_DRC2_KNEE_IP_WIDTH 6 /* DRC2_KNEE_IP - [10:5] */
  5482. #define ARIZONA_DRC2_KNEE_OP_MASK 0x001F /* DRC2_KNEE_OP - [4:0] */
  5483. #define ARIZONA_DRC2_KNEE_OP_SHIFT 0 /* DRC2_KNEE_OP - [4:0] */
  5484. #define ARIZONA_DRC2_KNEE_OP_WIDTH 5 /* DRC2_KNEE_OP - [4:0] */
  5485. /*
  5486. * R3725 (0xE8D) - DRC2 ctrl5
  5487. */
  5488. #define ARIZONA_DRC2_KNEE2_IP_MASK 0x03E0 /* DRC2_KNEE2_IP - [9:5] */
  5489. #define ARIZONA_DRC2_KNEE2_IP_SHIFT 5 /* DRC2_KNEE2_IP - [9:5] */
  5490. #define ARIZONA_DRC2_KNEE2_IP_WIDTH 5 /* DRC2_KNEE2_IP - [9:5] */
  5491. #define ARIZONA_DRC2_KNEE2_OP_MASK 0x001F /* DRC2_KNEE2_OP - [4:0] */
  5492. #define ARIZONA_DRC2_KNEE2_OP_SHIFT 0 /* DRC2_KNEE2_OP - [4:0] */
  5493. #define ARIZONA_DRC2_KNEE2_OP_WIDTH 5 /* DRC2_KNEE2_OP - [4:0] */
  5494. /*
  5495. * R3776 (0xEC0) - HPLPF1_1
  5496. */
  5497. #define ARIZONA_LHPF1_MODE 0x0002 /* LHPF1_MODE */
  5498. #define ARIZONA_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
  5499. #define ARIZONA_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
  5500. #define ARIZONA_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
  5501. #define ARIZONA_LHPF1_ENA 0x0001 /* LHPF1_ENA */
  5502. #define ARIZONA_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
  5503. #define ARIZONA_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
  5504. #define ARIZONA_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
  5505. /*
  5506. * R3777 (0xEC1) - HPLPF1_2
  5507. */
  5508. #define ARIZONA_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
  5509. #define ARIZONA_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
  5510. #define ARIZONA_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
  5511. /*
  5512. * R3780 (0xEC4) - HPLPF2_1
  5513. */
  5514. #define ARIZONA_LHPF2_MODE 0x0002 /* LHPF2_MODE */
  5515. #define ARIZONA_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
  5516. #define ARIZONA_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
  5517. #define ARIZONA_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
  5518. #define ARIZONA_LHPF2_ENA 0x0001 /* LHPF2_ENA */
  5519. #define ARIZONA_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
  5520. #define ARIZONA_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
  5521. #define ARIZONA_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
  5522. /*
  5523. * R3781 (0xEC5) - HPLPF2_2
  5524. */
  5525. #define ARIZONA_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
  5526. #define ARIZONA_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
  5527. #define ARIZONA_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
  5528. /*
  5529. * R3784 (0xEC8) - HPLPF3_1
  5530. */
  5531. #define ARIZONA_LHPF3_MODE 0x0002 /* LHPF3_MODE */
  5532. #define ARIZONA_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */
  5533. #define ARIZONA_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */
  5534. #define ARIZONA_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */
  5535. #define ARIZONA_LHPF3_ENA 0x0001 /* LHPF3_ENA */
  5536. #define ARIZONA_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */
  5537. #define ARIZONA_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */
  5538. #define ARIZONA_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */
  5539. /*
  5540. * R3785 (0xEC9) - HPLPF3_2
  5541. */
  5542. #define ARIZONA_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
  5543. #define ARIZONA_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
  5544. #define ARIZONA_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
  5545. /*
  5546. * R3788 (0xECC) - HPLPF4_1
  5547. */
  5548. #define ARIZONA_LHPF4_MODE 0x0002 /* LHPF4_MODE */
  5549. #define ARIZONA_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */
  5550. #define ARIZONA_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */
  5551. #define ARIZONA_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */
  5552. #define ARIZONA_LHPF4_ENA 0x0001 /* LHPF4_ENA */
  5553. #define ARIZONA_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */
  5554. #define ARIZONA_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */
  5555. #define ARIZONA_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */
  5556. /*
  5557. * R3789 (0xECD) - HPLPF4_2
  5558. */
  5559. #define ARIZONA_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
  5560. #define ARIZONA_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
  5561. #define ARIZONA_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
  5562. /*
  5563. * R3808 (0xEE0) - ASRC_ENABLE
  5564. */
  5565. #define ARIZONA_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */
  5566. #define ARIZONA_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */
  5567. #define ARIZONA_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */
  5568. #define ARIZONA_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */
  5569. #define ARIZONA_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */
  5570. #define ARIZONA_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */
  5571. #define ARIZONA_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */
  5572. #define ARIZONA_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */
  5573. #define ARIZONA_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */
  5574. #define ARIZONA_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */
  5575. #define ARIZONA_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */
  5576. #define ARIZONA_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */
  5577. #define ARIZONA_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */
  5578. #define ARIZONA_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */
  5579. #define ARIZONA_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */
  5580. #define ARIZONA_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */
  5581. /*
  5582. * R3810 (0xEE2) - ASRC_RATE1
  5583. */
  5584. #define ARIZONA_ASRC_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */
  5585. #define ARIZONA_ASRC_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */
  5586. #define ARIZONA_ASRC_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */
  5587. /*
  5588. * R3811 (0xEE3) - ASRC_RATE2
  5589. */
  5590. #define ARIZONA_ASRC_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */
  5591. #define ARIZONA_ASRC_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */
  5592. #define ARIZONA_ASRC_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */
  5593. /*
  5594. * R3824 (0xEF0) - ISRC 1 CTRL 1
  5595. */
  5596. #define ARIZONA_ISRC1_FSH_MASK 0x7800 /* ISRC1_FSH - [14:11] */
  5597. #define ARIZONA_ISRC1_FSH_SHIFT 11 /* ISRC1_FSH - [14:11] */
  5598. #define ARIZONA_ISRC1_FSH_WIDTH 4 /* ISRC1_FSH - [14:11] */
  5599. #define ARIZONA_ISRC1_CLK_SEL_MASK 0x0700 /* ISRC1_CLK_SEL - [10:8] */
  5600. #define ARIZONA_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [10:8] */
  5601. #define ARIZONA_ISRC1_CLK_SEL_WIDTH 3 /* ISRC1_CLK_SEL - [10:8] */
  5602. /*
  5603. * R3825 (0xEF1) - ISRC 1 CTRL 2
  5604. */
  5605. #define ARIZONA_ISRC1_FSL_MASK 0x7800 /* ISRC1_FSL - [14:11] */
  5606. #define ARIZONA_ISRC1_FSL_SHIFT 11 /* ISRC1_FSL - [14:11] */
  5607. #define ARIZONA_ISRC1_FSL_WIDTH 4 /* ISRC1_FSL - [14:11] */
  5608. /*
  5609. * R3826 (0xEF2) - ISRC 1 CTRL 3
  5610. */
  5611. #define ARIZONA_ISRC1_INT0_ENA 0x8000 /* ISRC1_INT0_ENA */
  5612. #define ARIZONA_ISRC1_INT0_ENA_MASK 0x8000 /* ISRC1_INT0_ENA */
  5613. #define ARIZONA_ISRC1_INT0_ENA_SHIFT 15 /* ISRC1_INT0_ENA */
  5614. #define ARIZONA_ISRC1_INT0_ENA_WIDTH 1 /* ISRC1_INT0_ENA */
  5615. #define ARIZONA_ISRC1_INT1_ENA 0x4000 /* ISRC1_INT1_ENA */
  5616. #define ARIZONA_ISRC1_INT1_ENA_MASK 0x4000 /* ISRC1_INT1_ENA */
  5617. #define ARIZONA_ISRC1_INT1_ENA_SHIFT 14 /* ISRC1_INT1_ENA */
  5618. #define ARIZONA_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */
  5619. #define ARIZONA_ISRC1_INT2_ENA 0x2000 /* ISRC1_INT2_ENA */
  5620. #define ARIZONA_ISRC1_INT2_ENA_MASK 0x2000 /* ISRC1_INT2_ENA */
  5621. #define ARIZONA_ISRC1_INT2_ENA_SHIFT 13 /* ISRC1_INT2_ENA */
  5622. #define ARIZONA_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */
  5623. #define ARIZONA_ISRC1_INT3_ENA 0x1000 /* ISRC1_INT3_ENA */
  5624. #define ARIZONA_ISRC1_INT3_ENA_MASK 0x1000 /* ISRC1_INT3_ENA */
  5625. #define ARIZONA_ISRC1_INT3_ENA_SHIFT 12 /* ISRC1_INT3_ENA */
  5626. #define ARIZONA_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */
  5627. #define ARIZONA_ISRC1_DEC0_ENA 0x0200 /* ISRC1_DEC0_ENA */
  5628. #define ARIZONA_ISRC1_DEC0_ENA_MASK 0x0200 /* ISRC1_DEC0_ENA */
  5629. #define ARIZONA_ISRC1_DEC0_ENA_SHIFT 9 /* ISRC1_DEC0_ENA */
  5630. #define ARIZONA_ISRC1_DEC0_ENA_WIDTH 1 /* ISRC1_DEC0_ENA */
  5631. #define ARIZONA_ISRC1_DEC1_ENA 0x0100 /* ISRC1_DEC1_ENA */
  5632. #define ARIZONA_ISRC1_DEC1_ENA_MASK 0x0100 /* ISRC1_DEC1_ENA */
  5633. #define ARIZONA_ISRC1_DEC1_ENA_SHIFT 8 /* ISRC1_DEC1_ENA */
  5634. #define ARIZONA_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */
  5635. #define ARIZONA_ISRC1_DEC2_ENA 0x0080 /* ISRC1_DEC2_ENA */
  5636. #define ARIZONA_ISRC1_DEC2_ENA_MASK 0x0080 /* ISRC1_DEC2_ENA */
  5637. #define ARIZONA_ISRC1_DEC2_ENA_SHIFT 7 /* ISRC1_DEC2_ENA */
  5638. #define ARIZONA_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */
  5639. #define ARIZONA_ISRC1_DEC3_ENA 0x0040 /* ISRC1_DEC3_ENA */
  5640. #define ARIZONA_ISRC1_DEC3_ENA_MASK 0x0040 /* ISRC1_DEC3_ENA */
  5641. #define ARIZONA_ISRC1_DEC3_ENA_SHIFT 6 /* ISRC1_DEC3_ENA */
  5642. #define ARIZONA_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */
  5643. #define ARIZONA_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */
  5644. #define ARIZONA_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */
  5645. #define ARIZONA_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */
  5646. #define ARIZONA_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */
  5647. /*
  5648. * R3827 (0xEF3) - ISRC 2 CTRL 1
  5649. */
  5650. #define ARIZONA_ISRC2_FSH_MASK 0x7800 /* ISRC2_FSH - [14:11] */
  5651. #define ARIZONA_ISRC2_FSH_SHIFT 11 /* ISRC2_FSH - [14:11] */
  5652. #define ARIZONA_ISRC2_FSH_WIDTH 4 /* ISRC2_FSH - [14:11] */
  5653. #define ARIZONA_ISRC2_CLK_SEL_MASK 0x0700 /* ISRC2_CLK_SEL - [10:8] */
  5654. #define ARIZONA_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [10:8] */
  5655. #define ARIZONA_ISRC2_CLK_SEL_WIDTH 3 /* ISRC2_CLK_SEL - [10:8] */
  5656. /*
  5657. * R3828 (0xEF4) - ISRC 2 CTRL 2
  5658. */
  5659. #define ARIZONA_ISRC2_FSL_MASK 0x7800 /* ISRC2_FSL - [14:11] */
  5660. #define ARIZONA_ISRC2_FSL_SHIFT 11 /* ISRC2_FSL - [14:11] */
  5661. #define ARIZONA_ISRC2_FSL_WIDTH 4 /* ISRC2_FSL - [14:11] */
  5662. /*
  5663. * R3829 (0xEF5) - ISRC 2 CTRL 3
  5664. */
  5665. #define ARIZONA_ISRC2_INT0_ENA 0x8000 /* ISRC2_INT0_ENA */
  5666. #define ARIZONA_ISRC2_INT0_ENA_MASK 0x8000 /* ISRC2_INT0_ENA */
  5667. #define ARIZONA_ISRC2_INT0_ENA_SHIFT 15 /* ISRC2_INT0_ENA */
  5668. #define ARIZONA_ISRC2_INT0_ENA_WIDTH 1 /* ISRC2_INT0_ENA */
  5669. #define ARIZONA_ISRC2_INT1_ENA 0x4000 /* ISRC2_INT1_ENA */
  5670. #define ARIZONA_ISRC2_INT1_ENA_MASK 0x4000 /* ISRC2_INT1_ENA */
  5671. #define ARIZONA_ISRC2_INT1_ENA_SHIFT 14 /* ISRC2_INT1_ENA */
  5672. #define ARIZONA_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */
  5673. #define ARIZONA_ISRC2_INT2_ENA 0x2000 /* ISRC2_INT2_ENA */
  5674. #define ARIZONA_ISRC2_INT2_ENA_MASK 0x2000 /* ISRC2_INT2_ENA */
  5675. #define ARIZONA_ISRC2_INT2_ENA_SHIFT 13 /* ISRC2_INT2_ENA */
  5676. #define ARIZONA_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */
  5677. #define ARIZONA_ISRC2_INT3_ENA 0x1000 /* ISRC2_INT3_ENA */
  5678. #define ARIZONA_ISRC2_INT3_ENA_MASK 0x1000 /* ISRC2_INT3_ENA */
  5679. #define ARIZONA_ISRC2_INT3_ENA_SHIFT 12 /* ISRC2_INT3_ENA */
  5680. #define ARIZONA_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */
  5681. #define ARIZONA_ISRC2_DEC0_ENA 0x0200 /* ISRC2_DEC0_ENA */
  5682. #define ARIZONA_ISRC2_DEC0_ENA_MASK 0x0200 /* ISRC2_DEC0_ENA */
  5683. #define ARIZONA_ISRC2_DEC0_ENA_SHIFT 9 /* ISRC2_DEC0_ENA */
  5684. #define ARIZONA_ISRC2_DEC0_ENA_WIDTH 1 /* ISRC2_DEC0_ENA */
  5685. #define ARIZONA_ISRC2_DEC1_ENA 0x0100 /* ISRC2_DEC1_ENA */
  5686. #define ARIZONA_ISRC2_DEC1_ENA_MASK 0x0100 /* ISRC2_DEC1_ENA */
  5687. #define ARIZONA_ISRC2_DEC1_ENA_SHIFT 8 /* ISRC2_DEC1_ENA */
  5688. #define ARIZONA_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */
  5689. #define ARIZONA_ISRC2_DEC2_ENA 0x0080 /* ISRC2_DEC2_ENA */
  5690. #define ARIZONA_ISRC2_DEC2_ENA_MASK 0x0080 /* ISRC2_DEC2_ENA */
  5691. #define ARIZONA_ISRC2_DEC2_ENA_SHIFT 7 /* ISRC2_DEC2_ENA */
  5692. #define ARIZONA_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */
  5693. #define ARIZONA_ISRC2_DEC3_ENA 0x0040 /* ISRC2_DEC3_ENA */
  5694. #define ARIZONA_ISRC2_DEC3_ENA_MASK 0x0040 /* ISRC2_DEC3_ENA */
  5695. #define ARIZONA_ISRC2_DEC3_ENA_SHIFT 6 /* ISRC2_DEC3_ENA */
  5696. #define ARIZONA_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */
  5697. #define ARIZONA_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */
  5698. #define ARIZONA_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */
  5699. #define ARIZONA_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */
  5700. #define ARIZONA_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */
  5701. /*
  5702. * R3830 (0xEF6) - ISRC 3 CTRL 1
  5703. */
  5704. #define ARIZONA_ISRC3_FSH_MASK 0x7800 /* ISRC3_FSH - [14:11] */
  5705. #define ARIZONA_ISRC3_FSH_SHIFT 11 /* ISRC3_FSH - [14:11] */
  5706. #define ARIZONA_ISRC3_FSH_WIDTH 4 /* ISRC3_FSH - [14:11] */
  5707. #define ARIZONA_ISRC3_CLK_SEL_MASK 0x0700 /* ISRC3_CLK_SEL - [10:8] */
  5708. #define ARIZONA_ISRC3_CLK_SEL_SHIFT 8 /* ISRC3_CLK_SEL - [10:8] */
  5709. #define ARIZONA_ISRC3_CLK_SEL_WIDTH 3 /* ISRC3_CLK_SEL - [10:8] */
  5710. /*
  5711. * R3831 (0xEF7) - ISRC 3 CTRL 2
  5712. */
  5713. #define ARIZONA_ISRC3_FSL_MASK 0x7800 /* ISRC3_FSL - [14:11] */
  5714. #define ARIZONA_ISRC3_FSL_SHIFT 11 /* ISRC3_FSL - [14:11] */
  5715. #define ARIZONA_ISRC3_FSL_WIDTH 4 /* ISRC3_FSL - [14:11] */
  5716. /*
  5717. * R3832 (0xEF8) - ISRC 3 CTRL 3
  5718. */
  5719. #define ARIZONA_ISRC3_INT0_ENA 0x8000 /* ISRC3_INT0_ENA */
  5720. #define ARIZONA_ISRC3_INT0_ENA_MASK 0x8000 /* ISRC3_INT0_ENA */
  5721. #define ARIZONA_ISRC3_INT0_ENA_SHIFT 15 /* ISRC3_INT0_ENA */
  5722. #define ARIZONA_ISRC3_INT0_ENA_WIDTH 1 /* ISRC3_INT0_ENA */
  5723. #define ARIZONA_ISRC3_INT1_ENA 0x4000 /* ISRC3_INT1_ENA */
  5724. #define ARIZONA_ISRC3_INT1_ENA_MASK 0x4000 /* ISRC3_INT1_ENA */
  5725. #define ARIZONA_ISRC3_INT1_ENA_SHIFT 14 /* ISRC3_INT1_ENA */
  5726. #define ARIZONA_ISRC3_INT1_ENA_WIDTH 1 /* ISRC3_INT1_ENA */
  5727. #define ARIZONA_ISRC3_INT2_ENA 0x2000 /* ISRC3_INT2_ENA */
  5728. #define ARIZONA_ISRC3_INT2_ENA_MASK 0x2000 /* ISRC3_INT2_ENA */
  5729. #define ARIZONA_ISRC3_INT2_ENA_SHIFT 13 /* ISRC3_INT2_ENA */
  5730. #define ARIZONA_ISRC3_INT2_ENA_WIDTH 1 /* ISRC3_INT2_ENA */
  5731. #define ARIZONA_ISRC3_INT3_ENA 0x1000 /* ISRC3_INT3_ENA */
  5732. #define ARIZONA_ISRC3_INT3_ENA_MASK 0x1000 /* ISRC3_INT3_ENA */
  5733. #define ARIZONA_ISRC3_INT3_ENA_SHIFT 12 /* ISRC3_INT3_ENA */
  5734. #define ARIZONA_ISRC3_INT3_ENA_WIDTH 1 /* ISRC3_INT3_ENA */
  5735. #define ARIZONA_ISRC3_DEC0_ENA 0x0200 /* ISRC3_DEC0_ENA */
  5736. #define ARIZONA_ISRC3_DEC0_ENA_MASK 0x0200 /* ISRC3_DEC0_ENA */
  5737. #define ARIZONA_ISRC3_DEC0_ENA_SHIFT 9 /* ISRC3_DEC0_ENA */
  5738. #define ARIZONA_ISRC3_DEC0_ENA_WIDTH 1 /* ISRC3_DEC0_ENA */
  5739. #define ARIZONA_ISRC3_DEC1_ENA 0x0100 /* ISRC3_DEC1_ENA */
  5740. #define ARIZONA_ISRC3_DEC1_ENA_MASK 0x0100 /* ISRC3_DEC1_ENA */
  5741. #define ARIZONA_ISRC3_DEC1_ENA_SHIFT 8 /* ISRC3_DEC1_ENA */
  5742. #define ARIZONA_ISRC3_DEC1_ENA_WIDTH 1 /* ISRC3_DEC1_ENA */
  5743. #define ARIZONA_ISRC3_DEC2_ENA 0x0080 /* ISRC3_DEC2_ENA */
  5744. #define ARIZONA_ISRC3_DEC2_ENA_MASK 0x0080 /* ISRC3_DEC2_ENA */
  5745. #define ARIZONA_ISRC3_DEC2_ENA_SHIFT 7 /* ISRC3_DEC2_ENA */
  5746. #define ARIZONA_ISRC3_DEC2_ENA_WIDTH 1 /* ISRC3_DEC2_ENA */
  5747. #define ARIZONA_ISRC3_DEC3_ENA 0x0040 /* ISRC3_DEC3_ENA */
  5748. #define ARIZONA_ISRC3_DEC3_ENA_MASK 0x0040 /* ISRC3_DEC3_ENA */
  5749. #define ARIZONA_ISRC3_DEC3_ENA_SHIFT 6 /* ISRC3_DEC3_ENA */
  5750. #define ARIZONA_ISRC3_DEC3_ENA_WIDTH 1 /* ISRC3_DEC3_ENA */
  5751. #define ARIZONA_ISRC3_NOTCH_ENA 0x0001 /* ISRC3_NOTCH_ENA */
  5752. #define ARIZONA_ISRC3_NOTCH_ENA_MASK 0x0001 /* ISRC3_NOTCH_ENA */
  5753. #define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */
  5754. #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */
  5755. /*
  5756. * R4352 (0x1100) - DSP1 Control 1
  5757. */
  5758. #define ARIZONA_DSP1_RATE_MASK 0x7800 /* DSP1_RATE - [14:11] */
  5759. #define ARIZONA_DSP1_RATE_SHIFT 11 /* DSP1_RATE - [14:11] */
  5760. #define ARIZONA_DSP1_RATE_WIDTH 4 /* DSP1_RATE - [14:11] */
  5761. #define ARIZONA_DSP1_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
  5762. #define ARIZONA_DSP1_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
  5763. #define ARIZONA_DSP1_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
  5764. #define ARIZONA_DSP1_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
  5765. #define ARIZONA_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
  5766. #define ARIZONA_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
  5767. #define ARIZONA_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
  5768. #define ARIZONA_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
  5769. #define ARIZONA_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
  5770. #define ARIZONA_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
  5771. #define ARIZONA_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
  5772. #define ARIZONA_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
  5773. #define ARIZONA_DSP1_START 0x0001 /* DSP1_START */
  5774. #define ARIZONA_DSP1_START_MASK 0x0001 /* DSP1_START */
  5775. #define ARIZONA_DSP1_START_SHIFT 0 /* DSP1_START */
  5776. #define ARIZONA_DSP1_START_WIDTH 1 /* DSP1_START */
  5777. /*
  5778. * R4353 (0x1101) - DSP1 Clocking 1
  5779. */
  5780. #define ARIZONA_DSP1_CLK_SEL_MASK 0x0007 /* DSP1_CLK_SEL - [2:0] */
  5781. #define ARIZONA_DSP1_CLK_SEL_SHIFT 0 /* DSP1_CLK_SEL - [2:0] */
  5782. #define ARIZONA_DSP1_CLK_SEL_WIDTH 3 /* DSP1_CLK_SEL - [2:0] */
  5783. /*
  5784. * R4356 (0x1104) - DSP1 Status 1
  5785. */
  5786. #define ARIZONA_DSP1_RAM_RDY 0x0001 /* DSP1_RAM_RDY */
  5787. #define ARIZONA_DSP1_RAM_RDY_MASK 0x0001 /* DSP1_RAM_RDY */
  5788. #define ARIZONA_DSP1_RAM_RDY_SHIFT 0 /* DSP1_RAM_RDY */
  5789. #define ARIZONA_DSP1_RAM_RDY_WIDTH 1 /* DSP1_RAM_RDY */
  5790. /*
  5791. * R4357 (0x1105) - DSP1 Status 2
  5792. */
  5793. #define ARIZONA_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
  5794. #define ARIZONA_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
  5795. #define ARIZONA_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */
  5796. #define ARIZONA_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */
  5797. #define ARIZONA_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
  5798. #define ARIZONA_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
  5799. #define ARIZONA_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */
  5800. #define ARIZONA_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */
  5801. #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  5802. #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  5803. #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  5804. #endif