bna_ctrl.c 81 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfa_sm.h"
  20. #include "bfa_wc.h"
  21. static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
  22. static void
  23. bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
  24. int status)
  25. {
  26. int i;
  27. u8 prio_map;
  28. port->llport.link_status = BNA_LINK_UP;
  29. if (aen->cee_linkup)
  30. port->llport.link_status = BNA_CEE_UP;
  31. /* Compute the priority */
  32. prio_map = aen->prio_map;
  33. if (prio_map) {
  34. for (i = 0; i < 8; i++) {
  35. if ((prio_map >> i) & 0x1)
  36. break;
  37. }
  38. port->priority = i;
  39. } else
  40. port->priority = 0;
  41. /* Dispatch events */
  42. bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
  43. bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
  44. port->link_cbfn(port->bna->bnad, port->llport.link_status);
  45. }
  46. static void
  47. bna_port_cb_link_down(struct bna_port *port, int status)
  48. {
  49. port->llport.link_status = BNA_LINK_DOWN;
  50. /* Dispatch events */
  51. bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
  52. port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
  53. }
  54. static inline int
  55. llport_can_be_up(struct bna_llport *llport)
  56. {
  57. int ready = 0;
  58. if (llport->type == BNA_PORT_T_REGULAR)
  59. ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
  60. (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
  61. (llport->flags & BNA_LLPORT_F_PORT_ENABLED));
  62. else
  63. ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
  64. (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
  65. !(llport->flags & BNA_LLPORT_F_PORT_ENABLED));
  66. return ready;
  67. }
  68. #define llport_is_up llport_can_be_up
  69. enum bna_llport_event {
  70. LLPORT_E_START = 1,
  71. LLPORT_E_STOP = 2,
  72. LLPORT_E_FAIL = 3,
  73. LLPORT_E_UP = 4,
  74. LLPORT_E_DOWN = 5,
  75. LLPORT_E_FWRESP_UP_OK = 6,
  76. LLPORT_E_FWRESP_UP_FAIL = 7,
  77. LLPORT_E_FWRESP_DOWN = 8
  78. };
  79. static void
  80. bna_llport_cb_port_enabled(struct bna_llport *llport)
  81. {
  82. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  83. if (llport_can_be_up(llport))
  84. bfa_fsm_send_event(llport, LLPORT_E_UP);
  85. }
  86. static void
  87. bna_llport_cb_port_disabled(struct bna_llport *llport)
  88. {
  89. int llport_up = llport_is_up(llport);
  90. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  91. if (llport_up)
  92. bfa_fsm_send_event(llport, LLPORT_E_DOWN);
  93. }
  94. /**
  95. * MBOX
  96. */
  97. static int
  98. bna_is_aen(u8 msg_id)
  99. {
  100. switch (msg_id) {
  101. case BFI_LL_I2H_LINK_DOWN_AEN:
  102. case BFI_LL_I2H_LINK_UP_AEN:
  103. case BFI_LL_I2H_PORT_ENABLE_AEN:
  104. case BFI_LL_I2H_PORT_DISABLE_AEN:
  105. return 1;
  106. default:
  107. return 0;
  108. }
  109. }
  110. static void
  111. bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
  112. {
  113. struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
  114. switch (aen->mh.msg_id) {
  115. case BFI_LL_I2H_LINK_UP_AEN:
  116. bna_port_cb_link_up(&bna->port, aen, aen->reason);
  117. break;
  118. case BFI_LL_I2H_LINK_DOWN_AEN:
  119. bna_port_cb_link_down(&bna->port, aen->reason);
  120. break;
  121. case BFI_LL_I2H_PORT_ENABLE_AEN:
  122. bna_llport_cb_port_enabled(&bna->port.llport);
  123. break;
  124. case BFI_LL_I2H_PORT_DISABLE_AEN:
  125. bna_llport_cb_port_disabled(&bna->port.llport);
  126. break;
  127. default:
  128. break;
  129. }
  130. }
  131. static void
  132. bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
  133. {
  134. struct bna *bna = (struct bna *)(llarg);
  135. struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
  136. struct bfi_mhdr *cmd_h, *rsp_h;
  137. struct bna_mbox_qe *mb_qe = NULL;
  138. int to_post = 0;
  139. u8 aen = 0;
  140. char message[BNA_MESSAGE_SIZE];
  141. aen = bna_is_aen(mb_rsp->mh.msg_id);
  142. if (!aen) {
  143. mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
  144. cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
  145. rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
  146. if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
  147. (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
  148. /* Remove the request from posted_q, update state */
  149. list_del(&mb_qe->qe);
  150. bna->mbox_mod.msg_pending--;
  151. if (list_empty(&bna->mbox_mod.posted_q))
  152. bna->mbox_mod.state = BNA_MBOX_FREE;
  153. else
  154. to_post = 1;
  155. /* Dispatch the cbfn */
  156. if (mb_qe->cbfn)
  157. mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
  158. /* Post the next entry, if needed */
  159. if (to_post) {
  160. mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
  161. bfa_nw_ioc_mbox_queue(&bna->device.ioc,
  162. &mb_qe->cmd);
  163. }
  164. } else {
  165. snprintf(message, BNA_MESSAGE_SIZE,
  166. "No matching rsp for [%d:%d:%d]\n",
  167. mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
  168. mb_rsp->mh.mtag.i2htok);
  169. pr_info("%s", message);
  170. }
  171. } else
  172. bna_mbox_aen_callback(bna, msg);
  173. }
  174. static void
  175. bna_err_handler(struct bna *bna, u32 intr_status)
  176. {
  177. u32 init_halt;
  178. if (intr_status & __HALT_STATUS_BITS) {
  179. init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
  180. init_halt &= ~__FW_INIT_HALT_P;
  181. writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
  182. }
  183. bfa_nw_ioc_error_isr(&bna->device.ioc);
  184. }
  185. void
  186. bna_mbox_handler(struct bna *bna, u32 intr_status)
  187. {
  188. if (BNA_IS_ERR_INTR(intr_status)) {
  189. bna_err_handler(bna, intr_status);
  190. return;
  191. }
  192. if (BNA_IS_MBOX_INTR(intr_status))
  193. bfa_nw_ioc_mbox_isr(&bna->device.ioc);
  194. }
  195. void
  196. bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
  197. {
  198. struct bfi_mhdr *mh;
  199. mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
  200. mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
  201. bna->mbox_mod.msg_ctr++;
  202. bna->mbox_mod.msg_pending++;
  203. if (bna->mbox_mod.state == BNA_MBOX_FREE) {
  204. list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
  205. bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
  206. bna->mbox_mod.state = BNA_MBOX_POSTED;
  207. } else {
  208. list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
  209. }
  210. }
  211. static void
  212. bna_mbox_flush_q(struct bna *bna, struct list_head *q)
  213. {
  214. struct bna_mbox_qe *mb_qe = NULL;
  215. struct bfi_mhdr *cmd_h;
  216. struct list_head *mb_q;
  217. void (*cbfn)(void *arg, int status);
  218. void *cbarg;
  219. mb_q = &bna->mbox_mod.posted_q;
  220. while (!list_empty(mb_q)) {
  221. bfa_q_deq(mb_q, &mb_qe);
  222. cbfn = mb_qe->cbfn;
  223. cbarg = mb_qe->cbarg;
  224. bfa_q_qe_init(mb_qe);
  225. bna->mbox_mod.msg_pending--;
  226. cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
  227. if (cbfn)
  228. cbfn(cbarg, BNA_CB_NOT_EXEC);
  229. }
  230. bna->mbox_mod.state = BNA_MBOX_FREE;
  231. }
  232. static void
  233. bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
  234. {
  235. }
  236. static void
  237. bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
  238. {
  239. bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
  240. }
  241. static void
  242. bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
  243. {
  244. bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
  245. mbox_mod->state = BNA_MBOX_FREE;
  246. mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
  247. INIT_LIST_HEAD(&mbox_mod->posted_q);
  248. mbox_mod->bna = bna;
  249. }
  250. static void
  251. bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
  252. {
  253. mbox_mod->bna = NULL;
  254. }
  255. /**
  256. * LLPORT
  257. */
  258. #define call_llport_stop_cbfn(llport, status)\
  259. do {\
  260. if ((llport)->stop_cbfn)\
  261. (llport)->stop_cbfn(&(llport)->bna->port, status);\
  262. (llport)->stop_cbfn = NULL;\
  263. } while (0)
  264. static void bna_fw_llport_up(struct bna_llport *llport);
  265. static void bna_fw_cb_llport_up(void *arg, int status);
  266. static void bna_fw_llport_down(struct bna_llport *llport);
  267. static void bna_fw_cb_llport_down(void *arg, int status);
  268. static void bna_llport_start(struct bna_llport *llport);
  269. static void bna_llport_stop(struct bna_llport *llport);
  270. static void bna_llport_fail(struct bna_llport *llport);
  271. enum bna_llport_state {
  272. BNA_LLPORT_STOPPED = 1,
  273. BNA_LLPORT_DOWN = 2,
  274. BNA_LLPORT_UP_RESP_WAIT = 3,
  275. BNA_LLPORT_DOWN_RESP_WAIT = 4,
  276. BNA_LLPORT_UP = 5,
  277. BNA_LLPORT_LAST_RESP_WAIT = 6
  278. };
  279. bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
  280. enum bna_llport_event);
  281. bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
  282. enum bna_llport_event);
  283. bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
  284. enum bna_llport_event);
  285. bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
  286. enum bna_llport_event);
  287. bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
  288. enum bna_llport_event);
  289. bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
  290. enum bna_llport_event);
  291. static struct bfa_sm_table llport_sm_table[] = {
  292. {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
  293. {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
  294. {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
  295. {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
  296. {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
  297. {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
  298. };
  299. static void
  300. bna_llport_sm_stopped_entry(struct bna_llport *llport)
  301. {
  302. llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
  303. call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
  304. }
  305. static void
  306. bna_llport_sm_stopped(struct bna_llport *llport,
  307. enum bna_llport_event event)
  308. {
  309. switch (event) {
  310. case LLPORT_E_START:
  311. bfa_fsm_set_state(llport, bna_llport_sm_down);
  312. break;
  313. case LLPORT_E_STOP:
  314. call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
  315. break;
  316. case LLPORT_E_FAIL:
  317. break;
  318. case LLPORT_E_DOWN:
  319. /* This event is received due to Rx objects failing */
  320. /* No-op */
  321. break;
  322. case LLPORT_E_FWRESP_UP_OK:
  323. case LLPORT_E_FWRESP_DOWN:
  324. /**
  325. * These events are received due to flushing of mbox when
  326. * device fails
  327. */
  328. /* No-op */
  329. break;
  330. default:
  331. bfa_sm_fault(llport->bna, event);
  332. }
  333. }
  334. static void
  335. bna_llport_sm_down_entry(struct bna_llport *llport)
  336. {
  337. bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
  338. }
  339. static void
  340. bna_llport_sm_down(struct bna_llport *llport,
  341. enum bna_llport_event event)
  342. {
  343. switch (event) {
  344. case LLPORT_E_STOP:
  345. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  346. break;
  347. case LLPORT_E_FAIL:
  348. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  349. break;
  350. case LLPORT_E_UP:
  351. bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
  352. bna_fw_llport_up(llport);
  353. break;
  354. default:
  355. bfa_sm_fault(llport->bna, event);
  356. }
  357. }
  358. static void
  359. bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
  360. {
  361. BUG_ON(!llport_can_be_up(llport));
  362. /**
  363. * NOTE: Do not call bna_fw_llport_up() here. That will over step
  364. * mbox due to down_resp_wait -> up_resp_wait transition on event
  365. * LLPORT_E_UP
  366. */
  367. }
  368. static void
  369. bna_llport_sm_up_resp_wait(struct bna_llport *llport,
  370. enum bna_llport_event event)
  371. {
  372. switch (event) {
  373. case LLPORT_E_STOP:
  374. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  375. break;
  376. case LLPORT_E_FAIL:
  377. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  378. break;
  379. case LLPORT_E_DOWN:
  380. bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
  381. break;
  382. case LLPORT_E_FWRESP_UP_OK:
  383. bfa_fsm_set_state(llport, bna_llport_sm_up);
  384. break;
  385. case LLPORT_E_FWRESP_UP_FAIL:
  386. bfa_fsm_set_state(llport, bna_llport_sm_down);
  387. break;
  388. case LLPORT_E_FWRESP_DOWN:
  389. /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
  390. bna_fw_llport_up(llport);
  391. break;
  392. default:
  393. bfa_sm_fault(llport->bna, event);
  394. }
  395. }
  396. static void
  397. bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
  398. {
  399. /**
  400. * NOTE: Do not call bna_fw_llport_down() here. That will over step
  401. * mbox due to up_resp_wait -> down_resp_wait transition on event
  402. * LLPORT_E_DOWN
  403. */
  404. }
  405. static void
  406. bna_llport_sm_down_resp_wait(struct bna_llport *llport,
  407. enum bna_llport_event event)
  408. {
  409. switch (event) {
  410. case LLPORT_E_STOP:
  411. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  412. break;
  413. case LLPORT_E_FAIL:
  414. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  415. break;
  416. case LLPORT_E_UP:
  417. bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
  418. break;
  419. case LLPORT_E_FWRESP_UP_OK:
  420. /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
  421. bna_fw_llport_down(llport);
  422. break;
  423. case LLPORT_E_FWRESP_UP_FAIL:
  424. case LLPORT_E_FWRESP_DOWN:
  425. bfa_fsm_set_state(llport, bna_llport_sm_down);
  426. break;
  427. default:
  428. bfa_sm_fault(llport->bna, event);
  429. }
  430. }
  431. static void
  432. bna_llport_sm_up_entry(struct bna_llport *llport)
  433. {
  434. }
  435. static void
  436. bna_llport_sm_up(struct bna_llport *llport,
  437. enum bna_llport_event event)
  438. {
  439. switch (event) {
  440. case LLPORT_E_STOP:
  441. bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
  442. bna_fw_llport_down(llport);
  443. break;
  444. case LLPORT_E_FAIL:
  445. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  446. break;
  447. case LLPORT_E_DOWN:
  448. bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
  449. bna_fw_llport_down(llport);
  450. break;
  451. default:
  452. bfa_sm_fault(llport->bna, event);
  453. }
  454. }
  455. static void
  456. bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
  457. {
  458. }
  459. static void
  460. bna_llport_sm_last_resp_wait(struct bna_llport *llport,
  461. enum bna_llport_event event)
  462. {
  463. switch (event) {
  464. case LLPORT_E_FAIL:
  465. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  466. break;
  467. case LLPORT_E_DOWN:
  468. /**
  469. * This event is received due to Rx objects stopping in
  470. * parallel to llport
  471. */
  472. /* No-op */
  473. break;
  474. case LLPORT_E_FWRESP_UP_OK:
  475. /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
  476. bna_fw_llport_down(llport);
  477. break;
  478. case LLPORT_E_FWRESP_UP_FAIL:
  479. case LLPORT_E_FWRESP_DOWN:
  480. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  481. break;
  482. default:
  483. bfa_sm_fault(llport->bna, event);
  484. }
  485. }
  486. static void
  487. bna_fw_llport_admin_up(struct bna_llport *llport)
  488. {
  489. struct bfi_ll_port_admin_req ll_req;
  490. memset(&ll_req, 0, sizeof(ll_req));
  491. ll_req.mh.msg_class = BFI_MC_LL;
  492. ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
  493. ll_req.mh.mtag.h2i.lpu_id = 0;
  494. ll_req.up = BNA_STATUS_T_ENABLED;
  495. bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
  496. bna_fw_cb_llport_up, llport);
  497. bna_mbox_send(llport->bna, &llport->mbox_qe);
  498. }
  499. static void
  500. bna_fw_llport_up(struct bna_llport *llport)
  501. {
  502. if (llport->type == BNA_PORT_T_REGULAR)
  503. bna_fw_llport_admin_up(llport);
  504. }
  505. static void
  506. bna_fw_cb_llport_up(void *arg, int status)
  507. {
  508. struct bna_llport *llport = (struct bna_llport *)arg;
  509. bfa_q_qe_init(&llport->mbox_qe.qe);
  510. if (status == BFI_LL_CMD_FAIL) {
  511. if (llport->type == BNA_PORT_T_REGULAR)
  512. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  513. else
  514. llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
  515. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL);
  516. } else
  517. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK);
  518. }
  519. static void
  520. bna_fw_llport_admin_down(struct bna_llport *llport)
  521. {
  522. struct bfi_ll_port_admin_req ll_req;
  523. memset(&ll_req, 0, sizeof(ll_req));
  524. ll_req.mh.msg_class = BFI_MC_LL;
  525. ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
  526. ll_req.mh.mtag.h2i.lpu_id = 0;
  527. ll_req.up = BNA_STATUS_T_DISABLED;
  528. bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
  529. bna_fw_cb_llport_down, llport);
  530. bna_mbox_send(llport->bna, &llport->mbox_qe);
  531. }
  532. static void
  533. bna_fw_llport_down(struct bna_llport *llport)
  534. {
  535. if (llport->type == BNA_PORT_T_REGULAR)
  536. bna_fw_llport_admin_down(llport);
  537. }
  538. static void
  539. bna_fw_cb_llport_down(void *arg, int status)
  540. {
  541. struct bna_llport *llport = (struct bna_llport *)arg;
  542. bfa_q_qe_init(&llport->mbox_qe.qe);
  543. bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
  544. }
  545. static void
  546. bna_port_cb_llport_stopped(struct bna_port *port,
  547. enum bna_cb_status status)
  548. {
  549. bfa_wc_down(&port->chld_stop_wc);
  550. }
  551. static void
  552. bna_llport_init(struct bna_llport *llport, struct bna *bna)
  553. {
  554. llport->flags |= BNA_LLPORT_F_ADMIN_UP;
  555. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  556. llport->type = BNA_PORT_T_REGULAR;
  557. llport->bna = bna;
  558. llport->link_status = BNA_LINK_DOWN;
  559. llport->rx_started_count = 0;
  560. llport->stop_cbfn = NULL;
  561. bfa_q_qe_init(&llport->mbox_qe.qe);
  562. bfa_fsm_set_state(llport, bna_llport_sm_stopped);
  563. }
  564. static void
  565. bna_llport_uninit(struct bna_llport *llport)
  566. {
  567. llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
  568. llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
  569. llport->bna = NULL;
  570. }
  571. static void
  572. bna_llport_start(struct bna_llport *llport)
  573. {
  574. bfa_fsm_send_event(llport, LLPORT_E_START);
  575. }
  576. static void
  577. bna_llport_stop(struct bna_llport *llport)
  578. {
  579. llport->stop_cbfn = bna_port_cb_llport_stopped;
  580. bfa_fsm_send_event(llport, LLPORT_E_STOP);
  581. }
  582. static void
  583. bna_llport_fail(struct bna_llport *llport)
  584. {
  585. /* Reset the physical port status to enabled */
  586. llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
  587. bfa_fsm_send_event(llport, LLPORT_E_FAIL);
  588. }
  589. static int
  590. bna_llport_state_get(struct bna_llport *llport)
  591. {
  592. return bfa_sm_to_state(llport_sm_table, llport->fsm);
  593. }
  594. void
  595. bna_llport_rx_started(struct bna_llport *llport)
  596. {
  597. llport->rx_started_count++;
  598. if (llport->rx_started_count == 1) {
  599. llport->flags |= BNA_LLPORT_F_RX_STARTED;
  600. if (llport_can_be_up(llport))
  601. bfa_fsm_send_event(llport, LLPORT_E_UP);
  602. }
  603. }
  604. void
  605. bna_llport_rx_stopped(struct bna_llport *llport)
  606. {
  607. int llport_up = llport_is_up(llport);
  608. llport->rx_started_count--;
  609. if (llport->rx_started_count == 0) {
  610. llport->flags &= ~BNA_LLPORT_F_RX_STARTED;
  611. if (llport_up)
  612. bfa_fsm_send_event(llport, LLPORT_E_DOWN);
  613. }
  614. }
  615. /**
  616. * PORT
  617. */
  618. #define bna_port_chld_start(port)\
  619. do {\
  620. enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  621. BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
  622. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  623. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  624. bna_llport_start(&(port)->llport);\
  625. bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
  626. bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
  627. } while (0)
  628. #define bna_port_chld_stop(port)\
  629. do {\
  630. enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  631. BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
  632. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  633. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  634. bfa_wc_up(&(port)->chld_stop_wc);\
  635. bfa_wc_up(&(port)->chld_stop_wc);\
  636. bfa_wc_up(&(port)->chld_stop_wc);\
  637. bna_llport_stop(&(port)->llport);\
  638. bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
  639. bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
  640. } while (0)
  641. #define bna_port_chld_fail(port)\
  642. do {\
  643. bna_llport_fail(&(port)->llport);\
  644. bna_tx_mod_fail(&(port)->bna->tx_mod);\
  645. bna_rx_mod_fail(&(port)->bna->rx_mod);\
  646. } while (0)
  647. #define bna_port_rx_start(port)\
  648. do {\
  649. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  650. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  651. bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
  652. } while (0)
  653. #define bna_port_rx_stop(port)\
  654. do {\
  655. enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
  656. BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
  657. bfa_wc_up(&(port)->chld_stop_wc);\
  658. bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
  659. } while (0)
  660. #define call_port_stop_cbfn(port, status)\
  661. do {\
  662. if ((port)->stop_cbfn)\
  663. (port)->stop_cbfn((port)->stop_cbarg, status);\
  664. (port)->stop_cbfn = NULL;\
  665. (port)->stop_cbarg = NULL;\
  666. } while (0)
  667. #define call_port_pause_cbfn(port, status)\
  668. do {\
  669. if ((port)->pause_cbfn)\
  670. (port)->pause_cbfn((port)->bna->bnad, status);\
  671. (port)->pause_cbfn = NULL;\
  672. } while (0)
  673. #define call_port_mtu_cbfn(port, status)\
  674. do {\
  675. if ((port)->mtu_cbfn)\
  676. (port)->mtu_cbfn((port)->bna->bnad, status);\
  677. (port)->mtu_cbfn = NULL;\
  678. } while (0)
  679. static void bna_fw_pause_set(struct bna_port *port);
  680. static void bna_fw_cb_pause_set(void *arg, int status);
  681. static void bna_fw_mtu_set(struct bna_port *port);
  682. static void bna_fw_cb_mtu_set(void *arg, int status);
  683. enum bna_port_event {
  684. PORT_E_START = 1,
  685. PORT_E_STOP = 2,
  686. PORT_E_FAIL = 3,
  687. PORT_E_PAUSE_CFG = 4,
  688. PORT_E_MTU_CFG = 5,
  689. PORT_E_CHLD_STOPPED = 6,
  690. PORT_E_FWRESP_PAUSE = 7,
  691. PORT_E_FWRESP_MTU = 8
  692. };
  693. enum bna_port_state {
  694. BNA_PORT_STOPPED = 1,
  695. BNA_PORT_MTU_INIT_WAIT = 2,
  696. BNA_PORT_PAUSE_INIT_WAIT = 3,
  697. BNA_PORT_LAST_RESP_WAIT = 4,
  698. BNA_PORT_STARTED = 5,
  699. BNA_PORT_PAUSE_CFG_WAIT = 6,
  700. BNA_PORT_RX_STOP_WAIT = 7,
  701. BNA_PORT_MTU_CFG_WAIT = 8,
  702. BNA_PORT_CHLD_STOP_WAIT = 9
  703. };
  704. bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
  705. enum bna_port_event);
  706. bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
  707. enum bna_port_event);
  708. bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
  709. enum bna_port_event);
  710. bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
  711. enum bna_port_event);
  712. bfa_fsm_state_decl(bna_port, started, struct bna_port,
  713. enum bna_port_event);
  714. bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
  715. enum bna_port_event);
  716. bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
  717. enum bna_port_event);
  718. bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
  719. enum bna_port_event);
  720. bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
  721. enum bna_port_event);
  722. static struct bfa_sm_table port_sm_table[] = {
  723. {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
  724. {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
  725. {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
  726. {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
  727. {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
  728. {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
  729. {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
  730. {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
  731. {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
  732. };
  733. static void
  734. bna_port_sm_stopped_entry(struct bna_port *port)
  735. {
  736. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  737. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  738. call_port_stop_cbfn(port, BNA_CB_SUCCESS);
  739. }
  740. static void
  741. bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
  742. {
  743. switch (event) {
  744. case PORT_E_START:
  745. bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
  746. break;
  747. case PORT_E_STOP:
  748. call_port_stop_cbfn(port, BNA_CB_SUCCESS);
  749. break;
  750. case PORT_E_FAIL:
  751. /* No-op */
  752. break;
  753. case PORT_E_PAUSE_CFG:
  754. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  755. break;
  756. case PORT_E_MTU_CFG:
  757. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  758. break;
  759. case PORT_E_CHLD_STOPPED:
  760. /**
  761. * This event is received due to LLPort, Tx and Rx objects
  762. * failing
  763. */
  764. /* No-op */
  765. break;
  766. case PORT_E_FWRESP_PAUSE:
  767. case PORT_E_FWRESP_MTU:
  768. /**
  769. * These events are received due to flushing of mbox when
  770. * device fails
  771. */
  772. /* No-op */
  773. break;
  774. default:
  775. bfa_sm_fault(port->bna, event);
  776. }
  777. }
  778. static void
  779. bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
  780. {
  781. bna_fw_mtu_set(port);
  782. }
  783. static void
  784. bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
  785. {
  786. switch (event) {
  787. case PORT_E_STOP:
  788. bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
  789. break;
  790. case PORT_E_FAIL:
  791. bfa_fsm_set_state(port, bna_port_sm_stopped);
  792. break;
  793. case PORT_E_PAUSE_CFG:
  794. /* No-op */
  795. break;
  796. case PORT_E_MTU_CFG:
  797. port->flags |= BNA_PORT_F_MTU_CHANGED;
  798. break;
  799. case PORT_E_FWRESP_MTU:
  800. if (port->flags & BNA_PORT_F_MTU_CHANGED) {
  801. port->flags &= ~BNA_PORT_F_MTU_CHANGED;
  802. bna_fw_mtu_set(port);
  803. } else {
  804. bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
  805. }
  806. break;
  807. default:
  808. bfa_sm_fault(port->bna, event);
  809. }
  810. }
  811. static void
  812. bna_port_sm_pause_init_wait_entry(struct bna_port *port)
  813. {
  814. bna_fw_pause_set(port);
  815. }
  816. static void
  817. bna_port_sm_pause_init_wait(struct bna_port *port,
  818. enum bna_port_event event)
  819. {
  820. switch (event) {
  821. case PORT_E_STOP:
  822. bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
  823. break;
  824. case PORT_E_FAIL:
  825. bfa_fsm_set_state(port, bna_port_sm_stopped);
  826. break;
  827. case PORT_E_PAUSE_CFG:
  828. port->flags |= BNA_PORT_F_PAUSE_CHANGED;
  829. break;
  830. case PORT_E_MTU_CFG:
  831. port->flags |= BNA_PORT_F_MTU_CHANGED;
  832. break;
  833. case PORT_E_FWRESP_PAUSE:
  834. if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
  835. port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
  836. bna_fw_pause_set(port);
  837. } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
  838. port->flags &= ~BNA_PORT_F_MTU_CHANGED;
  839. bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
  840. } else {
  841. bfa_fsm_set_state(port, bna_port_sm_started);
  842. bna_port_chld_start(port);
  843. }
  844. break;
  845. default:
  846. bfa_sm_fault(port->bna, event);
  847. }
  848. }
  849. static void
  850. bna_port_sm_last_resp_wait_entry(struct bna_port *port)
  851. {
  852. }
  853. static void
  854. bna_port_sm_last_resp_wait(struct bna_port *port,
  855. enum bna_port_event event)
  856. {
  857. switch (event) {
  858. case PORT_E_FAIL:
  859. case PORT_E_FWRESP_PAUSE:
  860. case PORT_E_FWRESP_MTU:
  861. bfa_fsm_set_state(port, bna_port_sm_stopped);
  862. break;
  863. default:
  864. bfa_sm_fault(port->bna, event);
  865. }
  866. }
  867. static void
  868. bna_port_sm_started_entry(struct bna_port *port)
  869. {
  870. /**
  871. * NOTE: Do not call bna_port_chld_start() here, since it will be
  872. * inadvertently called during pause_cfg_wait->started transition
  873. * as well
  874. */
  875. call_port_pause_cbfn(port, BNA_CB_SUCCESS);
  876. call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
  877. }
  878. static void
  879. bna_port_sm_started(struct bna_port *port,
  880. enum bna_port_event event)
  881. {
  882. switch (event) {
  883. case PORT_E_STOP:
  884. bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
  885. break;
  886. case PORT_E_FAIL:
  887. bfa_fsm_set_state(port, bna_port_sm_stopped);
  888. bna_port_chld_fail(port);
  889. break;
  890. case PORT_E_PAUSE_CFG:
  891. bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
  892. break;
  893. case PORT_E_MTU_CFG:
  894. bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
  895. break;
  896. default:
  897. bfa_sm_fault(port->bna, event);
  898. }
  899. }
  900. static void
  901. bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
  902. {
  903. bna_fw_pause_set(port);
  904. }
  905. static void
  906. bna_port_sm_pause_cfg_wait(struct bna_port *port,
  907. enum bna_port_event event)
  908. {
  909. switch (event) {
  910. case PORT_E_FAIL:
  911. bfa_fsm_set_state(port, bna_port_sm_stopped);
  912. bna_port_chld_fail(port);
  913. break;
  914. case PORT_E_FWRESP_PAUSE:
  915. bfa_fsm_set_state(port, bna_port_sm_started);
  916. break;
  917. default:
  918. bfa_sm_fault(port->bna, event);
  919. }
  920. }
  921. static void
  922. bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
  923. {
  924. bna_port_rx_stop(port);
  925. }
  926. static void
  927. bna_port_sm_rx_stop_wait(struct bna_port *port,
  928. enum bna_port_event event)
  929. {
  930. switch (event) {
  931. case PORT_E_FAIL:
  932. bfa_fsm_set_state(port, bna_port_sm_stopped);
  933. bna_port_chld_fail(port);
  934. break;
  935. case PORT_E_CHLD_STOPPED:
  936. bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
  937. break;
  938. default:
  939. bfa_sm_fault(port->bna, event);
  940. }
  941. }
  942. static void
  943. bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
  944. {
  945. bna_fw_mtu_set(port);
  946. }
  947. static void
  948. bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
  949. {
  950. switch (event) {
  951. case PORT_E_FAIL:
  952. bfa_fsm_set_state(port, bna_port_sm_stopped);
  953. bna_port_chld_fail(port);
  954. break;
  955. case PORT_E_FWRESP_MTU:
  956. bfa_fsm_set_state(port, bna_port_sm_started);
  957. bna_port_rx_start(port);
  958. break;
  959. default:
  960. bfa_sm_fault(port->bna, event);
  961. }
  962. }
  963. static void
  964. bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
  965. {
  966. bna_port_chld_stop(port);
  967. }
  968. static void
  969. bna_port_sm_chld_stop_wait(struct bna_port *port,
  970. enum bna_port_event event)
  971. {
  972. switch (event) {
  973. case PORT_E_FAIL:
  974. bfa_fsm_set_state(port, bna_port_sm_stopped);
  975. bna_port_chld_fail(port);
  976. break;
  977. case PORT_E_CHLD_STOPPED:
  978. bfa_fsm_set_state(port, bna_port_sm_stopped);
  979. break;
  980. default:
  981. bfa_sm_fault(port->bna, event);
  982. }
  983. }
  984. static void
  985. bna_fw_pause_set(struct bna_port *port)
  986. {
  987. struct bfi_ll_set_pause_req ll_req;
  988. memset(&ll_req, 0, sizeof(ll_req));
  989. ll_req.mh.msg_class = BFI_MC_LL;
  990. ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
  991. ll_req.mh.mtag.h2i.lpu_id = 0;
  992. ll_req.tx_pause = port->pause_config.tx_pause;
  993. ll_req.rx_pause = port->pause_config.rx_pause;
  994. bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
  995. bna_fw_cb_pause_set, port);
  996. bna_mbox_send(port->bna, &port->mbox_qe);
  997. }
  998. static void
  999. bna_fw_cb_pause_set(void *arg, int status)
  1000. {
  1001. struct bna_port *port = (struct bna_port *)arg;
  1002. bfa_q_qe_init(&port->mbox_qe.qe);
  1003. bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
  1004. }
  1005. void
  1006. bna_fw_mtu_set(struct bna_port *port)
  1007. {
  1008. struct bfi_ll_mtu_info_req ll_req;
  1009. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
  1010. ll_req.mtu = htons((u16)port->mtu);
  1011. bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
  1012. bna_fw_cb_mtu_set, port);
  1013. bna_mbox_send(port->bna, &port->mbox_qe);
  1014. }
  1015. void
  1016. bna_fw_cb_mtu_set(void *arg, int status)
  1017. {
  1018. struct bna_port *port = (struct bna_port *)arg;
  1019. bfa_q_qe_init(&port->mbox_qe.qe);
  1020. bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
  1021. }
  1022. static void
  1023. bna_port_cb_chld_stopped(void *arg)
  1024. {
  1025. struct bna_port *port = (struct bna_port *)arg;
  1026. bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
  1027. }
  1028. static void
  1029. bna_port_init(struct bna_port *port, struct bna *bna)
  1030. {
  1031. port->bna = bna;
  1032. port->flags = 0;
  1033. port->mtu = 0;
  1034. port->type = BNA_PORT_T_REGULAR;
  1035. port->link_cbfn = bnad_cb_port_link_status;
  1036. port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
  1037. port->chld_stop_wc.wc_cbarg = port;
  1038. port->chld_stop_wc.wc_count = 0;
  1039. port->stop_cbfn = NULL;
  1040. port->stop_cbarg = NULL;
  1041. port->pause_cbfn = NULL;
  1042. port->mtu_cbfn = NULL;
  1043. bfa_q_qe_init(&port->mbox_qe.qe);
  1044. bfa_fsm_set_state(port, bna_port_sm_stopped);
  1045. bna_llport_init(&port->llport, bna);
  1046. }
  1047. static void
  1048. bna_port_uninit(struct bna_port *port)
  1049. {
  1050. bna_llport_uninit(&port->llport);
  1051. port->flags = 0;
  1052. port->bna = NULL;
  1053. }
  1054. static int
  1055. bna_port_state_get(struct bna_port *port)
  1056. {
  1057. return bfa_sm_to_state(port_sm_table, port->fsm);
  1058. }
  1059. static void
  1060. bna_port_start(struct bna_port *port)
  1061. {
  1062. port->flags |= BNA_PORT_F_DEVICE_READY;
  1063. if (port->flags & BNA_PORT_F_ENABLED)
  1064. bfa_fsm_send_event(port, PORT_E_START);
  1065. }
  1066. static void
  1067. bna_port_stop(struct bna_port *port)
  1068. {
  1069. port->stop_cbfn = bna_device_cb_port_stopped;
  1070. port->stop_cbarg = &port->bna->device;
  1071. port->flags &= ~BNA_PORT_F_DEVICE_READY;
  1072. bfa_fsm_send_event(port, PORT_E_STOP);
  1073. }
  1074. static void
  1075. bna_port_fail(struct bna_port *port)
  1076. {
  1077. port->flags &= ~BNA_PORT_F_DEVICE_READY;
  1078. bfa_fsm_send_event(port, PORT_E_FAIL);
  1079. }
  1080. void
  1081. bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
  1082. {
  1083. bfa_wc_down(&port->chld_stop_wc);
  1084. }
  1085. void
  1086. bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
  1087. {
  1088. bfa_wc_down(&port->chld_stop_wc);
  1089. }
  1090. int
  1091. bna_port_mtu_get(struct bna_port *port)
  1092. {
  1093. return port->mtu;
  1094. }
  1095. void
  1096. bna_port_enable(struct bna_port *port)
  1097. {
  1098. if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
  1099. return;
  1100. port->flags |= BNA_PORT_F_ENABLED;
  1101. if (port->flags & BNA_PORT_F_DEVICE_READY)
  1102. bfa_fsm_send_event(port, PORT_E_START);
  1103. }
  1104. void
  1105. bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
  1106. void (*cbfn)(void *, enum bna_cb_status))
  1107. {
  1108. if (type == BNA_SOFT_CLEANUP) {
  1109. (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
  1110. return;
  1111. }
  1112. port->stop_cbfn = cbfn;
  1113. port->stop_cbarg = port->bna->bnad;
  1114. port->flags &= ~BNA_PORT_F_ENABLED;
  1115. bfa_fsm_send_event(port, PORT_E_STOP);
  1116. }
  1117. void
  1118. bna_port_pause_config(struct bna_port *port,
  1119. struct bna_pause_config *pause_config,
  1120. void (*cbfn)(struct bnad *, enum bna_cb_status))
  1121. {
  1122. port->pause_config = *pause_config;
  1123. port->pause_cbfn = cbfn;
  1124. bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
  1125. }
  1126. void
  1127. bna_port_mtu_set(struct bna_port *port, int mtu,
  1128. void (*cbfn)(struct bnad *, enum bna_cb_status))
  1129. {
  1130. port->mtu = mtu;
  1131. port->mtu_cbfn = cbfn;
  1132. bfa_fsm_send_event(port, PORT_E_MTU_CFG);
  1133. }
  1134. void
  1135. bna_port_mac_get(struct bna_port *port, mac_t *mac)
  1136. {
  1137. *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
  1138. }
  1139. /**
  1140. * DEVICE
  1141. */
  1142. #define enable_mbox_intr(_device)\
  1143. do {\
  1144. u32 intr_status;\
  1145. bna_intr_status_get((_device)->bna, intr_status);\
  1146. bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
  1147. bna_mbox_intr_enable((_device)->bna);\
  1148. } while (0)
  1149. #define disable_mbox_intr(_device)\
  1150. do {\
  1151. bna_mbox_intr_disable((_device)->bna);\
  1152. bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
  1153. } while (0)
  1154. static const struct bna_chip_regs_offset reg_offset[] =
  1155. {{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
  1156. HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
  1157. {HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
  1158. HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
  1159. {HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
  1160. HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
  1161. {HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
  1162. HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
  1163. };
  1164. enum bna_device_event {
  1165. DEVICE_E_ENABLE = 1,
  1166. DEVICE_E_DISABLE = 2,
  1167. DEVICE_E_IOC_READY = 3,
  1168. DEVICE_E_IOC_FAILED = 4,
  1169. DEVICE_E_IOC_DISABLED = 5,
  1170. DEVICE_E_IOC_RESET = 6,
  1171. DEVICE_E_PORT_STOPPED = 7,
  1172. };
  1173. enum bna_device_state {
  1174. BNA_DEVICE_STOPPED = 1,
  1175. BNA_DEVICE_IOC_READY_WAIT = 2,
  1176. BNA_DEVICE_READY = 3,
  1177. BNA_DEVICE_PORT_STOP_WAIT = 4,
  1178. BNA_DEVICE_IOC_DISABLE_WAIT = 5,
  1179. BNA_DEVICE_FAILED = 6
  1180. };
  1181. bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
  1182. enum bna_device_event);
  1183. bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
  1184. enum bna_device_event);
  1185. bfa_fsm_state_decl(bna_device, ready, struct bna_device,
  1186. enum bna_device_event);
  1187. bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
  1188. enum bna_device_event);
  1189. bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
  1190. enum bna_device_event);
  1191. bfa_fsm_state_decl(bna_device, failed, struct bna_device,
  1192. enum bna_device_event);
  1193. static struct bfa_sm_table device_sm_table[] = {
  1194. {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
  1195. {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
  1196. {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
  1197. {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
  1198. {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
  1199. {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
  1200. };
  1201. static void
  1202. bna_device_sm_stopped_entry(struct bna_device *device)
  1203. {
  1204. if (device->stop_cbfn)
  1205. device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
  1206. device->stop_cbfn = NULL;
  1207. device->stop_cbarg = NULL;
  1208. }
  1209. static void
  1210. bna_device_sm_stopped(struct bna_device *device,
  1211. enum bna_device_event event)
  1212. {
  1213. switch (event) {
  1214. case DEVICE_E_ENABLE:
  1215. if (device->intr_type == BNA_INTR_T_MSIX)
  1216. bna_mbox_msix_idx_set(device);
  1217. bfa_nw_ioc_enable(&device->ioc);
  1218. bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
  1219. break;
  1220. case DEVICE_E_DISABLE:
  1221. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1222. break;
  1223. case DEVICE_E_IOC_RESET:
  1224. enable_mbox_intr(device);
  1225. break;
  1226. case DEVICE_E_IOC_FAILED:
  1227. bfa_fsm_set_state(device, bna_device_sm_failed);
  1228. break;
  1229. default:
  1230. bfa_sm_fault(device->bna, event);
  1231. }
  1232. }
  1233. static void
  1234. bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
  1235. {
  1236. /**
  1237. * Do not call bfa_ioc_enable() here. It must be called in the
  1238. * previous state due to failed -> ioc_ready_wait transition.
  1239. */
  1240. }
  1241. static void
  1242. bna_device_sm_ioc_ready_wait(struct bna_device *device,
  1243. enum bna_device_event event)
  1244. {
  1245. switch (event) {
  1246. case DEVICE_E_DISABLE:
  1247. if (device->ready_cbfn)
  1248. device->ready_cbfn(device->ready_cbarg,
  1249. BNA_CB_INTERRUPT);
  1250. device->ready_cbfn = NULL;
  1251. device->ready_cbarg = NULL;
  1252. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1253. break;
  1254. case DEVICE_E_IOC_READY:
  1255. bfa_fsm_set_state(device, bna_device_sm_ready);
  1256. break;
  1257. case DEVICE_E_IOC_FAILED:
  1258. bfa_fsm_set_state(device, bna_device_sm_failed);
  1259. break;
  1260. case DEVICE_E_IOC_RESET:
  1261. enable_mbox_intr(device);
  1262. break;
  1263. default:
  1264. bfa_sm_fault(device->bna, event);
  1265. }
  1266. }
  1267. static void
  1268. bna_device_sm_ready_entry(struct bna_device *device)
  1269. {
  1270. bna_mbox_mod_start(&device->bna->mbox_mod);
  1271. bna_port_start(&device->bna->port);
  1272. if (device->ready_cbfn)
  1273. device->ready_cbfn(device->ready_cbarg,
  1274. BNA_CB_SUCCESS);
  1275. device->ready_cbfn = NULL;
  1276. device->ready_cbarg = NULL;
  1277. }
  1278. static void
  1279. bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
  1280. {
  1281. switch (event) {
  1282. case DEVICE_E_DISABLE:
  1283. bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
  1284. break;
  1285. case DEVICE_E_IOC_FAILED:
  1286. bfa_fsm_set_state(device, bna_device_sm_failed);
  1287. break;
  1288. default:
  1289. bfa_sm_fault(device->bna, event);
  1290. }
  1291. }
  1292. static void
  1293. bna_device_sm_port_stop_wait_entry(struct bna_device *device)
  1294. {
  1295. bna_port_stop(&device->bna->port);
  1296. }
  1297. static void
  1298. bna_device_sm_port_stop_wait(struct bna_device *device,
  1299. enum bna_device_event event)
  1300. {
  1301. switch (event) {
  1302. case DEVICE_E_PORT_STOPPED:
  1303. bna_mbox_mod_stop(&device->bna->mbox_mod);
  1304. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1305. break;
  1306. case DEVICE_E_IOC_FAILED:
  1307. disable_mbox_intr(device);
  1308. bna_port_fail(&device->bna->port);
  1309. break;
  1310. default:
  1311. bfa_sm_fault(device->bna, event);
  1312. }
  1313. }
  1314. static void
  1315. bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
  1316. {
  1317. bfa_nw_ioc_disable(&device->ioc);
  1318. }
  1319. static void
  1320. bna_device_sm_ioc_disable_wait(struct bna_device *device,
  1321. enum bna_device_event event)
  1322. {
  1323. switch (event) {
  1324. case DEVICE_E_IOC_DISABLED:
  1325. disable_mbox_intr(device);
  1326. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1327. break;
  1328. default:
  1329. bfa_sm_fault(device->bna, event);
  1330. }
  1331. }
  1332. static void
  1333. bna_device_sm_failed_entry(struct bna_device *device)
  1334. {
  1335. disable_mbox_intr(device);
  1336. bna_port_fail(&device->bna->port);
  1337. bna_mbox_mod_stop(&device->bna->mbox_mod);
  1338. if (device->ready_cbfn)
  1339. device->ready_cbfn(device->ready_cbarg,
  1340. BNA_CB_FAIL);
  1341. device->ready_cbfn = NULL;
  1342. device->ready_cbarg = NULL;
  1343. }
  1344. static void
  1345. bna_device_sm_failed(struct bna_device *device,
  1346. enum bna_device_event event)
  1347. {
  1348. switch (event) {
  1349. case DEVICE_E_DISABLE:
  1350. bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
  1351. break;
  1352. case DEVICE_E_IOC_RESET:
  1353. enable_mbox_intr(device);
  1354. bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
  1355. break;
  1356. default:
  1357. bfa_sm_fault(device->bna, event);
  1358. }
  1359. }
  1360. /* IOC callback functions */
  1361. static void
  1362. bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
  1363. {
  1364. struct bna_device *device = (struct bna_device *)dev;
  1365. if (error)
  1366. bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
  1367. else
  1368. bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
  1369. }
  1370. static void
  1371. bna_device_cb_iocll_disabled(void *dev)
  1372. {
  1373. struct bna_device *device = (struct bna_device *)dev;
  1374. bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
  1375. }
  1376. static void
  1377. bna_device_cb_iocll_failed(void *dev)
  1378. {
  1379. struct bna_device *device = (struct bna_device *)dev;
  1380. bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
  1381. }
  1382. static void
  1383. bna_device_cb_iocll_reset(void *dev)
  1384. {
  1385. struct bna_device *device = (struct bna_device *)dev;
  1386. bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
  1387. }
  1388. static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
  1389. bna_device_cb_iocll_ready,
  1390. bna_device_cb_iocll_disabled,
  1391. bna_device_cb_iocll_failed,
  1392. bna_device_cb_iocll_reset
  1393. };
  1394. /* device */
  1395. static void
  1396. bna_adv_device_init(struct bna_device *device, struct bna *bna,
  1397. struct bna_res_info *res_info)
  1398. {
  1399. u8 *kva;
  1400. u64 dma;
  1401. device->bna = bna;
  1402. kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
  1403. /**
  1404. * Attach common modules (Diag, SFP, CEE, Port) and claim respective
  1405. * DMA memory.
  1406. */
  1407. BNA_GET_DMA_ADDR(
  1408. &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
  1409. kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
  1410. bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
  1411. bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
  1412. kva += bfa_nw_cee_meminfo();
  1413. dma += bfa_nw_cee_meminfo();
  1414. }
  1415. static void
  1416. bna_device_init(struct bna_device *device, struct bna *bna,
  1417. struct bna_res_info *res_info)
  1418. {
  1419. u64 dma;
  1420. device->bna = bna;
  1421. /**
  1422. * Attach IOC and claim:
  1423. * 1. DMA memory for IOC attributes
  1424. * 2. Kernel memory for FW trace
  1425. */
  1426. bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
  1427. bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
  1428. BNA_GET_DMA_ADDR(
  1429. &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
  1430. bfa_nw_ioc_mem_claim(&device->ioc,
  1431. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
  1432. dma);
  1433. bna_adv_device_init(device, bna, res_info);
  1434. /*
  1435. * Initialize mbox_mod only after IOC, so that mbox handler
  1436. * registration goes through
  1437. */
  1438. device->intr_type =
  1439. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
  1440. device->vector =
  1441. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
  1442. bna_mbox_mod_init(&bna->mbox_mod, bna);
  1443. device->ready_cbfn = device->stop_cbfn = NULL;
  1444. device->ready_cbarg = device->stop_cbarg = NULL;
  1445. bfa_fsm_set_state(device, bna_device_sm_stopped);
  1446. }
  1447. static void
  1448. bna_device_uninit(struct bna_device *device)
  1449. {
  1450. bna_mbox_mod_uninit(&device->bna->mbox_mod);
  1451. bfa_nw_ioc_detach(&device->ioc);
  1452. device->bna = NULL;
  1453. }
  1454. static void
  1455. bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
  1456. {
  1457. struct bna_device *device = (struct bna_device *)arg;
  1458. bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
  1459. }
  1460. static int
  1461. bna_device_status_get(struct bna_device *device)
  1462. {
  1463. return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
  1464. }
  1465. void
  1466. bna_device_enable(struct bna_device *device)
  1467. {
  1468. if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
  1469. bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
  1470. return;
  1471. }
  1472. device->ready_cbfn = bnad_cb_device_enabled;
  1473. device->ready_cbarg = device->bna->bnad;
  1474. bfa_fsm_send_event(device, DEVICE_E_ENABLE);
  1475. }
  1476. void
  1477. bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
  1478. {
  1479. if (type == BNA_SOFT_CLEANUP) {
  1480. bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
  1481. return;
  1482. }
  1483. device->stop_cbfn = bnad_cb_device_disabled;
  1484. device->stop_cbarg = device->bna->bnad;
  1485. bfa_fsm_send_event(device, DEVICE_E_DISABLE);
  1486. }
  1487. static int
  1488. bna_device_state_get(struct bna_device *device)
  1489. {
  1490. return bfa_sm_to_state(device_sm_table, device->fsm);
  1491. }
  1492. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  1493. {12, 12},
  1494. {6, 10},
  1495. {5, 10},
  1496. {4, 8},
  1497. {3, 6},
  1498. {3, 6},
  1499. {2, 4},
  1500. {1, 2},
  1501. };
  1502. /* utils */
  1503. static void
  1504. bna_adv_res_req(struct bna_res_info *res_info)
  1505. {
  1506. /* DMA memory for COMMON_MODULE */
  1507. res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
  1508. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  1509. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
  1510. res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
  1511. bfa_nw_cee_meminfo(), PAGE_SIZE);
  1512. /* Virtual memory for retreiving fw_trc */
  1513. res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
  1514. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
  1515. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
  1516. res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
  1517. /* DMA memory for retreiving stats */
  1518. res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
  1519. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  1520. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
  1521. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
  1522. ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
  1523. /* Virtual memory for soft stats */
  1524. res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
  1525. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
  1526. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
  1527. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
  1528. sizeof(struct bna_sw_stats);
  1529. }
  1530. static void
  1531. bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
  1532. {
  1533. struct bna_tx *tx;
  1534. struct bna_txq *txq;
  1535. struct bna_rx *rx;
  1536. struct bna_rxp *rxp;
  1537. struct list_head *qe;
  1538. struct list_head *txq_qe;
  1539. struct list_head *rxp_qe;
  1540. struct list_head *mac_qe;
  1541. int i;
  1542. sw_stats->device_state = bna_device_state_get(&bna->device);
  1543. sw_stats->port_state = bna_port_state_get(&bna->port);
  1544. sw_stats->port_flags = bna->port.flags;
  1545. sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
  1546. sw_stats->priority = bna->port.priority;
  1547. i = 0;
  1548. list_for_each(qe, &bna->tx_mod.tx_active_q) {
  1549. tx = (struct bna_tx *)qe;
  1550. sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
  1551. sw_stats->tx_stats[i].tx_flags = tx->flags;
  1552. sw_stats->tx_stats[i].num_txqs = 0;
  1553. sw_stats->tx_stats[i].txq_bmap[0] = 0;
  1554. sw_stats->tx_stats[i].txq_bmap[1] = 0;
  1555. list_for_each(txq_qe, &tx->txq_q) {
  1556. txq = (struct bna_txq *)txq_qe;
  1557. if (txq->txq_id < 32)
  1558. sw_stats->tx_stats[i].txq_bmap[0] |=
  1559. ((u32)1 << txq->txq_id);
  1560. else
  1561. sw_stats->tx_stats[i].txq_bmap[1] |=
  1562. ((u32)
  1563. 1 << (txq->txq_id - 32));
  1564. sw_stats->tx_stats[i].num_txqs++;
  1565. }
  1566. sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
  1567. i++;
  1568. }
  1569. sw_stats->num_active_tx = i;
  1570. i = 0;
  1571. list_for_each(qe, &bna->rx_mod.rx_active_q) {
  1572. rx = (struct bna_rx *)qe;
  1573. sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
  1574. sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
  1575. sw_stats->rx_stats[i].num_rxps = 0;
  1576. sw_stats->rx_stats[i].num_rxqs = 0;
  1577. sw_stats->rx_stats[i].rxq_bmap[0] = 0;
  1578. sw_stats->rx_stats[i].rxq_bmap[1] = 0;
  1579. sw_stats->rx_stats[i].cq_bmap[0] = 0;
  1580. sw_stats->rx_stats[i].cq_bmap[1] = 0;
  1581. list_for_each(rxp_qe, &rx->rxp_q) {
  1582. rxp = (struct bna_rxp *)rxp_qe;
  1583. sw_stats->rx_stats[i].num_rxqs += 1;
  1584. if (rxp->type == BNA_RXP_SINGLE) {
  1585. if (rxp->rxq.single.only->rxq_id < 32) {
  1586. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1587. ((u32)1 <<
  1588. rxp->rxq.single.only->rxq_id);
  1589. } else {
  1590. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1591. ((u32)1 <<
  1592. (rxp->rxq.single.only->rxq_id - 32));
  1593. }
  1594. } else {
  1595. if (rxp->rxq.slr.large->rxq_id < 32) {
  1596. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1597. ((u32)1 <<
  1598. rxp->rxq.slr.large->rxq_id);
  1599. } else {
  1600. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1601. ((u32)1 <<
  1602. (rxp->rxq.slr.large->rxq_id - 32));
  1603. }
  1604. if (rxp->rxq.slr.small->rxq_id < 32) {
  1605. sw_stats->rx_stats[i].rxq_bmap[0] |=
  1606. ((u32)1 <<
  1607. rxp->rxq.slr.small->rxq_id);
  1608. } else {
  1609. sw_stats->rx_stats[i].rxq_bmap[1] |=
  1610. ((u32)1 <<
  1611. (rxp->rxq.slr.small->rxq_id - 32));
  1612. }
  1613. sw_stats->rx_stats[i].num_rxqs += 1;
  1614. }
  1615. if (rxp->cq.cq_id < 32)
  1616. sw_stats->rx_stats[i].cq_bmap[0] |=
  1617. (1 << rxp->cq.cq_id);
  1618. else
  1619. sw_stats->rx_stats[i].cq_bmap[1] |=
  1620. (1 << (rxp->cq.cq_id - 32));
  1621. sw_stats->rx_stats[i].num_rxps++;
  1622. }
  1623. sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
  1624. sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
  1625. sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
  1626. sw_stats->rx_stats[i].num_active_ucast = 0;
  1627. if (rx->rxf.ucast_active_mac)
  1628. sw_stats->rx_stats[i].num_active_ucast++;
  1629. list_for_each(mac_qe, &rx->rxf.ucast_active_q)
  1630. sw_stats->rx_stats[i].num_active_ucast++;
  1631. sw_stats->rx_stats[i].num_active_mcast = 0;
  1632. list_for_each(mac_qe, &rx->rxf.mcast_active_q)
  1633. sw_stats->rx_stats[i].num_active_mcast++;
  1634. sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
  1635. sw_stats->rx_stats[i].vlan_filter_status =
  1636. rx->rxf.vlan_filter_status;
  1637. memcpy(sw_stats->rx_stats[i].vlan_filter_table,
  1638. rx->rxf.vlan_filter_table,
  1639. sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
  1640. sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
  1641. sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
  1642. i++;
  1643. }
  1644. sw_stats->num_active_rx = i;
  1645. }
  1646. static void
  1647. bna_fw_cb_stats_get(void *arg, int status)
  1648. {
  1649. struct bna *bna = (struct bna *)arg;
  1650. u64 *p_stats;
  1651. int i, count;
  1652. int rxf_count, txf_count;
  1653. u64 rxf_bmap, txf_bmap;
  1654. bfa_q_qe_init(&bna->mbox_qe.qe);
  1655. if (status == 0) {
  1656. p_stats = (u64 *)bna->stats.hw_stats;
  1657. count = sizeof(struct bfi_ll_stats) / sizeof(u64);
  1658. for (i = 0; i < count; i++)
  1659. p_stats[i] = cpu_to_be64(p_stats[i]);
  1660. rxf_count = 0;
  1661. rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
  1662. ((u64)bna->stats.rxf_bmap[1] << 32);
  1663. for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
  1664. if (rxf_bmap & ((u64)1 << i))
  1665. rxf_count++;
  1666. txf_count = 0;
  1667. txf_bmap = (u64)bna->stats.txf_bmap[0] |
  1668. ((u64)bna->stats.txf_bmap[1] << 32);
  1669. for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
  1670. if (txf_bmap & ((u64)1 << i))
  1671. txf_count++;
  1672. p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
  1673. ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
  1674. txf_count * sizeof(struct bfi_ll_stats_txf))/
  1675. sizeof(u64));
  1676. /* Populate the TXF stats from the firmware DMAed copy */
  1677. for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
  1678. if (txf_bmap & ((u64)1 << i)) {
  1679. p_stats -= sizeof(struct bfi_ll_stats_txf)/
  1680. sizeof(u64);
  1681. memcpy(&bna->stats.hw_stats->txf_stats[i],
  1682. p_stats,
  1683. sizeof(struct bfi_ll_stats_txf));
  1684. }
  1685. /* Populate the RXF stats from the firmware DMAed copy */
  1686. for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
  1687. if (rxf_bmap & ((u64)1 << i)) {
  1688. p_stats -= sizeof(struct bfi_ll_stats_rxf)/
  1689. sizeof(u64);
  1690. memcpy(&bna->stats.hw_stats->rxf_stats[i],
  1691. p_stats,
  1692. sizeof(struct bfi_ll_stats_rxf));
  1693. }
  1694. bna_sw_stats_get(bna, bna->stats.sw_stats);
  1695. bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
  1696. } else
  1697. bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
  1698. }
  1699. static void
  1700. bna_fw_stats_get(struct bna *bna)
  1701. {
  1702. struct bfi_ll_stats_req ll_req;
  1703. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
  1704. ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
  1705. ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
  1706. ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
  1707. ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
  1708. ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
  1709. ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
  1710. ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
  1711. bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
  1712. bna_fw_cb_stats_get, bna);
  1713. bna_mbox_send(bna, &bna->mbox_qe);
  1714. bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
  1715. bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
  1716. bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
  1717. bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
  1718. }
  1719. void
  1720. bna_stats_get(struct bna *bna)
  1721. {
  1722. if (bna_device_status_get(&bna->device))
  1723. bna_fw_stats_get(bna);
  1724. else
  1725. bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
  1726. }
  1727. /* IB */
  1728. static void
  1729. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  1730. {
  1731. ib->ib_config.coalescing_timeo = coalescing_timeo;
  1732. if (ib->start_count)
  1733. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  1734. (u32)ib->ib_config.coalescing_timeo, 0);
  1735. }
  1736. /* RxF */
  1737. void
  1738. bna_rxf_adv_init(struct bna_rxf *rxf,
  1739. struct bna_rx *rx,
  1740. struct bna_rx_config *q_config)
  1741. {
  1742. switch (q_config->rxp_type) {
  1743. case BNA_RXP_SINGLE:
  1744. /* No-op */
  1745. break;
  1746. case BNA_RXP_SLR:
  1747. rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
  1748. break;
  1749. case BNA_RXP_HDS:
  1750. rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
  1751. rxf->hds_cfg.header_size =
  1752. q_config->hds_config.header_size;
  1753. rxf->forced_offset = 0;
  1754. break;
  1755. default:
  1756. break;
  1757. }
  1758. if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
  1759. rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
  1760. rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
  1761. rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
  1762. memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
  1763. &q_config->rss_config.toeplitz_hash_key[0],
  1764. sizeof(rxf->rss_cfg.toeplitz_hash_key));
  1765. }
  1766. }
  1767. static void
  1768. rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
  1769. {
  1770. struct bfi_ll_rxf_req req;
  1771. bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
  1772. req.rxf_id = rxf->rxf_id;
  1773. req.enable = status;
  1774. bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
  1775. rxf_cb_cam_fltr_mbox_cmd, rxf);
  1776. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  1777. }
  1778. static void
  1779. __rxf_default_function_config(struct bna_rxf *rxf, enum bna_status status)
  1780. {
  1781. struct bna_rx_fndb_ram *rx_fndb_ram;
  1782. u32 ctrl_flags;
  1783. int i;
  1784. rx_fndb_ram = (struct bna_rx_fndb_ram *)
  1785. BNA_GET_MEM_BASE_ADDR(rxf->rx->bna->pcidev.pci_bar_kva,
  1786. RX_FNDB_RAM_BASE_OFFSET);
  1787. for (i = 0; i < BFI_MAX_RXF; i++) {
  1788. if (status == BNA_STATUS_T_ENABLED) {
  1789. if (i == rxf->rxf_id)
  1790. continue;
  1791. ctrl_flags =
  1792. readl(&rx_fndb_ram[i].control_flags);
  1793. ctrl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
  1794. writel(ctrl_flags,
  1795. &rx_fndb_ram[i].control_flags);
  1796. } else {
  1797. ctrl_flags =
  1798. readl(&rx_fndb_ram[i].control_flags);
  1799. ctrl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
  1800. writel(ctrl_flags,
  1801. &rx_fndb_ram[i].control_flags);
  1802. }
  1803. }
  1804. }
  1805. int
  1806. rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
  1807. {
  1808. struct bna_mac *mac = NULL;
  1809. struct list_head *qe;
  1810. /* Add additional MAC entries */
  1811. if (!list_empty(&rxf->ucast_pending_add_q)) {
  1812. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  1813. bfa_q_qe_init(qe);
  1814. mac = (struct bna_mac *)qe;
  1815. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
  1816. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  1817. return 1;
  1818. }
  1819. /* Delete MAC addresses previousely added */
  1820. if (!list_empty(&rxf->ucast_pending_del_q)) {
  1821. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1822. bfa_q_qe_init(qe);
  1823. mac = (struct bna_mac *)qe;
  1824. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1825. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1826. return 1;
  1827. }
  1828. return 0;
  1829. }
  1830. int
  1831. rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
  1832. {
  1833. struct bna *bna = rxf->rx->bna;
  1834. /* Enable/disable promiscuous mode */
  1835. if (is_promisc_enable(rxf->rxmode_pending,
  1836. rxf->rxmode_pending_bitmask)) {
  1837. /* move promisc configuration from pending -> active */
  1838. promisc_inactive(rxf->rxmode_pending,
  1839. rxf->rxmode_pending_bitmask);
  1840. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  1841. /* Disable VLAN filter to allow all VLANs */
  1842. __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
  1843. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1844. BNA_STATUS_T_ENABLED);
  1845. return 1;
  1846. } else if (is_promisc_disable(rxf->rxmode_pending,
  1847. rxf->rxmode_pending_bitmask)) {
  1848. /* move promisc configuration from pending -> active */
  1849. promisc_inactive(rxf->rxmode_pending,
  1850. rxf->rxmode_pending_bitmask);
  1851. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1852. bna->rxf_promisc_id = BFI_MAX_RXF;
  1853. /* Revert VLAN filter */
  1854. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1855. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1856. BNA_STATUS_T_DISABLED);
  1857. return 1;
  1858. }
  1859. return 0;
  1860. }
  1861. int
  1862. rxf_process_packet_filter_default(struct bna_rxf *rxf)
  1863. {
  1864. struct bna *bna = rxf->rx->bna;
  1865. /* Enable/disable default mode */
  1866. if (is_default_enable(rxf->rxmode_pending,
  1867. rxf->rxmode_pending_bitmask)) {
  1868. /* move default configuration from pending -> active */
  1869. default_inactive(rxf->rxmode_pending,
  1870. rxf->rxmode_pending_bitmask);
  1871. rxf->rxmode_active |= BNA_RXMODE_DEFAULT;
  1872. /* Disable VLAN filter to allow all VLANs */
  1873. __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
  1874. /* Redirect all other RxF vlan filtering to this one */
  1875. __rxf_default_function_config(rxf, BNA_STATUS_T_ENABLED);
  1876. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
  1877. BNA_STATUS_T_ENABLED);
  1878. return 1;
  1879. } else if (is_default_disable(rxf->rxmode_pending,
  1880. rxf->rxmode_pending_bitmask)) {
  1881. /* move default configuration from pending -> active */
  1882. default_inactive(rxf->rxmode_pending,
  1883. rxf->rxmode_pending_bitmask);
  1884. rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
  1885. bna->rxf_default_id = BFI_MAX_RXF;
  1886. /* Revert VLAN filter */
  1887. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1888. /* Stop RxF vlan filter table redirection */
  1889. __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
  1890. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
  1891. BNA_STATUS_T_DISABLED);
  1892. return 1;
  1893. }
  1894. return 0;
  1895. }
  1896. int
  1897. rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
  1898. {
  1899. /* Enable/disable allmulti mode */
  1900. if (is_allmulti_enable(rxf->rxmode_pending,
  1901. rxf->rxmode_pending_bitmask)) {
  1902. /* move allmulti configuration from pending -> active */
  1903. allmulti_inactive(rxf->rxmode_pending,
  1904. rxf->rxmode_pending_bitmask);
  1905. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  1906. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1907. BNA_STATUS_T_ENABLED);
  1908. return 1;
  1909. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1910. rxf->rxmode_pending_bitmask)) {
  1911. /* move allmulti configuration from pending -> active */
  1912. allmulti_inactive(rxf->rxmode_pending,
  1913. rxf->rxmode_pending_bitmask);
  1914. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1915. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  1916. BNA_STATUS_T_DISABLED);
  1917. return 1;
  1918. }
  1919. return 0;
  1920. }
  1921. int
  1922. rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
  1923. {
  1924. struct bna_mac *mac = NULL;
  1925. struct list_head *qe;
  1926. /* 1. delete pending ucast entries */
  1927. if (!list_empty(&rxf->ucast_pending_del_q)) {
  1928. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  1929. bfa_q_qe_init(qe);
  1930. mac = (struct bna_mac *)qe;
  1931. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1932. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1933. return 1;
  1934. }
  1935. /* 2. clear active ucast entries; move them to pending_add_q */
  1936. if (!list_empty(&rxf->ucast_active_q)) {
  1937. bfa_q_deq(&rxf->ucast_active_q, &qe);
  1938. bfa_q_qe_init(qe);
  1939. mac = (struct bna_mac *)qe;
  1940. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
  1941. list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
  1942. return 1;
  1943. }
  1944. return 0;
  1945. }
  1946. int
  1947. rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
  1948. {
  1949. struct bna *bna = rxf->rx->bna;
  1950. /* 6. Execute pending promisc mode disable command */
  1951. if (is_promisc_disable(rxf->rxmode_pending,
  1952. rxf->rxmode_pending_bitmask)) {
  1953. /* move promisc configuration from pending -> active */
  1954. promisc_inactive(rxf->rxmode_pending,
  1955. rxf->rxmode_pending_bitmask);
  1956. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1957. bna->rxf_promisc_id = BFI_MAX_RXF;
  1958. /* Revert VLAN filter */
  1959. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1960. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1961. BNA_STATUS_T_DISABLED);
  1962. return 1;
  1963. }
  1964. /* 7. Clear active promisc mode; move it to pending enable */
  1965. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1966. /* move promisc configuration from active -> pending */
  1967. promisc_enable(rxf->rxmode_pending,
  1968. rxf->rxmode_pending_bitmask);
  1969. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  1970. /* Revert VLAN filter */
  1971. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1972. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
  1973. BNA_STATUS_T_DISABLED);
  1974. return 1;
  1975. }
  1976. return 0;
  1977. }
  1978. int
  1979. rxf_clear_packet_filter_default(struct bna_rxf *rxf)
  1980. {
  1981. struct bna *bna = rxf->rx->bna;
  1982. /* 8. Execute pending default mode disable command */
  1983. if (is_default_disable(rxf->rxmode_pending,
  1984. rxf->rxmode_pending_bitmask)) {
  1985. /* move default configuration from pending -> active */
  1986. default_inactive(rxf->rxmode_pending,
  1987. rxf->rxmode_pending_bitmask);
  1988. rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
  1989. bna->rxf_default_id = BFI_MAX_RXF;
  1990. /* Revert VLAN filter */
  1991. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1992. /* Stop RxF vlan filter table redirection */
  1993. __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
  1994. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
  1995. BNA_STATUS_T_DISABLED);
  1996. return 1;
  1997. }
  1998. /* 9. Clear active default mode; move it to pending enable */
  1999. if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
  2000. /* move default configuration from active -> pending */
  2001. default_enable(rxf->rxmode_pending,
  2002. rxf->rxmode_pending_bitmask);
  2003. rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
  2004. /* Revert VLAN filter */
  2005. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  2006. /* Stop RxF vlan filter table redirection */
  2007. __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
  2008. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
  2009. BNA_STATUS_T_DISABLED);
  2010. return 1;
  2011. }
  2012. return 0;
  2013. }
  2014. int
  2015. rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
  2016. {
  2017. /* 10. Execute pending allmulti mode disable command */
  2018. if (is_allmulti_disable(rxf->rxmode_pending,
  2019. rxf->rxmode_pending_bitmask)) {
  2020. /* move allmulti configuration from pending -> active */
  2021. allmulti_inactive(rxf->rxmode_pending,
  2022. rxf->rxmode_pending_bitmask);
  2023. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  2024. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  2025. BNA_STATUS_T_DISABLED);
  2026. return 1;
  2027. }
  2028. /* 11. Clear active allmulti mode; move it to pending enable */
  2029. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  2030. /* move allmulti configuration from active -> pending */
  2031. allmulti_enable(rxf->rxmode_pending,
  2032. rxf->rxmode_pending_bitmask);
  2033. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  2034. rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
  2035. BNA_STATUS_T_DISABLED);
  2036. return 1;
  2037. }
  2038. return 0;
  2039. }
  2040. void
  2041. rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
  2042. {
  2043. struct list_head *qe;
  2044. struct bna_mac *mac;
  2045. /* 1. Move active ucast entries to pending_add_q */
  2046. while (!list_empty(&rxf->ucast_active_q)) {
  2047. bfa_q_deq(&rxf->ucast_active_q, &qe);
  2048. bfa_q_qe_init(qe);
  2049. list_add_tail(qe, &rxf->ucast_pending_add_q);
  2050. }
  2051. /* 2. Throw away delete pending ucast entries */
  2052. while (!list_empty(&rxf->ucast_pending_del_q)) {
  2053. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  2054. bfa_q_qe_init(qe);
  2055. mac = (struct bna_mac *)qe;
  2056. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  2057. }
  2058. }
  2059. void
  2060. rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
  2061. {
  2062. struct bna *bna = rxf->rx->bna;
  2063. /* 6. Clear pending promisc mode disable */
  2064. if (is_promisc_disable(rxf->rxmode_pending,
  2065. rxf->rxmode_pending_bitmask)) {
  2066. promisc_inactive(rxf->rxmode_pending,
  2067. rxf->rxmode_pending_bitmask);
  2068. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  2069. bna->rxf_promisc_id = BFI_MAX_RXF;
  2070. }
  2071. /* 7. Move promisc mode config from active -> pending */
  2072. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  2073. promisc_enable(rxf->rxmode_pending,
  2074. rxf->rxmode_pending_bitmask);
  2075. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  2076. }
  2077. }
  2078. void
  2079. rxf_reset_packet_filter_default(struct bna_rxf *rxf)
  2080. {
  2081. struct bna *bna = rxf->rx->bna;
  2082. /* 8. Clear pending default mode disable */
  2083. if (is_default_disable(rxf->rxmode_pending,
  2084. rxf->rxmode_pending_bitmask)) {
  2085. default_inactive(rxf->rxmode_pending,
  2086. rxf->rxmode_pending_bitmask);
  2087. rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
  2088. bna->rxf_default_id = BFI_MAX_RXF;
  2089. }
  2090. /* 9. Move default mode config from active -> pending */
  2091. if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
  2092. default_enable(rxf->rxmode_pending,
  2093. rxf->rxmode_pending_bitmask);
  2094. rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
  2095. }
  2096. }
  2097. void
  2098. rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
  2099. {
  2100. /* 10. Clear pending allmulti mode disable */
  2101. if (is_allmulti_disable(rxf->rxmode_pending,
  2102. rxf->rxmode_pending_bitmask)) {
  2103. allmulti_inactive(rxf->rxmode_pending,
  2104. rxf->rxmode_pending_bitmask);
  2105. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  2106. }
  2107. /* 11. Move allmulti mode config from active -> pending */
  2108. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  2109. allmulti_enable(rxf->rxmode_pending,
  2110. rxf->rxmode_pending_bitmask);
  2111. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  2112. }
  2113. }
  2114. /**
  2115. * Should only be called by bna_rxf_mode_set.
  2116. * Helps deciding if h/w configuration is needed or not.
  2117. * Returns:
  2118. * 0 = no h/w change
  2119. * 1 = need h/w change
  2120. */
  2121. static int
  2122. rxf_promisc_enable(struct bna_rxf *rxf)
  2123. {
  2124. struct bna *bna = rxf->rx->bna;
  2125. int ret = 0;
  2126. /* There can not be any pending disable command */
  2127. /* Do nothing if pending enable or already enabled */
  2128. if (is_promisc_enable(rxf->rxmode_pending,
  2129. rxf->rxmode_pending_bitmask) ||
  2130. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  2131. /* Schedule enable */
  2132. } else {
  2133. /* Promisc mode should not be active in the system */
  2134. promisc_enable(rxf->rxmode_pending,
  2135. rxf->rxmode_pending_bitmask);
  2136. bna->rxf_promisc_id = rxf->rxf_id;
  2137. ret = 1;
  2138. }
  2139. return ret;
  2140. }
  2141. /**
  2142. * Should only be called by bna_rxf_mode_set.
  2143. * Helps deciding if h/w configuration is needed or not.
  2144. * Returns:
  2145. * 0 = no h/w change
  2146. * 1 = need h/w change
  2147. */
  2148. static int
  2149. rxf_promisc_disable(struct bna_rxf *rxf)
  2150. {
  2151. struct bna *bna = rxf->rx->bna;
  2152. int ret = 0;
  2153. /* There can not be any pending disable */
  2154. /* Turn off pending enable command , if any */
  2155. if (is_promisc_enable(rxf->rxmode_pending,
  2156. rxf->rxmode_pending_bitmask)) {
  2157. /* Promisc mode should not be active */
  2158. /* system promisc state should be pending */
  2159. promisc_inactive(rxf->rxmode_pending,
  2160. rxf->rxmode_pending_bitmask);
  2161. /* Remove the promisc state from the system */
  2162. bna->rxf_promisc_id = BFI_MAX_RXF;
  2163. /* Schedule disable */
  2164. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  2165. /* Promisc mode should be active in the system */
  2166. promisc_disable(rxf->rxmode_pending,
  2167. rxf->rxmode_pending_bitmask);
  2168. ret = 1;
  2169. /* Do nothing if already disabled */
  2170. } else {
  2171. }
  2172. return ret;
  2173. }
  2174. /**
  2175. * Should only be called by bna_rxf_mode_set.
  2176. * Helps deciding if h/w configuration is needed or not.
  2177. * Returns:
  2178. * 0 = no h/w change
  2179. * 1 = need h/w change
  2180. */
  2181. static int
  2182. rxf_default_enable(struct bna_rxf *rxf)
  2183. {
  2184. struct bna *bna = rxf->rx->bna;
  2185. int ret = 0;
  2186. /* There can not be any pending disable command */
  2187. /* Do nothing if pending enable or already enabled */
  2188. if (is_default_enable(rxf->rxmode_pending,
  2189. rxf->rxmode_pending_bitmask) ||
  2190. (rxf->rxmode_active & BNA_RXMODE_DEFAULT)) {
  2191. /* Schedule enable */
  2192. } else {
  2193. /* Default mode should not be active in the system */
  2194. default_enable(rxf->rxmode_pending,
  2195. rxf->rxmode_pending_bitmask);
  2196. bna->rxf_default_id = rxf->rxf_id;
  2197. ret = 1;
  2198. }
  2199. return ret;
  2200. }
  2201. /**
  2202. * Should only be called by bna_rxf_mode_set.
  2203. * Helps deciding if h/w configuration is needed or not.
  2204. * Returns:
  2205. * 0 = no h/w change
  2206. * 1 = need h/w change
  2207. */
  2208. static int
  2209. rxf_default_disable(struct bna_rxf *rxf)
  2210. {
  2211. struct bna *bna = rxf->rx->bna;
  2212. int ret = 0;
  2213. /* There can not be any pending disable */
  2214. /* Turn off pending enable command , if any */
  2215. if (is_default_enable(rxf->rxmode_pending,
  2216. rxf->rxmode_pending_bitmask)) {
  2217. /* Promisc mode should not be active */
  2218. /* system default state should be pending */
  2219. default_inactive(rxf->rxmode_pending,
  2220. rxf->rxmode_pending_bitmask);
  2221. /* Remove the default state from the system */
  2222. bna->rxf_default_id = BFI_MAX_RXF;
  2223. /* Schedule disable */
  2224. } else if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
  2225. /* Default mode should be active in the system */
  2226. default_disable(rxf->rxmode_pending,
  2227. rxf->rxmode_pending_bitmask);
  2228. ret = 1;
  2229. /* Do nothing if already disabled */
  2230. } else {
  2231. }
  2232. return ret;
  2233. }
  2234. /**
  2235. * Should only be called by bna_rxf_mode_set.
  2236. * Helps deciding if h/w configuration is needed or not.
  2237. * Returns:
  2238. * 0 = no h/w change
  2239. * 1 = need h/w change
  2240. */
  2241. static int
  2242. rxf_allmulti_enable(struct bna_rxf *rxf)
  2243. {
  2244. int ret = 0;
  2245. /* There can not be any pending disable command */
  2246. /* Do nothing if pending enable or already enabled */
  2247. if (is_allmulti_enable(rxf->rxmode_pending,
  2248. rxf->rxmode_pending_bitmask) ||
  2249. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  2250. /* Schedule enable */
  2251. } else {
  2252. allmulti_enable(rxf->rxmode_pending,
  2253. rxf->rxmode_pending_bitmask);
  2254. ret = 1;
  2255. }
  2256. return ret;
  2257. }
  2258. /**
  2259. * Should only be called by bna_rxf_mode_set.
  2260. * Helps deciding if h/w configuration is needed or not.
  2261. * Returns:
  2262. * 0 = no h/w change
  2263. * 1 = need h/w change
  2264. */
  2265. static int
  2266. rxf_allmulti_disable(struct bna_rxf *rxf)
  2267. {
  2268. int ret = 0;
  2269. /* There can not be any pending disable */
  2270. /* Turn off pending enable command , if any */
  2271. if (is_allmulti_enable(rxf->rxmode_pending,
  2272. rxf->rxmode_pending_bitmask)) {
  2273. /* Allmulti mode should not be active */
  2274. allmulti_inactive(rxf->rxmode_pending,
  2275. rxf->rxmode_pending_bitmask);
  2276. /* Schedule disable */
  2277. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  2278. allmulti_disable(rxf->rxmode_pending,
  2279. rxf->rxmode_pending_bitmask);
  2280. ret = 1;
  2281. }
  2282. return ret;
  2283. }
  2284. /* RxF <- bnad */
  2285. enum bna_cb_status
  2286. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2287. enum bna_rxmode bitmask,
  2288. void (*cbfn)(struct bnad *, struct bna_rx *,
  2289. enum bna_cb_status))
  2290. {
  2291. struct bna_rxf *rxf = &rx->rxf;
  2292. int need_hw_config = 0;
  2293. /* Error checks */
  2294. if (is_promisc_enable(new_mode, bitmask)) {
  2295. /* If promisc mode is already enabled elsewhere in the system */
  2296. if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
  2297. (rx->bna->rxf_promisc_id != rxf->rxf_id))
  2298. goto err_return;
  2299. /* If default mode is already enabled in the system */
  2300. if (rx->bna->rxf_default_id != BFI_MAX_RXF)
  2301. goto err_return;
  2302. /* Trying to enable promiscuous and default mode together */
  2303. if (is_default_enable(new_mode, bitmask))
  2304. goto err_return;
  2305. }
  2306. if (is_default_enable(new_mode, bitmask)) {
  2307. /* If default mode is already enabled elsewhere in the system */
  2308. if ((rx->bna->rxf_default_id != BFI_MAX_RXF) &&
  2309. (rx->bna->rxf_default_id != rxf->rxf_id)) {
  2310. goto err_return;
  2311. }
  2312. /* If promiscuous mode is already enabled in the system */
  2313. if (rx->bna->rxf_promisc_id != BFI_MAX_RXF)
  2314. goto err_return;
  2315. }
  2316. /* Process the commands */
  2317. if (is_promisc_enable(new_mode, bitmask)) {
  2318. if (rxf_promisc_enable(rxf))
  2319. need_hw_config = 1;
  2320. } else if (is_promisc_disable(new_mode, bitmask)) {
  2321. if (rxf_promisc_disable(rxf))
  2322. need_hw_config = 1;
  2323. }
  2324. if (is_default_enable(new_mode, bitmask)) {
  2325. if (rxf_default_enable(rxf))
  2326. need_hw_config = 1;
  2327. } else if (is_default_disable(new_mode, bitmask)) {
  2328. if (rxf_default_disable(rxf))
  2329. need_hw_config = 1;
  2330. }
  2331. if (is_allmulti_enable(new_mode, bitmask)) {
  2332. if (rxf_allmulti_enable(rxf))
  2333. need_hw_config = 1;
  2334. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2335. if (rxf_allmulti_disable(rxf))
  2336. need_hw_config = 1;
  2337. }
  2338. /* Trigger h/w if needed */
  2339. if (need_hw_config) {
  2340. rxf->cam_fltr_cbfn = cbfn;
  2341. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2342. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  2343. } else if (cbfn)
  2344. (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
  2345. return BNA_CB_SUCCESS;
  2346. err_return:
  2347. return BNA_CB_FAIL;
  2348. }
  2349. void
  2350. /* RxF <- bnad */
  2351. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2352. {
  2353. struct bna_rxf *rxf = &rx->rxf;
  2354. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2355. rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
  2356. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2357. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  2358. }
  2359. }
  2360. /* Rx */
  2361. /* Rx <- bnad */
  2362. void
  2363. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2364. {
  2365. struct bna_rxp *rxp;
  2366. struct list_head *qe;
  2367. list_for_each(qe, &rx->rxp_q) {
  2368. rxp = (struct bna_rxp *)qe;
  2369. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2370. bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
  2371. }
  2372. }
  2373. /* Rx <- bnad */
  2374. void
  2375. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2376. {
  2377. int i, j;
  2378. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2379. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2380. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2381. }
  2382. /* Rx <- bnad */
  2383. void
  2384. bna_rx_dim_update(struct bna_ccb *ccb)
  2385. {
  2386. struct bna *bna = ccb->cq->rx->bna;
  2387. u32 load, bias;
  2388. u32 pkt_rt, small_rt, large_rt;
  2389. u8 coalescing_timeo;
  2390. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2391. (ccb->pkt_rate.large_pkt_cnt == 0))
  2392. return;
  2393. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2394. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2395. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2396. pkt_rt = small_rt + large_rt;
  2397. if (pkt_rt < BNA_PKT_RATE_10K)
  2398. load = BNA_LOAD_T_LOW_4;
  2399. else if (pkt_rt < BNA_PKT_RATE_20K)
  2400. load = BNA_LOAD_T_LOW_3;
  2401. else if (pkt_rt < BNA_PKT_RATE_30K)
  2402. load = BNA_LOAD_T_LOW_2;
  2403. else if (pkt_rt < BNA_PKT_RATE_40K)
  2404. load = BNA_LOAD_T_LOW_1;
  2405. else if (pkt_rt < BNA_PKT_RATE_50K)
  2406. load = BNA_LOAD_T_HIGH_1;
  2407. else if (pkt_rt < BNA_PKT_RATE_60K)
  2408. load = BNA_LOAD_T_HIGH_2;
  2409. else if (pkt_rt < BNA_PKT_RATE_80K)
  2410. load = BNA_LOAD_T_HIGH_3;
  2411. else
  2412. load = BNA_LOAD_T_HIGH_4;
  2413. if (small_rt > (large_rt << 1))
  2414. bias = 0;
  2415. else
  2416. bias = 1;
  2417. ccb->pkt_rate.small_pkt_cnt = 0;
  2418. ccb->pkt_rate.large_pkt_cnt = 0;
  2419. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2420. ccb->rx_coalescing_timeo = coalescing_timeo;
  2421. /* Set it to IB */
  2422. bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
  2423. }
  2424. /* Tx */
  2425. /* TX <- bnad */
  2426. void
  2427. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  2428. {
  2429. struct bna_txq *txq;
  2430. struct list_head *qe;
  2431. list_for_each(qe, &tx->txq_q) {
  2432. txq = (struct bna_txq *)qe;
  2433. bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
  2434. }
  2435. }
  2436. /*
  2437. * Private data
  2438. */
  2439. struct bna_ritseg_pool_cfg {
  2440. u32 pool_size;
  2441. u32 pool_entry_size;
  2442. };
  2443. init_ritseg_pool(ritseg_pool_cfg);
  2444. /*
  2445. * Private functions
  2446. */
  2447. static void
  2448. bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
  2449. struct bna_res_info *res_info)
  2450. {
  2451. int i;
  2452. ucam_mod->ucmac = (struct bna_mac *)
  2453. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
  2454. INIT_LIST_HEAD(&ucam_mod->free_q);
  2455. for (i = 0; i < BFI_MAX_UCMAC; i++) {
  2456. bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
  2457. list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
  2458. }
  2459. ucam_mod->bna = bna;
  2460. }
  2461. static void
  2462. bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
  2463. {
  2464. struct list_head *qe;
  2465. int i = 0;
  2466. list_for_each(qe, &ucam_mod->free_q)
  2467. i++;
  2468. ucam_mod->bna = NULL;
  2469. }
  2470. static void
  2471. bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
  2472. struct bna_res_info *res_info)
  2473. {
  2474. int i;
  2475. mcam_mod->mcmac = (struct bna_mac *)
  2476. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
  2477. INIT_LIST_HEAD(&mcam_mod->free_q);
  2478. for (i = 0; i < BFI_MAX_MCMAC; i++) {
  2479. bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
  2480. list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
  2481. }
  2482. mcam_mod->bna = bna;
  2483. }
  2484. static void
  2485. bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
  2486. {
  2487. struct list_head *qe;
  2488. int i = 0;
  2489. list_for_each(qe, &mcam_mod->free_q)
  2490. i++;
  2491. mcam_mod->bna = NULL;
  2492. }
  2493. static void
  2494. bna_rit_mod_init(struct bna_rit_mod *rit_mod,
  2495. struct bna_res_info *res_info)
  2496. {
  2497. int i;
  2498. int j;
  2499. int count;
  2500. int offset;
  2501. rit_mod->rit = (struct bna_rit_entry *)
  2502. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
  2503. rit_mod->rit_segment = (struct bna_rit_segment *)
  2504. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
  2505. count = 0;
  2506. offset = 0;
  2507. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2508. INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
  2509. for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
  2510. bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
  2511. rit_mod->rit_segment[count].max_rit_size =
  2512. ritseg_pool_cfg[i].pool_entry_size;
  2513. rit_mod->rit_segment[count].rit_offset = offset;
  2514. rit_mod->rit_segment[count].rit =
  2515. &rit_mod->rit[offset];
  2516. list_add_tail(&rit_mod->rit_segment[count].qe,
  2517. &rit_mod->rit_seg_pool[i]);
  2518. count++;
  2519. offset += ritseg_pool_cfg[i].pool_entry_size;
  2520. }
  2521. }
  2522. }
  2523. static void
  2524. bna_rit_mod_uninit(struct bna_rit_mod *rit_mod)
  2525. {
  2526. struct bna_rit_segment *rit_segment;
  2527. struct list_head *qe;
  2528. int i;
  2529. int j;
  2530. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2531. j = 0;
  2532. list_for_each(qe, &rit_mod->rit_seg_pool[i]) {
  2533. rit_segment = (struct bna_rit_segment *)qe;
  2534. j++;
  2535. }
  2536. }
  2537. }
  2538. /*
  2539. * Public functions
  2540. */
  2541. /* Called during probe(), before calling bna_init() */
  2542. void
  2543. bna_res_req(struct bna_res_info *res_info)
  2544. {
  2545. bna_adv_res_req(res_info);
  2546. /* DMA memory for retrieving IOC attributes */
  2547. res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
  2548. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  2549. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
  2550. res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
  2551. ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
  2552. /* DMA memory for index segment of an IB */
  2553. res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2554. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
  2555. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
  2556. BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
  2557. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
  2558. /* Virtual memory for IB objects - stored by IB module */
  2559. res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
  2560. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
  2561. BNA_MEM_T_KVA;
  2562. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
  2563. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
  2564. BFI_MAX_IB * sizeof(struct bna_ib);
  2565. /* Virtual memory for intr objects - stored by IB module */
  2566. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
  2567. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
  2568. BNA_MEM_T_KVA;
  2569. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
  2570. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
  2571. BFI_MAX_IB * sizeof(struct bna_intr);
  2572. /* Virtual memory for idx_seg objects - stored by IB module */
  2573. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
  2574. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
  2575. BNA_MEM_T_KVA;
  2576. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
  2577. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
  2578. BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
  2579. /* Virtual memory for Tx objects - stored by Tx module */
  2580. res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
  2581. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
  2582. BNA_MEM_T_KVA;
  2583. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
  2584. res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
  2585. BFI_MAX_TXQ * sizeof(struct bna_tx);
  2586. /* Virtual memory for TxQ - stored by Tx module */
  2587. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
  2588. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
  2589. BNA_MEM_T_KVA;
  2590. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
  2591. res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
  2592. BFI_MAX_TXQ * sizeof(struct bna_txq);
  2593. /* Virtual memory for Rx objects - stored by Rx module */
  2594. res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
  2595. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
  2596. BNA_MEM_T_KVA;
  2597. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
  2598. res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
  2599. BFI_MAX_RXQ * sizeof(struct bna_rx);
  2600. /* Virtual memory for RxPath - stored by Rx module */
  2601. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
  2602. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
  2603. BNA_MEM_T_KVA;
  2604. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
  2605. res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
  2606. BFI_MAX_RXQ * sizeof(struct bna_rxp);
  2607. /* Virtual memory for RxQ - stored by Rx module */
  2608. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
  2609. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
  2610. BNA_MEM_T_KVA;
  2611. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
  2612. res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
  2613. BFI_MAX_RXQ * sizeof(struct bna_rxq);
  2614. /* Virtual memory for Unicast MAC address - stored by ucam module */
  2615. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
  2616. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
  2617. BNA_MEM_T_KVA;
  2618. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
  2619. res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
  2620. BFI_MAX_UCMAC * sizeof(struct bna_mac);
  2621. /* Virtual memory for Multicast MAC address - stored by mcam module */
  2622. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
  2623. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
  2624. BNA_MEM_T_KVA;
  2625. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
  2626. res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
  2627. BFI_MAX_MCMAC * sizeof(struct bna_mac);
  2628. /* Virtual memory for RIT entries */
  2629. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
  2630. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
  2631. BNA_MEM_T_KVA;
  2632. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
  2633. res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
  2634. BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
  2635. /* Virtual memory for RIT segment table */
  2636. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
  2637. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
  2638. BNA_MEM_T_KVA;
  2639. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
  2640. res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
  2641. BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
  2642. /* Interrupt resource for mailbox interrupt */
  2643. res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
  2644. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
  2645. BNA_INTR_T_MSIX;
  2646. res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
  2647. }
  2648. /* Called during probe() */
  2649. void
  2650. bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
  2651. struct bna_res_info *res_info)
  2652. {
  2653. bna->bnad = bnad;
  2654. bna->pcidev = *pcidev;
  2655. bna->stats.hw_stats = (struct bfi_ll_stats *)
  2656. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
  2657. bna->hw_stats_dma.msb =
  2658. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
  2659. bna->hw_stats_dma.lsb =
  2660. res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
  2661. bna->stats.sw_stats = (struct bna_sw_stats *)
  2662. res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
  2663. bna->regs.page_addr = bna->pcidev.pci_bar_kva +
  2664. reg_offset[bna->pcidev.pci_func].page_addr;
  2665. bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
  2666. reg_offset[bna->pcidev.pci_func].fn_int_status;
  2667. bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
  2668. reg_offset[bna->pcidev.pci_func].fn_int_mask;
  2669. if (bna->pcidev.pci_func < 3)
  2670. bna->port_num = 0;
  2671. else
  2672. bna->port_num = 1;
  2673. /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
  2674. bna_device_init(&bna->device, bna, res_info);
  2675. bna_port_init(&bna->port, bna);
  2676. bna_tx_mod_init(&bna->tx_mod, bna, res_info);
  2677. bna_rx_mod_init(&bna->rx_mod, bna, res_info);
  2678. bna_ib_mod_init(&bna->ib_mod, bna, res_info);
  2679. bna_rit_mod_init(&bna->rit_mod, res_info);
  2680. bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
  2681. bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
  2682. bna->rxf_default_id = BFI_MAX_RXF;
  2683. bna->rxf_promisc_id = BFI_MAX_RXF;
  2684. /* Mbox q element for posting stat request to f/w */
  2685. bfa_q_qe_init(&bna->mbox_qe.qe);
  2686. }
  2687. void
  2688. bna_uninit(struct bna *bna)
  2689. {
  2690. bna_mcam_mod_uninit(&bna->mcam_mod);
  2691. bna_ucam_mod_uninit(&bna->ucam_mod);
  2692. bna_rit_mod_uninit(&bna->rit_mod);
  2693. bna_ib_mod_uninit(&bna->ib_mod);
  2694. bna_rx_mod_uninit(&bna->rx_mod);
  2695. bna_tx_mod_uninit(&bna->tx_mod);
  2696. bna_port_uninit(&bna->port);
  2697. bna_device_uninit(&bna->device);
  2698. bna->bnad = NULL;
  2699. }
  2700. struct bna_mac *
  2701. bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
  2702. {
  2703. struct list_head *qe;
  2704. if (list_empty(&ucam_mod->free_q))
  2705. return NULL;
  2706. bfa_q_deq(&ucam_mod->free_q, &qe);
  2707. return (struct bna_mac *)qe;
  2708. }
  2709. void
  2710. bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
  2711. {
  2712. list_add_tail(&mac->qe, &ucam_mod->free_q);
  2713. }
  2714. struct bna_mac *
  2715. bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
  2716. {
  2717. struct list_head *qe;
  2718. if (list_empty(&mcam_mod->free_q))
  2719. return NULL;
  2720. bfa_q_deq(&mcam_mod->free_q, &qe);
  2721. return (struct bna_mac *)qe;
  2722. }
  2723. void
  2724. bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
  2725. {
  2726. list_add_tail(&mac->qe, &mcam_mod->free_q);
  2727. }
  2728. /**
  2729. * Note: This should be called in the same locking context as the call to
  2730. * bna_rit_mod_seg_get()
  2731. */
  2732. int
  2733. bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
  2734. {
  2735. int i;
  2736. /* Select the pool for seg_size */
  2737. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2738. if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
  2739. break;
  2740. }
  2741. if (i == BFI_RIT_SEG_TOTAL_POOLS)
  2742. return 0;
  2743. if (list_empty(&rit_mod->rit_seg_pool[i]))
  2744. return 0;
  2745. return 1;
  2746. }
  2747. struct bna_rit_segment *
  2748. bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
  2749. {
  2750. struct bna_rit_segment *seg;
  2751. struct list_head *qe;
  2752. int i;
  2753. /* Select the pool for seg_size */
  2754. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2755. if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
  2756. break;
  2757. }
  2758. if (i == BFI_RIT_SEG_TOTAL_POOLS)
  2759. return NULL;
  2760. if (list_empty(&rit_mod->rit_seg_pool[i]))
  2761. return NULL;
  2762. bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
  2763. seg = (struct bna_rit_segment *)qe;
  2764. bfa_q_qe_init(&seg->qe);
  2765. seg->rit_size = seg_size;
  2766. return seg;
  2767. }
  2768. void
  2769. bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
  2770. struct bna_rit_segment *seg)
  2771. {
  2772. int i;
  2773. /* Select the pool for seg->max_rit_size */
  2774. for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
  2775. if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
  2776. break;
  2777. }
  2778. seg->rit_size = 0;
  2779. list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
  2780. }